ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ CMOS. Εαρινό Εξάμηνο ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ

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1 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 6: ΚΥΚΛΩΜΑΤΑ CMOS ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]

2 CMOS Circuit Styles l Static complementary CMOS - except during switching, output connected to either or GND via a low-resistance path high noise margins full rail to rail swing V OH and V OL are at and GND, respectively low output impedance, high input impedance no steady state path between and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) l Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise ΗΜΥ307 Δ6 Κυκλώματα CMOS.2 Θεοχαρίδης, ΗΜΥ, 2017

3 Static Complementary CMOS q Pull-up network (PUN) and pull-down network (PDN) In 1 In 2 In N In 1 In 2 In N PUN PDN PMOS transistors only pull-up: make a connection from to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pull-down: make a connection from F to GND when F(In 1,In 2, In N ) = 0 NMOS transistors only PUN and PDN are dual logic networks ΗΜΥ307 Δ6 Κυκλώματα CMOS.3 Θεοχαρίδης, ΗΜΥ, 2017

4 Threshold Drops PUN 0 0 C L C L PDN C L C L ΗΜΥ307 Δ6 Κυκλώματα CMOS.4 Θεοχαρίδης, ΗΜΥ, 2017

5 Threshold Drops PUN S D D 0 V GS S 0 - V Tn C L C L PDN 0 V Tp D C L V GS S C L S D ΗΜΥ307 Δ6 Κυκλώματα CMOS.5 Θεοχαρίδης, ΗΜΥ, 2017

6 Construction of PDN l NMOS devices in series implement a NND function l NMOS devices in parallel implement a NOR function + ΗΜΥ307 Δ6 Κυκλώματα CMOS.6 Θεοχαρίδης, ΗΜΥ, 2017

7 Dual PUN and PDN l PUN and PDN are dual networks DeMorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN l Complementary gate is naturally inverting (NND, NOR, OI, OI) l Number of transistors for an N-input logic gate is 2N ΗΜΥ307 Δ6 Κυκλώματα CMOS.7 Θεοχαρίδης, ΗΜΥ, 2017

8 CMOS NND F ΗΜΥ307 Δ6 Κυκλώματα CMOS.8 Θεοχαρίδης, ΗΜΥ, 2017

9 CMOS NOR + F ΗΜΥ307 Δ6 Κυκλώματα CMOS.9 Θεοχαρίδης, ΗΜΥ, 2017

10 Complex CMOS Gate D C OUT =!(D + ( + C)) ΗΜΥ307 Δ6 Κυκλώματα CMOS.10 Θεοχαρίδης, ΗΜΥ, 2017

11 Complex CMOS Gate C D D C OUT =!(D + ( + C)) ΗΜΥ307 Δ6 Κυκλώματα CMOS.11 Θεοχαρίδης, ΗΜΥ, 2017

12 Standard Cell Layout Methodology 1980s Routing channel signals GND 12 ΗΜΥ307 Δ6 Κυκλώματα CMOS.12 Θεοχαρίδης, ΗΜΥ, 2017

13 Standard Cell Layout Methodology 1990s Mirrored Cell No Routing channels M2 M3 GND Mirrored Cell GND 13 ΗΜΥ307 Δ6 Κυκλώματα CMOS.13 Θεοχαρίδης, ΗΜΥ, 2017

14 Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3l + 3l Pitch = repetitive distance between objects Cell height is 12 pitch 2l In Out Cell boundary GND Rails ~10l 14 ΗΜΥ307 Δ6 Κυκλώματα CMOS.14 Θεοχαρίδης, ΗΜΥ, 2017

15 Standard Cells With minimal diffusion routing With silicided diffusion In M 2 Out In Out In Out M 1 GND GND 15 ΗΜΥ307 Δ6 Κυκλώματα CMOS.15 Θεοχαρίδης, ΗΜΥ, 2017

16 Standard Cells 2-input NND gate Out GND 16 ΗΜΥ307 Δ6 Κυκλώματα CMOS.16 Θεοχαρίδης, ΗΜΥ, 2017

17 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance 17 ΗΜΥ307 Δ6 Κυκλώματα CMOS.17 Θεοχαρίδης, ΗΜΥ, 2017

18 Standard Cell Layout Methodology Routing channel signals GND What logic function is this? ΗΜΥ307 Δ6 Κυκλώματα CMOS.18 Θεοχαρίδης, ΗΜΥ, 2017

19 OI21 Logic Graph j C X C PUN X =!(C ( + )) X i C i j C GND PDN ΗΜΥ307 Δ6 Κυκλώματα CMOS.19 Θεοχαρίδης, ΗΜΥ, 2017

20 Two Stick Layouts of!(c ( + )) C C X X GND GND uninterrupted diffusion strip ΗΜΥ307 Δ6 Κυκλώματα CMOS.20 Θεοχαρίδης, ΗΜΥ, 2017

21 Consistent Euler Path q n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C X i j GND C q For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) ΗΜΥ307 Δ6 Κυκλώματα CMOS.21 Θεοχαρίδης, ΗΜΥ, 2017

22 OI22 Logic Graph C X PUN D D C X =!((+) (C+D)) X C D C D GND PDN ΗΜΥ307 Δ6 Κυκλώματα CMOS.22 Θεοχαρίδης, ΗΜΥ, 2017

23 OI22 Layout D C X GND q Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) ΗΜΥ307 Δ6 Κυκλώματα CMOS.23 Θεοχαρίδης, ΗΜΥ, 2017

24 XNOR/XOR Implementation XNOR XOR Å Å Å Å q How many transistors in each? q Can you create the stick transistor layout for the lower left circuit? ΗΜΥ307 Δ6 Κυκλώματα CMOS.24 Θεοχαρίδης, ΗΜΥ, 2017

25 VTC is Data-Dependent V GS2 = V V DS1 V GS1 = V M 3 M 4 D M 2 S D M 1 S F= Cint weaker PUN 0.5µ/0.25µ NMOS 0.75µ /0.25µ PMOS 0 1 2,: 0 -> 1 =1, :0 -> 1 =1, :0->1 q The threshold voltage of M 2 is higher than M 1 due to the body effect (g) V Tn1 = V Tn0 V Tn2 = V Tn0 + g(ö( 2f F + V int ) - Ö 2f F ) since V S of M 2 is not zero (when V = 0) due to the presence of Cint ΗΜΥ307 Δ6 Κυκλώματα CMOS.25 Θεοχαρίδης, ΗΜΥ, 2017

26 Static CMOS Full dder Circuit C in C in!c out!sum C in C in C in ΗΜΥ307 Δ6 Κυκλώματα CMOS.26 Θεοχαρίδης, ΗΜΥ, 2017

27 Static CMOS Full dder Circuit!C out =!C in & (!!) (! &!)!Sum = C out & (!!!C in ) (! &! &!C in ) C in C in!c out!sum C in C in C in C out = C in & ( ) ( & ) Sum =!C out & ( C in ) ( & & C in ) ΗΜΥ307 Δ6 Κυκλώματα CMOS.27 Θεοχαρίδης, ΗΜΥ, 2017

28 NMOS Transistors in Series/Parallel l Primary inputs drive both gate and source/drain terminals l NMOS switch closes when the gate input is high X Y X = Y if and X Y X = Y if or l Remember - NMOS transistors pass a strong 0 but a weak 1 ΗΜΥ307 Δ6 Κυκλώματα CMOS.28 Θεοχαρίδης, ΗΜΥ, 2017

29 PMOS Transistors in Series/Parallel l Primary inputs drive both gate and source/drain terminals l PMOS switch closes when the gate input is low X Y X = Y if and = + X Y X = Y if or = l Remember - PMOS transistors pass a strong 1 but a weak 0 ΗΜΥ307 Δ6 Κυκλώματα CMOS.29 Θεοχαρίδης, ΗΜΥ, 2017

30 Pass Transistor (PT) Logic 0 F 0 F q Gate is static a low-impedance path exists to both supply rails under all circumstances q N transistors instead of 2N q No static power consumption q Ratioless q idirectional (versus undirectional) ΗΜΥ307 Δ6 Κυκλώματα CMOS.30 Θεοχαρίδης, ΗΜΥ, 2017

31 Pass Transistor (PT) Logic 0 F = 0 F = q Gate is static a low-impedance path exists to both supply rails under all circumstances q N transistors instead of 2N q No static power consumption q Ratioless q idirectional (versus undirectional) ΗΜΥ307 Δ6 Κυκλώματα CMOS.31 Θεοχαρίδης, ΗΜΥ, 2017

32 VTC of PT ND Gate 1.5/ / / /0.25 F= V out, V 1 0 =, =0 =, =0 == Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion) ΗΜΥ307 Δ6 Κυκλώματα CMOS.32 Θεοχαρίδης, ΗΜΥ, 2017

33 Differential PT Logic (CPL) PT Network F F Inverse PT Network F F F= F=+ F=Å ND/NND F= OR/NOR F=+ XOR/XNOR F=Å ΗΜΥ307 Δ6 Κυκλώματα CMOS.33 Θεοχαρίδης, ΗΜΥ, 2017

34 CPL Properties l Differential so complementary data inputs and outputs are always available (so don t need extra inverters) l Still static, since the output defining nodes are always tied to or GND through a low resistance path l Design is modular; all gates use the same topology, only the inputs are permuted. l Simple XOR makes it attractive for structures like adders l Fast (assuming number of transistors in series is small) l dditional routing overhead for complementary signals l Still have static power dissipation problems ΗΜΥ307 Δ6 Κυκλώματα CMOS.34 Θεοχαρίδης, ΗΜΥ, 2017

35 CPL Full dder C in C in!sum Sum C in C in!c out C in C out C in ΗΜΥ307 Δ6 Κυκλώματα CMOS.35 Θεοχαρίδης, ΗΜΥ, 2017

36 CPL Full dder C in C in!sum Sum C in C in!c out C in C out C in ΗΜΥ307 Δ6 Κυκλώματα CMOS.36 Θεοχαρίδης, ΗΜΥ, 2017

37 NMOS Only PT Driving an Inverter In = V x = V GS = V V DD DD -V Tn D S M 2 M 1 l V x does not pull up to, but V Tn q Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from to GND) q Notice V Tn increases of pass transistor due to body effect (V S ) ΗΜΥ307 Δ6 Κυκλώματα CMOS.37 Θεοχαρίδης, ΗΜΥ, 2017

38 Voltage Swing of PT Driving an Inverter 3 In In = 0 D 0.5/0.25 S x 1.5/ /0.25 Out Voltage, V 2 1 x = 1.8V Out Time, ns l ody effect large V S at x - when pulling high ( is tied to GND and S charged up close to ) l So the voltage drop is even worse V x = - (V Tn0 + g(ö( 2f f + V x ) - Ö 2f f )) ΗΜΥ307 Δ6 Κυκλώματα CMOS.38 Θεοχαρίδης, ΗΜΥ, 2017

39 Cascaded NMOS Only PTs = = M 1 G C = S M 2 x = - V Tn1 G S y = Out = M 1 x C = M 2 y Out Swing on y = - V Tn1 - V Tn2 Swing on y = - V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins ΗΜΥ307 Δ6 Κυκλώματα CMOS.39 Θεοχαρίδης, ΗΜΥ, 2017

40 Solution 1: Level Restorer Level Restorer =1 M 2 Out=0 =0 M n M r on off x= 0 1 M 1 Out =1 q Full swing on x (due to Level Restorer) so no static power consumption by inverter q No static backward current path through Level Restorer and PT since Restorer is only active when is high l For correct operation M r must be sized correctly (ratioed) ΗΜΥ307 Δ6 Κυκλώματα CMOS.40 Θεοχαρίδης, ΗΜΥ, 2017

41 Transient Level Restorer Circuit Response 3 W/L 2 =1.50/0.25 W/L n =0.50/0.25 W/L 1 =0.50/0.25 Voltage, V 2 1 W/L r =1.75/0.25 W/L r =1.50/0.25 node x never goes below V M of inverter so output never switches 0 W/L r =1.0/ Time, ps W/L r =1.25/0.25 q Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) ΗΜΥ307 Δ6 Κυκλώματα CMOS.41 Θεοχαρίδης, ΗΜΥ, 2017

42 Solution 2: Multiple V T Transistors l Technology solution: Use (near) zero V T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to ) low V T transistors In 2 = 0V = 2.5V on Out In 1 = 2.5V = 0V sneak path off but leaking q Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V GS is below V T ) ΗΜΥ307 Δ6 Κυκλώματα CMOS.42 Θεοχαρίδης, ΗΜΥ, 2017

43 Solution 3: Transmission Gates (TGs) q Most widely used solution C C C C C = GND C = GND = = GND C = C = l Full swing bidirectional switch controlled by the gate signal C, = if C = 1 ΗΜΥ307 Δ6 Κυκλώματα CMOS.43 Θεοχαρίδης, ΗΜΥ, 2017

44 Solution 3: Transmission Gates (TGs) q Most widely used solution C C C C C = GND C = GND = = GND C = C = l Full swing bidirectional switch controlled by the gate signal C, = if C = 1 ΗΜΥ307 Δ6 Κυκλώματα CMOS.44 Θεοχαρίδης, ΗΜΥ, 2017

45 Resistance of TG 30 W/L p =0.50/0.25 0V 25 R n R p V V out Resistance, kw R p R n 2.5V R eq W/L n =0.50/ ΗΜΥ307 Δ6 Κυκλώματα CMOS.45 Θεοχαρίδης, ΗΜΥ, 2017

46 TG Multiplexer S S S F In 2 S F In 1 S F =!(In 1 S + In 2 S) GND In 1 S S In 2 ΗΜΥ307 Δ6 Κυκλώματα CMOS.46 Θεοχαρίδης, ΗΜΥ, 2017

47 Transmission Gate XOR Å ΗΜΥ307 Δ6 Κυκλώματα CMOS.47 Θεοχαρίδης, ΗΜΥ, 2017

48 Transmission Gate XOR weak 0 if! 0 1 off on off on! Å! weak 1 if an inverter ΗΜΥ307 Δ6 Κυκλώματα CMOS.48 Θεοχαρίδης, ΗΜΥ, 2017

49 TG Full dder C in Sum C out ΗΜΥ307 Δ6 Κυκλώματα CMOS.49 Θεοχαρίδης, ΗΜΥ, 2017

50 Differential TG Logic (DPL) GND F= F=Å GND F= F=Å ND/NND XOR/XNOR ΗΜΥ307 Δ6 Κυκλώματα CMOS.50 Θεοχαρίδης, ΗΜΥ, 2017

51 Next Lecture: The MOS Transistor l MOS transistor dynamic behavior (R and C) l Wire capacitance ΗΜΥ307 Δ6 Κυκλώματα CMOS.51 Θεοχαρίδης, ΗΜΥ, 2017