THE MOTOROLA 68XXX MICROPROCESSORS

Transcript

1 THE MOTOROLA 68XXX MICROPROCESSORS THE MOTOROLA 68XXX MICROPROCESSORS 14.1 Introduction 14.2 Programming Model 14.3 Addressing Modes 微處理機原理與應用 Lecture 14-2

2 14.1 Introduction The Motorola MC68000 microprocessor was introduced in 1976 in integrated circuit form with an architecture similar to the 6800 family of 8-bit microprocessor and to the DEC PDP-11 family 16-bit minicomputers. The MC68000 is found in a popular line of personal computers and is also popular for industrial and graphic-intense applications. Internally, all versions of the have a 32-bit architecture. However, the external bus widths vary from 16 to 32 bits 微處理機原理與應用 Lecture Introduction The MC68000 is the CPU used in Apple s Macintosh series of microcomputers 微處理機原理與應用 Lecture 14-4

3 14.1 Introduction The use a 16-bit data bus and a 24-bit memory address bus and therefore can address only 16 Mbytes of physical memory. Special instructions added to the give it virtual memory addressing capability. The introduced the 32-bit data bus and a coprocessor interface which supports up to eight coprocessors and added a 256-byte on-chip instruction cache. The internal design of is split into two independent 32-bit processors to speed up processing. It also has internal MMU to address the full 4 Gbytes of memory space 微處理機原理與應用 Lecture Introduction The adds an internal floating point arithmetic unit to speed up complex calculations. Its internal design allow the to carry out many of its instruction execution in a pipeline mode. The uses a new superscalar execution technique which allows it to process more than one instruction per clock cycle. The virtual memory techniques cause information to be loaded from mass storage devices before the information is addressed by the processor 微處理機原理與應用 Lecture 14-6

4 14.1 Introduction Major attributes of the 68XXX processors Attribute 微處理機原理與應用 Lecture Introduction Performance comparisons of Apple Mac computers MODEL CPU GRAPHICS DISK MATH PROCESSOR Mac II MHz Classic II MHz SE/ MHz IIcx MHz Color Classic MHz IIsi MHz IIsi* MHz IIci MHz IIci, cache MHz PB MHz LC III MHz IIfx MHz Co. Cl MHz C/Q 660av MHz Quadra MHz LC040 Quadra MHz IIci, MHz PB MHz LC040 PB 540C MHz LC040 Quadra MHz Q 700/PPC MHz 601 Quadra MHz Quadra MHz Quadra MHz Q 950/PPC MHz / MHz / MHz /66 L2# MHz 601# UMAX J n/a** MHz 604e imac Rev. B n/a** MHz G3 P-Mac G3/ n/a** MHz G3 S900/G3-333## n/a** MHz 604e FW ibook n/a** MHz G3e PB G4/ n/a** MHz G 微處理機原理與應用 Lecture 14-8

5 14.1 Introduction Performance comparisons of Apple Mac computers PB G4/400 FW ibook S900/G3-333 P-Mac G3/266 imac Rev. B UMAX J /66 L2 6100/ /60 Q 950/PPC Quadra 950 Quadra 650 Quadra 630 Q 700/PPC Quadra 700 PB 540C PB 540 IIci, 040 Quadra 605 Quadra 605 C/Q 660av Co. Cl. 040 IIfx LC III PB 170 IIci, cache IIci Iisi IIsi Color Classic IIcx SE/30 Classic II Mac II 微處理機原理與應用 Lecture 14-9 Speedometer 4.02 Mac Benchmarks 14.2 Programming Model The internal architecture uses 32-bit buses and registers. The external address bus has 23 bits. It can address 8,388, bit memory location (16-Mbyte memory address space). All new 68XXX processors, starting with the 68020, have a 32-bit external address bus and can therefore address 4 Gbytes of physical memory. The 68XXX family programming model is broken down into the user and system sections. The user section is where ordinary tasks run, and the system section is where the full power of the microprocessor is allowed 微處理機原理與應用 Lecture 14-10

6 14.2 Programming Model The 68XXX user programming model 微處理機原理與應用 Lecture Programming Model The 68XXX family has seventeen 32-bit registers, a 32-bit program counter (23-bit for the 68000), and a 16-bit status register. Data registers: D 0 ~D 7, work in the bit, BCD, byte, word, or long word modes. Address registers: A 0 ~A 7, are used to help calculate the memory location address. Program counter: PC Condition code register: CCR Seven 80-bit data registers: when floating point unit is used 32-bit control register: when floating point unit is used. Beside the program counter, all other 16 registers are general-purpose 微處理機原理與應用 Lecture 14-12

7 14.2 Programming Model The 68XXX status register Original 6802 flags 微處理機原理與應用 Lecture Programming Model The user and supervisor states provide the protection from user programming error that might contaminate the content of stack or memory. When the processor is in the supervisor state, you have access to many more instructions and a number of system register in the more advance versions of the 68XXX family of processors The 68XXX processors are always in one of three major processing states: Normal processing state Program instructions Exception processing state Interrupts Halt processing state Wait for an interrupt 微處理機原理與應用 Lecture 14-14

8 14.2 Programming Model The 68XXX supervisor programming model 微處理機原理與應用 Lecture Programming Model The exception states Type of Cause Exception Type Exception Caused by 微處理機原理與應用 Lecture 14-16

9 14.3 Addressing Modes The program counter is used for instruction fetches, and one of the address registers (A 0 to A 7 ) is used for data fetches. The 68XXX processors can address bit, BCD, byte, word, long-word and quad-word data in memory. There are six different kinds of addressing modes on the earlier processors and nine on the later versions (68020 and later). All the addressing mode do the same thing: They generate an effective address 微處理機原理與應用 Lecture Addressing Modes The organization of data in 68XXX memory locations 微處理機原理與應用 Lecture 14-18

10 14.3 Addressing Modes 68XXX addressing modes by processor type Addressing Modes Mode , Number and Syntax Syntax 微處理機原理與應用 Lecture Addressing Modes A 68XXX instruction word showing the part used for the instruction, the mode, and register to be used 微處理機原理與應用 Lecture 14-20

11 14.3 Addressing Modes Register direct addressing Data register direct Address register direct 微處理機原理與應用 Lecture Addressing Modes Register indirect addressing 微處理機原理與應用 Lecture 14-22

12 14.3 Addressing Modes Register indirect addressing Address register indirect (mode 010) Address register indirect with postincrement (mode 011) Address register indirect with preincrement (mode 100) Address register indirect with displacement (mode 101) Address register indirect with postincrement 微處理機原理與應用 Lecture Addressing Modes Register indirect addressing with displacement 微處理機原理與應用 Lecture 14-24

13 14.3 Addressing Modes Indirect addressing with an index 微處理機原理與應用 Lecture Addressing Modes The program counter with displacement mode 微處理機原理與應用 Lecture 14-26

14 14.3 Addressing Modes Relative addressing using a displacement and an index 微處理機原理與應用 Lecture Addressing Modes The long and short addressing modes 微處理機原理與應用 Lecture 14-28

15 The 68XXX processors are upwardly compatible. The 68XXX instructions can grouped into: The data move instructions The integer arithmetic instructions The logical instructions The shift and rotate instructions The bit manipulation instructions The bit field instructions The BCD instructions The program control instructions The floating point instructions The special data movement instructions The supervisory control instructions The trap instructions The special function instructions 微處理機原理與應用 Lecture The data move instructions Data move instructions Move bytes, words or long words Address move instructions Move words or long words Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-30

16 The integer arithmetic instructions Mnemonic Description 68000, 微處理機原理與應用 Lecture The logical instructions The TST instruction test the operand by comparing it to zero, and the status register bits are set. No other results are saved. Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-32

17 The shift and rotate instructions Memory shifts and rotates must work on a word. Register shifts and rotates support all operand lengths. Mnemonic Description 68000, 微處理機原理與應用 Lecture The bit manipulation instructions Each bit-oriented instructions must have not only an effective address but also a bit address. Only the status register zero flag is changed by bit operation. Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-34

18 The bit field instructions The bit field instructions let the programmer work with a variable-length bit field; that is, the operand can be from 1 to 32 bits long. Mnemonic Description 68000, 微處理機原理與應用 Lecture The BCD instructions The BCD instructions let you perform arithmetic operations (add, subtract, and negate) on byte operands. Packed BCD must be used in BCD instructions PACK and UNPK instructions allow a programmer to convert ASCII or EBCDIC data string into BCD data or to make BCD data into ASCII or EBCDIC data string. Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-36

19 The program control instructions Mnemonic Description 68000, 微處理機原理與應用 Lecture The floating point instructions Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-38

20 The special data movement instructions supervisory mode These special data movement instruction introduce the ability to move blocks of data, multiple registers, and the special function registers. Mnemonic Description 68000, 微處理機原理與應用 Lecture The supervisory control instructions supervisory mode The privileged instructions work only when the status register S bit is set. Mnemonic Description 68000, 微處理機原理與應用 Lecture 14-40

21 The supervisory control instructions supervisory mode The trap instructions are like interrupts. They cause the processor to move to the exception processing state. Mnemonic Description 68000, 微處理機原理與應用 Lecture The special functions instructions The processor allows the programmer access to virtual memory by using address translation tables which are stored in memory. The most recently used translations are stored in an address translation cache (ATC) in the MMU. The PFLUSH and PTEST instructions are provided to allow programmer control over the ATC contents. The introduced the ability to support multiple processors (one to eight processors). The CAS, CAS2, and TAS are used to manage multiple processor. The CASH, CINV, and CPUSH are provided for on-chip cache memory support 微處理機原理與應用 Lecture 14-42

22 The special functions instructions Mnemonic Description 68000, 微處理機原理與應用 Lecture Implicit instruction addresses Instruction Implied Register SP (System Stack Pointer) USP (User Stack Pointer) SSP (Supervisor Stack Pointer) 微處理機原理與應用 Lecture 14-44

23 The and use a 64-pin package. They do not use any multiplexed address or data lines. The and newer processors support a full 32-bit address bus and a full 32-bit data bus. They are usually packaged in pin grid array package or quad flat pack. The 68XXX common signals Address bus Data bus Asynchronous bus control Bus arbitration control Interrupt control Bus exception control or system control Processor status or function codes Power, ground, clock 微處理機原理與應用 Lecture The logical pinout groupings 微處理機原理與應用 Lecture 14-46

24 A functional pinning breakout for the 68XXX processors 微處理機原理與應用 Lecture A 114-pin pin grid array package used for 68XXX microprocessor 微處理機原理與應用 Lecture 14-48

25 A 132-pin quad flat pack 微處理機原理與應用 Lecture XXX processor packages and pin count Attribute 微處理機原理與應用 Lecture 14-50

26 The block diagram 微處理機原理與應用 Lecture The Macintosh II (68020) block diagram 微處理機原理與應用 Lecture 14-52

27 Logic Board Picture for Apple Macintosh Color Classic Reference: 微處理機原理與應用 Lecture The and newer processors offer three different types of bus operation: asynchronous, synchronous, and burst data transfer. The synchronous mode requires the external device to work at the processor speed rather than telling the processor when it is finished. The burst data transfer allows a continuous flow of data from memory into the on-chip cache memory until the cache is full. The asynchronous bus control lines manage exchanges between external devices and the 68XXX address and data buses. The 68XXX processors support DMA with the three bus arbitration control lines: BR (bus request), BG (bus grant), BGACK (bus grant acknowledge) 微處理機原理與應用 Lecture 14-54

28 There are three interrupt inputs on a 68XXX processor indicating no interrupt (000) or seven different levels of interrupt priority (001 to 111). Bits 8, 9, and 10 of a 68XXX status register are called the interrupt priority mask. The programmer can set these bits to indicate the priority level of interrupt of 68XXX processor will recognize. When a 68XXX processor recognizes an interrupt, it starts an exception processing routine, and the processor is put in the privileged mode. All exception mode processing must be done in the privileged state. The 68XXX processors use interrupt vectors given by the external interrupt device 微處理機原理與應用 Lecture Generating a complete address from the 8-bit interrupt vector supplied by an external device 微處理機原理與應用 Lecture 14-56

29 68XXX vector assignments Vector Hex Address Assignment 微處理機原理與應用 Lecture XXX vector assignments Vector Hex Address Assignment 微處理機原理與應用 Lecture 14-58