SSB RADIO TELEPHONE ic-m700pro

Transcript

1 SSB RADIO TPHONE ic-m00pro S-0XZ-C June. 00

2 INTRODUCTION CAUTION This service manual describes the latest service information for the IC-M00PRO SSB RADIO TPHON at the time of publication. NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than specified. This will ruin the transceiver. MODEL VERSION GEN- GEN- GEN- GEN- GEN- GEN- CHN IC-M00PRO ALARM UNIT N/A Yes N/A Yes N/A Yes N/A DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dbm (00 mw) to the antenna connector. This could damage the transceiver s front-end. To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. ING PARTS REPAIR NOTES Be sure to include the following four points when ordering replacement parts:. Make sure the problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective.. DO NOT transmit power into a Standard Signal Generator or a Sweep Generator.. ALWAYS connect a 0 db to 0 db attenuator between the transceiver and a Deviation Meter or Spectrum Analyzer when using such test equipment.. READ the instructions of test equipment throughly before connecting a test equipment to the transceiver.. 0-digit Icom parts numbers. Component name. Equipment model name and unit name. Quantity required < EXLE> 000 TAFNG IC-M00PRO MAIN UNIT 0000 Screw screw IC-M00PRO Top cover pieces 0 pieces Addresses are provided on the inside back cover for your convenience. Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom, Germany, France, Spain, Russia and/or other countries.

3 CONTENTS SECTION SPECIFICATIONS SECTION INSIDE VIEWS SECTION CIRCUIT - RECEIVER CIRCUITS TRANSMITTER CIRCUITS PLL CIRCUIT PORT ALLOCATIONS... - SECTION ADJUSTMENT PROCEDU - PREPARATION PLL ADJUSTMENT TRANSMITTER ADJUSTMENTS RECEIVER ADJUSTMENTS... - SECTION PARTS LIST SECTION MECHANICAL PARTS AND DISASSEMBLY SECTION SEMICONDUCTOR INFORMATION SECTION BOARD LAYOUTS - PLL UNIT MAIN UNIT LOGIC-J UNIT, ALARM AND PA0W BOARD'S MIC-J, VR/-J, SENSOR/, FILTER-J AND TERMINAL-J BOARD'S... - SECTION BLOCK DIAGRAM SECTION 0 VOLTAGE DIAGRAM LOGIC-J UNIT, VR/-J, SENSOR/-J AND MIC-J BOARD'S MAIN UNIT PLL UNIT PA0W, FILTER-J, TERMINAL-J BOARD'S

4 SECTION SPECIFICATIONS M GENERAL Frequency coverage : Receive Transmit Mode Number of channels 00 khz. MHz.000. MHz MHz MHz MHz MHz MHz MHz MHz MHz : JE (USB), HE (AM), JB (AFSK), FB (FSK), RE, AA (CW) (Available modes differ with version) : 0 channels (max.) groups of 0 channels each Antenna impedance : 0 Ω (nominal) Usable temperature range : 0 C to +0 C; F to +0 F Frequency stability : ±0 Hz ( 0 C to +0 C; F to +0 F) (±0 Hz above MHz) Power supply requirement :. V DC ±% Negative ground Current drain (at. V DC) : Transmit (max. output power) 0 A Receive (max. audio output). A Dimensions (projections not included) :.(W).(H) (D) mm; (W) (H) (D) in Weight (with ant., battery case and cells) :. kg; lb oz Remote connector : NMEA D-sub -pin (female) ACC connector : DIN -pin (female) ACC connector : DIN -pin (female) M TRANSMITTER Output power (at. V DC) : 0, 0, 0 W PEP (0, 0 W PEP only above MHz) Spurious emissions : db typical Carrier suppressions : db typical Unwanted sideband suppression : db typical Microphone impedance : 00 Ω M RECEIVER Sensitivity JE, RE, JB, AA HE (for 0dB S/N) : 0. µv typical (.000. MHz) (for db SINAD).0 µv (.000. MHz). µv ( MHz). µv typical (.000. MHz). µv (.000. MHz) µv ( MHz) Spurious response rejection : 0 db (.000. MHz) Audio output power :.0 W typical (at 0% distortion with a Ω load) Audio impeadance : to Ω Clarity variable range : ±0 Hz All stated specifications are subject to change without notice or obligation. -

5 SECTION INSIDE VIEWS PA0W, FILTER AND TERMINAL BOARDS TERMINAL board REG board [EUR-], [EUR-] only Fuse (F00) Drive amplifiers (Q00, Q00: SC) FILTER board Thermal switches S00: OHD- 0M S00: OHD- 0M Power detector circuit Power amplifiers (Q00, Q00: SC0) PA0W board MAIN, PLL AND LOGIC UNITS MAIN unit RF filter circuit ALARM board except [GEN-] Noise blanker circuit nd mixer circuit Squelch circuit st IF amplifier (Q: SK) Demodulator circuit (IC0: NJMV) st IF filter (FI: FL-0) PLL IC (IC00: LCM) BFO DDS IC (IC00: SC-) PLL/-A unit DDS IC (IC00: SC-A) Reference oscillator (X00: CR-) [GEN-], [GEN-], [EUR-] only LOGIC unit -

6 SECTION CIRCUIT - RECEIVER CIRCUITS -- ND MIXER AND IF CIRCUITS (MAIN UNIT) -- RF FILTER CIRCUIT (MAIN UNIT) The st IF signal from the crystal filter (FIb) is converted again into a.0 MHz nd IF signal at the nd mixer circuit (D, L, L). The 0 MHz nd local signal (LO) from the PLL unit enters the MAIN unit via J to be applied to the nd mixer. Received signals from the antenna connector pass through the transmit/receive switching relay (FILTER board RL) and are then applied to the MAIN unit via J. The signals pass through the protection relay (RL),. MHz cut off high-pass filter (L L, C C, C) and are then applied to one of nine bandpass filters (including one low-pass filter for below.0 MHz). These filters are selected by the filter control signals (B0 B) as described in the table below. The nd IF signal is passed through the noise blanker gate (D, D) and amplified at the nd IF amplifier (Q) and then applied to one of the MHz IF filters as described below. The passed signal is amplified at the two stage nd IF amplifiers (Q, Q) and is applied to a demodulator circuit (D for HE or IC0 for JE and others). The filtered signals pass through the 0 MHz cut-off lowpass filter (L, L, C0 C, C), and are then applied to the st mixer circuit (Q, Q). ND IF FILTERS USED RF FILTERS USED MODE Used filter Control signal JE, RE, FSK FI SEL: low, HE: low HE FI/FI SEL: low, HE: high FSK narrow, AA narrow Optional narrow filter* SEL: high, HE: low Frequency Control Entrance Frequency Control Entrance (MHz) signal signal coil coil (MHz) 0.. B0 L 0. B L. B L. B L. B L. B L. B L. B L. B L *Built-in to the GMDSS versions -- NOISE BLANKER CIRCUIT (MAIN UNIT) The noise blanker circuit cuts off the IF circuit line at the moment of receiving a pulse-type noise. A portion of the nd IF signal between resonator circuits (L, L after stage of the nd mixer, D) is amplified at the noise amplifiers (Q, IC, Q). The signal is then detected at the noise detector (D) to convert the noise components to DC voltages. -- ST MIXER AND IF CIRCUITS (MAIN UNIT) The st mixer circuit converts the received signals into a fixed frequency,.0 MHz st IF signal using the PLL output frequency. By changing the PLL frequency, only the desired frequency is picked up at the pair of crystal filters (FIa, FIb) at the next stage. The signals are then applied to the noise blanker switch (Q, Q). At the moment the detected voltage exceeds the Q s threshold level, Q outputs a blanking signal to close the noise blanker gate (D, D) by applying reverse-biased voltage. Q turns the noise blanker circuit ON and OFF. The IF amplifier (Q) and resonator circuits are designed between the filter pair. The PLL output signal (LO) enters the MAIN unit via J and is amplified at the st LO amplifier (Q) and then applied to the st mixer (Q, Q) RECEIVE FREQUEY CONSTRUCTION HE st mixer Q, Q LPF or BPF 0.. MHz Fla/Flb Crystal filter.0 MHz st LO:..0 MHz nd mixer D Fl or Fl/Fl Crystal filter.0 MHz nd LO: 0.0 MHz - Detector D Other modes Demodulator IC0 Audio output BFO JE, JB, RE, FSK:.0 MHz FSK narrow, JB narrow:.0 MHz.0 MHz AA:

7 The detected voltage is also applied to the noise blanker AGC circuit (Q, Q0) and is then fed back to the noise amplifier (IC) as a bias voltage. The noise AGC circuit prevents closure of the noise blanker gate for long periods by non-pulse-type noise. The time constant of the noise blanker AGC circuit is determined by R and C. -- S-METER CIRCUIT (MAIN UNIT) The S-meter indicates the AGC level on the display, since the AGC level varies with the received signal strength. The AGC bias voltage (AGC time constant line) from the AGC amplifier (Q) is inverted and amplified at the meter amplifier (ICb). The amplified signal is applied to the CPU via the RSM line. -- DEMODULATOR CIRCUIT (MAN UNIT) This circuit mixes the nd IF and BFO signals to pick up the AF components (except HE mode). The nd IF signal from the nd IF amplifier (Q) is applied to the balanced mixer (IC0, pin ). The.0.00 MHz BFO signal from the PLL unit is also applied to IC0 (pin 0). AF signals are output from pin and are then applied to the AF circuits. -- AF LIFIER CIRCUITS (MAIN UNIT AND LOGIC BOARD) AF signals from the demodulator or HE detector circuits pass through the active low-pass filter (IC0b) and squelch gate (ICa), and are then applied to the electronic volume control (IC). The CPU (IC, pin ) outputs the volume control signal ( to V) according to the [VOLUME] control setting. -- HE DETECTOR CIRCUIT (MAIN UNIT) The nd IF signal from the nd IF amplifier (Q) is applied to the AM detector circuit (D) to be demodulated into AF signals. The detected signals are amplified at the buffer amplifier (Q), and are then applied to the AF circuits. The AF output signal from IC ( pin) are supplied to the LOGIC unit via J. The signals are amplified at the AF power amplifier (IC00) and are then applied to the internal speaker via microphone connector (pins, ) and external [SP] jack via the MAIN unit. -- AGC CIRCUIT (MAIN UNIT) The speaker switch relay (RL00) is connected to the ( ) terminal of internal speaker for the [SPEAKER] switch function. The AGC (Automatic Gain Control) circuit reduces IF amplifier gain to prevent the receiver circuit from distorting and to keep the audio output at a constant level. A portion of the IF signals from the nd IF amplifier (Q) is detected at the AGC detector circuit (D) and is then applied to the AGC amplifier (Q) to control the AGC time constant line. The reference voltage of the AGC line is controlled by the RFG line which comes from the CPU for the RF gain setting. --0 SQUELCH CIRCUIT (MAIN UNIT) The transceiver has two squelch circuits, voice activated squelch for JE/HE and S-meter squelch for AA/FB/ JB. () AF ACTIVATED SQUELCH A portion of the AF signal from the active low-pass filter (IC0b) is amplified at the limiter amplifier (IC0a) and is then applied to the one-shot multi-vibrator (ICc, ICd). The one shot multi-vibrator functions as an F-V converter which generates a signal only when audio signals are received. When receiving a strong signal, the detected voltage increases and the voltage of the AGC line is decreased by the AGC amplifier (Q) via the V voltage line. The AGC line is used for the bias voltage of the IF amplifiers (Q, Q, Q, Q), so that these amplifiers reduce gain. When the strong signal disappears, the AGC line voltage is released by C/R and C0/R. The output signals pass through the NOR gate (ICb) and then the Hz low-pass filter (ICa) to remove the remaining noise components. The filtered signal is applied to the window comparator (ICb). The NOR gate (ICb) deactivates the audio activated squelch during AA/FB/JB mode operation. The AGC switch (Q, D) turns the AGC circuit OFF when the AGC OFF function activates. The AGC-fast switch (Q) sets the AGC line as fast-release during scanning, AA mode selection and DSC operation. nd IF filters AGC CIRCUIT HE derector st IF signal Q D Q AGC-fast control V AGC time constant line Q Q CW, DSC, SCAN Demodulator Q C0 C R C AGC amplifier RFG (RF gain control) 0 to V D AGC detector V Q - AGC OFF control Q

8 The comparator outputs High when the integrated signals exceed the reference voltage. C, R0 and R0 are used as a time constant circuit. The resulting signal output from ICa is inverted at Q and is then applied to the CPU as the SQLS signal. The CPU controls the squelch gate (ICa) when the SQLS signal is received. The SSB signal from FI is amplified at the MHz amplifiers (Q Q) and is then applied to the mixer circuit (D). The switching diode (D) is turned ON when R voltage disappears. () HE AND RE MODES An SSB signal is applied to the IF amplifier (Q) in the same manner as with JE/JB mode. The BFO signal from the PLL unit is amplified at the buffer amplifier (Q0) and is then applied to the IF amplifier (Q) as a carrier signal to be added to an SSB signal. R and R adjust the carrier levels in HE and RE modes, respectively. () S-METER SQUELCH The S-meter signal from ICb is applied to the squelch comparator (ICa) to close or open the squelch circuit. The reference voltage is adjusted by R and then applied to the ( ) terminal of the comparator (ICa). When the S-meter signal exceeds the reference voltage, the comparator outputs High to the CPU via ICa and Q in the same manner as the voice activated squelch circuit. () AA AND FB MODES The CW or FSK voltage are applied to the balanced modulator (IC, pin ) to upset the balance and create a carrier signal. In AA mode, the CW keying circuit (ICa) controls the bias voltage of the IF amplifiers (Q, Q) and T/R switching diode (D) to switch the carrier transmission. - TRANSMITTER CIRCUITS -- MICROPHONE LIFIER CIRCUIT (LOGIC BOARD) The AF signals from the [MICROPHONE] connector are pass through the AF amplifier (IC00a), and are applied to the balanced modulator (MAIN unit; IC, pin ) via the AF switch (ICb). The microphone AGC circuit (D00, D00, Q00) controls the amplifier gain to prevent signal distortion. In FB mode, BFO frequency is shifted in the PLL unit to create the mark and space frequencies. -- ST MIXER CIRCUIT (MAIN UNIT) The amplified signal from the IF amplifier (Q) is mixed with a 0 MHz LO signal at the st mixer circuit (D) to produce a.0 MHz IF signal. The mixer is commonly used with the receiver nd mixer. External modulation inputs from the ACC, NBDP, DSC sockets or a -tone emergency signal from the CPU are applied to the balanced modulator directly via AF switches (IC IC). The.0 MHz IF signal passes through the filter (FIb) and is then applied to the nd mixer circuit. -- MODULATION CIRCUIT (MAIN UNIT) () JE AND JB MODES The balanced modulator is used for JE and JB modes to add the audio signal to the BFO frequency, and outputs the IF signal while suppressing the BFO signal. -- ND MIXER CIRCUIT (MAIN UNIT) The filtered signal is mixed with a PLL output frequency (LO:..0 MHz) at the nd mixer circuit (Q, Q) to produce an RF signal which is the same frequency as the displayed one. The AF signals from the microphone amplifier or external audio from the modulation terminals are applied to the balanced modulator (IC, pin ). The BFO signal from the PLL unit is applied to (IC, pin 0) as a carrier signal. A double sideband signal is output from IC (pin ), and is then applied to the MHz filter (FI) to create an SSB signal. -- RF FILTER CIRCUIT (MAIN UNIT) The RF signal passes through the low-pass filter (L, L, C C, C0, C) and is then amplified at the RF amplifier (Q). R adjusts the balanced level of IC for maximum carrier suppression. In JB mode, the BFO frequency is shifted. khz to set the transmit frequency the same as the displayed frequency. The amplified signal is applied to one of nine RF filters. These RF filters are commonly used with the receiver circuit which consists of eight high-pass filters and one lowpass filter. The filtered signal is amplified at the RF amplifier (Q) and is then applied to the PA0W board via J. MODULATOR CIRCUIT Microphone IC00a -tone alarm ACC() socket NBDP socket DSC socket (GMDSS version only) ICb ICa ICa ICb ICb Balance upset duing CW, FSK, Modulator IC 0 FI Crystal filter D Q BFO from the PLL/PLLA unit (MHz) JE, RE, HE, JB:.0.0 AA:.0 (center) FSK:.00 (center) FSK narrow.0 JB narrow.0 During tuning - CW keying control (AA only) Q Q.0 MHz carrier (RE, HE only)

9 -- POWER LIFIER CIRCUIT (PA0W BOARD) -- ALC CIRCUIT The transceiver has two ALC (Auto Level Control) loops for constant output power over all marine bands and for high power setting. This circuit provides a stable 0 W (at. V) of output power. The RF signal from the MAIN unit is amplified at the pre-driver (Q00), drivers (Q00, Q00), and power amplifiers (Q00, Q00). () IF ALC CIRCUIT (MAIN UNIT) A portion of the IF signals from the IF amplifier (Q) is applied to the IF ALC circuit. The signal is amplified at Q and then detected at the ALC detector (D). The detected signal is amplified at the ALC amplifier (ICb) and is then applied to the comparator (ICa). The driver and power amplifiers form class AB push-pull circuits. Bias voltage to these transistors is produced by diodes (D00 D00) which have temperature junctions with the transistors. The reference voltage for the comparator is set by R. The antenna tuning control voltage (TUN) and low power set signal (POC) are also affected by the reference voltage to decrease the IF signal level. The amplified signal is then applied to one of eight lowpass filters to suppress high harmonic components. The filtered signal passes through the power detector circuit (FILTER board; L) and transmit/receive switching relay (FILTER board; RL) and is then applied to the antenna connector. The comparator output controls the gate bias of the IF amplifier (Q), so that the IF signal level is determined by the reference voltage of the comparator (ICa). LOW-PASS FILTERS USED (FILTER BOARD) Frequency Control Entrance Frequency Control Entrance Relay signal signal Relay (MHz) (MHz) 0.. L0 RL0 0. L RL. L RL0. L RL0.. L RL. L RL0 L RL0 L RL () RF ALC CIRCUIT (FILTER BOARD) The RF output power level is detected at D0 of the power detector circuit (FILTER board; L, D0, D0). The detected signal ( FOR signal) is applied to the RF ALC amplifier (MAIN unit; ICa). The amplified signal enters the transmit gain controller (ICb) which functions as an inversion amplifier. The gain controller decrease the gain of the IF amplifier (MAIN unit; Q) to constant output power from differential amplifier gains which are occurred by their frequency characteristics. The bias voltage of the RF ALC amplifier (ICa) is controlled by the low power control signal (POC for 0 W, POC for 0 W) and APC signal. ALC CIRCUIT Q D Q, Q Q Q Q00 Q00 Q00 Q00 Q00 L V FOR IF ALC CIRCUIT ICa D0 Q FILTER UNIT ICb Q High power set (R) Low power during tune (Q) 0 W low power set (Q) ICb ICa Current APC control (Q) Low power during tune (Q, Q) Current APC Q 0 W power set (Q) 0 W power set (Q) RF ALC CIRCUIT V - Q PA UNIT D0 MAIN UNIT

10 -- APC CIRCUIT - PLL CIRCUIT The APC (Auto Power Control) circuit protects the power amplifiers on the PA unit from high R and excessive current. -- GENERAL The PLL unit generates a st LO frequency (..0 MHz), nd LO frequency (0 MHz) and a BFO frequency (.00.0 MHz) for the MAIN unit. The st LO PLL adopts a mixerless dual loop PLL system. The BFO uses a DDS and a nd LO as a fixed frequency double that the crystal oscillator. () R APC (FILTER BOARD AND MAIN UNIT) The reflected wave signal appears and increases on the antenna connector. When the antenna is mismatched, D0 of the power detector circuit (FILTER board; D0, D0, L) detects the signal and applies it to the APC amplifier (MAIN unit; Q). The amplified signal decreases the bias voltage of the RF ALC amplifier to reduce the output power. -- ST LO PLL (PLL UNIT) The st LO PLL contains a main loop and reference loop as a dual loop system. The reference loop generates a 0. to 0. MHz frequency using a DDS circuit, and the main loop generates a. to.0 MHz frequency using the reference loop frequency. () CURRENT APC (PA0W BOARD AND MAIN UNIT) The power transistor current is detected from the different voltages between both terminals of a 0.0 Ω resistor (R0) on the PA0W board. The detected voltage is applied to the differential amplifier (IC00b). When the current of the final transistors is more than 0 A, the detected voltage is applied to the APC amplifier controller (MAIN unit; Q) to reduce the gate- voltage of the IF amplifier (MAIN unit; Q) and thus reduce the output power. () EREE LOOP PLL The oscillated signal at the reference VCO (Q00, D00) is amplified at the buffer amplifiers (Q00, Q0) and is then applied to the DDS IC (IC00, pin ). The signal is then divided and detected on phase with the DDS generated frequency. The detected signal output from IC00 (pin ) is converted into a DC voltage (lock voltage) at the loop filter (R0, R0, C0) and then fed back to the varactor diode (D00) in the VCO circuit. -- TEMPERATURE DETECTION (PA0W BOARD) Thermal switches (S00, S00) protect the final transistors from excessive temperatures. When the temperature of the final transistors exceeds 0 C ( F), S00 is turned ON to start the cooling fan. When the temperature of the final transistors exceeds 0 C (0 F), S00 is turned ON to control the POC line and sets the power to 0 W. () MAIN LOOP PLL The oscillated signal at the main loop VCO (Q00, D00) is amplified at the buffer amplifiers (Q00, Q00), and is then applied to the PLL IC (IC00, pin ). The signal is then divided and detected on phase with the reference loop output frequency. --0 RF METER CIRCUIT (MAIN UNIT) The detected signal output from IC00 (pins 00, 00) is converted into a DC voltage (lock voltage) at the loop filter and then fed back to the varactor diode (D00) in the VCO circuit. The output of the ALC amplifier (ICa) is applied to the CPU (pin ) to indicate the transmit power level on the display. For antenna current meter indication, the ANTC signal from an optional AT-0E is applied to the CPU (pin ). The oscillated signal is amplified at the buffer amplifiers (Q00, Q0, Q0) and then applied to the MAIN unit as a st LO signal. PLL CIRCUIT PLL IC (IC00) Main loop VCO Q00 Phase detector Programmable Programmable divider divider Q0 LO (..0 MHz) Loop filter Q00/D00 Q MHz Q00 DDS IC (IC00) Q0 Q00 Doubler LO (0.0 MHz) Loop filter Phase detector Reference loop VCO Q00/D00 Programmable divider Q0 Programmable divider DDS DDS IC00 D/A convertor D/A convertor Reference OSC (X00; 0.0 MHz) - BFO (.00.0 MHz)

11 - PORT ALLOCATIONS -- ND LO AND EREE OSCILLATOR CIRCUITS CPU (MAIN unit; IC) The reference oscillator (X00) generates 0.0 MHz frequency used for the both DDS ICs as a system clock and for the LO output. The oscillated signal is doubled at the driver (Q00) and picked up the 0 MHz frequency at the resonator circuit (L00, L00). The 0 MHz signal is applied to the MAIN unit as a nd LO signal. Pin number Port name Input port for the CPU reset signal. When receiving a LOW pulse, the CPU is reset. 0 RXDO Data input port from the sub CPU in the FRONT unit. TXDO Data output port to the sub CPU in the FRONT unit. NSEN Input port to the sub CPU in the FRONT unit. POC Outputs low power control signal for 0 W power. POC Outputs low power control signal for 0 W power. 0 CWIN Input port for the CW keying. High: When key is closed. ASEN Outputs a SEND control signal for the ACC () and ACC () sockets. CSEN Outputs a SEND control signal for T and R voltage line control. Low : For transmit. ALMS Outputs an alarm control signal to activate the -tone emergency alarm encoder. High : Alarm ON. ALMC Outputs a tone switching signal for the -tone emergency alarm encoder. High : High tone. SCL Outputs a clock signal for the EEPROM (IC). SDA Data bus line for the EEPROM (IC). SO Outputs a serial signal for the EEPROM (IC). SDA Data bus line for the EEPROM (IC). 0 RSM Input port for the S-meter indication. MFOR Input port for the RF-meter indication. ANTC Input port for the antenna current meter indication for [EUR] version. The ANTC signal can be received when an optional AT-0E is connected. SQLS Input port for the squelch detected signal. High : When squelch is open. TRC Input port for the transmit/receive switching signal. SCAS Input port for the scan control signal from the ACC () socket. RFG Outputs RF gain control signal to the AGC circuit. -- BFO CIRCUIT The DDS IC (IC00) generates a 0-bit digital signal using the 0 MHz system clock. The digital signal is converted to an analog wave signal at the D/A converter (R0 R). The analog wave is passed through the low-pass filter (L0, L0, C C), and is then applied to the MAIN unit as the BFO signal. The PA unit separate grounding from the other units to obtain floating. - Description

12 (MAIN unit; IC) Continued Pin number Port name Description AFG Outputs AF gain control signal to the control (IC). STAT Outputs the "tuner start" pulse to an optional AT-0E. 0 BEEP Outputs a BEEP signal ( khz or 00 Hz). STB Outputs a strobe signal to the main loop PLL IC (C00). STB Outputs a strobe signal to the reference loop DSS IC (IC00). STB Outputs a strobe signal to the BFO PLL IC (IC00). DATA Outputs a data signal to PLL and DDS ICs. 0 CK Outputs a clock signal to PLL and DDS ICs. SQL C Outputs an AF mute signal for squelch function. High : Squelch closed. NBS AGCS Outputs an AGC -OFF signal. High: AGC deactivate. NMS Outputs an external NBDP equipment control signal. Low: During NBDP data output. P0 Outputs a strobe signal for an initial matrix. 0 Outputs a noise blanker signal. High : Noise blanker is on P P Input ports for an initial matrix. PD PA Output band signals for RF LPF and BPF selection. JB, RE, Outputs mode signals. HE KEY Input port for an optional AT-0E. Low : During tuning. CW Outputs a mode signal. 0 TUNE Outputs an antenna tuner tuning control signal for transceiver s power/ mode control. FSEL Outputs a narrow filter selection signal. Low : Optional narrow filter selection. PROG Outputs a program scan control signal for AGC fast and audio squelch deactivation. -

13 SECTION ADJUSTMENT PROCEDURE - PREPARATION REQUIRED TEST EQUIPMENT GRADE AND RANGE EQUIPMENT DC power supply Output voltage Current capacity :. V DC : 0 A or more RF power meter (terminated type) Measuring range Frequency range Impedance R : 0 00 W :. 0 MHz : 0 Ω : Less than. : Frequency counter Frequency range Frequency accuracy Sensitivity : MHz : ± ppm or better : 00 mv or better RF voltmeter Frequency range Measuring range DC voltmeter Input impedance Spectram analyzer Frequency minimum : At least 0 MHz Spectraum bandwidth : 00 khz or more GRADE AND RANGE EQUIPMENT Frequency range Measuring range : Hz : 00 mv Frequency range Output level : 0. 0 MHz : 0. µv mv ( to dbm) Oscilloscope Frequency range Measuring range : DC 00 MHz : V AC millivoltmeter Measuring range : 0 mv 0 V : MHz : V External speaker Input impedance Capacity :Ω : W or more : 0 Ω/V DC or better Attenuator Power attenuation Capacity : 0 or 0 db : 0 W or more DC ammeter Measurement capability: A/ A/0 A Audio generator Standard signal generator (SSG) CONNECTION Attenuator 0 or 0 db to [EXT SP] AC millivoltmeter Spectrum analyzer RF power meter 00 W/0 Ω Speaker [MICROPHONE] connector (front view) Audio generator Standard signal generator Pin MICE Pin MIC [PTT] Connect pins and for AF output CAUTION: DO NOT connect the signal generator while transmitting. DC power supply to DC power receptacle. V/0 A [DC. V] [ANT] IC-M00PRO to [MICROPHONE] -

14 - PLL ADJUSTMENTS ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT UNIT EREE Display frequency LOOP LOCK Mode VOLTAGE Receiving :. MHz : JE Display frequency : MHz Display frequency Receiving : MHz Display frequency :. MHz MAIN LOOP LOCK VOLTAGE EREE Wait for min. after power ON. FREQUEY Terminate P00 to ground with a 0 ohms resister. Receiving VALUE UNIT ADJUST Connect a digital. V multimeter or oscilloscope to check point J00. More than. V PLL C0 PLL Connect a digital.0 V multimeter or oscilloscope to check point J00. More than.0 V PLL L0 PLL C o n n e c t a n R F Maximum level voltmeter to check (More than + dbm) point P00. PLL L00, L00 PLL LOCATION ADJUSTMENT POINT Connect a frequency MHz counter to check point P00. - Verify Verify L00

15 MAIN AND PLL UNITS C0 Reference loop lock voltage adjustment J00 Reference loop lock voltage check point P00 Reference frequency check point J00 Main loop lock voltage check point L00 L00 L00 L0 Main loop lock voltage adjustment - Reference frequency adjustment

16 - TRANSMITTER ADJUSTMENTS ADJUSTMENT MEASUREMENT ADJUSTMENT CONDITION UNIT IDLING CURRENT (For drive transistors) Display frequency :.00 MHz mode : JE Apply no audio signal to the [MICROPHONE] connector. Transmitting VALUE LOCATION UNIT ADJUST PA R0 U n s o l d e r R 0 00 ma and connect the DC ammeter ( A) to the unsoldered points. PA R0 C o n n e c t a D C 0 A ammeter (0 A) between the DC power supply and DC power receptacle (DC input +). PA R0 Audio generator Output level FILTER C MAIN Adjust in sequence L, L, L, L, L Cut the lead wire 00 ma (W0) and connect a DC ammeter ( A) to the cut points. PA ADJUSTMENT POINT After adjustment, re-solder the lead wire (W0). (For final transistors) Display frequency :.00 MHz mode : JE Apply no audio signal to the [MICROPHONE] connector. Transmitting PA After adjustment, re-solder R0. IC APC Display frequency :.0000 MHz Mode : JE Preset R0 on the PA unit to the maximum counterclockwise position. Connect a dummy load (0 A) between lead of R0 (power line) and EP00 (power ground) on the PA unit. Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Level : 00 mv rms Connect an RF power meter to the [ANT] connector. Transmitting Rear Panel After adjustment, remove the dummy load. R DETECTOR TRANSMIT PEAK Rear Display frequency :.0000 MHz Panel Mode : JE Ground the lead of R on the MAIN unit with a wire. Connect an audio generator to the MAIN [MICROPHONE] connector and set as: Frequency :. khz Transmitting After adjustment, remove the wire from R. Display frequency :.00 MHz Mode : JE Ground the lead of R on the MAIN unit with a wire. Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Level : mv Transmitting Rear Panel C o n n e c t a n R F 0 W power meter to the [ANT] connector. C o n n e c t a D C Minimum level voltmeter to R0. C o n n e c t a n R F Maximum output power power meter to the [ANT] connector. After adjustment, remove the wire from R. -

17 PA AND FILTER BOARDS IC APC check point Ammeter DC power supply R0 Idling current (for drive transistors) adjustment R0 Idling current (for final transistors) adjustment W0 Idling current (for drive transistors) check point Ammeter EP00 EP00 W0 Cut C R detector R0 Idling current adjustment (for final transistors) check point Ammeter IC APC preparation R0 EP00 EP00 0 A dummy load Unsolder R0 R0 IC APC adjustment MAIN UNIT R0 R detector check point R R detector transmit peak preparation L L Transmit peak L adjustment L L -

18 TRANSMITTER ADJUSTMENTS (continued) ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT UNIT TRANSMIT GAIN OUTPUT POWER VALUE LOCATION Display frequency :.00 MHz mode : AA Transmitting Rear Panel C o n n e c t a n R F 0 W power meter to the [ANT] connector. Display frequency :.0 MHz Transmitting MAIN Connect a digital 0. V multimeter to R. Display frequency :.00 MHz Mode : HE Apply no audio signal to the [MICROPHONE] connector. Transmitting Rear Panel C o n n e c t a n R F W power meter to the [ANT] connector. ADJUSTMENT POINT UNIT ADJUST MAIN R R MAIN R Mode Transmitting : RE.0 W R Mode Transmitting : AA 0 W R CARRIER Display frequency :.00 MHz SUPPSION Mode : JE Apply no audio signal to the [MICROPHONE] connector. Transmitting Rear Panel Connect a spectrum Minimum carrier level a n a l y z e r o r R F (Less than 0 db) voltmeter to the [ANT] connector via an attenuator. MAIN Adjust alternately R, R TUNE POWER Display frequency :.00 MHz Ground the lead of L0 (KEY line) on the MAIN unit with a wire. Transmitting Rear Panel C o n n e c t a n R F 0 W power meter to the [ANT] connector. MAIN R0 POWER METER While pushing the [SQL] and [ENT] switches, turn power ON. Display frequency :.00 MHz Mode : JE Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Level : 00 mv Set the transmit power: [PO-] (0 W PEP) Transmitting Rear Panel C o n n e c t a n R F W power meter to the [ANT] connector. Audio generator Output level Font Panel [DIMMER] MIC LIMITTER Display frequency :.00 MHz Mode : JE Disconnect BFO plug (J) on the MAIN unit. Connect an audio generator to the [MICROPHONE] connector and set as: Frequency :. khz Level : 0 mv Transmitting MAIN C o n n e c t a n 0 mv oscilloscope to R. LOGIC R00 MIC GAIN Display frequency Mode Connect an audio [MICROPHONE] set as: Frequency Level Transmitting Rear Panel C o n n e c t a n R F 00 W power meter to the [ANT] connector. LOGIC R0 :.00 MHz : JE generator to the connector and Push the [DIMMER] switch. :. khz : 0 mv - PEP

19 MAIN UNIT AND LOGIC BOARD L0 Tune power R preparation Transmit gain check point Transmit R gain adjustment R R0 Tune power adjustment R R R Output power adjustment R R Carrier suppression adjustment R0 Mic gain adjustment R00 Mic limitter adjustment -

20 - RECEIVER ADJUSTMENTS ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT UNIT ADJUSTMENT POINT VALUE LOCATION RECEIVER GAIN CLARITY While pushing the [SQL] and [CL] Set the [CLARITY] control to the center position and push the [DIMMER] switch. switches, turn power ON. TOTAL GAIN Display frequency :.00 MHz Mode : JE Connect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level : 0. mv ( dbm) modulation : OFF Receiving S-METER NOISE BLANKER Display frequency Mode Noise blanker Squelch Speaker AGC RF gain R (MAIN unit) R (MAIN unit) :.0 MHz : JE : OFF : OFF : OFF : ON : : Max. clockwise : Max.counter clockwise R00 (MAIN unit) : Center Connect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level : 0. µv ( dbm) modulation : OFF Receiving Rear Panel Rear Panel C o n n e c t a n A C Muximum output level millivoltmeter to the [EXT SP] jack with a dummy load. C o n n e c t a n A C.0 V millivoltmeter to the [EXT SP] jack with a ohms dummy load. UNIT ADJUST MAIN Adjust in sequence L, L, L, L, L, L, L, L, L Front Panel [CLARITY] Front Panel [VOLUME] Set the signal generator to OFF (no output). 0 db ( mv) MAIN R While pushing the [SQL] and [T Function S/RF meter display ONLY] switchs, turn power ON. Display frequency :.00 MHz Mode : JE Connect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level : mv ( dbm) Receiving Push the [DIMMER] switch. Font Panel [DIMMER] Display frequency :.00 MHz Mode : JE Connect a standard signal generator to the [ANT] connector and set as: Frequency :. MHz Level :. µv ( dbm) Add the following signal into the signal generator output. MAIN Verify th dot just appears while pushing the [DIMMER]. C o n n e c t a n Adjust the maximum oscilloscope to R. noise wave displayed on the oscilloscope. 00 msec. msec. Receiving This output level of the standard signal generator (SSG) is indicated as SSG s open circuit. - MAIN L0, L

21 SECTION PARTS LIST [FRONT UNIT] S0 [LOGIC-J UNIT] 000 JPZ0-00F SP SP FG0-0 (-) W0 W0 W0 W0 W OPC-A (P.,N,L00) <TJM> OPC-A (P.,N,L00) <TJM> OPC- (N:0 L:0) OPC-A (P.,N,L00) <TJM> OPC-A (P.,N,L00) <TJM> CBL CBL CBL CBL CBL [LOGIC-J UNIT] IC00 IC00 IC00 IC00 IC00 IC00 IC IC HDAFV (SX-SA) HD00F S-0CLUA-B-TG upcl0t-e-az upcl0t-e-az TAAP NJMM-TE Q00 Q00 Q00 Q00 Q00 Q00 Q00 Q0 Q0 Q TR SC-TB-A-L SB0-Y SC-TB-A-L SC-TB-A-L DTCEKA T DTCEKA T SC-TB-A-L DTCEKA T DTCEKA T DTCEKA T D00 D00 D00 D00 D00 D00 D00 D00 D00 D S.ZEN SS (TER,F) RD.M-TB-A B SS (TER,F) SS (TER,F) SS (TER,F) SS (TER,F) SS (TER,F) SS (TER,F) SS (TER,F) SS (TER,F) X XTL CR- (.0 MHz) L00 L00 L00 L00 L00 L00 L00 L00 L S. S. S. S. S. BL0RNADB (BL0RN-A) BL0RNADB (BL0RN-A) NLVT-0J BL0RNADB (BL0RN-A) NLVT-0J NLVT-0J NLVT-0J NLVT-0J LW- R00 R00 R00 R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R MCR0EZHJ k MCR0EZHJ. k MCR0EZHJ. k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ M MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ 00 k MCR0EZHJ k MCR0EZHJ 0 k MCR0EZHJ 0 k MCR0EZHJ 0 k MCR0EZHJ 00 k MCR0EZHJ JPW (000) MCR0EZHJ k MCR0EZHJ k MCR0EZHJ. k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ 0 k MCR0EZHJ 0 k MCR0EZHJ 0 k MCR0EZHJ. k MCR0EZHJ k MCR0EZHJ k PSD/V MCR0EZHJ 0 k MCR0EZHJ (00) MCR0EZHJ k [GEN-] only R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R00 R0 R0 R0 R0 R0 R0 R0 R0 R TRI TRI PSD/V. MCR0EZHJ 00 (0) MCR0EZHJ. k MCR0EZHJ 0 () MCR0EZHJ k MCR0EZHJ 00 k KVSFAC 0 0 k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k KVSFAC 0 00 k MCR0EZHJ. k MCR0EZHJ 0 () MCR0EZHJ 0 () MCR0EZHJ k MCR0EZHJ 0 k MCR0EZHJ k MCR0EZHJ 0 k MCR0EZHJ k MCR0EZHJ 0 k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ k MCR0EZHJ (0) C00 C00 C00 C00 C00 C00 C00 C00 C0 C0 C0 C0 C0 C0 C0 C0 C00 C0 C0 C0 C0 C0 C0 C0 C0 C0 C00 C0 C0 C0 C0 C0 C0 C0 C0 C0 C00 C0 C0 C0 C0 C0 C00 C MLR MLR C0 JB H K-T C0 JB H K-T C0 JB H K-T C0 CH H 0J-T C0 CH H 0J-T C0 JB H 0K-T 0 FD J C0 JB H 0K-T 0 ME 0 HC C0 JB H K-T C0 JB H K-T C0 JB H K-T C0 JB H K-T C0 JB H K-T C0 JB H K-T C0 JB H K-T ME 000 HC C0 JB H K-T ME 0 CA C0 JB C 0K-T ME HC ME 00 HC ME HC C0 JB H K-T ME HC ME HC C0 JB H K-T 0 ME R HC 0 ME HC 0 ME HC ME R HC ME R HC ME HC ME R HC ME 0 HC C0 JB H K-T ME HC C0 JB H K-T ME HC C0 JB H K-T ME 0 HC C0 JB C 0K-T C0 JB C 0K-T 0 FD 0J RL RLY AG 0 J00 J00 J00 J00 J0 J0 J0 J B0B-EH-S (LF) (SN) 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N 0FE-BT-VK-N RTB-.-F (LF) RTB-.-F (LF) DS00 DS00 DS00 DS LMP LMP LMP LCD HRT-0A-F-PF G0 HRT-0A-F-PF G0 HRT-0A-F-PF G0 DLC-00P S00 S00 S00 S (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) [GEN-] only [GEN-] only [GEN-] only [GEN-] only [GEN-] only S.=Surface mount -

22 [LOGIC-J UNIT] [MAIN UNIT] S00 S00 S00 S00 S0 S0 S0 S0 S0 S0 S0 S0 S0 S00 S0 S0 S0 S0 S0 S0 S (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) - (SKHHPM) W0 W0 W0 W0 W0 W MCR0EZHJ JPW (000) MCR0EZHJ JPW (000) MCR0EZHJ JPW (000) MCR0EZHJ JPW (000) MCR0EZHJ JPW (000) J/ZC EP TUB IRRAX 0. (d) L=0 mm [MAIN UNIT] IC IC IC IC IC IC0 IC IC IC IC IC IC IC0 IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC IC TDAFG (S,EL) TDAFG (S,EL) TDAFG (S,EL) LA0N-E NJMV-TE NJMV-TE BU0BF-E TCWF (TEL,F) NJMM-TE NJMM-TE NJMM-TE NJMM-TE NJMM-TE NJMM-TE BU00BF-E upcg-e-a TA0F (TEL,Q) TLP (GB-TPL,F) CD0BNSR TCSF (TER,F) TCSF (TER,F) BU0UBF-E CD0BNSR MFP 0CD TCWF (TEL,F) TCWF (TEL,F) TAL0F (TER,F) HDBFV (SX-0) HDBFV (SX-0A) S-0CLUA-B-TG LCBT-I/SNG LCBT-I/SNG Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q0 Q S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET S.FET SCD-TD-E SK-T MAS SK-T MAS SK-T MAS SCD-TD-E SK--TD-E SK--TD-E SK-T MAS SK0-GR (TER,F) SA-GR (TER,F) SC-GR (TER,F) SC-GR (TER,F) SC-GR (TER,F) DTAEUA T0 DTCEUA T0 SK-T MAS SDT-TD-E SC-GR (TER,F) SK-T MAS DTCEUA T0 DTCEUA T0 DTCEUA T0 SC-GR (TER,F) DTCEUA T0 DTCEUA T0 SA-GR (TER,F) SC-GR (TER,F) DTCEUA T0 SC-GR (TER,F) SC-B (TER,F) [CHN] only [GEN-] only Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q0 Q Q Q Q Q Q0 Q Q Q Q0 Q0 Q0 Q0 Q0 Q Q Q Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q0 Q S.FET S.FET S.FET SK-T MAS SK-T MAS SC-GR (TER,F) DTCEUA T0 DTAEUA T0 DTCEUA T0 SC-B (TER,F) DTCEUA T0 DTCEUA T0 DTAEUA T0 SC-GR (TER,F) DTCEUA T0 SC-GR (TER,F) SDT-TD-E DTCEUA T0 DTCEUA T0 SC-GR (TER,F) SCS-TD-E SC-GR (TER,F) SC-GR (TER,F) SDT-TD-E SDT-TD-E SC-GR (TER,F) DTCEUA T0 DTCEUA T0 SC-GR (TER,F) DTAEUA T0 DTCEUA T0 DTAEUA T0 SC-GR (TER,F) DTCEUA T0 DTCEUA T0 SC-GR (TER,F) DTCEUA T0 DTCEUA T0 SA-GR (TER,F) DTCEUA T0 SC-GR (TER,F) SC-GR (TER,F) SA-GR (TER,F) SA-GR (TER,F) SC-GR (TER,F) SC-GR (TER,F) DTCEUA T0 SC-GR (TER,F) DTCEUA T0 DTCEUA T0 DTCEUA T0 DTCEUA T0 SK0-GR (TER,F) SC-GR (TER,F) DTCEUA T0 DTAEUA T0 SC-GR (TER,F) DTCEUA T0 DTAEUA T0 SC-GR (TER,F) SDT-TD-E SC-GR (TER,F) DTCEUA T0 DTCEUA T0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D0 D D D D D D D D D D0 D D DIO ZEN MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) HSMASRTR-E MA (TX) L0BBB SS0 (TER,F) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) MA (TX) SS0 (TER,F) SS0 (TER,F) MA (TX) HSMASRTR-E DANTL MA (TX) DANTL SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) RD.E-AZ B HSMASRTR-E SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) S.=Surface mount -

23 [MAIN UNIT] [MAIN UNIT] D D D D D D D0 D D D D0 D D D D D D D D0 D D D D D D D D0 D D D D00 D0 D0 D0 D0 D0 D D D D D D D D0 D D D D D D D D0 D D D D D D ZEN ZEN DIO ZEN ZEN S.ZEN DIO SS0 (TER,F) SS0 (TER,F) HSMASRTR-E SS0 (TER,F) SS0 (TER,F) MA (TX) DANTL MA (TX) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) RD.E-AZ B RD.E-AZ B SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) HSMASRTR-E SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) MA (TX) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) RDE-AZ B SS0 (TER,F) SS0 (TER,F) RDE-AZ B SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) SS0 (TER,F) L0 (0) L0 (0) MAS-(TX) MAS-(TX) MA0-M (TX) SS FI FI FI FI FIL FIL FIL FIL MB (FL-0) MD (FL-0) M A (FL-) M A (FL-) X 0000 S.XTL MA-0 (.0 MHz-F) L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L LR- LAL 0NA 0K NLVT-RJ NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J NLVT-R0J NLVT-R0J NLVT-R0J NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. L L L0 L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L00 L0 L0 L0 L0 L0 L0 L0 L0 L L L L L L0 L L L L L L L L L0 L L L L L L L L L L0 L L L L L L L L S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. S. NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-0J NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ LAL 0NA K LR- (RIBX.X A) LAL 0NA K NLVT-0J NLVT-R0J NLVT-RJ NLVT-0J LR-0 (TRXX A) LS-A (C-) LR- NLVT-00J NLVT-RJ NLVT-RJ LS-B (C-) LS-B (C-) LR- (RIBX.X A) LR- (RIBX.X A) NLVT-RJ NLVT-RJ NLVT-RJ NLVT-RJ LR- LS-A (C-) LS- LA- NLVT-00J LS-B (C-) LS-A (C-) LS- LS- NLVT-0J LS-A (C-0) LS-A (C-) LS-A (C-) NLVT-00J LR- LF LS- LS- NLVT-0J NLVT-0J LS-0 (C-) LS-A (C-) EXC-ELDRC LAL 0NA 0K LAL 0NA 0K NLVT-RJ EXC-ELDRC EXC-ELDRC EXC-ELDRC EXC-ELDRC - - LAL 0NA K LAL 0NA K NLVT-0J NLVT-0J LAL 0NA K LAL 0NA K LAL 0NA K LAL 0NA K LAL 0NA K LAL 0NA K NLVT-RJ NLVT-RJ NLVT-0J LAL 0NA 0K NLVT-0J LAL 0NA 0K LAL 0NA 0K LAL 0NA 0K NLVT-0J EXC-ELDRC EXC-ELDRC EXC-ELDRC EXC-ELDRC NLVT-R0J EXC-ELDRC NLVT-00J NLVT-0J EXC-ELDRC LAL 0NA 0K EXC-ELDRC NLVT-0J NLVT-0J NLVT-0J NLVT-0J NLVT-0J R R R R ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ 00 V (0) ERJGEYJ V (. k) S.=Surface mount -

24 [MAIN UNIT] R R R0 R R R R R R R R R R0 R R R R R R R R R R R R R R R R R R R R R R0 R R R R R R R R R0 R R R R R R R R R0 R R R R R R R R0 R R R R R R R R R R0 R R R R R R00 R0 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R0 R R R R R R R R R [MAIN UNIT] I TMR ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ 0 V ( k) ERJGEYJ 0 V ( k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ 0 V (0 k) RH0ADCSX (0) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (. k) ERJGEYJ V ( k) ERJGEYJ 0 V ( k) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V () ERJGEYJ V (. k) ERJGEYJ 00 V (0) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00 k) ERJGEYJ V ( k) ERJGEYJ V ( k) ERJGEYJ 0 V (00) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V (0 k) ERJGEYJ V ( k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ V ( k) ERJGEYJ 0 V () ERJGEYJ 00 V (0) ERJGEYJ V (. k) ERJGEYJ 0 V () ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V ( k) ERJGEYJ 0 V () ERJGEYJ V ( k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V ( M) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ 0 V ( k) ERJGEYJ V ( k) ERJGEYJ V ( k) ERJGEYJ V (0 k) ERT-DZGL 0S ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ 0 V ( k) ERJGEYJ V ( k) ERJGEYJ 0 V (00) ERJGEYJ 0 V ( k) ERJGEYJ V (0) ERJGEYJ 0 V (0 k) ERJGEYJ V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V (00) ERJGEYJ V (0) ERJGEYJ 0 V (00 k) ERJGEYJ 0 V (00 k) ERJGEYJ V (0 k) ERJGEYJ V (. k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ 0 V (00) R0 R R R R R R R R0 R R R R R R R R R R R R R R0 R R R R R R R R R R R R R R0 R R R R R R R R R00 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R R0 R R R R R R R R R R R R R R R R R R R R I TRI I I TMR I I TRI ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ 0 V (00) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (00 k) ERJGEYJ V ( k) ERJGEYJ 0 V (00 k) ERJGEYJ V ( k) ERJGEYJ 00 V (0) ERJGEYJ V ( k) ERJGEYJ 0 V (0 k) ERJGEYJ V (. M) ERJGEYJ 0 V ( M) ERJGEYJ V (. M) ERJGEYJ V (0 k) ERJGEYJ V (0 k) ERJGEYJ 0 V (00 k) ERJGEYJ V (0) ERJGEYJ V (0 k) ERJGEYJ V (0 k) ERJGEYJ 0 V (0 k) ERJGEYJ V ( k) ERJGEYJ 0 V (00) ERJGEYJ V ( k) ERJGEYJ 0 V ( k) ERJGEYJ V ( k) ERJGEYJ 0 V (00 k) ERJGEYJ V ( k) RH0ADCX (0 k) ERJGEYJ V (. k) ERJGEYJ 0 V (00 k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V (0 k) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ 0 V (00 k) ERJGEYJ V (. k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (0 k) ERJGEYJ 0 V (0 k) ERJGEYJ V (0) ERJGEYJ V ( k) ERJGEYJ V (. k) RH0CJA (0) ERJGEYJ 0 V (00) ERJGEYJ V (. k) ERJGEYJ V ( k) ERJGEYJ V (0) RH0ADCSX (0) RH0ADCX (00) ERT-DZGL S ERJGEYJ 0 V (0 k) ERJGEYJ 0 V ( k) ERJGEYJ V (. k) ERJGEYJ 0 V (0 k) ERJGEYJ V ( k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) RH0ADCSX (. k) ERJGEYJ V ( k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ 0 V (00) ERJGEYJ 0 V (00) ERJGEYJ V (0) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ V (. k) ERJGEYJ 0 V (0 k) ERJGEYJ R0 V () ERJGEYJ V (. k) ERJGEYJ V (0) RH0ADCNX (. k) ERJGEYJ V (0) ERJGEYJ V (0) ERJGEYJ V ( k) ERJGEYJ V ( k) PSD/ 0 ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ 0 V (00 k) ERJGEYJ V (. k) ERJGEYJ V (0) ERJGEYJ V (. k) ERJGEYJ 0 V (00) RH0CJA (0) ERJGEYJ V ( k) ERJGEYJ V (. M) ERJGEYJ V (. M) ERJGEYJ 0 V ( M) ERJGEYJ 0 V ( M) ERJGEYJ V (0) ERJGEYJ V (0 k) ERJGEYJ V ( k) ERJGEYJ 0 V ( M) [GEN-] only [GEN-] only S.=Surface mount -