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1 Faculty of Engineering Benha university Electrical EngDept Dr Hossam Labibb Zayed Microelectronics (E302) Final-Term Exam (June 203) Data: 2/5/203 Time: 3 Hours Answer the following questions: Q: Complete the following sentences: i The family of FET transistors may be divided into: and ii The MOSFET has a physical channel between the drain and source iii The high input resistance of a JFET is due to iv The non-inverting configuration has a gain greater than or equally v The detectors can be used to produce a square wave from a sine wave vi The feedback element in an integrator is vii The bandwidth of the ideal op amp is approximately equal to viii The input stage of every op amp is amplifier ix When same signals are applied to the inputs of a differential amplifier it knownn as x The input differential resistancee of BJT differential amplifier is equal to xi is a measure of a differential amplifier s ability to reject common mode signal Q2: (a) the NMOS transistors in the circuit of Fig () have t =, μ n C ox = 20 μa/ 2, λ = 0, and L =L 2 = L3 = μm Find the required values of gate width for each of Q, Q 2, and Q 3 to obtain the voltages and current values indicated (b) Find the input resistance of the circuit shown in Fig(2) Assuming ideal op amp, R = 0 kω, R 2 = 000 kω, and R 3 = 5 kω Q3: A common gate amplifier using an n-channel E-MOS transistor for whichh g m m=5ma/, shown in Fig(3), has R D =5KΩ, and R L =2 KΩ The amplifier is driven by voltage source having a 200ΩΩ resistance What are the input resistance and the overall voltage gain of the amplifier? f the circuits allow a bias current increase by a factor of 4 while maintaining linear operation, what do the input resistance and voltage gain become? Q4: The two op amps in the circuit shown in fig(4) are ideal Find v o,i x and i o o Q5: Find the overall voltage gain v o /v s and the differential input resistance of the amplifier shown in fig (5) Assuming β = 00 PTO Page / /2

2 Fig(2) Fig () Fig(4) Fig(3) Fig(5) BEST WSHESS Hossam Labibb Page 2/2

3 Faculty of Engineering Benha university Electrical EngDept Dr Hossam Labibb Zayed Microelectronics (E302) Final-Term Exam (June 203) Data: 2/5/203 Time: 3 Hours Model Answer ii Q: Complete the following sentences: i The family of FET transistors may be divided into: Junction FET (JFET) and Metal- Oxide-Semiconductor FET (MOSFET) The depletion MOSFET has a physical channel between the drain and source iii The high input resistance of a JFET is due to the reverse-biased or equally one gate source junction iv The non-inverting configuration has a gain greater than v The zero crossing detectors can be used to produce a square wave from a sine wave vi vii viii The feedback element in an integrator is a capacitor The bandwidth of the ideal op amp is approximately equal to The input stage of every op amp is a differential amplifier ix When same signals are applied to the inputs of a differential amplifier it known as common mode signal x The input (+ +β)2r e differential resistance of BJT differential amplifier is equal to xi CMRR is a signal measure of a differential amplifier s ability to reject common mode Page

4 > Q =s v t i DJ" DJ /0&7, /-3_ Q2: (a) the NMOS transistors in the circuit of Fig () have H,' =»HnC<>x=20 HA/2, K = 0, and L =L2= L3 = mm Find the required values of gate Width for each of Q] Q2 and if 20 HA Q3 to obtain the voltages and current values indicated E: Q ---~+w0 4 Kb XQL: Z0 +[ 5y _~?_,:*_; f Q: EQW Q >_, -/'*'/ /?-,= Q Q9 ' b xi 2? i(>s (,,- 45' = T Q55 ; ld»- 5 ==' M6 xi /<>>$J,<, ~t= -"5 = '5J f057 <> Qt M 6* E -XD = ]< _; CiS Hl7- JJKX/l O a4>" "'< 2 2 Q os,- H-) L<>~ 5) KL <_,,)>M,,Xt,J : 7W =z ' T J"v(a é Q W 7, ' X Z u_m M % gown CQ Z<> H9 3 j"" wt: 3; r '2 ]C7dL: ]G -5~,,=3»-~ D, 5 -- W5 -- "Lg D5'7 - i'>'z_"i 7':'3') w M_: 55 2 Q65? - qt _ w ~= ukufbii >-A ' ~» lr>, t Q Q lh K Km L<»;~A, xzn a~n~ ' *"" 'f7' U3 e w Li<=- L : L /<2 ' bé{ l ~_ 2 MM :» z: :'l06 EQTQ -5 ~(, -do =5 v3): 3 '9,3 _ '/ <;/J/L)» )<; _~, -r J:= -5-'> -<- i '>>3 :3 El-E Q3 Z<=) # Q8, y'p~ 2' K6, _,'9_2_-f" L : ---<-) T-5'_: L: kj6>3-vi) i ) $~/ 3=-um:-'%J

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6 '3 i Q3: A common gate amplier using an n- i oz: channel E-MOS transistor for which gm=5ma/, shown in Fig, has RDSKQ, RH Q: and RL=2 KQ The amplier is driven by W l~~<>_~»--~t~ voltage source having a ZOOQ resistance What are the input resistance and the pk f h f > overall voltage gain o t e amp i ier %, _ _ the circuits allow a bias current increase by a factor of 4 while maintaining linear operation, what do the input resistance 2" f ' * - and voltage gain become? Rm Solution: +4 on O6,_: Rs) :»~::l'f l % i 0 Ru '2 at EX», = 5 Kgil ",,,,,, - '= "- 5' * ';» 7 Q» C ~ E - ~ *<t>~» - /l l Cr» "W",, '', t )r S C Q,/ Q/~C4 OK $QJ/("3 ~Q,/*5 ;,_l)_q ->t_c_ To _c - ~/U X ii L ~L La -$ 5 2 K,_,_,_ A ES J 7- ~= L j, 4P~4" ' _ so 7 v / xv ii, "2 _ i_- L,_ / 6 A r» /v K;l/Ru) ' U9 5 Kiizmn _ Mp okgwag R5 A, i,/3 + /55& 3» "g,(z_s,: "" /lg Q/,_ :,_~ 8% J5, L/ - 0 w '2 -*,~ ~-~--_;i ~ R c~>,q?_, ) /it//q <=* M»» K =55»-,/4 : _ -_/<» 9),»z 32 t_t_,l_i_,,,,,,,_m -l< t _* wt we -_A,l»~<} g5; / l~'r' ~, ~?> + 2 ~;

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