Πειραματική υλοποίηση ευρυζωνικών ολοκληρωμένων οπτικών κελιών

ΑΡΙΣΤΟΤΕΛΕΙΟ ΠΑΝΕΠΙΣΤΗΜΙΟ ΘΕΣΣΑΛΟΝΙΚΗΣ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΤΜΗΜΑ ΠΛΗΡΟΦΟΡΙΚΗΣ Πειραματική υλοποίηση ευρυζωνικών ολοκληρωμένων οπτικών κελιών Experimental implementation of broadband alloptical integrated memory cells Διπλωματική Εργασία Χρήστος Παππάς, ΑΕΜ: 47 Επιβλέπων καθηγητής: Πλέρος Νικόλαος, Αναπληρωτής καθηγητής Α.Π.Θ. Θεσσαλονίκη, Φεβρουάριος 2021

ΠΕΡΙΛΗΨΗ Περίληψη Τα ηλεκτρονικά κυκλώματα ήταν μέχρι πρότινος η κύρια τεχνολογία που χρησιμοποιούνταν για την υλοποίηση μνημών, επεξεργαστών και της μεταξύ τους επικοινωνίας. Τα τελευταία χρόνια όμως έχει δημιουργηθεί συμφόρηση μεταξύ επεξεργαστή και μνήμης λόγω της άνισης εξέλιξης αυτών, πρόβλημα γνωστό και ως «Τείχος Μνήμης». Στην παρούσα πτυχιακή παρουσιάζονται κάποιες σύγχρονες τεχνολογίες υλοποίησης των ηλεκτρονικών βασικών μονάδων για μνήμες τυχαίας προσπέλασης και για πίνακες αναζήτησης διευθύνσεων, όπως και οπτικές υλοποιήσεις αυτών. Επίσης, παρουσιάζονται δύο καινοτόμες υλοποιήσεις αμιγών οπτικών ολοκληρωμένων κελιών μνήμης οι οποίες είναι βασικά δομικά στοιχεία για την επέκταση σε οπτικές μνήμες τυχαίας προσπέλασης και πίνακες αναζήτησης. Η πρώτη αρχιτεκτονική που μελετάται, αφορά μια μνήμη κυματοδηγού «waveguide memory» η οποία χρησιμοποιεί δύο μεταγωγείς, βασισμένους σε ημιαγώγιμους οπτικούς ενισχυτές (SOA), σε μια «σταυρωτή» διασύνδεση. Τα πειραματικά αποτελέσματα έδειξαν μια σωστή λειτουργία μνήμης στα 5Gb/s. Η δεύτερη αρχιτεκτονική αφορά τον ευρυζωνικό χαρακτηρισμό κελιού μνήμης για χρήση σε συστοιχίες μνημών. Στα πειραματικά αποτελέσματα αποδείχθηκε η λειτουργεία στα 5Gb/s σε ένα εύρος ζώνης ίσο με περίπου 26 nm, ενώ παρατηρήθηκε απόδοση μηδενικών σφαλμάτων στη διάδοση σημάτων, με μέγιστη ποινή ισχύος 4.4dB σε 49 διαφορετικές μετρήσεις. Η παρούσα εργασία απαρτίζεται από 5 κεφάλαια. Το κεφάλαιο 1 αποτελεί μια εισαγωγή στο αντικείμενο της εργασίας και αναλύονται οι κατηγορίες οπτικών μνημών καθώς και οι τεχνολογίες αποθήκευσης βάσει του φωτός. Στο κεφάλαιο 2 περιγράφονται οι πιο σύγχρονες τεχνολογίες υλοποίησης οπτικών μνημών. Στα κεφάλαια 3 και 4 παρουσιάζονται τα πειραματικά αποτελέσματα για τις δύο υλοποιήσεις οπτικών κελιών μνήμης. Τέλος, στο κεφάλαιο 5 εξάγονται τα συμπεράσματα λαμβάνοντας υπόψιν τα πειραματικά αποτελέσματα και αναφέρονται πιθανές μελλοντικές ερευνητικές δραστηριότητες. Λέξεις Κλειδιά: Μνήμες τυχαίας προσπέλασης, Πίνακες αναζήτησης διευθύνσεων, Οπτικές μνήμες, Μνήμηκυματοδηγού, Ευρυζωνική λειτουργεία ii

ABSTRACT Abstract Electronic circuits have been the main technology to realize all necessary technologies required for computing, including memories, processors and the memory-processor interconnection. In recent years, a bottleneck between memories and processors has been created that is commonly referred to as Memory Wall. This thesis presents the state-of-theart electronic memory in its applications as random-access memories and address look-up tables. Moreover, two different all-optical integrated memory cell implementations are presented as a basic building block for optical random-access memories and address look-up tables. The first architecture refers to a waveguide memory consisting of two SOA-based switches in cross-coupled configuration. Experimental results reveal a successful an operation at 5Gb/s. The second architecture is experimentally evaluated as a broadband device for RAM Banks. Experimental results validate its operation at 5Gb/s with error free performance for all 49 different wavelength-pairs extending along a spectrum of 26 nm, with a max power penalty 4.4dB. The thesis is divided into 5 chapters. Chapter 1 is an introduction to the topic of the thesis and the optical memory categories are analyzed, along with light-storage technologies. Chapter 2 describes the state-of-the-art optical memory architectures. In chapters 3 and 4, the experimental results are presented, for both optical memory implementations. Finally, chapter 5 concludes the work based on the experimental results and proposes possible future research work. Key Words: Random access memories, Address look-up tables, Optical memories, Waveguide memory, Broadband operation iii

iv ABSTRACT

ΕΥΧΑΡΙΣΤΙΕΣ Ευχαριστίες Η παρούσα διπλωματική εργασία με θέμα «Πειραματική υλοποίηση ευρυζωνικών ολοκληρωμένων οπτικών κελιών μνήμης» πραγματοποιήθηκε στο πλαίσιο των μεταπτυχιακών μου σπουδών στο τμήμα Πληροφορική της Σχολής Θετικών Επιστημών του Αριστοτελείου Πανεπιστημίου Θεσσαλονίκης με τίτλο «Δίκτυα Επικοινωνιών και Ασφάλεια Συστημάτων», στην κατεύθυνση «Δίκτυα Επικοινωνιών» κατά το έτος 2021. Ήταν το πιο ενδιαφέρον κομμάτι των σπουδών μου, καθώς αποτέλεσε μια ευκαιρία να ασχοληθώ με ένα πολλά υποσχόμενο ερευνητικό ζήτημα. Θα ήθελα να εκφράσω τις ειλικρινείς και θερμές ευχαριστίες μου σε όσους συνέβαλλαν στην ολοκλήρωση αυτής της προσπάθειας: Πρωτίστως θα ήθελα να ευχαριστήσω θερμά τον αναπληρωτή καθηγητή του τμήματος Πληροφορικής του Αριστοτελείου Πανεπιστημίου Θεσσαλονίκης κ. Πλέρο Νικόλαο, επιβλέποντα της παρούσας διπλωματικής, για την πολύτιμη βοήθεια και την στήριξη που μου παρείχε κατά τη διάρκεια των σπουδών και την εκπόνηση της εργασίας. Έπειτα θα ήθελα να πω ένα ευχαριστώ στα μέλη του ερευνητικού εργαστηρίου WinPhos για την άριστη συνεργασία που είχαμε κατά τη διάρκεια εκπόνησης της εργασίας αυτής. Επιπλέον, ιδιαίτερες ευχαριστίες θα ήθελα να απευθύνω στον υποψήφιο διδάκτορα Γεώργιο Μουργιά-Αλεξανδρή για όλο τον χρόνο που αφιέρωσε και την υπομονή που έδειξε για να μου μεταλαμπαδεύσει όλες εκείνες τις πολύτιμες και απαραίτητες γνώσεις για την διεκπεραίωση της παρούσας εργασίας, και όχι μόνο, παρέχοντας μου έτσι εφόδια για το μέλλον μου ως επιστήμων. Τέλος θα ήθελα να πω ένα μεγάλο ευχαριστώ στην οικογένεια μου και στους φίλους μου οι οποίοι με στήριξαν σε όλη την διάρκεια των σπουδών μου. Σας ευχαριστώ, Θεσσαλονίκη, Φεβρουάριος 2021 v

TABLE OF CONTENTS Table of Contents Περίληψη... ii Abstract... iii Ευχαριστίες... v Table of Contents... vi Table of Figures... vii Chapter 1: Introduction... 1 1.1. Electronic memories... 2 1.2. Optical memories classification... 4 1.3. Light-based information storage... 4 1.4. Thesis Objectives... 7 1.5. Thesis Structure... 7 Chapter 2: Optical Memories Implementations... 9 2.1. State-of-the-Art... 10 2.1.1. Volatile memories... 10 2.1.2. Non-volatile memories... 14 2.2. Applications... 15 2.3. CAMs and RAM-banks... 16 Chapter 3: XGM-based Photonic Waveguide Memory... 18 3.1. Device characterization... 19 3.2. Experimental analysis and setup... 20 3.3. Experimental results... 21 Chapter 4: XPM-based Broadband Optical RAM Cell... 26 4.1. Device characterization... 27 4.2. Experimental analysis and setup... 28 4.3. Experimental results... 29 Chapter 5: Conclusion and Future Work... 33 References... 35 vi

TABLE OF FIGURES Table of Figures Figure 1: Typical layouts of (a) DRAM cell, (b) SRAM cell and (c) CAM cell... 2 Figure 2: Classification of the optical memory technologies. Ref [10]... 4 Figure 3: Optical bistability technologies, a) and b) bistability of engineered optical resonances, and c) and d) bistability from characteristics of certain material properties. Ref [10]... 5 Figure 4: VCSEL-based optical memory operation... 10 Figure 5: SOA-MZI coupled optical memory in master-slave configuration... 11 Figure 6: 1 Two micro-ring lasers coupled via a waveguide, a) clockwise (CW) and b) anticlockwise (ACW) lasing modes... 12 Figure 7: Principle of operation of an InP microdisk laser... 12 Figure 8: High-integration-memory based on nanocavities, on a photonic crystal chip... 13 Figure 9: (a) Schematic representation of the device and (b) principle of operation when relying on wavelength bistability through injection locking... 14 Figure 10: A cross-sectional view of the coupling region showing the control port on the left side and the GST covered free-standing waveguide section on the right side... 14 Figure 11: Demonstration of binary memory operation between the crystalline (lower, level 0) and amorphous (upper, level 1) states of a 5 μm GST device for multiple repetitions of the same switching cycle... 15 Figure 12: i) Conceptual architecture of T-CAM based AL tables and ii) T-CAM cell layout... 17 Figure 13: WDM-enabled optical RAM bank with different SET/RESET wavelengths, shared Access Gate (AG) mechanism among all optical Flip Flops (AOFFs) and Passive DEMUX-based decoding... 17 Figure 14: a) GDS mask of XGM-FF configuration, b) Microscope image of the XGM-FF and c) Photo of the electro-optic packaged chip... 19 Figure 15: Experimental setup of the monolithic InP memory chip evaluation... 20 Figure 16: SOA Gain curves for both SOAs at 100mA and 240mA... 21 Figure 17: Output spectrum of a single SOA, and output spectrum of the PIC during operation as a bistable optical memory... 22 Figure 18: Proof of principle for 5Gb/s memory operation i)-iii) traces (1.000ns/div) of Set, Reset and FF out and iv)-vi) corresponding eye diagrams (50ps/div).... 22 Figure 19: Photo of the packaged chips... 23 Figure 20: Experimental results for ASE spectra for SOA1... 24 Figure 21: Eye diagrams for 5Gb/s Wavelength Conversion operation... 24 Figure 22: Eye diagrams for 4 different Flip-Flop operations at 5Gb/s in 4 different chips (50ps/div)... 25 Figure 23: a) GDS mask of XGM-FF configuration and b) Photo of the electro-optic packaged chip... 27 Figure 24: Experimental setup for the broadband evaluation... 28 Figure 25: SOA Gain curves for both SOA4 and SOA5 at 240mA... 29 vii

TABLE OF FIGURES Figure 26: Output spectrum of a single SOA (left) and output spectrum of the PIC during FF operation (right)... 30 Figure 27: Experimental traces of 5Gb/s RAM operation... 30 Figure 28: Output spectra for wavelength pairs at the four edges of the tested cases... 31 Figure 29: Eye diagrams for wavelength pairs at the four edges of the tested cases... 31 Figure 30: BER values for 49 different CW-control wavelength pair combinations... 32 viii

CHAPTER 1: INTRODUCTION Chapter 1: Introduction 1

1.1. Electronic memories CHAPTER 1: INTRODUCTION In the history of computers, the storage components, as any other component, have seen great development during the years. The first memory devices were very simple without any real random-access capabilities. A first approach of random-access memory (RAM) device was IBM s Williams Tube, back in 1947. In 1959, Bell Labs invented the metaloxide-semiconductor field-effect transistor (MOSFET) which has been the main fabrication process for transistors with most recent the planar complementary metal-oxide-semiconductor (CMOS). Memories can be divided into two big categories, volatile and non-volatile, depending on whether they will lose the stored data or not. RAMs contain Row/Column decoders and Read/Write operations and are usually implemented via volatile type, which is divided again in two categories, static RAM (SRAM) and dynamic RAM (DRAM). Fig. 1, illustrates the typical layouts of CMOS-based technology memory cells. A one-transistor (1T) DRAM cell and a six-transistor (6T) SRAM cell are presented in Fig. 1(a) and Fig. 1(b), respectively. Fig. 1(c), shows a binary ten-transistor (10T) content-addressable memory (CAM) cell. CAMs are faster memories than RAMs and thus, they are used mainly in network devices, for forwarding and routing tables, and cache memories. In CAMs, a data word is provided as input and the CAM searches its entire memory and returns all addresses where the word was found. Binary CAMs uses words consisting only by logical 1 and 0. A more complex yet flexible type, is the ternary CAM (T-CAM) T-CAM is using the 1 and 0 along with the X state for the care/don t care state which is implemented by adding a mask bit. For example, an input data word 10X will return 101 and 100. Figure 1: Typical layouts of (a) DRAM cell, (b) SRAM cell and (c) CAM cell Among the most recent SRAM topologies, is an 8T SRAM 2D array, consisting of 32x32 cells [1]. It proposes an array with configurable word lines which supports three different computing modes, a ternary multiplication mode, an unsigned multibit multiplication mode and a logic operation mode which realizes all logic operations in one cycle simultaneously. The respective energy consumptions are 1.273, 411.75, and 11.375 fj/bit and the frequencies 526, 154, 909 MHz. A rather new compute-in-memory (CIM) SRAM structure is an 8T SRAM array based on 7 nm fin field-effect transistor (FinFet) CMOS technology [2]. The proposed device is destined for machine learning applications and is capable of computing 64x16 4-bit multiplication in one computation cycle (5.5 ns) with maximum energy consumption 7.8 pj. It 2

CHAPTER 1: INTRODUCTION has a throughput of 372.4 GOPS and mean energy efficiency 351 TOPS/W. The size of this device is in the macro area (0.032 mm 2 ). Regarding the DRAM technology, an innovative scheme, uses a duo-binary signal to transmitters and receivers to achieve high speeds and low powers [3]. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duobinary driver and a 2-tap feed-forward equalizer. The proposed device is fabricated in a 28 nm CMOS process and validated its operation at 12 Gb/s with the energy efficiency of 0.41 pj/bit. Collocated SRAM and DRAM or collocated random-access memory (CRAM) is a new technology featuring charge-based computing. A 9T bit-cell-based CRAM has demonstrated as a storage and computation device [4]. The structed fabricated in a standard 65nm CMOS technology exhibiting error-free Read/Write operation at 1 GHz. The energy efficiency of the device is at 233 TOPS/W. Volatile technology is the most common for realizing RAMs, though, non-volatile memories have attracted intense interest within research community. Three different nonvolatile SRAMs (NVSRAMs) cells based on resistive RAM (RRAM) have been recently demonstrated. A 6T2R, a 10T1R and an 8T1R cells have compared, achieving energy consumption 4.14-52.6 pj, noise margin 365-420 mv in duration up to 1μs and footprint of 32.6-45 μm 2 [5]. An ultra-low-power non-volatile memory has also demonstrated, for Internet of Things use, named ULTRARAM under the ATTRACT project [6]. This novelty combines ultra-low switching energy (~10 aj) and switching time (<10 ns) all in a device of 34 μm 2. Regarding the CAMs, the evolution is as significant as for RAMs. An analog memristorbased CAM structure has recently demonstrated which increases the data density and reduces operational energy and footprint [7]. The 6T2M device is fabricated in 180 nm technology, and each memristor can store 4-bits. In the same work, the 6T2M cells were used to create an 86x12 CAM array with a footprint of 12.5 μm 2. The total power consumption was ~0.052 fj/cell. The latest approaches use Field Programmable Gate Arrays (FPGAs) to realize TCAM cells. With this technology a block and partial reconfiguration TCAM (BPR-TCAM) was demonstrated based on Xilinx FPGA s slice resources [8]. The proposed methodology exploited the fracturable nature of look-up tables and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. The proposed device exploited 4608 slices, creating a 1024x144 array and has a performance of 3.57 Mbit/s/slice and a throughput of 16.05 Gbit/s. Although these architecture are excelling as the state of the art in the electronic domain, the well-known memory-related bottlenecks in the fields of computing and routing have served as the main motivating use-cases for transferring the speed and energy advantages of light technology to the memory domain, with the CPU-memory bandwidth bottleneck and the more recent decline of Koomey s law comprising just two indicative examples driving research toward optical RAMs and optical memories for non-von-neumann computing paradigms, respectively. 3

CHAPTER 1: INTRODUCTION 1.2. Optical memories classification This section aims to be a first approach in optical memories, by categorizing the technologies based on the information data they are capable to store, as shown in Fig. 2. As so, optical memories can be categorized in two configurations (a) bit-level and (b) packet-level. Packet-level optical memories are implemented via more conventional technologies, as delay lines and recirculating loops. Here we are more interested in the bit-level topologies since both experiments that are analyzed in Chapters 3 and 4 are also in the bit-level domain. Going a step further into the categorization of the bit-level optical memories, they are labeled as volatile when the stored data are lost or non-volatile when the stored data are maintained, when turning off the power supply. Figure 2: Classification of the optical memory technologies. Ref [10] Optical RAM cell architectures are implemented by optical volatile memories as they offer faster access time and higher operation speed compared to non-volatile memories. RAM cells are again divided into two categories (i) the optical DRAM and (ii) the optical SRAM with their main difference lying in their requirement for refreshing (DRAM) or not (SRAM) the stored bit value. The implementation of optical SRAM layouts has been based on bistable optical devices, whereas for the optical DRAM cells relied on either low speed optical physical mechanisms or recirculating loop arrangements. On the other hand, optical non-volatile memories, which are a rather recent technology, mainly taking advantage of the phase change materials (PCMs), which have been shown to allow for permanent light storage in a continuously growing field of diverse applications. 1.3. Light-based information storage Towards achieving light-based storage, research community designed and tested several methods with the predominant being optical bistability. This can rely either on bistability of engineered optical resonances -artificial cavities- e.g. master-slave configurations and 4

CHAPTER 1: INTRODUCTION feedback loops or the bistable characteristics from certain material properties e.g. injection locking and phase-change materials, as depicted in Fig. 3. To obtain this bistability, two main conditions should be applied, (a) provide at least two discrete, stable states that represent the logical one and logical zero and (b) allow switching between the two states under certain conditions. Figure 3: Optical bistability technologies, a) and b) bistability of engineered optical resonances, and c) and d) bistability from characteristics of certain material properties. Ref [10] Fig. 3(a), presents the master-slave configuration which uses two active components in a coupled arrangement to form a cavity. In this case, the two discrete states we need, logical value 1 and logical value 0, are represented by two different wavelengths. As long the configuration is operating, only one of the two wavelengths can be dominant inside the cavity, suppressing the second for the same time. Wavelength λ1, corresponds to active component #1 and the logical value 1, whereas wavelength λ2, corresponds to active component #2 and the logical value 0. Two possible states are represented here, State 1 where λ1 dominates in the cavity and suppresses λ2 and State 2 where λ2 dominate in the cavity and suppresses λ1. In State 1, the active component #1 serves as the master, whereas active component #2 is the slave, with the memory output signal obtained at wavelength λ1. On the other hand, in State 2, wavelength λ2 suppresses wavelength λ1, and the memory output emits a signal at wavelength λ2. In order to change between the two states, an external light, in appropriate power and wavelength, needs to fall into the master component suppressing its own operation allowing the slave device to reach its equilibrium state. As so, the wavelength emitted by slave can now reach the master, suppressing it and taking the place as the new master even if the external light injection stops. Set-reset flip-flops (SR-FFs) are typically implemented with this technique, which are employed in optical SRAM cells. Research has shown that the time between switching into states, is inversely proportional to the length of the cavity formed between the two active components [11], as so, in the view of picosecond switching times, integrated solutions are a necessity. Fig. 3(b), shows optical memories based on feedback loops. This layout requires a single active component and an external cavity implemented by loops that feed the output signal back 5

CHAPTER 1: INTRODUCTION to the active component through a fiber or integrated waveguide [11,12]. The so far demonstrated implementations, use a 1x2 optical switch, that either feeds the switched signal back to the loop or switching the signal out of the loop. SR-FFs can also be realized by this type of optical memory [13], thus, toggle flip-flops (TFFs) can as well be implemented by applying a single external pulsed signal [14]. The T-FFs implementations have two available options: either (a) maintain the current state's value for another cycle in the case of a logical 0 or (b) toggle the value (negate it) at the next clock edge in the case of a logical 1 at each input. In that case, the loop retains its state when the incoming signal is blocked; otherwise, the memory content is changed, yielding a TFF functionality that is highly useful for shift registers and counters [14]. The injection locking scheme which is presented in Fig. 3(c), can provide optical bistability by forcing specific light characteristics of the lasing device to lock to the respective characteristics of an externally injected optical beam. These characteristics are usually, (a) the wavelength [15-18], (b) the polarization state [19,20], and (c) propagation direction [13,21,22]. The bistability can observed as an interchange between an unlocked and a locked state. The paradigm in the figure concerns the wavelength bistability and more specifically illustrates a hysteresis loop formed by a laser. Initially the laser emits at the unlocked state (red in figure), but it starts emitting in the locked state (blue in figure) while the power of a wavelengthdetuned input signal, called control signal, increases above a threshold. As long as the scheme remains in the locked state and the optical power of the control signal drops to a certain value, the device enters a hysteresis loop retaining this emission state even when the control signal optical power is decreased to a certain cut-off level. As soon as the optical power of the control signal drops below the cut-off level, the laser returns to its unlocked state. Consequently, the laser has two distinct states, locked (low) and unlocked (high), depending on the ascending or descending direction of the injection signal power, and the memory operation can be achieved when operating within the bistable range of the laser device. Polarization-based bistability can achieved by interchanging between orthogonal and vertical polarization of the control signal, whereas propagation-based bistability is based on the clockwise or anticlockwise propagation of the control signal. Finally, the last technology for optical memory bistability as shown in Fig. 3(d), relies on the PCMs [23-25] PCMs composed of materials that can greatly change their optical properties (index change Δn > 1 and Δκ ~ order of magnitude) in response to an external stimulus (e.g. temperature, applied voltage). The most commonly PCM relies on chalcogen-based alloys such as Ge2Sb2Te5 (known as GST) in which the material undergoes transitions between its amorphous and crystalline states. In the figure an example of a recent PCM-based all optical memory operation [23] is presented. For the memory bistability, in the small patch of GST that is loaded on top of a silicon-nitride waveguide optical pulses are injected that can lead the thin film to adopt either an ordered crystalline or disordered amorphous state. The two states can be observed at the output by the intensity of the propagating light as the phase of the GTS affects the optical properties of the waveguide. While the output has low intensity, corresponding to logical 0, the device is in its crystalline state and the attenuation to the propagated light is strong, due to the GTS is more absorptive in this state. On the other hand, 6

CHAPTER 1: INTRODUCTION in the amorphous state, the absorption is reduced, thus, the output has high intensity, which corresponds to logical 1. Switching between the two phase-states occurs when high-intensity optical pulses are injected and based on their total energy, can initiate either amorphization (write) or crystallization (erase). Also, multi-bit operation is supported as this type of memory can also support multiple intermediate absorption levels. 1.4. Thesis Objectives This thesis reviews the state-of-the-art optical memory implementations, for both volatile and non-volatile technologies. Moreover, the conceptual figures of address look-up tables and RAM banks are presented, as they constitute desirable targets-steps for realizing an all-optical operational RAM which can operate in a broad spectral range. In view of this realization, two memory-cell implementations have been studied, experimentally validating fast (5 Gb/s) and broadband (about 26 nm range) operation. The first demonstrated device, which is a single structure of a monolithically integrated InP chip, is a bistable photonic memory relying on two SOAs in a cross-gain modulation (XGM)-based scheme. Both SOAs have been characterized initially as generic non-linear components, before a simple Wavelength Conversion (WC) at 5Gb/s was performed with combinations of Set-CW2 and Reset CW1 signals at 1550.4-1549 nm and 1551.2 1548 nm. The proof of principle of the waveguide memory was validated for operation at 5Gb/s providing clear eye diagrams with extinction ratio of 6 db. The second device utilized two SOAs in the more mature cross-phase modulation (XPM)- based scheme. It is a different structure in the same integrated InP chip and also employs an integrated Access Gate (AG). As before, the first step was to characterize the SOAs as generic devices. RAM operation was experimentally validated at 5Gb/s revealing error free performance within a broad spectral range of about 26 nm. For the broadband evaluation, the testing cases used combinations of Set-Reset, in ranges of [1534.4-1558.4] nm and [1535.2-1559.2] nm with a step of 4 nm, respectively, and CW1-CW2, in ranges [1535.7-1559.7] nm and [1534-1558] nm, with a step of 4 nm, respectively, creating 49 testing cases in total. All 49 cases had a power penalty threshold at 4.5 dbm. 1.5. Thesis Structure The rest of the thesis is organized in 4 Chapters. Chapter 2 reviews the state-of-the-art technologies for both bit-level optical memories categories, volatile and non-volatile. Moreover, applications that already have realized using 7

CHAPTER 1: INTRODUCTION the above topologies are presented. Finally, the conceptual schemes for T-CAMs based address look-up tables as well as RAM-banks, are analyzed. Chapter 3 demonstrates an XGM-based photonic waveguide memory cell. Firstly, the integrated device characterization is presented, followed by the experimental setup analysis. The experimental results are proving a clear memory operation at 5Gb/s. Moreover, a same validation has been made for another 3 chips, in order to use them in the future and demonstrate a complete look-up table. Chapter 4 reports on an XPM-based broadband optical RAM cell. In the first place, the device characterization is presented focusing in the integrated chip, followed again by the experimental analysis of the setup. In this context, the demonstrated experimental results are proving a perfect RAM operation in 5Gb/s. Furthermore, the broadband operation of the FF is validated through bit-error-rate tester (BERT) measurements in a spectrum range of 26nm on the C-band. Finally, in Chapter 5 a conclusion of the thesis is reported along with plans and ideas on the future work regarding the proposed optical memory cells, exploiting their full potential and scalability. 8

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS Chapter 2: Optical Memory Implementations 9

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS 2.1. State-of-the-Art This thesis focuses in the bit-level optical memory technologies thus, the state-of-the-art will concern only volatile and non-volatile memories. In terms of optical volatile memories, the most popular technologies that have been successfully implemented and achieved lightbased storage, relying mainly on (i) vertical cavity surface emitting lasers (VCSELs) [19,20,26-28], (ii) semiconductor optical amplifiers (SOAs) [29-33], (iii) Indium Phosphide (InP) coupled micro-ring lasers [13,21,34,35], (iv) InP microdisk lasers [22], (v) InP buried heterostructure (BH)-photonic crystal (PhC) nanocavity switches [15,16,36,45], and (vi) hybrid InP-on-SOI (silicon-on-insulator) PhC lasers [17,18,36-38]. On the other hand, the most popular non-volatile optical memory technology is based on PCMs [22-25,39-41]. 2.1.1. Volatile memories The first optical volatile memory implementation was VCSEL-based. In Fig. 4, the VCSEL operation for polarization bistability at the 1.55 μm wavelength region is shown. An external optical signal is responsible for the polarization bistability of the device, as the polarization state of the VCSEL output signal, orthogonal or vertical, follows the polarization state of the injected optical pulse and as so, the memory content (logical 1 or 0 ) is identified by the polarization state of the output. Polarization bistable VCSEL-based memories at 980 nm have been demonstrated with 20-Gb/s RZ and 40-Gb/s NRZ optical pulses at slower repetition periods, enabling multi-bit memory implementations [19,26]. The main advantages of polarization-bistable VCSELs include (a) their potential for high-speed memory operation up to 40 Gb/s [27], (b) their attractive properties for logic gate functionalities [28], (c) their lowenergy consumption requirements compared to other types of bistable laser diodes (~105 fj for 40 GHz operation [19,20]) and (d) their established and mature laser technology platform, Figure 4: VCSEL-based optical memory operation 10

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS which can form the basis of a reliable optical memory solution. The main limitations are their increased footprint as only the active square corresponds to ~36 μm [27] and the need for perfect polarization state and alignment. A bit later in time, all-optical flip-flops (AOFFs) demonstrations were introduced based on SOA lasers or switches, performing in master-slave configurations. The first demonstrations were realized with fiber-pigtailed components utilizing hybrid silica-on-silicon integration technology and a coupled semiconductor optical amplifier Mach Zehnder interferometer (SOA-MZI) and were destinated for all-optical packed switching. Bit-level optical memory implementations were demonstrated exploiting cross-phase modulation (XPM) phenomena in SOA-MZIs [42], XGM in coupled SOAs [43] or SOA-based coupled ring lasers [14]. The integration into InP photonic integrated circuits (PICs) initiated the true RAM cells demonstrations with the fastest reported operation being up to 10Gb/s [30]. The devices principle of operation is illustrated in Fig. 5. The device follows a master-slave configuration, with the two coupled SOA-MZIs being powered by two external continuous-wave (CW) input signals CW1 and CW2 and the logical value of the memory cell being determined by the wavelength of the Figure 5: SOA-MZI coupled optical memory in masterslave configuration dominant CW signal. Some other AOFF technologies utilize (i) SOA-based DFBs [30], (ii) SOAs and DFB laser diodes [31], (iii) loop mirrors [33] and (iv) feedback loops [12]. The benefits of using SOA-based technologies are (a) their enhanced maturity level and flexibility characteristics that allowed the demonstration of novel memory concepts in both fiber-pigtailed [42,43] and integrated versions [12,29] and (b) their high-speed potential, having already resulted in 10 Gb/s memory line rates [ref-45] and being theoretically predicted to allow up to 40 Gb/s operating speeds [44]. However, they lag behind in means of footprint and energy as they require (~120 pj [29] and ~180 pj [30]) for SOA biasing and s (~3 pj [29], ~0.5 pj [30]) for optically switching between set and reset states, with the current footprint requirements hardly going below a few mm 2. Integrated micro-ring laser-based AOFF were demonstrated after the SOA-based implementations. Fig. 6, depicts the layout and the two operations. The micro-rings are connected via a waveguide, whereas two inherent lasing modes create a system where the master micro-laser injection locks the slave laser under certain conditions and defines the direction of the propagating light. The two possible states are: (a) the laser light traveling clockwise (CW) and (b) the laser light traveling anticlockwise (ACW).To switch states, a CWsignal close to the lasers characteristics needs to be injected into the waveguide to set both lasers to lase simultaneously in either the CW or ACW direction. Alternative AOFFs and optical memory demonstrations are: (i) a single semiconductor micro-ring laser employing a retro-reflector cavity to enable 2-bit optical storage while achieving fast ON/OFF switching 11

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS times [34] and (ii) high-speed operation at 10 Gb/s and an improvement in the switch-on times up to 10ps [13]. Integrated ring laser schemes offer advantages such as (a) high operational speeds up to 10 Gb/s [13] and fast switching times of 20ps [22] and (b) high-output-signal extinction ratio values that can reach almost 40 db [34]. Though they have major drawbacks in terms of (a) the total energy consumption ~1.2pJ [21] 30 and ~54pJ [13]) and (b) their large footprint, occupying more than 1000 μm 2 [34] and reaching even several mm 2 [13]. Figure 6: 1 Two micro-ring lasers coupled via a waveguide, a) clockwise (CW) and b) anticlockwise (ACW) lasing modes The next technology appeared later by IMEC and it was an ultra-small, low-power AOFF on a silicon chip [22]. Fig. 7, illustrates the principle of operation which is again exploiting the propagation direction of the light to establish the AOFFs states. The microdisk supports the whispering gallery modes (WGMs) which relies on the interchange between CW and ACW directions. Initially, the microdisk works in the dominant state (Fig. 7(i)), thus, the ACW mode is suppressed, and the optical power at the left output of thw waveguide is high. Then, a Reset pulse is injected (Fig. 7(ii)) changing the mode to ACW, which is retained even after the pulse has passed through the microdisk (Fig. 7(iii)) and the power in the left port is now low. To switch back to CW state, a Set pulse must be injected from the right side of the waveguide (Fig. 7(iv-v)). Microdisk-laser based memories have low switching power requirements (1.8 fj) and fast switching times (~60 ps) but requires additional power for thermal tuning (~0.8 mw/ bit) that increases the total energy consumption [22]. Figure 7: Principle of operation of an InP microdisk laser 12

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS Most recently, research community has investigated InP BH-PhC lasers [15] and nanocavities [16,45] for all-optical signal processing and optical packet switching as well as optical memory operations. The first implementation of AOFF based on PhC relied on a wavelength-injection technique in a InGaAsP/InP BH-PhC laser that exhibited fast switching times of 60ps and switching powers in the range of ~20 70μW [15]. An improved layout was demonstrated, by integrating BH-PhC nanocavities in InGaAsP to create optical memory bistability achieving a record-low static energy consumption of 30nW and lead to speeds of 40Gb/s[45], however, the switch-off time was on the order of 7ns. With this technology it was able to scale-up and demonstrate a high-density memory, as shown in Fig. 8, exploiting wavelength division multiplexing (WDM) and yielding 128-bit storage capacity [16]. The most important advantages of the InP BH-PhC nanocavity-based memory technology are (a) the ultra-low-energy consumption and (b) the proven capability to produce multi-bit photonic memory chips and high integration, with the main drawback thus far being the rather long switch-off time. Figure 8: High-integration-memory based on nanocavities, on a photonic crystal chip The latest volatile optical memory technology that has been demonstrated is based on InPon SOI PhC laser. The device has successfully operated with pseudorandom bit sequence (PRBS) data patterns in both gating and latching functionalities [17,36]. The device structure along with the principle of operation is depicted in Fig. 9. The device operates as a SR-FF, utilizing the three discrete power areas. In Area I, the injection power levels allow for the set operation, as the laser output is changed from an unlocked to a locked state. In Area II, the injection power levels are below a certain threshold, enabling the reset operation, as the laser output returns to the unlocked state. Finally, in Area III, the injection power levels cover the bistable range and enable the storing operation, because the laser emission retains its previous state. Hybrid InP-on-SOI PhCs satisfy important advantages, (a) low footprint (6.4 μm 2 ), (b) low-energy consumption (13 fj) and (c) high-speed bit-level operation up to 10 Gb/s, as already verified experimentally [18]. This platform is promising for real application needs as it can migrate to an electrically pumped scheme as already demonstrated for PhC laser nanocavities [38]. 13

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS Figure 9: (a) Schematic representation of the device and (b) principle of operation when relying on wavelength bistability through injection locking 2.1.2. Non-volatile memories Optical non-volatile memory is a rather new term in means of implementations as so far, the implementations are based on PCMs [23-25,39-41]. PCMs operate between two states, amorphous and crystalline, which represent logical 1 and 0 respectively. Depending on the state the device is in, the light absorption level can be lower or higher, translating into different optical memory functions by encoding the material phase into the power level of propagating light. The transition between the two phases can be performed on a picosecond to subnanosecond timescale for amorphization and on a sub-nanosecond to nanosecond timescale for crystallization. An all-optical non-volatile memory was proposed in 2015, based on GST, achieving operation at 1 GHz, and allowing for all-optical multi-level and multi-bit memory capabilities. Fig. 10, shows a cross-sectional view of the suggested device. Information is stored in the phase state of GST which is placed on top of a Silicon Nitride (Si3N4 or SiN) waveguide. Both reading and writing of the memory can be performed with ultrashort optical pulses, utilizing the interaction between the evanescent field of the guided light and the GST material. Read operation requires a weak optical pulse to obtain the material phase encoded Figure 10: A cross-sectional view of the coupling region showing the control port on the left side and the GST covered free-standing waveguide section on the right side 14

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS onto the power level of the pulse, while write and erase operations require more powerful optical pulses to enforce a phase transition within the GST. As illustrated in Fig. 11, the crystalline state of GST (level 0) results in higher absorption levels and, as such, increased attenuation compared to its amorphous state (level 1). The data stored in different phases, of different attenuations, can be read in the output of the waveguide by the power of the lightsignal. By following this principal, a fast GST-based PCM memory with a capacity of 5 bits has demonstrated [39], occupying an area of only 4 1.3 µm 2. Another effort was made reaching the speed close to 1 GHz in the all-optical memory cell while using only 13.4 pj [23]. As such, PCM-based optical memories offer some highly attractive benefits, which include (a) their small footprint [39], (b) their ability to carry out the multi-bit and multi-level memory operation [23,24], (c) their compatibility with silicon processing [25], (d) the ultra-low energy requirements and (e) their non-volatile nature, which has triggered a series of new and highly interesting applications, including their use as synaptic elements for neuromorphic computing architectures [40,41]. Figure 11: Demonstration of binary memory operation between the crystalline (lower, level 0) and amorphous (upper, level 1) states of a 5 μm GST device for multiple repetitions of the same switching cycle 2.2. Applications As already happened with electronic memory technologies, optical memories have started to infiltrate into multiple applications such as processing, routing, and computing. Optical digital signal processing deploys an optical building block for realizing the complete toolkit needed to copy the electronic digital signal circuitry, including different types of FFs, shift registers and counters. SR-FFs [11-14,21,22,29,42,43,47], delay flip-flop (D-FFs) [14], and toggling FFs [11,14,47], as well as shift registers and bit counters [19,28], have all been implemented with technologies analyzed above, in Section 2. This application aims to replicate 15

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS well-known functions and layouts at much higher operational speeds toward enabling true processing via optics. Another application, regarding routing this time, is the contention resolution and buffering in optical packet switches (OPSs). In networks, collisions can happen between incoming data packets, when those packets require the same router output at the same time. This would result in signal degradation and loss of information. To avoid these collisions buffers are added to delay one of the 2 packets until the desired output has an available output. An early approach to implement the buffers, was through recirculating loops [48,49] or fiber delay lines [50,51], however both had a limited buffering time. An R&D in Japan proposed the use of InP PhC nanocavities for packet buffering in OPS fabrics [12,15,16,45]. Address lookup (AL) tables and forwarding, an additional application, used in routers to identify the destination of the incoming data and route them to the correct output port. AL compares the incoming address with a set of possible addresses stored locally in the router, while forwarding associates that address, if it is a match, with the output port that has to be activated. AL is typically realized by CAMs and can operate as a memory and as a comparator, simultaneously, within a single clock cycle [52]. Optical look-up tables have not yet been realized, but the recent demonstrations of optical binary [53] and ternary [54] CAM cells using coupled SOA- MZI-based FFs might release new perspectives for all-optical look-up table deployments. Forwarding is usually implemented by a 2-dimensional RAM bank, where every RAM row stores the address of a router output port and is activated by the look-up CAM-based table. Cache memories are the last application that will be mentioned. Cache memories are the closest to CPU, static memory units, which can store a small amount of data but are ultra-fast. As so, the CPU can fetch the data stored in cache without the need to communicate with the conventional, slower, DRAM. An all-optical cache memory implementation has already been proposed [55], including read/write control, row/column decoding and tag comparison [56,57,29,42,43]. 2.3. CAMs and RAM-banks While all applications mentioned in Section 2.2, are worth to be further investigated, this will happen only for CAMs and RAM-banks as they are the topologies we aim to implement in the future. The experiments in Chapters 3 and 4 analyze the basic scalable single memory cell that can establish full CAMs and RAM-banks. Fig. 12(i), depicts a conceptual architecture of AL tables based on T-CAM cells. As it is shown, a typical AL-table layout comprises a T-CAM table in which the input search words are provided for a fast-parallel comparison across the AL-entries and a RAM table to maintain the respective router output ports. The comparison takes place within one clock cycle. Upon a match, they enable through an appropriate Encoder/Decoder network the respective RAMtable entry, where the next hop is stored. The most important component for implementing an AL table, is the T-CAM cell itself. Recently, an all-optical T-CAM cell was demonstrated [58], with the layout presented in Fig. 12(ii). The layout of the proposed T-CAM cell employed two integrated InP FFs as the TFF and XFF and a Silica-on-Silicon SOA-MZI device as the XOR 16

CHAPTER 2: OPTICAL MEMORY IMPLEMENTATIONS gate. This device was demonstrated for 10Gb/s but through a theoretical analysis [59] it has a potential of reaching 40Gb/s. Figure 12: i) Conceptual architecture of T-CAM based AL tables and ii) T-CAM cell layout In Fig. 13, an optical M N RAM bank is presented, using the WDM technique. The WDM-enabled optical Ram bank incorporates Row and Column Decoding stages for directing the necessary data words in the needed row and column of the RAM bank, based on specific row/column addresses, respectively. In our proposed WDM-enabled RAM bank concept the Column Decoding stage is performed passively through an passive Arrayed Waveguide Grating (AWG) and a shared InP SOA-MZI device serving as a high-speed shared Access Gate (AG) among different broadband optical memory cells, while employing WDM incoming data words. The WDM technique that is exploited can reap significant benefits such as energy consumption minimization through hardware reduction as indicated in [60]. A rather resent proposed WDM static RAM cell [61], comprised a SOA-MZI used as the AG and an integrated InP chip that incorporated the all-optical FF. The device was successfully demonstrated at 5Gb/s for both Read and Write operations. Figure 13: WDM-enabled optical RAM bank with different SET/RESET wavelengths, shared Access Gate (AG) mechanism among all optical Flip Flops (AOFFs) and Passive DEMUX-based decoding 17

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY Chapter 3: XGM-based Photonic Waveguide Memory 18

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY 3.1. Device characterization The electro-optic packaged chip used to evaluate experimentally the integrated InP monolithic photonic waveguide SOA-XGM memory, has been fabricated at a Multi-Project Wafer (MPW) run of Fraunhofer HHI packaged by PHIX to facilitate fast prototyping and easier testing. The design mask layout of one of the monolithically integrated InP optical memory cells is shown in Fig. 14(a), exploiting two SOA-XGM switches in a cross-coupled configuration. The proposed device exploits two 1mm-long SOAs (SOA1, SOA2), coupled together via a 1.2mm-long waveguide with interleaved Multimode Interference (MMI) couplers. The configuration relies on a standard master-slave configuration, where an injected Set or Reset pulse can suppress the gain of one of the SOAs, setting it in the suppressed slave gain-regime, allowing the opposite gain to recover at a master state. Fig. 14(b) and (c) show a microscope photo of the fabricated SOA-XGM-based optical FF cell and a photo of the packaged PIC. The chip itself includes more than one structures, thus, for the XGM-based FF the needed connections are four electrical pads to power up the two SOAs and four waveguides for the optical signals. Figure 14: a) GDS mask of XGM-FF configuration, b) Microscope image of the XGM-FF and c) Photo of the electro-optic packaged chip Το operate the memory, each PIC is equipped with a dedicated electrical current injections metals pads, which are manufactured by structuring metal patterns based on gold layers. The gold layers are routed to the bond pads at the edges of the PIC with certain metal leads. The metal routing-network of the leads and the heaters reaching the edge bond pads can be identified at the center of the chip in the zoom-in inset of Fig. 14(b). To avoid the thermal cross-talk by multiple on-chip heaters, these are separated by a distance greater than 250 μm that provides sufficient separation and the pads are separate by more than 100 μm. For temperature stabilization purposes, the chip is placed on a large copper block, which acts as a heat sink, as can be clearly seen underneath the chip at the zoom inset of Fig. 14(c), connected underneath to a Peltier-cooling element with temperature-dependent resistor and controller. For accurate temperature control, a resistor has been attached close to the PIC, and 19

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY connected to a closed feedback loop Laser Diode Controller (LDS). Electronics are connected via a flexible flat ribbon cable to a small PCB fan-out interface, shown with brown and green color in Fig. 14(c) respectively, which is wire bonded to the on-chip metal-bond pads. Using this system, the heaters have been shown to be very reliable and straightforward to manufacture, supporting tuning speeds in the order of 1ms and an accuracy better than 0.01K, allowing for a stable operation of the cascaded SOAs. 3.2. Experimental analysis and setup The experimental setup for the characterization of the optical memory is shown in Fig. 15. Four Tunable Laser Sources (TLS) were used to generate, two CWs (λcw#1, λcw#2) at 1548 nm and 1549 nm which were pumping the waveguide structure in a counter-directional manner and two CW beams (λset, λreset) were modulated in two respective Ti:LiNbO3 modulators (MOD) driven by the complementary data of a Pulse Pattern Generator (PPG) at 5Gb/s to generate the custom Set/Reset NRZ data-stream based on PRBS 2 7-1 sequences and fed into the InP SOA-XGM-based FF cell through the MMI stages. The λset and λreset were set at 1550.4 nm and 1551.2 nm, respectively. Figure 15: Experimental setup of the monolithic InP memory chip evaluation Prior to and past MOD two Polarization Controllers (PC) were used to achieve the best polarization state. MOD insertion losses were counterbalanced by Erbium Doped Fiber Amplifier (EDFA) while a Tunable Optical Filter (TOF) employed to cut the Amplified Spontaneous Emission (ASE) noise from EDFA. Four Variable Optical Attenuators (VOAs) were used to control the optical signals powers. The output signals were collected through a time oscilloscope (OSC) and a Bit-Error-Rate-Tester (BERT) for further signal quality evaluation. In order to have a complete evaluation in both FF cell s outputs, two circulators were used in both Set/Reset paths. During the time setting up the experiment, special concern and effort has been dedicated on identifying the proper operational conditions for the PIC memory, including temperature 20

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY stability, optical gain and stable operation of the device. The two SOAs were driven at around 200 ma, while the optical signal powers were around 11 dbm for λcw#1 and λcw#2, and 14 dbm for λctr#1 (SET) and λctr#2 (RESET). The same experimental setup used to evaluate every PIC device and the operation conditions in means of SOA powers and optical signals powers were similar. 3.3. Experimental results The current section aims to present the detailed experimental characterization-validation and the results for the proof-of-principle operation of the first developed integrated photonic memory unit. We initially started by experimentally characterizing the SOAs as gain elements as the most basic building blocks. Fig. 16 presents the gain curves of the two on-chip SOAs, while both SOAs are externally driven by 100 ma or 240 ma. For current of 100 ma, black lines in graph, the two SOAs has a similar incline with an output power difference of -10 to -5 dbm. For SOAs current of 240mA, red lines in graph, SOAs operated in the small signal regime, as CW optical powers fed into the SOA where from -50 to -20 dbm, while the saturated SOA output power was - 15dBm for SOA1 and -10 dbm for SOA2. Figure 16: SOA Gain curves for both SOAs at 100mA and 240mA Fig. 17(i), presents the output spectrum of a single SOA device, when this is only powered up electrically, while the second SOA is not switched on, indicating a gain peak in the 1550 21

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY nm region, as expected for a standard SOA operation. Moreover, the device was also operated in wavelength conversion and bistable optical memory, with its optical spectrum during normal operation being illustrated in Fig. 17(ii), for a CW and control signal. Figure 17: Output spectrum of a single SOA, and output spectrum of the PIC during operation as a bistable optical memory Fig. 18, presents the proof of principle operation of the waveguide memory operation at 5Gb/s. Specifically, Fig. 18. i), ii) and iii) show the pulse traces of Set and Reset signals and the FF output signal at 5Gb/s respectively. The time traces are synchronized, and provide a consecutive sequence of alternative Set or Reset pulses that define the state of the optical memory, and are never considered to beat the same time both 1 and 1 value, in order to drive correctly of the optical memory operation. The output traces indicate that the ff optical memory can sufficiently change its state upon a Set or Reset pulse, verifying proper Write and memory change operation. The highlighted areas depict a retention time of >10 nsec. The performance of the 5Gb/s operation of the optical memory was evaluated also with eye diagrams as shown in Fig. 18. iv), v) and vi) depict the respective eye diagrams for the Set/Reset Figure 18: Proof of principle for 5Gb/s memory operation i)-iii) traces (1.000ns/div) of Set, Reset and FF out and iv)-vi) corresponding eye diagrams (50ps/div). 22

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY and output signals. All diagrams are wide-open with extinction ratio of 6 db and Amplitude Modulation (AM) of 1.6 db, that is only limited at the moment by the triangular pulse shape of the recovery time of the generic SOA-XGM device, rather than any complex memory loop or the round-trip travelling-time of the intermediate coupling waveguide between the SOAs. In order to present the full scalable scheme, the same procedure of characterizing the performance of the photonic memory, repeated for three more chips Fig. 19, four in total, allowing to generate 4-bit optical CAM tables for optical look-up table architecture. Figure 19: Photo of the packaged chips Fig. 20, depicts the characterization of the SOAs, as generic optical non-linear components. Initially the SOAs of the four chips were characterized. Fig. 7(a), shows the indicative gain spectrum of the on-chip SOA1, with the ASE gain-peak being around 1546-1550 nm. For the observed results the external current for the SOA was around 240 ma. SOA2 characterized under the same currents and the results were similar as SOA1. The output spectra recorded for four PICs are using the same operational conditions as in the previous sections. Therefore, the optical spectra recorded with the same resolution of 0.1 are almost identical with a peak gain around 1550 nm (with the main differentiation of course being the ripples or small lasing phenomena). The four chips were also operated as standard wavelength converters, where a control signal was imprinted on a CW signal, performing standard switching operation based on crossgain modulation phenomena. Indicative eye diagrams are shown in Fig. 21, revealing wide open eye diagrams. Fig. 21, shows the simple Wavelength Conversion (WC) study of a single library-based 1mm-long SOA-XGM switch component was performed at 5 Gb/s with combinations of Set-CW2 and Reset CW1 signals at 1550.4-1549nm and 1551.2 1548nm, respectively. The recorded WC eye diagrams indicate a 10%-to-90% recovery time of around 150 ps for operation at 5 Gb/s. All four integrated photonic devices were operated as optical memory units. In Fig. 22, four different FF output eye diagrams are depicted, corresponding to the four different chips that were used with operation at 5Gb/s. since the four integrated photonic chips share the same design and operational parameters, it is expected that all the obtained results would be very 23

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY Figure 20: Experimental results for ASE spectra for SOA 1 similar, with any differentiations being attributed to environmental settings (e.g. temperature, noise, polarization etc). This was indeed confirmed during the experimental evaluation of the 4-bit memory operation. All four obtained eye diagrams are wide-open, in Fig 22. In both upper diagrams the extinction ratio is 6 db and AM 1.6 db, while in both lower diagrams, the extinction ratio is 4 db and AM 1.6 db. Figure 21: Eye diagrams for 5Gb/s Wavelength Conversion operation 24

CHAPTER 3: XGM-BASED PHOTONIC WAVEGUIDE MEMORY Figure 22: Eye diagrams for 4 different Flip-Flop operations at 5Gb/s in 4 different chips (50ps/div) 25

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL Chapter 4: XPM-based Broadband Optical RAM Cell 26

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL 4.1. Device characterization As shown in Fig. 23, the chip used for this experiment is the same as the one used for the XGM-based memory cell experiment, thus as mentioned in Section 3.1, the chip itself contains more than one structures. In order to evaluate the broadband capabilities of the XPM-based memory cell two different structures of the PIC ship were used. Fig. 23(a), depicts the design mask layout of both structures used, the XPM FF cell and the Mach-Zehnder Interferometer Access-Gate (MZI-AG), which are highlighted in red dotted frames. Figure 23: a) GDS mask of XGM-FF configuration and b) Photo of the electro-optic packaged chip The proposed FF device exploits two 1mm-long SOAs (SOA4, SOA5), coupled together with two 1mm long phase sifters. The phase shifters are not used in this scheme. In this structure are also used interleaved MMI couplers. The configuration relies on a standard master-slave configuration, where an injected Set or Reset pulse can suppress the gain of one of the SOAs, setting it in the suppressed slave gain-regime, allowing the opposite gain to recover at a master state. The MZI-AG device exploits two 1.25 mm long SOAs interleaved again with MMI couplers. Fig. 23(b) shows a photo of the packaged PIC. For the XPM-based FF and the AG the needed connections are eight electrical pads to power up the four SOAs and twelve waveguides for the optical signals. The operation of the chip is the same as mentioned in Section 3.1, each PIC is equipped with dedicated electrical current injections metals pads based on gold layers, which are routed to the bond pads at the edges of the PIC with certain metal leads. To avoid the thermal crosstalk, on-chip heaters are separated by a distance greater than 250 μm and the pads are separate by 100 μm. For temperature stabilization purposes, the chip is placed on a large copper block, as can be clearly seen underneath the chip at the zoom inset of Fig. xx(b), which acts as a heat sink. For accurate temperature control, a resistor has been attached close to the PIC, and connected to a closed feedback loop LDC. A flexible flat ribbon cable is responsible for electronics through a small PCB fan-out interface, shown with brown and green color in Fig. xx(b), which is wire bonded to the on-chip metal-bond pads. Using this system, the heaters have been shown to be very reliable and straightforward to manufacture allowing for a stable operation. 27

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL 4.2. Experimental analysis and setup For the second experiment, the setup was more complicated, and the evaluation was more thorough. Fig. 24 depicts the experimental setup that was used to verify experimentally the concept at 5Gb/s. As shown, two CWs (λbit, λbbbbbb ) by TLS were modulated by two Ti:LiNbO3 MODs, respectively, by 5Gb/s PPG in order to produce complementary custom Bit and BBBBBB data-stream based on NRZ PRBS 2 7-1. The data were then multiplexed via an AWG. The Bit and BBBBBB were injected into the SOA-MZI-AG as input signals, along with an Inverted Access Bit signal, decorrelated through different fiber propagation and fed as control to the SOA-MZI XPM On/Off-switch, determining if the data signals will be propagated to the memory or not. The propagated data streams were then split via a 1:2 coupler and then filtered by two optical bandpass filters, forming the SET and RESET wavelengths, respectively. Then, both entered the Memory cell through ports B and C, while λcw#1 and λcw#2 are propagated through ports A and D, thus providing 5Gb/s RAM cell operation. The λbit and λbbbbbb were tested for [1534.4 1558.4] nm and [1535.2 1559.2] nm with a step of 4 nm, respectively and the two CWs (λcw#1, λcw#2), which were also generated by TLS, were tested for [1535.7 1559.7] nm and [1534-1558] nm, with a step of 4 nm, respectively. The Inverse Access Bit signal was set at 1554.8 nm and modulated by one Ti:LiNbO3 MOD getting the same custom-data stream at 5Gb/s. The output signals during WRITE operation of the RAM cell were collected at C and E ports through an OSC and at a BERT for further signal quality evaluation. Figure 24: Experimental setup for the broadband evaluation 28

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL Prior modulation, PCs were used to realize best polarization state whereas MODs insertion losses where counterbalanced by EDFAs. For controlling the optical power before the MZI- AG, two VOAs were employed, along with TOFs to cut the ASE noise from the EDFAs. The desired power levels of the signals to enter the FF cell, were in the range of [8.5-11] dbm for the λcw#1 and λcw#2 and [13.5-16] dbm for λctr#1 (SET) and the λctr#2 (RESET), while the SOAs were driven by 250 ma. 4.3. Experimental results As before, in this section will be presented the results for the proof-of-principle operation starting by experimentally characterizing the SOAs as the most basic building blocks. Fig. 25, depicts the gain curves for FFs SOAs, SOA4 and SOA5, while both SOAs are externally driven by 240 ma. For this current, both SOAs operated in the small signal regime. CW optical powers fed into the SOAs where in the range of -50 to -10 dbm, while the saturated SOA output power was almost identical for both SOAs at -15 dbm. Figure 25: SOA Gain curves for both SOA4 and SOA5 at 240mA Fig. 26, presents the output spectrum of a single SOA device, when this is only powered up electrically, while the second SOA is not switched on, indicating a gain peak in the 1550nm region, as expected for a standard SOA operation A couple of spikes are visible prior and post the gain peak, due to more reflections in this device. Moreover, the device was also operated 29

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL in wavelength conversion, with its optical spectrum during normal operation being illustrated in Fig. 26, for a CW and control signal. Figure 26: Output spectrum of a single SOA (left) and output spectrum of the PIC during FF operation (right) Fig. 27, shows the synchronized time traces, which indicate the principle of operation at 5Gb/s during WRITE operation, granting Memory Access as it is shown in (i)- (ii) the Bit/BBBBBB, iii) Inverse Access, (iv)-(v) SET/RESET and (vi) RAM cell output signals. As explained earlier and shown in Fig. 24, Set is created by Bit and Inverse Access after the AG while Reset is created by BBBBBB and Inverse Access again after the AG. For example, the first five 0 bits of the Set sequence are created by the first two 1 of Inverse Access, which are denying access to Bit and the rest three are 0 in Bit sequence. As a result, Random Access is not granted to the Bit, leading to 0 SET pulses, where memory is retained for 1 ns, while the red marker highlights a successful Write of Bits 00 in the cell when the Inverted Access is 00. Figure 27: Experimental traces of 5Gb/s RAM operation Fig. 28, shows the output spectra for the four distinctly different cases of SET/RESET and CW wavelength pair combinations, placed at the four edges of the tested cases while Fig. 29, represent the eye diagrams of the same cases. The results were obtained at C and E ports of the InP memory chip, where the RAM output, CW1 and RESET emerge as powerful signals and CW2 and SET appear weakly after reflection. For all four cases, the eye diagrams exhibit an Extinction Ratio of 4.5 db. Finally, various possible combinations of control and CW pairs in the SOA-gain spectrum were tested with a 4nm step-resolution in the 26nm range of the C- band (Broadband evaluation), resulting in a two-dimensional set of 49 measurements (7x7 steps) as can be observed from Tables 1 and 2. 30

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL Figure 28: Output spectra for wavelength pairs at the four edges of the tested cases Figure 29: Eye diagrams for wavelength pairs at the four edges of the tested cases CASE NO. CW 1 CW 2 1-X 1535.7 nm 1534 nm 2-X 1539.7 nm 1538 nm 3-X 1543.7 nm 1542 nm 4-X 1547.7 nm 1546 nm 5-X 1551.7 nm 1550 nm 6-X 1555.7 nm 1554 nm 7-X 1559.7 nm 1558 nm Table 1: CW testing pairs CASE NO. CONTROL 1 (SET) CONTROL 2 (RESET) Y-1 1534.4 nm 1535.2 nm Y-2 1538.4 nm 1539.2 nm Y-3 1542.4 nm 1543.2 nm Y-4 1546.4 nm 1547.2 nm Y-5 1550.4 nm 1551.2 nm Y-6 1554.4 nm 1555.2 nm Y-7 1558.4 nm 1559.2 nm Table 2: Control testing pairs 31

CHAPTER 4: XPM-BASED BROADBAND OPTICAL RAM CELL In Fig. 30, the BER penalty values, of the 49 measurements, are plotted in a 3D bar diagram, with a light-to-dark coloring between a 0.4-to-4.4 db range. All the 49 db values were constantly lower than a 4.5 db upper limit, verifying 5Gb/s fast, error-free, and broadband optical RAM cell operation across almost whole C-band. Figure 30: BER values for 49 different CW-control wavelength pair combinations 32