1: INTRODUCTION: ANALOG VS. DIGITAL... 1

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1 Contents 1: INTRODUCTION: ANALOG VS. DIGITAL DIFFERENCES BETWEEN ANALOG AND DIGITAL SYSTEMS ADVANTAGES OF DIGITAL SYSTEMS OVER ANALOG SYSTEMS : NUMBER SYSTEMS POSITIONAL NUMBER SYSTEMS Generic Structure Decimal Number System (Base 10) Binary Number System (Base 2) Octal Number System (Base 8) Hexadecimal Number System (Base 16) BASE CONVERSION Converting to Decimal Converting from Decimal Converting Between 2 n Bases BINARY ARITHMETIC Addition (Carries) Subtraction (Borrows) UNSIGNED AND SIGNED NUMBERS Unsigned Numbers Signed Numbers : DIGITAL CIRCUITRY AND INTERFACING BASIC GATES Describing the Operation of a Logic Circuit The Buffer The Inverter The AND Gate The NAND Gate The OR Gate The NOR Gate The XOR Gate The XNOR Gate DIGITAL CIRCUIT OPERATION Logic Levels Output DC Specifications Input DC Specifications Noise Margins Power Supplies Switching Characteristics Data Sheets xi

2 xii Contents 3.3 LOGIC FAMILIES Complementary Metal Oxide Semiconductors Transistor-Transistor Logic The 7400 Series Logic Families DRIVING LOADS Driving Other Gates Driving Resistive Loads Driving LEDs : COMBINATIONAL LOGIC DESIGN BOOLEAN ALGEBRA Operations Axioms Theorems Functionally Complete Operation Sets COMBINATIONAL LOGIC ANALYSIS Finding the Logic Expression from a Logic Diagram Finding the Truth Table from a Logic Diagram Timing Analysis of a Combinational Logic Circuit COMBINATIONAL LOGIC SYNTHESIS Canonical Sum of Products The Minterm List (Σ) Canonical Product of Sums (POS) The Maxterm List (Π) Minterm and Maxterm List Equivalence LOGIC MINIMIZATION Algebraic Minimization Minimization Using Karnaugh Maps Don t Cares Using XOR Gates TIMING HAZARDS AND GLITCHES : VHDL (PART 1) HISTORY OF HARDWARE DESCRIPTION LANGUAGES HDL ABSTRACTION THE MODERN DIGITAL DESIGN FLOW VHDL CONSTRUCTS Data Types Libraries and Packages The Entity The Architecture MODELING CONCURRENT FUNCTIONALITY IN VHDL VHDL Operators Concurrent Signal Assignments Concurrent Signal Assignments with Logical Operators

3 Contents xiii Conditional Signal Assignments Selected Signal Assignments Delayed Signal Assignments STRUCTURAL DESIGN USING COMPONENTS Component Instantiation OVERVIEW OF SIMULATION TEST BENCHES : MSI LOGIC DECODERS Example: One-Hot Decoder Example: Seven-Segment Display Decoder ENCODERS Example: One-Hot Binary Encoder MULTIPLEXERS DEMULTIPLEXERS : SEQUENTIAL LOGIC DESIGN SEQUENTIAL LOGIC STORAGE DEVICES The Cross-Coupled Inverter Pair Metastability The SR Latch The S 0 R 0 Latch SR Latch with Enable The D-Latch The D-Flip-Flop SEQUENTIAL LOGIC TIMING CONSIDERATIONS COMMON CIRCUITS BASED ON SEQUENTIAL STORAGE DEVICES Toggle Flop Clock Divider Ripple Counter Switch Debouncing Shift Registers FINITE-STATE MACHINES Describing the Functionality of an FSM Logic Synthesis for an FSM FSM Design Process Overview FSM Design Examples COUNTERS Bit Binary Up Counter Bit Binary Up/Down Counter Bit Gray Code Up Counter Bit Gray Code Up/Down Counter Bit One-Hot Up Counter Bit One-Hot Up/Down Counter FINITE-STATE MACHINE S RESET CONDITION

4 xiv Contents 7.7 SEQUENTIAL LOGIC ANALYSIS Finding the State Equations and Output Logic Expressions of an FSM Finding the State Transition Table of an FSM Finding the State Diagram of an FSM Determining the Maximum Clock Frequency of an FSM : VHDL (PART 2) THE PROCESS Sensitivity List The Wait Statement Sequential Signal Assignments Variables CONDITIONAL PROGRAMMING CONSTRUCTS If/Then Statements Case Statements Infinite Loops While Loops For Loops SIGNAL ATTRIBUTES TEST BENCHES Report Statement Assert Statement PACKAGES STD_LOGIC_ NUMERIC_STD NUMERIC_STD_UNSIGNED NUMERIC_BIT NUMERIC_BIT_UNSIGNED MATH_REAL MATH_COMPLEX TEXTIO and STD_LOGIC_TEXTIO Legacy Packages (STD_LOGIC_ARITH/UNSIGNED/SIGNED) : BEHAVIORAL MODELING OF SEQUENTIAL LOGIC MODELING SEQUENTIAL STORAGE DEVICES IN VHDL D-Latch D-Flip-Flop D-Flip-Flop with Asynchronous Reset D-Flip-Flop with Asynchronous Reset and Preset D-Flip-Flop with Synchronous Enable MODELING FINITE-STATE MACHINES IN VHDL Modeling the States with User-Defined, Enumerated Data Types The State Memory Process The Next State Logic Process The Output Logic Process Explicitly Defining State Codes with Subtypes

5 Contents xv 9.3 FSM DESIGN EXAMPLES IN VHDL Serial Bit Sequence Detector in VHDL Vending Machine Controller in VHDL Bit, Binary Up/Down Counter in VHDL MODELING COUNTERS IN VHDL Counters in VHDL Using the Type UNSIGNED Counters in VHDL Using the Type INTEGER Counters in VHDL Using the Type STD_LOGIC_VECTOR Counters with Enables in VHDL Counters with Loads RTL MODELING Modeling Registers in VHDL Shift Registers in VHDL Registers as Agents on a Data Bus : MEMORY MEMORY ARCHITECTURE AND TERMINOLOGY Memory Map Model Volatile vs. Nonvolatile Memory Read-Only vs. Read/Write Memory Random Access vs. Sequential Access NONVOLATILE MEMORY TECHNOLOGY ROM Architecture Mask Read-Only Memory Programmable Read-Only Memory Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory FLASH Memory VOLATILE MEMORY TECHNOLOGY Static Random Access Memory Dynamic Random Access Memory MODELING MEMORY WITH VHDL Read-Only Memory in VHDL Read/Write Memory in VHDL : PROGRAMMABLE LOGIC PROGRAMMABLE ARRAYS Programmable Logic Array Programmable Array Logic Generic Array Logic Hard Array Logic Complex Programmable Logic Devices FIELD PROGRAMMABLE GATE ARRAYS Configurable Logic Block (or Logic Element) Look-Up Tables Programmable Interconnect Points (PIPs)

6 xvi Contents Input/Output Block Configuration Memory : ARITHMETIC CIRCUITS ADDITION Half Adders Full Adders Ripple Carry Adder (RCA) Carry Look Ahead Adder (CLA) Adders in VHDL SUBTRACTION MULTIPLICATION Unsigned Multiplication A Simple Circuit to Multiply by Powers of Two Signed Multiplication DIVISION Unsigned Division A Simple Circuit to Divide by Powers of Two Signed Division : COMPUTER SYSTEM DESIGN COMPUTER HARDWARE Program Memory Data Memory Input/Output Ports Central Processing Unit A Memory Mapped System COMPUTER SOFTWARE Opcodes and Operands Addressing Modes Classes of Instructions COMPUTER IMPLEMENTATION: AN 8-BIT COMPUTER EXAMPLE Top-Level Block Diagram Instruction Set Design Memory System Implementation CPU Implementation ARCHITECTURE CONSIDERATIONS Von Neumann Architecture Harvard Architecture APPENDIX A: LIST OF WORKED EXAMPLES SUGGESTED READINGS INDEX

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