CONTENTS. vlsi technology and design (ECE, VLSI, VLSI SYSTEM DESIGN AND VLSI & EMBEDDED SYSTEMS) THE FUTURE OF MICROELECTRONICS... 1.

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1 Contents vlsi technology and design FOR m.tech (jntu - hyderabad) i year i semester (ECE, VLSI, VLSI SYSTEM DESIGN AND VLSI & EMBEDDED SYSTEMS) CONTENTS i UNIT - I [CH. H. - 1] ] [REVIEW OF MICROELECTRONICS AND INTRODUCTION TO MOS TECHNOLOGIES] THE FUTURE OF MICROELECTRONICS THE INTEGRATED TED CIRCUIT (IC) ERA Classification of ICs Evolution of IC Technology Advantages of ICs Moore s Law IC Manufacturing Process IC Design Challenges System Design Cycle Transistor Modeling Integration of Technologies METAL AL OXIDE SEMICONDUCTOR OR (MOS) VLSI TECHNOLOG OGY Basic MOS Transistors ransistors Enhancement Mode Transistor Action Depletion Mode Transistor Action nmos FABRICATION CMOS FABRICATION The P-Well Process

2 ii Contents The N-Well Process The Berkely n well Process Twin Tub Process rocess Silicon On Insulator (SOI) Process Thermal Aspects of Processing BICMOS TECHNOLOGY BiCMOS Fabrication in n-well Process Production of E-Beam Masks BASIC ELECTRICAL PROPERTIES OF MOS, CMOS AND BICMOS CIRCUITS I ds -V ds Relationships elationships The Non-Saturated Region The Saturated Region I ds Vs V ds Graph for Depletion Mode I ds Vs V ds Graph for Enhancement Mode THRESHOLD VOLTAGE GE AND BODY Y EFFECT Threshold Voltage (V t ) Body Effect MOS TRANSISTOR OR TRANSCONDUCTANCE ANCE (g M ) AND OUTPUT CONDUCTANCE ( DS ) MOS TRANSISTOR OR FIGURE OF MERIT ( ω O ) PASS TRANSISTOR OR DESIGN OF NMOS INVERTER WITH DIFFERENT LOADS nmos Inverter With Resistive Load nmos Inverter With Depletion Mode nmos as a Load Z p.u p.d Ratio for an nmos Inverter Driven by Another nmos Inverter Z p.u p.d Ratio for an nmos Inverter Driven Through One (or) More Pass Transistors ransistors

3 Contents iii 1.13 ALTERNA TERNATIVE TIVE FORM OF PULL-UP nmos Enhancement Mode Transistor Pull Up Complementary Transistor Pull Up CMOS INVERTER ANALYSIS AND DESIGN SOME CHARACTERISTICS CTERISTICS OF NPN BIPOLAR TRANSISTORS BICMOS INVERTER MOS TRANSISTOR CIRCUIT MODEL LATCH UP IN CMOS CIRCUITS Expected University Questions with Solutions UNIT - II [CH. - 2] ] [LAYOUT DESIGN AND TOOLS] INTRODUCTION TRANSISTORS Structure of the Transistor A Simple Transistor Model Transistor Parasitics arasitics Oxide Junction Capacitances Tub ub Ties ies and Latchup Advanced Transistor Characteristics Leakage and Subthreshold Currents Advance Transistor Structures Spice Models WIRES AND VIAS Wire Parasitics arasitics Skin Effect in Copper Interconnect

4 iv Contents 2.4 DESIGN RULES Lambda-Based Design Rules (Scabble Design Rule) Lambda Based Design Rules for Conducting Paths Lambda Based Design Rules for Transistors Lambda Based Design Rules for Contact Cuts Double Metal MOS Process Rules SCMOS Design Rules Typical Process Parameters arameters LAYOUT DESIGN AND TOOLS Layouts for Circuits Stick Diagram Hierarchical Stick Diagrams layout Analysis Tools (CAD Tool) ool) Automatic layout Tools Expected University Questions with Solutions UNIT - II [CH. - 3] ] [LOGIC GATES AND LAYOUTS] INTRODUCTION Combinational Logic Functions STATIC TIC COMPLEMENTAR ARY Y GATES TES Gate Structures Basic Gate Layouts Logic Levels Delay and Transition Time Power Consumption The Power Delay Product Layout and Parasitics

5 Contents v Driving Large Loads Cascaded Inverters as Drivers Super Buffers BiCMOS Drivers SWITCH LOGIC Transmission Gates ALTERNA TERNATIVE TIVE GATE CIRCUITS Pseudo nmos Logic DCVS Logic Dynamic CMOS Logic CMOS Domino Logic Clocked CMOS Logic n-p CMOS Logic LOW POWER GATES INTERCONNECTED DELAY Y MODELLING Delay Through Resistive Interconnect RC Delay Model The Elmore s Model Delay Through RC Trees rees Buffer Insertion in RC Transmission Lines Crosstalk Between RC Wires Delay Through Inductive Interconnect RLC Basics RLC Transmission Line Delay Buffer Insertion in RLC Transmission Lines Expected University Questions with Solutions

6 vi Contents UNIT - III [CH. H. - 4] ] [COMBINATIONAL LOGIC NETWORKS] INTRODUCTION STAND ANDARD ARD CELL BASED LAYOUT Single Row Layout Design Standard Cell Layout Design SIMULATION Simulation Efficiency Advantages of Simulation Applications of Simulation COMBINATIONAL NETWORK DELAY Fanout Path ath Delay Transistor Sizing Transistor Sizing in an Adder Carry Chain Example Transistor Sizing with Logic Effort Example Automated Logic Optimization Flattening Structuring LOGIC AND INTERCONNECT DESIGN Delay Modeling Buffer Insertion Wire Sizing Crosstalk Minimization POWER OPTIMIZATION TION SWITCH LOGIC NETWORKS COMBINATIONAL LOGIC TESTING Gate Testing Combinational Network Testing Expected University Questions with Solutions

7 Contents vii UNIT - IV [CH. H. - 5] ] [SEQUENTIAL SYSTEMS] INTRODUCTION LATCHES AND FLIP-FL -FLOPS Categories of Memory Elements Latches Flip-Flops SYSTEM TIMING CONSIDERATION COMMONLY USED STORA ORAGE/ MEMORY ELEMENTS (MEMORY CELLS) Dynamic Shift Register Dynamic Ram am Cell (Three Transistors) One Transistor Dynamic Memory Cell Pseudo Static Ram / Register Cell Four Transistor Dynamic and Six Transistor Static CMOS Memory Cells JK Flip-Flop D Flip-Flop ARRAYS YS OF MEMORY Y CELLS x 4 Bit Register Array Ram Arrays Read Only Memory (ROM S) SEQUENTIAL SYSTEMS AND CLOCKING DISCIPLINES One-Phase Systems for Flip-Flops Two wo-phase Systems for Latches Shift Register Design Example Advanced Clocking Analysis Clock Generation

8 viii Contents 5.7 SEQUENTIAL SYSTEM DESIGN Structural Specification of Sequential Machines State Transition Graphs and Tables ables State Assignment POWER OPTIMIZATION TION DESIGN VALIDATION SEQUENTIAL TESTING Expected University Questions with Solutions UNIT - V [CH. H. - 6] ] [FLOOR PLANNING] INTRODUCTION FLOOR PLANNING METHODS Block Placement and Channel Definition Block Placement Channel Definition Global Routing Switchbox Routing Power Distribution Clock Distribution Floorplanning Tips Design Validation OFF CHIP CONNECTIONS Packages Die Separation Package Types Wire Bonding Tape Automated Bonding Flip-Chip Bonding The I/O Architecture Pad Design Expected University Questions with Solutions

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