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- Άιμον Γαλάνης
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1 SVO TV LVS VGA Mero ufp RT Port H (SATA) O (PATA) Finger USB6 Page 9 Page 6 Page 6 USB Port x USB0~ Page 7 Bluetooth USB Page L ONN (."WXGA) Page 0 VI / 707 hrontel (only for ezock) Page S-VIEO ONN Page 0 LOK GENERATOR K505 Page ZU SYSTEM
2 lock Generator EA:(/6) hange 5 from 0805(H60K9A0 +V L55 88.U_ BKP608HS8-T_ _6 9.U_ *.7U_6 R6 0U_6 87 0U_8 AA:(9/) IS FAE suggest to change 50.U_ U9 <escription> 5,87 from.7uf to 0uF V_K_V_PI 9.U_ V_K_V_8 V_PI IO_V 9 AA:(9/8) V_K_V_SR V_8 6 Reverse R060 footprint for EMI V_K_V_REF V_PLL 6 V_REF K505 0_6 9.U_ V_K_V_SR 9 R99 V_K_V_PU V_SR S 55 V_PU S +.5V_V 0_6 8.U_ V_96_IO 0 R V_PLL_IO 6 V_SR_IO_ 5 V_SR_IO_ 6 V_SR_I 9 V_PU AA:(9/0) remove SATALKREQ function, change R88 value from 75ohm to ohm R88 _ PI_LK_50_R PI_LK_50 R _ PI_LK_B7_R PI_LK_B7 +V R9 0K_ R _ PLK_9_R 5 PLK_9 R87 _ PLK_59_R 8 PLK_59 +V R8 *0K_ R _ PI_LK_ 7,0 PI_LK_SIO R7 0K_ R86 _ PLK +V R8 *0K_ 5 PLK_IH R8 0K_ R0 6 LKUSB_8 LK_BSEL0 R6.K_ LK_BSEL LK_BSEL R 0K_ FS R _ 6 M_IH R _ 0 SIO_M AA:(9/) FAE : (M_IH and SIO_M) signals trace shoul AA:(9/) IS FAE suggest AA:(9/0) change R86 value from ohm t A:(/6) Base on vendor change 0/99 from H 0
3 B TP_PU_RSV05 H_A# TP_PU_RSV0 TP_PU_RSV H_A#9 H_A# H_A# H_A#5 H_REQ# H_REQ# H_A#7 H_A#0 H_A# H_A# H_A#5 TP_PU_RS H_A#8 H_A#9 TP_PU_ H_A#6 H_A#7 H_REQ#0 H_REQ# H_REQ# H_A#8 H_A# H_A#6 H_A#7 H_A#0 H_A# TP_P H_STPLK_R# H_A#8 H_A#9 H_A#0 TP_PU_RSV0 H_A# H_A# TP_PU_RSV0 H_A# H_A# H_A#5 H_A#6 TP_PU_RSV0 TP_PU_RSV0 H_A# H_A# H_A# H_A#5 XP_TRS H_IERR# XP_TMS XP_TI XP_TK XP_ H_A#[6:] 5 H_ASTB0# 5 H_REQ#[:0] 5 H_A#[5:7] 5 H_ASTB# 5 H_A0M# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# H_FERR# H_#[5:0] 5 H H_INI +.05V PU(HOST) T9 T9 T50 T50 T56 T56 A[0]# N A[]# P5 A[]# P A[]# L A[]# P A[5]# P A[6]# R A[7]# Y A[8]# U5 A[9]# R A[0]# W6 A[]# U A[]# Y5 A[]# U A[]# R A[5]# T5 A[6]# T A[7]# W A[8]# W5 A[9]# Y A[]# J A[0]# U A[]# V M N5 T A[]# L5 A[5]# L A[6]# K5 A[7]# M A[8]# N A[9]# J A0M# A6 AS# H ASTB[0]# M ASTB[]# V BNR# E BPM[0]# A BPM[]# A BPM[]# A BPM[]# A BPRI# G5 BR0# F BR# 0 BSY# E EFER# H5 RY# F FERR# A5 HIT# G6 HITM# E IERR# 0 IGNNE# INIT# B LINT0 6 LINT B LOK# H PRY# A PREQ# A PROHOT# REQ[0]# K REQ[]# H REQ[]# K REQ[]# J REQ[]# L RESET# RS[0]# F RS[]# F RS[]# G SMI# A STPLK# 5 TK A5 TI AA6 TO AB THERM THERMA THERM TMS AB5 TRY# G TRST# AB6 A[]# W A[]# AA A[]# AB A[5]# AA AR GROUP 0 AR GROUP ONTROL XP/ITP SIGNALS THERMAL IH U0A AR GROUP 0 AR GROUP ONTROL XP/ITP SIGNALS THERMAL IH U0A T55 T55 R7 0_ R7 0_ T08 T08 T5 T5 T5 T5 T5 T5 T5 T5 T8 T8 R09 56._ R09 56._
4 + 98 0U_7 AA:(0/) stuff 98, unstuff (base on layout location) <heck list> Option:0U*6(ESR=.5m ohm Option:0U*6(ESR=.5m o 56 0U_8 9 0U_8 0U_ U_8 0U_ U_8 0U_ U_8 H600ME <escripti 50 0U_ U_8 78 0U_8 0U_8 0U_8 80 0U_8 0U_ U_8 50 0U_8 5 0U_8 ESIGN GUIE HANGE FROM UF *0 0U_ U_8 0U_ U_8 0U_8 V_ORE PU(Power) 9 0U_8 0U_ U_8 5 0U_8 5 0U_8 A A A5 A7 A8 A V U_ U_8 0U_8 0U_8 A7 A9 A0 U0 V[00] V[00] V[00] V[00 V
5 R V_GMH.9_ R95 H_ROMP <check list> 0:0 mils(wid 7.U_ H_SWING NB(HOST) H_ H_# H_# H_# H_# H_#5 H_#6 H_#7 H_#8 H_ H <check list> 0.U close to B R86 _ R85 00_ A:(/) hange 965GM from ES sample to QS sample hange U9 P/N from AJ0QN0T7 to AJ0QP00T09 H_#[6:0] +.05V_GMH
6 B MH_RSV MH_RSV MH_RSV MH_RSV MH_RSV5 MH_RSV6 MH_RSV7 MH_RSV9 MH_RSV0 MH_RSV MH_RSV MH_RSV MH_RSV8 MH_RSV7 MH_RSV0 MH_RSV MH_RSV MH_RSV MH_RSV MH_RSV5 MH_RSV6 MH_RSV8 MH_RSV9 MH_RSV0 MH_RSV MH_RSV MH_RSV MH_RSV5 MH_RSV6 MH_RSV7 MH_RSV8 MH_RSV9 MH_RSV0 MH_RSV MH_RSV MH_RSV MH_RSV5 MH_ MH MH_RSV M M_ M_LK M_ M_K M PM 6,6,5 MH_BSEL0 MH_BSEL MH_BSEL MH_FG_9 MH_FG_,,5 MH_FG_5 MH_FG_9 MH_FG_ MH_FG_ MH_FG_6 M_A_A, M_B_A, A:(/6) Intel schematic Rev.5: change ball-8 from RSV8 to LVSA_ATA#_ change ball-7 from RSV7 to LVSA_ATA_ change ball-b from RSV9 to LVSB_ATA#_ change ball- from RSV0 to LVSB_ATA_ T87 T87 T8 T8 T7 T7 T T T0 T0 T T T7 T7 T8 T8 T6 T6 T98 T98 T T T6 T6 T8 T8 SM_K_0 AV9 SM_K_ BB RSV8 BF SM_K_ BA5 SM_K#_0 AW0 SM_K#_ BA RSV9 BG SM_K#_ AW5 SM_KE_0 BE9 SM_KE_ AY SM_KE_ B9 SM_KE_ BG7 SM_S#_0 BG0 SM_S#_ BK6 SM_S#_ BG6 SM_S#_ BE RSV BH9 SM_OT_0 BH SM_OT_ B SM_OT_ SM_OT SM_R SM_ RSV0 AR7 RSV AL6 RSV AM6 RSV AM7 RSV BJ0 RSV BK RSV BF9 RSV5 BH0 RSV6 BK8 SM_K_ AV SM_K#_ AW RSV0 B RSV B RSV5 AW0 RSV6 BK0 RSV5 AR RSV6 AR RSV7 AM RSV8 AN RSV P6 RSV P7 RSV R5 RSV N5 RSV7 BJ8 SM_ S RSV9 J RSV7 8 RSV8 7 RSV9 B RSV0 RSV BJ9 RSV BE RSV B5 RSV 0 RSV0 H0 RSV A5 RSV B7 RSV B6 RSV B RSV R MUXING RSV U9B R MUXING RSV U9B T T T90 T90 T5 T5 T7 T7 T T T6 T6 T96 T96 T9 T9 T T T T T89 T89 T9 T9 T T T T T85 T85 T95 T95 T5 T5 T86 T86 T5 T5 T8 T8 T T T0 T0 T0 T0 57.U_ 57.U_ T9 T9 T T T T T0 T0 T8 T8 T9 T9 T88 T88 T5 T5 T8 T8
7 B M_A_Q M_A_Q M_A_Q M_A_Q M_A_Q5 M_A_Q6 M_A_Q7 M_A_Q8 M_A_Q9 M_A_Q0 M_A_Q M_A_Q M_A_Q M_A_Q M_A_Q5 M_A_Q6 M_A_Q7 M_A_Q8 M_A_Q9 M_A_Q0 M_A_Q M_A_Q M_A_Q M_A_Q M_A_Q5 M_A_Q6 M_A_Q7 M_A_Q8 M_A_Q9 M_A_Q0 M_A_Q M_A_Q M_A_Q M_A_Q M_A_Q5 M_A_Q6 M_A_Q7 M_A_Q8 M_A_Q9 M_A_Q0 M_A_Q M_A_Q M_A_Q M_A_ M_A M M_A_Q0 M_A_ M_A M M_A_Q[6:0] NB(Memory controller) SA_Q_0 AR SA_Q_ AW SA_Q_0 BG7 SA_Q_ BJ5 SA_Q_ BB7 SA_Q_ BG50 SA_Q_ BH9 SA_Q_5 BE5 SA_Q_6 AW SA_Q_7 BE SA_Q_8 BG SA_Q_9 BE0 SA_Q_ BA5 SA_Q_0 BF SA_Q_ BH5 SA_Q_ BG0 SA_Q_ BF0 SA_Q_ AR0 SA_Q_5 AW0 SA_Q_6 AT9 SA_Q_7 AW6 SA_Q_8 AW SA_Q_9 AY SA_Q_ AY6 SA_Q_0 AV8 SA_Q_ AT8 SA_Q AV SA_ AT S AW AV AU5 AT B SA_Q_ AR SA_Q_5 AR5 SA_Q_6 AT SA_Q_7 AW7 SA_Q_8 BB5 SA_Q_9 BF8 SA_BS_0 BB9 SA_BS_ BK9 SA_BS_ BF9 SA_AS# BL7 SA_M_0 AT5 SA_M_ B SA_M_ B SA_M_ AW8 SA_M_ AW SA_M_5 BG8 SA_M_6 AY5 SA_QS_ SA_QS SA_ SA S SA_M_7 AN ORY A U9 ORY A U9
8 B +.05V_V_GMH_V +.8VSUS_GMH +.05V_V_GMH +.8VSUS NB(Power-) R7 0_ R7 0_ + 0U_7 + 0U_7 V_5 A V_6 AK V_7 AJ V_8 AJ8 V_9 AH V_0 AH V_ AH9 V_ AF V_ AT V_ A AW5 AY B V_ AU V AU5 V_AXG V_AX V_ V V V_AXG_NTF_ T8 V_AXG_NTF_ T9 V_AXG_NTF_ T V_AXG_NTF_5 V_AXG_NTF_ V_AXG_NT V_AXG_N V_AXG_ V AV AW V_AXG_NTF_ T7 V_ AT5 V_SM AU V_ R0 V_ AH8 V ORE U9G V ORE U9G 5 U_8 5 U_8 U_8 U_8 0.U_ 0.U_
9 +V V VQ_ VA_A_ VA B:(/9) change from H700MJ8 L5 BKP608HS8-T_ V 65 U_8 +.5V BKP608HS8-T_6 L50 69 U_8 BKP608HS8-T_6 L9 V.5M_MPLL_R R8 0.5_6 R L5 0UH_8 <escription> U_7 +.5V +.5V 8.U_ 6.U_ +V_TV_A NB(Power-) <escription> L5 0UH_ U_7 6.U_ +V_VSYN +V R0 0_6 05 <FAE> INT VGA disable.u_ VSYN connect to GN +V L8 BKP608HS8-T_ R *U_8.U_ N_ *0_ R8 0_ R.U_ N_
10 B NB(Power-) VSS_ A VSS_ A5 VSS_ A7 VSS_ A VSS_5 AA VSS_6 AA VSS_7 AA9 VSS_8 AB0 VSS_9 AB VSS_0 AB6 VSS_ AB8 VSS_ AB VSS_ A0 VSS_ A VSS_5 A VSS_6 A9 VSS_7 A VSS_9 A VSS_0 A VSS_ A6 VSS_ A9 VSS_ A VSS_ A VSS_5 A5 VSS_6 A9 VSS_7 A5 VSS_8 A50 VSS_9 A8 VSS_0 AE0 VSS_ AE VSS_ AE6 VSS_ AF0 VSS_ AF VSS_5 AF VSS_6 AF VSS_7 AG VSS_8 AG8 VSS_9 AG VSS_0 AG7 VSS_ AG50 VSS_ AH VSS_ AH0 VSS AH VS AH7 AH9 AJ AJ A VSS_00 AW VSS_0 AW9 VSS_0 AW VSS_0 AW5 VSS_0 AW7 VSS_05 AY0 VSS_06 AY VSS_07 AY7 VSS_08 AY VSS_09 AY VSS_0 AY5 VSS_ AY7 VSS_ AY50 VSS_ B0 VSS_ B0 VSS_5 B VSS_6 B9 VSS_7 B0 VSS_8 B5 VSS_9 B8 VSS_0 B VSS_ B6 VSS_ B5 VSS_ B8 VSS_ BA VSS_5 VSS_6 VSS_ VSS V VSS_8 A7 VSS U9I VSS U9I
11 MI FG FG6 FG[8:7] SVO_TRLATA FG9 FG[5:] FG[:0] FG[:] FG9 Rese FG8 FG7 Reserved XOR/ALLZ FG6 FG5 All strap are sampled with respect to the leading edge of the GMH Power OK(P FG[7:] Have internal Pull-up FG[8:9] Have internal Pull-down Any signal strapping option not list below should be left N Pin Pin Name Strap description FG[:0] FSB Frequency Select 00 0 FG[:] Reserved MI X Select Reserved PU Strap Low power PI Express PI Express Graphics Lane Strap table
12 M_A_ M_ 7, 6, 6, B M_KE M_A_A7 M_A_A5 M_A_A M_A_A.U_ SMR_VTERM 60.U_ A RP6 9.U_ 6 5.U_ 8.U_ R ual channel A/B PU RII A HANNEL 7 6.U_.U_.U_
13 A B M_A_M M_A_QS M_A_QS# M_ M_A_Q M_A_A M_A_Q M_A_A M_A_A5 M_A_QS M_A_ M_A_Q8 M_A_M M_A_M0 M_A_Q5 M_A_Q9 M_A_Q M_A_Q M_A_Q8 M_A_A8 M_A_Q M_A_Q M_A_Q9 M_A_QS0 M_A_Q9 M_A_Q5 M_A_Q M_A_Q0 M_A_Q M_A_Q6 M_A_QS#0 M_A_Q M_A_Q8 M_ M_A_Q M_A_Q7 M_A_QS M_A_QS# M_A_Q M_A_Q5 M_A_M M_A_Q6 M_A_Q0 M_A_ M_A_Q M_A_Q0 M_A_Q M_A_Q7 M_A_Q6 M_A_Q7 M_A_A M_A_A9 M_A_A0 M_A_Q[0..6] 7 M_A_M[0..7] 7 M_A_A[0..] 7, M_A_WE# 7, M_S# 6, M_A_AS# 7, M_A_QS#[0..7] 7 M_OT 6, M_LK_R0 6 M_LK_R#0 6 M_A_QS[0..7] 7 M_KE0 6, M_A_BS# 7, P M_A_BS#0 7, SMR_VREF_IMM +.8VSUS +.8VSUS R ual channel A/B ONN VREF VSS7 Q0 5 Q 7 VSS7 9 QS#0 QS0 VSS8 5 Q 7 Q 9 VSS8 Q8 Q9 5 VSS9 7 QS# 9 QS VSS9 Q0 5 Q 7 VSS50 9 VSS8 Q6 Q7 5 VSS 7 QS# 9 QS 5 VSS9 5 Q8 55 Q9 57 VSS 59 Q 6 Q5 6 VSS 65 M 67 N 69 VSS9 7 Q6 7 Q7 75 VSS 77 KE0 79 V7 8 N 8 A6_BA 85 V9 87 A 89 A9 9 A8 9 V5 95 A5 97 A 99 A 0 V0 0 A0/A 05 BA VSS6 Q Q5 6 VSS5 8 M0 0 VSS5 Q6 Q7 6 VSS6 8 Q 0 Q VSS7 M 6 VSS5 8 K0 0 K0# VSS Q 6 Q5 8 VSS5 0 VSS0 Q0 Q 6 VSS6 8 N 50 M 5 VSS 5 Q 56 Q 58 VSS 60 Q8 6 Q9 6 VSS5 66 QS# 68 QS 70 VSS0 7 Q0 7 Q 76 VSS8 78 KE 80 V8 8 A5 8 A 86 V 8 A P800 R SRAM SO-IMM (00P) N5 P800 R SRAM SO-IMM (00P) N5
14 SATA isable.onnect to GN: S.N: SATA[:0]T.VccSATAPLL.BIOS disab 5K_ R06.7K_ R0 R0.K_6 +5VPU VRT_ VRT HANGE FROM 8PF H500H-0 VRT 8 U_6 TO 0PF <check list> elay 8~5ms 58 0P_ VRT_ H500H-0 R0 0K_6 R05 R6 G 6 Y R K_ U_6.768KHZ 0M_ M_6 *SHORT_PA 57 0P_ N AS_ L AA: (9/) change RT ONN (follow Z) MOS Setting G lear MOS Short Keep MOS Open VRT_ EA:(/0) The GLAN_ remains Stuff R00 K_ VRT_ Q MMBT90 RT +VPU
15 SB-PI,,5 A[0..] SB-PIE/USB/MI U PIE_RXN P7 PERN MI0RXN V7 PIE_RXP P6.U_ PIE_TXN_ PERP MI0RXP V6 PIE_TXN N9.U_ PIE_TXP_ PETN MI0TXN U9 PIE_TXP N8 PETP MI0TXP U8 to ocking M7 PERN MIRXN Y7 M6 PERP MIRXP Y6 L9 PETN MITXN W9 L8 PETP MITXP W8 8 PIE_RXN K7 PERN MIRXN AB6 MI_R 8 PIE_RXP K6 M to LAN 5.U_ PIE_TXN_ PERP MIRXP AB5 8 PIE_TXN J9.U_ PIE_TXP_ PETN MITXN AA9 8 PIE_TXP J8 PETP MITXP AA8 7 PIE_RXN H7 PERN MIRXN A7 7 PIE_RXP H6 7.U_ PIE_TXN_ PERP MIRXP A6 7 PIE_TXN G9 6.U_ PIE_TXP_ PETN MITXN A9 7 PIE_TXP G8 PETP MITXP A8 to WLAN F7 PERN5 MI_LKN T6 F6 PERP5 MI_LKP T5 E9 PETN5 E8 PETP5 MI_ZOMP MI_IROM 7 PERN6/GLAN_RXN 6 PERP6/GLAN_RXP U 9 PETN6/GLAN_TXN 8 PETP6/GLAN_TXP AA: 9/ remove SPI interface T SPI_LK A:(/) Add test point for ASF function T B SPI_S0# T E SPI_S# T SPI_MOSI T5 F SPI_MISO USBO#0 AJ9 USBO# O0# AG6 USBO# O AG5 USBO# AE5 USBO# AF USBO#5 AG USBO#6 USBO#7 USBO#8 USBO#9 PI-Express irect Media Interface MI_ MI_R MI_TXN MI_TXP
16 AA:(9/9) no support iamt, remove N_MBLK, 6 MH_IH_SYN# SB-GPIO PLK_SMB,,8,7, PLK_SMB AJ PAT_SMB,,8,7, PAT_SMB A9 L_RST# 7 L_RST# AG A:(/) ASF issue:when iamt is not implemented, PLK_SMB R7 0_ SMLINK0 L A7 IH8M SMBus and SMLink should be connected together to support slave mode PAT_SMB R75 0_ SMLINK SML AE9 onnect SMLINK0 to SMBLK and SMLINK to SMBATA (Add R7,R75 for debug use) SMLIN AA:(9/9) no support iamt, remove SMB_LK_ME,SMB_ATA_ME RI# AF7 +V AA: (9/) Remove RI# RI# 0 LP_P# F SYS_RST# SUS_STAT#/LP SYS_RST# A5 SYS_RESET# 6 PM_BMBUSY# AG R56 R5 BMBUSY#/GPIO0 *0K_ *0K_ SMB_ALERT# AG SMBALERT#/GP R59 0_ PM_STPPI_IH# PM_STPPI# AE0 R60 0_ PM_STPPU_IH# STP_PI#/G PM_STPPU# AG8 STP_PU +V LKRUN# AA: (9/6) change name from VR_PWRG_LKEN# 8,0 LKRUN# AH LKR to VR_PWRG_K0# 8.U_ PIE_WAKE# 8,7 PIE_WAKE# AE7 U SERIRQ,,8,0 SERIRQ AF 5 THERM_ALERT# THERM_ALERT# A 5 VR_PWRG_K0# VR_PWRG_LKEN N7SZ0 R50 00K_ T0 IH_TP7 B: (/) add, to stop leakage from E to SB KBSMI# BAS6 KBSMI#_IH 8 KBSMI# LI59# BAS6 LI59#_ 0,8,9 LI59# T0 GPIO7 B:(/8) change OKIN# from GPIO7 to GPIO SI# 8 SI# OKI 8, OKIN# BOAR_I0 BAS6 BOAR_I T8 T +V AA: (9/6) Remove SATALKREQ# 6 RST_H# R68 *0K_ <check list> AZ_ internal P R69 0_
17 R50 0_8 +.5V U_7 U_8 AA: (9/0) hange back R89 to 0 ohm +.5V_SATA R89 0_8+.5V_APLL_RR L60 0UH_8 V000MN U_6 +.5V L56 Intel use 0.5UH inductor 0.U_ FBMJ5HS0-T_8 +.5V_PIE +5V_S5 R 0_6 +.5V_APLL 96 U 6 U_8 +5V PZ5.6B H H J J K V_5_ V_ V V V V V V V +V VRT U_.U_.U_ UF A5 PZ5.6B VRT A6 R66 00_6 +5VREF_SB V5REF[] T7 V5REF[] 85 +5VREF_SUS_SB G V5REF_SUS.U_ AA5 V_5_B[0] AA6 V_5_B[0] AA7 V_5_B[0] AB7 V_5_B[0] AB8 V_5_B[05] AB9 V_5_B[06] 8 V_5_B[07] 9 V_5_B[08] E5 V_5_B[09] E6 V_5_B[0] E7 5 V_5_B[ F F5.U_6 G +V_S5 5
18 B +V_S5 Q7 TEUA R80.7K_ PIE_WAKE_R# 6,7 PIE_WAKE# 5 PIE_RXP 5 PIE_RXN 5 PIE_TXP 5 PIE_TX 5,6,,5,6,7,8,0, P AA:(9/ BM recommend) LK_P Pull up Vmainprsnt (U0/Pin5) to the system main power (.v), LK but not the standby power. R806 *0_ 8 LOW_PWR A:(/) Add ablesence cir EA:(/) Stuff R78 (isab EA:(/0) Base on PM sug add serial 0 (default : L9 BLM VAUX_ Giga LAN BN5787M AA:(9/7) hange +V_LAN_S5 to +V_S5 6 8.U-6V_.U-6V_.U-6V_.U-6V_ 7.7U-0V_8 67.U-6V_ 79.U-6V_.U-6V_ VAUX_ 9 VAUX_ L0 BLMA60S_6 58 L BLMA60S_6 L BLMA60S_6.U-6V_ 89.U-6V_.7U-0V_8 57 VAUX_ 5 AV +V_S U-0V_8.U-6V_ U0 BM5787MKML
19 SYS_VGA_RE SYS_VGA_GRN SYS_VGA_BLU RT ONNETOR AN ES +5V A:(/) EMI suggest add 65 B LOW HIGH SEL IN_ 0, 6 PR_INSERT_5V FUNTION IN_0 A U INT_RT_RE _A A0 INT_RT_GRN A 7 _B B0 INT_RT_BLU B 6 9 _ 0 0 _ 0 PR_INSERT_5V SE 5 EN# GN 8 SN7BTLV57PWR AA: (9/0) Remove NEZ@ ciucuit 6 6 INT_RT_RE INT_RT_GRN INT_RT_BLU RT Select A:(/) R OK_R OK_G OK_B SYS_VGA_RE SYS_VGA_GRN SYS_VGA_BLU V 6 5
20 6 TV Out (SVHS) MiniIN 7-pin <demo circuit> restline suggest 00K G7 suggest 0K(ZS efault) 8/7 change back to 00K INT_LVS_IGON N LVS 6 INT_TXLOUT- INT_TXLOUT- INT_TXLOUT+ 6 INT_TXLOUT+ B: (/0) 5 () change PWM control from 965GM to E INT_TXLOUT- 5 6 INT_TXLOUT- 7 () Short L7, un-stuff 8 (L- filter will impact PWM signal) 6 INT_TXLOUT+ INT_TXLOUT+ 7 9 ()stuff R,no stuff R5 9 6 INT_TXLOUT0- INT_TXLOUT0- A:(/8) EMI request: reserve L- footprint for debug use (R5,650) 6 INT_TXLOUT0+ INT_TXLOUT0+ 5 A:(/) Stuff R5, hange PWM control from E to 965GM 5 7 A:(/) Acer inform no support PST in build, remove R5 INT_TXLLKOUT- 7 6 INT_TXLLKOUT- 9 EA:(/)hange MB L conn INT_TXLLKOUT+ 9 6 INT_TXLLKOUT+ (Inverter short with ()pin 7,9->N INT_LVS_EILK 6 INT_LVS_EILK 5 ()pin 8,0->INV(VIN T 5 7 ()pin 8->INT_LVS_EIA T 7 9 AA:(0/) change from USB7 to USB8 R0 0_ USBP8-_N 9 5 USBP8- R9 0_ USBP8+_N 5 USBP8+ 6 AA: (9/0) ome from 965GM for PWM control INT_LVS_EIATA 6 6 INT_LVS_EIATA 8 R5 *0_ ISPON 8 6 INT_LVS_PWM 0 R 0_ VAJNEW 0 8 ONTRAST 8 *.U_ +V 6 _POWER 6 8 MI-LK R5 0_ MI-LK_ 8 MI-LK 0 MI- 0 EA:(/5) Link 650 from MI-LK to MI-LK_ MI- 650 LV *0P_ 6 VIN R8 0_8 INV V AS_ U-5V_0 000P_ 000P_ AA(0/5):hange from H60M9900 to H600ME5 (refer to Z) EA:(/) EOL issue change from H600ME5 to H600M98 AA: +V (9 U.U_ 6 IN OUT IN GN ISP_ON ON/OFF AAT80 R 00K_
21 +.5V 9.U_ 87.U_ L6 BLMA60S_6 L7 BLMA60S_6 +V VI_V.U_ 8 0U_8 08 0U_8 6 SVOB_R+ 6 SVOB_R- 6 SVOB_G+ 6 SVOB_G- 6 SVOB_B+ 6 SVOB_B- 6 SVOB_LK+ 6 SVOB_LK- V AS->Address Select (Internal pull-up) This pin determines the serial port address of the device (0,,,,0,0,AS*,0). When is low the address is 7h, when high the address is 70h. +.5V R6 0K_ R6 *0 5,6,8,5,6,7,8,0, PLTRST# VI_AV_PLL 5 6 SVO_TRLLK 6 SVO_TRLATA OK OK_ SVO-VI VI_AV
22 .7U_6 PLK_ R 8.U_ 8.U_ 5,,5 A[..0] +5V +V U8 +V V0# V# V0# SHN# 6 V# VPP0 5.V VPP AV AVPP.V AV 5 5V AV 6 5V AV 7 GN AVPP 0 8 O# V 9 ENE P- AV AVPP AV U_6.U_.7U_6 +5V + VPP0 VPP.U_ 55 A[..0] 56.U_.U_ 5 A0 A A 5,,5 95.U_.U_ +V STOP# PERR# SERR# 5,,5 PI_LK_B7 R90 *_ 57.U_ B_RSMRST# INTA# 5 INTA# SERIRQ 6,,8,0 SERIRQ PI_PME# R5 0_ PM_PME# 5,,5 PI_PME# PMSPK_ELAY R805 0_ PMSPK R80 *0_ REQ0# 5 REQ0# GNT0# 5 GNT0# A7 R89 7_ P PIRST# PIRST# PI_LK_B7 FRAME# IRY# TRY# EVSEL# STOP# PERR# SERR# 5,,7 PI_LK_B7 5,,5 FRAME# 5,,5 IRY# 5,,5 TRY# 5,,5 EVSEL# 5,,5 0.U_ 5.U_ 5
23 5,,5 A0 A A A A A5 A6 A7 A8 A9 A0 A A A[..0] A[..0] I Select : A8 Interrupt Pin : INTB# Request Indicate : REQ# Grant Indicate : GNT# AA:(9/) no stuff R96,R5 GRST# should connect to Power On reset if support S +V_RV R96 *0_ XRE#/MSLK R SWP S#
24 B XBSY# XRE#/MSLK_R XE# XLE/SAT XALE/SM XWE#/SLK_R XWP# XATA/MSBS XATA0/SAT XLE/SAT XATA/SAT XALE/SM XRE#/MSLK_R XATA/MSATA MSINX# XATA5/MSATA XATA/MSATA0 XATA6/MSATA XATA/MSBS XWE#/SLK_R XATA7/SAT0 XATA/MSATA0 XATA/MSATA XATA/SAT XATA0/SAT XATA5/MSATA XATA6/MSATA XATA7/SAT0 X# S# SWP MSINX# S# SWP XBSY# XE# XLE/SAT XALE/SM XWP# XATA0/SAT XATA/MSBS XATA/MSATA0 XATA/MSATA XATA/SAT XATA5/MSATA XATA6/MSATA XATA7/SAT0 X# XWE#/SLK +V_RV Main Source:TTN FH6MR000 nd Source:NorthStar FHS6FR00 x- 9 x-e x-re MS-BS x-we 6 MS-ATA 6 MS-SLK 5 x-r/b MS-INS 7 MS-ATA 0 MS-ATA 8 x-wp 7 MS-ATA0 9 MS-V x-ale 5 x-le x-0 8 in-gn S-M in-gn S-V S-AT 0 S-AT S-LK S-AT0 5 x- 6 x- 7 x- 8 S-AT 9 x- 0 x N5 N5
25 B A A A A0 A9 A8 A7 A6 A5 A A7 A8 A9 A A5 A A6 A0 R R0 XI XO FILTER FILTER0 G_RST# A5 PLTRST# INTE# 5 PLK_9 GNT# 5 REQ# 5 PI_PME# 5,, A[0..] 5,, BE# 5,, BE# 5,, FRAME# 5,, IRY# 5,, TRY# 5,, EVSEL# 5,, STOP# 5,, PERR# 5,, SERR# 5,, PAR 5,, BE# 5,, 5,6, +V +V +V A:(/6) Base on vendor-fe change 580/579 from H006JB05 Y5.576MHZ Y5.576MHZ 609.U-0V_ 609.U-0V_ R50.7K_ R50.7K_ 57.U-0V_ 57.U-0V_ 579 P-50V_ 579 P-50V_ GN PI_/BE# VP PI_ISEL PI_A 5 PI_A 6 V 7 PI_A 8 PI_A0 9 PI_A9 0 PI_A8 GN PI_A7 PI_A6 PI_/BE# 5 VP 6 PI_FRAME# 7 PI_IRY# 8 V 9 PI_TRY 0 PI_E PI_ G P O 06 EN# 07 RUN# 08 I_INTA# 09 G_RST# 0 V PI_PLK GN PI_GNT# PI_REQ# 5 VP 6 PI_PME# 7 PI_A 8 GN 9 PI_A0 0 PI_A9 PI_A8 V PI_A7 PI_A6 5 REG8 6 PI_A5 7 PI_A 8 U U R87 6 R87 6 R5 50_ R5 50_ 588.U-0V_ 588.U-0V_ 580 P-50V_ 580 P-50V_ R56 K_ R56 K_
26 +5V B PATA O A SATA H 68.U_ R9 0_8 50U_ U_ 7.U_ AA:(0/)change footprint to SATA B- AA:(0/9)change footprint to SATA A-P H_V
27 5 5 5,, PIRST#,0 PI_LK_SIO 6 L_RST# 6 L_ATA 6 L_LK AA(0/0): +V_WL_V Add (N8/Pin9,) to +V_WL_V (follow ZO) 5 PIE_TXP 5 PIE_TX P B:(/ B A:(/) Stuff R9,R50 for debug use AA:9/ Reserved for debug only PIRST# R9 PLK_SIO R50 A L8 FBJ6HS800_ +V MINI-ard AA: (9/0) hange AA: (0/)chang B: (0/)cha
28 FOLLOW INTEL ME-E INTERFAE N_SMB IS EIATE FOR I +VPU AA: (9/5) change VBAT from +VP L5 BLM8AG60SN_6 +AVPU AA:(9/6)hange from WP8769 to WP U_ 0U_8 8769AGN U_8.U_.U_.U_.U_.U_ U AA: (9/5) place the above capacitors as close to the pins as possible LFRAME#,7,0 LFRAME# LA0 LFRAME,7,0 LA0 6 LA LA0,7,0 LA 7 LA LA,7,0 LA 8 LA LA,7,0 LA PLK_59 LA PLK_59 LLK PLK_59 6,0 LKRUN# 8 LKRUN/GPIO/H GATEA0 GA0 R RIN# KBRST *_ BAS6 SI#_uR 6 SI# 9 ES 9 APSLE# 6 0 AA: (9/6) Remove LAN_WOL_EN *0P_ PLTRST# 5,6,8,,5,6,7,0, PLTRST# 9 NUMLE# SERIRQ 6,,,0 SERIRQ 08/0 FAE: SMI OESN'T NEE IOE 6 KBSMI# 9 MX0 9 MX 9 MX 9 MX 9 M V 9 V 6 V 76 V 88 V5 5 AV 0 80
29 INT K/B N7 MY5 8 MY5 MY MY0 +VPU 8 MY MY MY 8 MY MY MY 8 MY MY MY 8 MY MY0 5 MY 8 MY0 RP MY9 6 MY5 MX 8 MY9 MY8 7 0 MY6 MX MX7 8 MY8 MY7 8 9 MY7 MX MX6 8 MY7 MY6 9 8 MY8 MX MX5 8 MY6 MY5 0 7 MY9 MX0 8 MY5 MY 6 5 MY0 8 MY MY MY 8 MY 0KX8 MX7 MY 8 MX7 MX6 MY 8 MX6 MY 5 MY 8 MY MX5 6 MY5 8 MX5 MX 7 MX0 8 MX MX 8 MX 8 MX MX 9 MX 8 MX MY 0 MX 8 MY MY0 MX 8 MY0 MX MX5 8 MX AA: (9/6) Refer to ZH, change K/B matrix MX0 MX6 8 MX0 MX7 5 AS_ N BOT ONTAT LE +VPU R67 0_ LE SUSLE# LE_Y_LTST-90KFKT R800 0_ PWRLE LE5 LE_G_LTST-90KGKT R66 0_ LE6 LE_Y_LTST-90KFKT R80 0_ LE7 LE_G_LTST-90 B:(/7)Base on ME request, refer to ZH, change B:(/8)Base on ME request, change LE type A:(/) Base on SMT-ME request, change LE ty EL LE,LE5,LE6,LE7,R570,R57,A EA:(/6)hange LE, LE type base on ME EA:(/0) ES issue, change type (fo ur REQUEST MY OES NOT N MY AN NOT USE
30 B HOLE h-c6d8p A:(/) L h-c HOLE5 *h-c6d6 HOLE *h-c6d6 HOLE8 HOLE HOLE *h-c6d6 *h-c6d6 *h- HOLE HOLE7 *h-c6d6 HOLE7 *h-c76d9p A:(/8) change Hole7 type to improve thermal issue, (change footprint to H-769N-) HOLE HOLE8 HOLE6 HOLE9 HOLE7 *h-c6d6 *h-c6d6 *h-c6d6 *h-c6d6 HOLE HOLE *h-c6d6 *h-c6d *0P_,7,8 5,6,8,,5,6,7,8, 6,,,8 SER NS SIO P878 R9 *_ 55 *0P_ PI_LK_SIO SIO_M R9 *_,7,7,,7,8,7,8 L,7 PI_LK_SIO LRQ#0 LFRAME# PLTRST
31 T B: (/) stuff R0 for Int-SP AA:(9/8) EMI suggest: Add Additional two more b between AGN and GN R0 R558 R5 EAP AU_SPIF SURR-L AOGN SURR-R AOGN AA:(0/8) reserve R5 to reduce ringing MI-LK R5 00_MI-L EAP SPIF_OUT R50 0_ +V +.5V FRONT-R 6 FRONT-L 5 Sense B N -R SURR-L SURR-R FRONT-L FRONT-R MI-VREFO-R MI-VREFO MI-VR SENSEB +5V_AO R5 0K_6 U 7 MONO-OUT 8 AV 9 HP-OUT-L 0 JREF HP- OE(AL68) +5V +5V_AO L6 TI6U80_ U-0V_ 0U-0V_8.U-0V_.U-0V_.U-0V_ 0U-0V_8 AOGN R8 0_6 R8 *0_6 +AZA_V U-0V_8.U-0V_
32 LINE SYSTEM LINE IN 6 MTW55 8 MTW55 7 *MTW55 A:(/5) STEVEN: no stuff d7 INSPKL- L9 BK608LL_6 INSPKL-N INSPKL+ L0 BK608LL_6 INSPKL+N INSPKR- L BK608LL_6 INSPKR-N INSPKR+ L BK608LL_6 INSPKR+N AA:(0/7) SWAP R&L channel for ME request AOGN 8 AMP_MUTE# EAP, AZ_RST#_AUIO N700 MUTE# 00K_ Q6 R59 MUTE# MUTE Speaker Amplifier +5V_AO +V_AV 59 6 AA(0/5):Refer to Z, change R60~R607 to 0K 0U-0V_8.U-0V_ T9 A:(/5) change R56/R50 from 0k to 9.k AOGN U6 6.U/0V_8 SURR-L- R56 9.K_6 SURR-L- SURR-L LIN VOL U/0V_8 SURR-R- R50 9.K_6 SURR-R 8 RIN SURR-R- +5V_AO INSPKL+ R55 0K_6 6 0P_ LIN IN/IN 7 INSPKR+ R59 0K_6 RIN ROUT P_ ROUT- AOGN.7U/6.V_6 589 LOUT+ 6 RBYPASS LOU.7U/6.V_6 65 LBYPASS MUTE R5 0_ 5 SHN R56 0_ SE/BTL G AOGN +V_AV R 0K_ MUTE# 5 THRMPA GN/HS N/HS /HS /HS LV RV 5 V T 6 N 8 SENTL AOGN 6 U-6V_6
33 6,8 AA:(/) add B:(/0) a OK T R7.K_ OK K AA: (9/0) ()Remove Level-shift circuit (already in d ()change Power from +V to +.5V ()stuff.k (R7,R75) OKIN# VI K +.5V R75.K_,,6,8,7 PLK_SMB VI T +.5V,,6,8,7 A B 5 IN VA VA +VSUS SW00 P A:(/8)The system side should have a diode (5,6) to block the A ad Q RHU00N06 A:(/0)Acer VR0_esign Requirement hecklist: The system side should have a diode to block the A adaptor power coming from ezock. EZ_AT_SMB AA: (9/0) EA:(/)hange 6 footprint from SBM00-P to SBM00-P-ZU for SMT -test open issue +VSUS Q5 RHU00N06 EA:(/) change 5 (H00KB9) to 0 EZ_LK_SMB EA:(/6)hange Q,Q5 Pin from +V to +VSUS. (ocking side pull up to +VSUS plane) PAT_SMB
34 O P95 0U/X6S-5V_06 P 0U/6.V_6X5.7 +5VPU P77 P79 0.U/X7R-50V_6 00P/X7R-50V_ P7 0U/X6S-5V_06 hange PL part number from (-5A0006) to (-5A0000 PQ OP: 0A F P 5VPU PR *0_ P9 0.U/X7R-5 P PL7 HI0805R800R-00_8 VIN SUS 8 P8 0U/X6S-5V_06 + PL0 HI0805R800R-00_8 MAIN VL PR 0_ MAIN 8 SUS 8 SYS_SHN#
35 ELAY_ AA:(0/0) no stuff PR75 already have PU R in PU side *0K_ H_PROHOT# E8-B -06-add Panasonic ERT-J0EV7J PSI#_ PR7 *0_6 PRSLPVR 6 6,6,6, 8 VR_PW PR6 70K_ NT P6.0U/X7R-6V_ H_VI0 H_VI H_VI H_VI H_VI H_VI5 H_VI6 PM_PRSL IH_ VRON H_V PSI# PR 0_ PSI#_ VR_ON PR *0_ PG_IN PR 7K_6 H_VI0 H_VI H_VI PR.0K_ PR6 PR5 0_8 lose to Phase Inductor +VSUS Throttling temp. 05 degree P 5N PSI# PWR_MON +.05V PR8 PR9 PR0 PR PR PR *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 H_VI6 H_VI5 H_VI H_VI H_VI H_VI H_VI0 PR.99K_6 PG_IN VIN_66 +V for ISL66A P7 PR6 AA:(0/7) change from 0k to 0.U/X7R-50V_6 0_6 PR7 0_ PR6 +5V_S5 AA:(0/) change from +5VSUS to +5V_S5.9K_ PSI# PR60 P0 0_6 0.U/X7R-50V_6 P 0.U/X7R-50V_6 PU P U/X7R-5V_8 ISL66A GN 9 GN_T PSI# PG V VIN 0 V 8 OO PR *0_6
36 A B 8 000P/X7R-50V_6 P5 0.U/X7R-50V_6 HWPG_.05V 8,7,8 MAINON.0U/X7R-50V_6 P0 P PR7 *0K_6 8.U_6 B:(/0) T Power sequence issue ()change PR from 0 ohm to 7k ohm. ()stuff 8 0.uF AA:(0/8) Reserve.UF PR 7K_6 +V PU8 SMLTRT 5 EN/PSV BST 6 VIN VOUT VA FBK PG 6 PR6 0_6 PR M_6 P6 *.U_6
37 +.8VSUS SMR_VREF AA(0/5):change net name from +SMR_VREF to SMR_VREF PR8 *0_6 PR85 0_6 IS_MOE +.8VSUS P55 0U/X6S-5V_06 AA(0/5):change net name from PU +SMR_VTERM to SMR_VTERM TPS56 A:(/) EMI suggest to add.ohm BST VLOIN RVH 9 PR5._6 SMR_VTERM VTT VBST 0 P58 0.U/X7R-50V_6 P5 P56 VTTSNS LL 8 0U/X6S-5V_06 5 0U/X6S-5V_06 GN RVL 7 VTTGN PGN 6 IS_MOE 6 S_.8V PR9 0_6 PR88 MOE S 7 S5_.8V S5 PR9 VTTREF 0_6 5VIN 8 5VIN P60 OMP V5IN 0.0U/50V_6 9 *.U_6 PR89 VSNS PGOO 5VIN 0 VQSET S 5 0_6 PR86 FOR R II P59 *000P/50V_6 K/F_ PR87 5VIN +5VPU 0_6 GN GN GN GN 5 GN 6 GN 7 GN
38 8,7 VIN SUSON 8,6,7 8 MAINON AA:(0/8) Reserve.UF HWPG_PUIO MAINON PG 98EN EN AJ +5VPU V 9 P69 PU6 *.U_6 0.U/X7R-50V_6 G98 AJ GN +V A:(/) EL P7 footprint PR99 00K_ REV:A MOIFY PR05 0_ PQ9 FS VSUS P65 P6 5 0.U/X7R-50V_6 0U/X5R-6.V_6 98RV PR7 0_6 P8 RV 6.0U/X7R-6V_ 5 Vout = (+Rg/Rh)*0.5 Rg PR0 0
39 7 6 5 N0 AA:(9/7)change Pin define AA:(9/9) change footpint: BAT-5 PR68 0K_6 PR6 6.8K_6 PR6 0K_6 AIN_ AA:(9/7)change ONN (Follow ZH) 8 AIN P P 0.U/X7R-50V_6 0.U/X7R-50V_6 5 PJ SIT_-G06-I06 /9 /9 /9 Add fuse EA:(/)hange P9 footprint fro VA to SBM00-P-ZU for SMT -test op HI0805R800R-00_8 PL PF BUS-7A-06 PL P9 PS00S HI0805R800R-00_8 P SW00 P09 P 0.U/X7R-50V_6 0.U/X7R-50V_6 P5 ZV
40 B PU VIN BATTERY AAPTER harger ISL65 ISL66 PU7 +5VPU <A/ In FS6 PQ +5VPU ISL66A PU V_O <VRON>
41 B PU PU ORE VR VRON 0 MAINON Battery SUSON A Adapter 9 NBSWON# +VPU Always System power +5V PU7 VIN SLP_S#(SUSB#): ontrol non-critical power plane when system into S(Suspend to RAM)/S(Suspend to isk)/s5(soft off). SLP_S#(SUS#): ontrol non-critical power plane when system into S(Suspend to isk)/s5(soft off).used to control RAM power harger ircuit PU
42 0 Item: Fixed Issue Modif PU lock select issue Stuff R79,R98,R PI lock issue change R86 value fro K505 issue IS FAE suggest to chan EMI issue EMI suggest to rese K505 issue Add PIE_LKREQ K505 issue SWAP SR an K505 issue Add PIE K505 issue Remo K505 issue K505 issue K505 issue PU issue PU issue Thermal Trip issue PU FAN issue PU FAN issue PU FAN issue PU Thermal mo PU Therma PU Th PU
43 Item: Fixed Issue Modif 5 Power sequence issue change (U/Pin5) 6 IH8-M issue Remove WOL_EN (U/Pi 7 IH8-M issue Remove SUSM# (used to c 8 IH8-M issue Remove ()ME_E_ALE 9 IH8-M issue connect LAN_RST 0 IH8-M issue change OKI EMI issue EMI sugg IH8-M Power issue Rese LAN Power issue LAN Power issue 5 LAN Power issue 6 LAN Power issue 7 LAN Switch issue 8 LAN Switch issue 9 LAN Switch issue 50 LAN Transformer issue 5 LAN ONN issue 5 LAN ONN issue 5 RT issue RT is RT
44 Item: Fixed Issue Modif 69 PATA O issue change R5 from 70 PATA O issue Add 6,7, fo 7 PATA O issue Remove, already add 7 Mini ard issue Reserve R9,R50,R 7 Mini ard issue Add (N8/Pin9 7 Mini ard issue Remove (N8 75 Mini ard issue Remove ( 76 Mini ard issue Remo 77 Bluetooth issue 78 USB ONN issue 79 E issue 80 E issue 8 E issue 8 E issue 8 E issue 8 E issue 85 Finger Printer iss 86 SuperIO issue 87 Audio issu Audio Aud
45 5 Item: Fixed Issue Modif 0 PMIA issue Reserve R57 for 0 9 issue hange R7,R06,R07 05 Mini ard issue no stuff R5,R8,R56 06 Mini ard issue need support BM WL 07 E issue SWAP GPIO and 08 E issue hange N0/ 09 LE issue Base on 0 Audio issue Stuf ocking issue Mini ard issue GMH Power issue PU lock issue 5 S5_ON issue 6 K505 issue 7 G995 issue 8 BIOS EMI issue 9 LAN issue 0 Audio issue VI etect IH8M SV
46 Item: Fixed Issue Modif 7 Audio issue change R56/R50 8 GMH POWER issue hange restline V_ 9 XTAL issue Base on vendor-fe sugg 0 XTAL issue Base on vendor-fe XTAL issue Base on vendor- EMI issue EMI request: EMI issue EMI requ EMI issue EMI 5 debug issue 6 Modem wake from S fail issue 7 ablesence circuit issue 8 ablesence circuit issue 9 LE type issue 50 SW button issue 5 change Modem capacitor to m 5 Power issue 5 EMI issue 5 VI issue 55 ASF issue SMT B op abl
47 Item: Fixed Issue Modif 7 Quanta S Team issue Base on S comma 7 rise time of LV is >0.5ms and <=0ms. change U from AL00 7 ard reader issue no stuff K(S0JB 7 ard reader issue no stuff 0k(S00 75 ard reader issue hange R57 fro 76 ard reader issue hange R58 77 Shortage issue hange R 78 EMI issue EMI 79 PST issue 80 Shortage issue 8 IH8M Power issue 8 implement it for PU protect in build 8 Battery life issue. 8 hange EMI Spring Material 85 -Test SMT open issue 86 ZR issue 87 -Test SMT open iss 88 hange NB P/N f 89 hange SB P/ Material G995
48 Item: Fixed Issue Modif 05 PMIA POP SOUN issue Refer to BU, add 06 GLAN issue Stuff R (S09FB 07 ES issue change LE type (follow ES issue change ES protect isable LAN Low power mode Base on PM sugg
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