ZR6 SYSTEM BLOCK DIAGRAM

Transcript

1 OM MRK INT VG STUFF FOR EXT VG STUFF FOR UM or VG REV: X'TL.MHz LOK GENERTOR IS: SELGO: SLGSPTTR RIII SO-IMM 0 SO-IMM P ZR SYSTEM LOK IGRM P ual hannel R /00 MHz Penryn ufpg N antiga P, P FS /00/0 Mhz (GM/ PM/ GL0) P, P, P, P, P, P0, P Thermal Sensor (G0-PU) PIE X LVS RG P NVII N0M-GE VRM RII M P-P Fan river (G) P EXT_LVS EXT_RT EXT_HMI INT_LVS INT_RT INT_HMI R PWR TPS THERML PROTETION SWITH IRUIT P P0 ISHRGER P VG ORE OZ P HMI switch (PS0T) P RT LVS HMI HRGER ISL P /V SYS PWR P ISL PU ORE PWR OZLN.0V UPQ P P P P P H (ST) * X MI interface P Ext US Port x US 0, P Int US Port x US P luetooth US US P P udio mplifier GL P P O (ST) udio OE (X0) P MI Jack P P Int. MI P ST0 ST US.0 zalia S IHM P,P,P,P LP E (WPLG) SPI ROM P Touch Pad P P X'TL.KHz X'TL.KHz PI-Express US K/ OON. P Media ardreader (RTS) US ard Reader onnector P0 P0 PIE- theros Giga-LN (R) Transformer RJ PIE- P X'TL MHz P P Mini ard WLN P Int. Speaker P Quanta omputer Inc. PROJET : ZR Size ocument Number Rev lock iagram ate: Monday, pril, 00 Sheet of

2 lock Generator (LK) V PI/M RS= ohm when one loading = ohm when two loading PLK_EUG PLK_ PLK_IH L KP0HST..u/0V_ *0p/0V_ PLK_EUG_R *0p/0V_ PLK R *0p/0V_ PLK_IH_R *.u/0v_ R _ PLK_EUG_R R _ PLK R R _ PLK_IH_R.u/0V_ V_LK.u/0V_ 0u/.V_ *.u/0v_.u/0v_ p/0v_ G_XIN 0 Y The trace within 00mil.MHz G_XOUT p/0v_ STLKREQ# R /F_ STLKREQ#_R LN_LKREQ# R /F_ LN_LKREQ#_R PLK_EUG_R PLK R PLK_PM_R PLK_IH_R PU_SEL0 R.K_ R _ LKUS_ R0 _ FS 0 LK_ard 0 PU_SEL PU_SEL R 0K_ R0 _ M_IH *0p/0V_ FS U V_PI V_I/O V_ V_PLL_I/O 0 V_PLL V_SR_I/O_ V_SR V_SR_I/O_ V_PU V_SR_I/O_ V_REF V_PU_I/O XTL_IN XTL_OUT PU_STOP# PI_STOP# KPWRG/P# PU_0 PU_0# PI_0/LKREQ_# PU MH PI_/LKREQ_# PU MH# 0 PI_ SR_/PU_ITP PI_ SR_#/PU_ITP# ^PI_/LLK_SEL PIF_/ITP_EN N US_MHz/FS_ FS_/TEST_MOE LLK/M LLK#/M_SS REF/FS_/TEST_SEL LK_REFSSLK_R LK_REFSSLK#_R V0_LK 0 0 0u/.V_.u/0V_.u/0V_ PM_STPPU# PM_STPPI# K_PWRG LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK V power range.0v~.v *.u/0v_.u/0v_.u/0v_ L KP0HST..u/0V_ 0.0V Pin : It acts as a level sensitive strobe to latch the FS pins and other multiplexed inputs. *0p/0V_ FS,,, PT_SM,,, PLK_SM Q MN0K- V V Q MN0K- R 0K_ R 0K_ GT_SM GLK_SM LK_REFLK_R LK_REFLK#_R GLK_SM GT_SM SR_0/OT_ SR_ SR_0#/OT_# SR_# SR_/LKREQ_# SL SR_#/LKREQ_# S SR_ SR_# SR_ SR_# SR_/LKREQ_F# VSS_PI SR_#/LKREQ_E# VSS_ SR_ VSS_I/O SR_# VSS_PLL SR_0 VSS_SR_ SR_0# VSS_SR_ SR_/LKREQ_H# VSS_SR_ SR_#/LKREQ_G# VSS_PU VSS_REF LK-GEN_SLGSPTTR 0 0 LK_PIE_SR LK_PIE_SR# LK_PIE_SR LK_PIE_SR# LK_MH_OE#_ LK_PIE_SR# LK_PIE_ST LK_PIE_ST# T T LK_PIE_LN LK_PIE_LN# LK_PIE_IH LK_PIE_IH# T0 T LK_PIE_MINI LK_PIE_MINI# LK_PIE_GPLL LK_PIE_GPLL# From GMH From eisceret R0 R RN LK_REFLK_R LK_REFLK#_R RN LK_REFSSLK_R LK_REFSSLK#_R /F_ /F_ RN LK_REFLK_R LK_REFLK#_R RN LK_REFSSLK_R LK_REFSSLK#_R IV@0_PR IV@0_PR EV@0_PR EV@_PR LK_MH_OE# MINI_LKREQ# LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_VG LK_PIE_VG# M_NONSS 0 M_SS 0 PU lock select Pin 0// : For Pin PU frequency selection SEL Frequency Select Table FS FS FS Frequency Mhz V R R R0 R 0K_ 0K_ *0K_ 0K_ STLKREQ#_R LN_LKREQ#_R PLK_EUG_R R0 LK_PIE_SR# Strap table LKREQ_# ontrol SR_0 & SR_ LKREQ_# ontrol LLK & SR_ *0K_ Reserve overclocking PU_SEL0 PU_SEL PU_SEL0 R PU_SEL R *short00 *short00 MH_SEL0 MH_SEL Mhz Mhz 00Mhz 00Mhz R EV@0K_ PLK_PM_R R00 IV@0K_ Pin : For Pin / and / selection 0 = LLK & OT for internal graphic controller support = M & M_SS &SR_0 for external graphic controller support PU_SEL R *short00 PU_SEL LOK GENERTOR MH_SEL Mhz Mhz Pin : For Pin / selection = PU_ITP 0 = SR_ PLK_IH_R R0 0K_ Quanta omputer Inc. PROJET : ZR Size ocument Number Rev LOK GENERTOR ate: Monday, pril, 00 Sheet of

3 PU / (PU) H_#[..] H_ST#0 H_REQ#[0..] H_#[..] H_ST# H_0M# H_FERR# H_IGNNE# H_STPLK# H_INTR H_NMI H_SMI# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U J []# L []# L []# K []# M []# N []# J []# N [0]# P []# P []# L []# P []# P []# R []# M ST[0]# R GROUP_0 R GROUP_ K REQ[0]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# Y []# U []# R []# W [0]# U []# Y []# U []# R []# T []# T []# W []# W []# Y []# U [0]# V []# W []# []# []# []# V ST[]# 0M# FERR# IGNNE# IH STPLK# LINT0 LINT SMI# M RSV[0] N RSV[0] T RSV[0] V RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] F RSV[0] RESERVE XP/ITP SIGNLS ONTROL S# NR# PRI# EFER# RY# SY# R0# IERR# INIT# LOK# RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERML PROHOT# THERM THERM THERMTRIP# H LK LK[0] LK[] H E G H F E F 0 H F F G G G E 0 H_IERR# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TMS XP_TRST# SYS_RST# H_PROHOT#_ H_THERM H_THERM PM_THRMTRIP# R _ T T T T T H_S# H_NR# H_PRI# H_EFER# H_RY# H_SY# H_REQ#.0V H_INIT# H_LOK# H_PURST# H_RS#0 H_RS# H_RS# H_TRY# H_HIT# H_HITM# onnect it to PU R# is for ITP debug port or PU interposer (like IE) to reset the system SYS_RST# LK_PU_LK LK_PU_LK#.0V R K/F_ R K/F_ Layout note: H_GTLREF: Zo= ohm L<0.", /*VP-% H_#[0..] H_STN#0 H_STP#0 H_INV#0 H_#[..] H_STN# H_STP# H_INV# PU_SEL0 PU_SEL PU_SEL H_#[0..] H_#[..] R R T T0 T T T H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# U E [0]# F []# E []# G []# F []# G []# E []# E []# K []# G []# J [0]# J []# H []# F []# K []# H []# J STN[0]# H STP[0]# H INV[0]# N []# K []# P []# R []# L [0]# M []# L []# M []# P []# P []# P []# T []# R []# L []# T [0]# N []# L STN[]# M STP[]# N INV[]# H_GTLREF *K_ PU_TEST GTLREF *K_ PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST PU_TEST TEST TEST SEL[0] SEL[] SEL[] Penryn T GRP 0 T GRP MIS T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# Y V V V T U U Y W Y W W Y U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# E H_# H_# H_#0 H_# H_# H_# 0 E F H_# H_# H_# E H_# H_# H_# H_#0 H_# F H_# H_# E F 0 R OMP0 R U OMP R OMP R Y OMP R E E H_#[..] H_#[..]./F_./F_./F_./F_ H_#[..] H_STN# H_STP# H_INV# H_#[..] Layout note: comp0,: Zo=.ohm, L<0." comp,: Zo=ohm, L<0." Layout note: PRSTP#, aisy hain (S>Power>N>PU) H_STN# H_STP# H_INV# 0 For ual ore IH_PRSTP#,, H_PSLP# H_PWR# H_PWRG H_PUSLP# PSI# Penryn Thermal Trip.0V PU Thermal monitor (THM) V XP PU/P V,,, ELY_VR_PWRGOO.0V Q MN0K- R 00_ V_TH SYS_RST# R *K_.0V, PM_THRMTRIP# Processor hot PM_THRMTRIP# R _ Q MMT0 SYS_SHN#,0 No use Thermal trip PU side still PU ohm. Use Thermal trip can share PU at S side N_MLK N_MT V R *0K_ U SLK S LERT# OVERT# V XP XN GN 0.u/0V_ H_THERM 00p_ H_THERM XP_TO XP_TI XP_TMS XP_PM# XP_TK XP_TRST# R0 R R R R R *./F_./F_./F_./F_./F_./F_ H_PROHOT#_.0V R _ R No use PROHOT PU side still PU ohm. Use PROHOT to optional receiver PU side PU ohm and through isolat.k ohm to receiver side *0_ H_PROHOT# THERM_LERT# R0 *0_ G0-PU RESS: H V R 0K_ THER_OVERT# GMT L Use 00p WINON LL00 heck XP_RESET# and XP_TO reserve for XP Quanta omputer Inc. PROJET : ZR Size ocument Number Rev PU Host us ate: Monday, pril, 00 Sheet of

4 PU / (PU) 0 U V_ORE V_ORE V: (Low power type) VSS[00] VSS[0] P V: (Standard type) VSS[00] VSS[0] P U VSS[00] VSS[0] P V[00] V[0] 0 VSS[00] VSS[0] R V[00] V[0] VSS[00] VSS[0] R 0 0 VSS[00] VSS[0] R V[00] V[00] V[00] V[0] VSS[00] VSS[0] R Layout Note: *0u/0V_ F 0u/.V_ VSS[00] VSS[0] T *0u/0V_ 0u/.V_ 0u/.V_ *0u/0V_ V[00] V[0] *0u/0V_ *0u/0V_ V[00] V[0] Inside PU center cavity in rows VSS[00] VSS[00] T V[00] V[0] VSS[00] VSS[0] T V[00] V[0] VSS[0] VSS[0] T 0 V[00] V[0] VSS[0] VSS[0] U V[00] V[0] VSS[0] VSS[0] U V[0] V[0] VP :.(Supply after V Stable) VSS[0] VSS[0] U 0 V[0] V[0] 0.(Supply before V Stable) VSS[0] VSS[0] U V[0] V[00] VSS[0] VSS[0] V 0 VSS[0] VSS[0] V V[0] V[0] V[0] V[0].0V VSS[0] VSS[0] V 0u/.V_ *0u/0V_ *0u/0V_ 0u/.V_ VSS[0] VSS[00] V 0u/.V_ *0u/0V_ V[0] V[0] *0u/0V_ *0u/0V_ V[0] V[0] VSS[00] VSS[0] W 0 V[0] V[0] E VSS[0] VSS[0] W V[0] V[0] E0 VSS[0] VSS[0] W 0 V[00] V[0] E VSS[0] VSS[0] W 00 V[0] V[0] E.u/V_ VSS[0] VSS[0] Y.u/V_.u/V_ V[0] V[0] E VSS[0] VSS[0] Y 0u/V_ V[0] V[00] E VSS[0] VSS[0] Y V[0] V[0] E VSS[0] VSS[0] Y V[0] V[0] E0 VSS[0] VSS[0] VSS[0] VSS[0] V[0] V[0] F 0 V[0] V[0] F0 VSS[00] VSS[] 0u/.V_ VSS[0] VSS[] *0u/0V_ V[0] V[0] F *0u/0V_ *0u/0V_ 0u/.V_ V[0] V[0] F VSS[0] VSS[] V[00] V[0] F VSS[0] VSS[] V[0] V[0] F VSS[0] VSS[] V[0] V[0] F E *.u/v_ VSS[0] VSS[] E.u/V_.u/V_ V[0] V[00] F0 E VSS[0] VSS[] Layout Note: E V[0] E VSS[0] VSS[] E0 E Place these parts V[0] VP[0] G VSS[0] VSS[] E V[0] VP[0] V E VSS[0] VSS[0] reference to Intel demo E E VSS[00] VSS[] V[0] VP[0] J E E board. V[0] VP[0] K VSS[0] VSS[] E E VSS[0] VSS[] *0u/0V_ 0u/.V_ V[0] VP[0] M *0u/0V_ E V[00] VP[0] J E VSS[0] VSS[] E0 V[0] VP[0] K F VSS[0] VSS[] F V[0] VP[0] M F VSS[0] VSS[] F V[0] VP[0] N F VSS[0] VSS[] F0 V[0] VP[0] N F VSS[0] VSS[] F V[0] VP[] R F VSS[0] VSS[] F V[0] VP[] R F VSS[0] VSS[0] F V[0] VP[] T F VSS[00] VSS[] F F 0 0 VSS[0] VSS[] V[0] VP[] T F V[0] VP[] V F.V VSS[0] VSS[] F0 V:0m G *0u/0V_ 0u/.V_ *0u/0V_ *0u/0V_ VSS[0] VSS[] *0u/0V_ 0u/.V_ V[00] VP[] W V[0] G VSS[0] VSS[] V[0] V[0] G VSS[0] VSS[] 0 V[0] V[0] G VSS[0] VSS[] V[0] H VSS[0] VSS[] V[0] VI[0] H_VI0 H VSS[0] VSS[] V[0] VI[] F H_VI H VSS[0] VSS[0] V[0] VI[] E.0u/V_ 0u/.V_ H_VI H VSS[00] VSS[] V[0] VI[] F H_VI J VSS[0] VSS[] 0 H_VI J VSS[0] VSS[] V[0] VI[] E V[00] VI[] F H_VI J VSS[0] VSS[] 0 H_VI J 0u/.V_ *0u/0V_ VSS[0] VSS[] E *0u/0V_ V[0] VI[] E 0u/.V_ 0u/.V_ 0u/.V_ 0 R 00/F_ V[0] V_ORE K VSS[0] VSS[] E V[0] K VSS[0] VSS[] E V[0] VSENSE F VSENSE K VSS[0] VSS[] E V[0] K VSS[0] VSS[] E V[0] L VSS[0] VSS[0] E V[0] VSSSENSE E VSSSENSE L VSS[00] VSS[] E L R VSS[0] VSS[] E Penryn L VSS[0] VSS[] E. M 00/F_ VSS[0] VSS[] M VSS[0] VSS[] F M *0u/V_ *0u/V_ VSS[0] VSS[] F *0u/V_ *0u/V_ M VSS[0] VSS[] F Layout Note: N VSS[0] VSS[] F N Z0=.,PU/P L<" VSS[0] VSS[] F N VSS[0] VSS[0] F N VSS[00] VSS[] F P VSS[0] VSS[] VSS[] F Penryn. Montevina platform : Early Reference oard Schematics Feb 00. Rev.0 stuff U*, N U* stuff 0U*, N0U* Quanta omputer Inc. PROJET : ZR Size ocument Number Rev PU Power ate: Monday, pril, 00 Sheet of

5 GMH-NTIG(LG) 0 H_#[..] U H_#[0..] H_# H_#0 H_#_ F H_# H_# H_#_0 H_#_ G H_# H_# H_#_ H_#_ F F H_# H_# H_#_ H_#_ H QI P/N E H_# H_# H_#_ H_#_ G H_# H_# H_#_ H_#_ M H H_# H_# H_#_ H_#_ J Intel antiga (G)M JSL0T0 H H_#0 H_# H_#_ H_#_0 P F H_# H_# H_#_ H_#_ R H_# H_# H_#_ H_#_ N Intel antiga (P)M JSL0T0 H H_# H_#0 H_#_ H_#_ M M H_# H_# H_#_0 H_#_ E M H_# H_# H_#_ H_#_ P Intel antiga (G)L JSLGGM0T0 J H_# H_# H_#_ H_#_ F J H_# H_# H_#_ H_#_ G0 N H_# H_# H_#_ H_#_ J H_# H_# H_#_ H_#_ J P H_#0 H_# H_#_ H_#_0 E0 L H_# H_# H_#_ H_#_ H R H_# H_# H_#_ H_#_ J0 N H_# H_#0 H_#_ H_#_ L L H_# H_# H_#_0 H_#_ M H_# H_# H_#_ H_#_ J H_# H_# H_#_ H_#_ L N H_# H_# H_#_ H_#_ R H_# H_# H_#_ H_#_ J N H_# H_# H_#_ H_#_ H0 N H_#0 H_# H_#_ H_#_0 P H_# H_# H_#_ H_#_ K N H_# H_# H_#_ H_#_ 0 L H_# H_#0 H_#_ H_#_ F N0 H_#.0V H_# H_#_0 H_#_ K M H_# H_# H_#_ H_#_ L0 Y 0.*VP H_# H_#_ H_S# H_# H_#_ H_S# H Y WIE(0):SPING(0), H_ST#0 H_# H_#_ H_ST#_0 Y0 H_ST# L<0." H_# H_ST#_ G R0 H_#_ Y H_NR# H_# H_#_ H_NR# Y H_PRI# H_# H_PRI# F /F_ H_#_ Y H_REQ# H_# H_#_ H_REQ# G W H_EFER# H_SWING H_#0 H_#_ H_EFER# E H_SY# H_# H_#_0 H_SY# 0 Y LK_MH_LK H_# H_#_ HPLL_LK H LK_MH_LK# H_# HPLL_LK# H R H_#_ H_PWR# H_# H_#_ H_PWR# J H_RY# H_# H_#_ H_RY# F 00/F_.u/0V_ H_HIT# H_# H_#_ H_HIT# H 0 H_HITM# H_# H_#_ H_HITM# E H_LOK# H_# H_#_ H_LOK# H E H_TRY# H_# H_#_ H_TRY# E H_#0 H_#_ H_# H_#_0 H_# H_#_ H_INV#[..0] H_# H_#_ H_INV#0 H_# H_#_ H_INV#_0 J H_INV# H_ROMP H_# H_#_ H_INV#_ L E H_INV# H_# H_#_ H_INV#_ Y F H_INV# H_# H_#_ H_INV#_ Y H_STN#[..0] H_# H_#_ E H_STN#0 H_# H_#_ H_STN#_0 L0 R H_STN# Layout Note: H_#0 H_#_ H_STN#_ M E H_STN# H_# H_#_0 H_STN#_./F_ E H_STN# WIE(0):SPING(0), H_# H_#_ H_STN#_ E G H_STP#[..0] L<0." H_# H_#_ H_STP#0 H_#_ H_STP#_0 L H_STP# H_STP#_ M H_STP# H_SWING H_STP#_ H_STP# H_ROMP H_SWING H_STP#_ E E.0V H_ROMP H_REQ#[0..] H_REQ#0 H_REQ#_0 H_REQ# H_REQ#_ K H_REQ# H_REQ#_ F H_REQ# H_REQ#_ H_REQ# H_PURST# H_PURST# H_REQ#_ R H_PUSLP# E H_PUSLP# H_RS#[0..] /*VP H_RS#0 H_RS#_0 K/F_ H_RS# WIE(0):SPING(0), H_RS#_ F H_RS# L<0." H_VREF H_RS#_ H_VREF H_VREF R0 NTIG_PM K/F_ *.u/0v_ HOST Quanta omputer Inc. PROJET : ZR Size ocument Number Rev GMH HOST ate: Monday, pril, 00 Sheet of

6 GMH-NTIG(LG) V_S 0 Strap table Pin Name FG[:0] FG[:] FG FG FG FG FG FG0 FG FG FG FG[:] FG FG[:] FG FG0 SVO_TRLT P_TRLT PIE Graphics Lane Reversal PIE Loopback enable XOR Strap description FS Frequency Select MI X Select itpm Host Interface ME TLS onfidentiality LLZ FS ynamic OT MI Lane Reversal igital isplay Port (SVO/P/iHMI) oncurrent with PIE SVO Present igital isplay Present Strap pin V V VSUS R R0 R R R R R R R R R R R R R R R *.0K/F_ *.0K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ IV@.K_ IV@.K_ *.K/F_ *.K/F_ 0K_ 0K_ 0K_ 000= FS 0MHz 00 = FS 00MHz 0 = FS MHz 0 = MI X = MI X(efault) 0 = itpm Host Interface is enabled = itpm Host Interface is disabled(efault) 0 = MT Firmware will use TLS cipher suite with no confidentiality = MT Firmware will use TLS cipher suite with confidentiality(efault) 0 = Reverse Lanes = Normal operation(efault) 0 = Enabled = isabled (efault) 0 = LLZ mode enable = disable(efault) 0 = XOR mode enable = disable(efault) 0 = ynamic OT disable = ynamic OT Enable(efault) 0 = Normal (efault) = Lanes Reversed 0 = Only igital isplay port (SVO/P/iHMI) or PIE is operational (efault) = igital isplay port (SVO/P/iHMI) and PIE are operating simultaneously via PEG port 0 = No SVO/HMI evice Present(efault) = SVO/HMI evice present 0 = igital display(hmi/p) device absent(efault) = igital display(hmi/p) device present MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ SVO_TRLT SVO_TRLLK P_T P_TRLLK LK_MH_OE# PM_EXTTS#0 PM_EXTTS# onfiguration TPM isable,,, PM_SYN#,, IH_PRSTP# PM_EXTTS#0 PM_EXTTS# ELY_VR_PWRGOO PLT_RST#, PM_THRMTRIP#, PM_PRSLPVR MH_SEL0 MH_SEL MH_SEL T T R0 R T T T T T T T T0 00/F_ *0_ N Thermal trip pin No use Thermal trip N side can N.(N has OT) PM_PRSTP# The aisy chain topology should be routed from IHM to IMVP, then to (G)MH and PU, in that order. JTG_TO_GMHN JTG_TMS_GMHM MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 RST_IN#_MH THRMTRIP#_R M N R T H H0 H H K T M Y G F H F L K T R P P0 P N M E N P T R0 M0 L H P R T R N P T0 T T0 R G F H G E H F G H H H H G H F H G E G F F U RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV ME_JTG_TK ME_JTG_TI ME_JTG_TO ME_JTG_TMS FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 PM_SYN# PM_PRSTP# PM_EXT_TS#_0 PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ NTIG_PM FG PM RSV ME JTG N R LK/ ONTROL/OMPENSTION LK MI GRPHIS VI ME MIS H S_K_0 S_K_ S_K_0 S_K_ S_K#_0 S_K#_ S_K#_0 S_K#_ S_KE_0 S_KE_ S_KE_0 S_KE_ S_S#_0 S_S#_ S_S#_0 S_S#_ S_OT_0 S_OT_ S_OT_0 S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN# H_LK H_RST# H_SI H_SO H_SYN P T V U0 R R U V0 Y Y Y V R Y F Y G H F H V R F E F F E E E E H E0 E E H0 E E E H E F H G F E H H N J H N M G E K H 0 M_ROMP M_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT R0 R_RMRST# LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVREF_R P_TRLLK P_T LK_MH_OE# TSTN# H_IT_LK_HMI H_RST#_HMI H_SIN_HMI H_SOUT_HMI H_SYN_HMI /F_ M_LK0 M_LK M_LK M_LK M_LK#0 M_LK# M_LK# M_LK# M_KE0 M_KE M_KE M_KE M_S#0 M_S# M_S# M_S# M_OT0 M_OT M_OT M_OT R_RMRST#, LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] 0 *0p/0V_ L_LK0 L_T0 MPWROK, L_RST#0 SVO_TRLLK SVO_TRLT LK_MH_OE# MH_IH_SYN#.0V H_IT_LK_HMI H_RST#_HMI H_SIN_HMI H_SOUT_HMI H_SYN_HMI R *_ H_IT_LK_HMI heck list note : L_VREF=0.V R0 _ SM_VREF=0.*V_SM SM_PWROK only for R.(R P only) SM_RMRST# only for R.(R:N) For EMI.u/0V_.0V If HMI not support H --> N V_H-->GN ifferential signal-->n Impact IHM VH and VSUSH supply.v/.v NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. R K/F_ R /F_ R.K_ SM_PWROK R0 0K_ U TSH0FU M_ROMP M_ROMP# SM_VREF TSTN# LK_REFLK# LK_REFLK LK_REFSSLK# LK_REFSSLK SM_ROMP_VOH.u/.V_ SM_ROMP_VOL.0V P_TRL for HMI port SVO_TRL for HMI port.vsus SM_VREF.efault use voltage divider for poor layout cause SMR_VREF not meet spec.nd Intel circuit PU/P is K,ut heck list PU/P is 0K. HWPG_.V, SUS#, SUS#, INTEL FE Suggest P for Ext graphics N Thermaltrip.u/.V_ R R R0 R R R R0 *0K_ R0 R R R.0u/V_.0u/V_ Q0 *MMT0 *short00 *0_ 0./F_ 0./F_.VSUS 0K/F_ 0K/F_ K/F_ R.0K/F_ R K/F_ EV@0_ EV@0_ EV@0_ EV@0_.VSUS R TSTN_E# <hecklist ver0.> If TSTN# is not used, then it must be terminated with a - pull-up resistor to VP. <Pin out check issue> antiga ES 0. change all to TSTN# from TSTN Quanta omputer Inc. PROJET : ZR Size ocument Number Rev GMH MI Monday, pril, 00 ate: Sheet of

7 IV&EV is/enable setting If LVS no use,all signal can N L_KLT_TRL INT_LVS_LON INT_LVS_EILK INT_LVS_EIT INT_LVS_IGON INT_RT_LK INT_RT_T INT_HSYN INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT0 INT_TXLOUT INT_TXLOUT INT_VSYN HSYN_G VSYN_G V iscrete Stuffed. (RT) SP@ INT_RT_LU INT_RT_GRN INT_RT_RE LVS_IG INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT0 INT_TXLOUT INT_TXLOUT TV_// For IV: ohm For EV:0ohm L_TRL_LK L_TRL_T INT_TV_OMP INT_TV_Y/G INT_TV_/R INT_RT_LU INT_RT_GRN INT_RT_RE HSYN_G RTIREF VSYN_G HSYN/VSYN serial R place close to N RTIREF pull down for IV cantiga.0k ohm/f GMH-NTIG(LG) 0 U R R R IV@.K/F_ R R R R R IV@0K_ IV@0K_ SP@_ SP@_ SP@_ IV@0._ IV@0._ L G M M K J M E E 0 H E G0 0 H F0 0 H G J G F K F H K H E E G J G H J J E L L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_PM LVS PI-EXPRESS GRPHIS TV VG PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ T T L<0.", If PIE not support still connect to V_PEG EXP OMPX H PEG_RXN0 J PEG_RXN L PEG_RXN L0 PEG_RXN N PEG_RXN P PEG_RXN N PEG_RXN T PEG_RXN U PEG_RXN Y PEG_RXN Y PEG_RXN0 Y PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN H PEG_RXP0 J PEG_RXP L PEG_RXP L PEG_RXP N0 PEG_RXP P PEG_RXP N PEG_RXP T PEG_RXP U PEG_RXP Y PEG_RXP W PEG_RXP0 Y PEG_RXP PEG_RXP PEG_RXP PEG_RXP 0 PEG_RXP J M M M0 M R N T0 U U0 Y0 0 J L M M M R N T U U Y Y _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN R _PEG_TXP0 0 _PEG_TXP _PEG_TXP 0 _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP 0 _PEG_TXP _PEG_TXP 0 _PEG_TXP 0 _PEG_TXP0 0 _PEG_TXP _PEG_TXP _PEG_TXP 0 _PEG_TXP _PEG_TXP.0V./F_ PEG_RXN[:0] PEG_RXP[:0], an support reversal routing.if FG=, PI Express is normal operation. If FG=0, then PEG_TXP0 becomes PEG_TXP, PEG_TXP becomes PEG_TXP, PEG_TXP becomes PEG_TXP, etc. similarly for PEG_RXP[:0] and PEG_RXN[:0].u/0V_.u/0V_.u/0V_.u/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ EV@.U/0V_ PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN.u/0V_ PEG_TXP0.u/0V_ PEG_TXP.u/0V_ PEG_TXP.u/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP0 EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP EV@.U/0V_ PEG_TXP PEG_TXN[:0], PEG_TXP[:0], IV&EV is/enable setting </>Montevina_Schematics_hecklist_Rev0_ a)for TVOUT isabled, TV_ONSEL[:0] onnect to GN. ut design guide Rev0. show N.What is correct. b)for RT isable, RT LK, RT T. RT_HSYN, RT_VSYNThese signals should be connected to GN. ut design guide Rev0. show N, Intel suggest follow esign guide. <check list> <check list> For EV@ For IV@ RT R/G/ 0ohm to GN RT R/G/ 0ohm to GN RTIREF 0ohm to GN RTIREF Kohm to GN For topology without the analog switch - if the total motherboard route length is less than ", the recommended reference resistor value is k ±% RTIREF For IV: Kohm For EV:0ohm SP@ R R R R0 RT_R/G/ For IV: 0ohm For EV:0ohm SP@K/F_ SP@0/F_ SP@0/F_ SP@0/F_ RTIREF INT_RT_LU INT_RT_GRN INT_RT_RE R EV@0_ R EV@0_ Quanta omputer Inc. PROJET : ZR Size ocument Number Rev GMH VG ate: Monday, pril, 00 Sheet of

8 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M M0 M M M M M M M M M M M M M M M QS M QS M QS0 M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M 0 M M M M M M M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M QS# M M QS# M 0 M M QS# M 0 M QS# M M M M QS# M M QS M QS# M M M M M M QS M M M M0 M QS M M QS M QS M M QS M M M M QS0 M QS M M M M M QS# M QS#0 M M M M M Q[:0] M S0 M M[:0] M QS[:0] M QS#[:0] M [:0] M RS# M S# M WE# M Q[:0] M S0 M M[:0] M QS[:0] M QS#[:0] M [:0] M RS# M S# M WE# M S M S M S M S Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RIII Monday, pril, 00 ZR Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RIII Monday, pril, 00 ZR Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RIII Monday, pril, 00 ZR GMH-NTIG(LG) 0 R SYSTEM MEMORY U NTIG_PM R SYSTEM MEMORY U NTIG_PM S_Q_0 J S_Q_ J S_Q_0 U0 S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ 0 S_Q_ S_Q_ N S_Q_0 V S_Q_ Y S_Q_ S_Q_ 0 S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_0 V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_0 S_Q_ S_Q_ U0 S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J0 S_Q_0 T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N0 S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_0 N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_0 S_S_ G S_S_ T S_S# 0 S_M_0 M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_0 J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_0 J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_0 S_M_ S_M_0 S_M_ G S_M_ H S_M_ H S_M_ G S_M_ H S_M_ G S_M_ S_M_ S_M_ G S_M_ F S_M_ W S_RS# 0 S_WE# Y0 S_M_ Y R SYSTEM MEMORY UE NTIG_PM R SYSTEM MEMORY UE NTIG_PM S_Q_0 K S_Q_ H S_Q_0 S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ P S_Q_0 E S_Q_ S_Q_ F0 S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H0 S_Q_ G S_Q_ P S_Q_0 G S_Q_ H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ J S_Q_0 S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_0 R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_0 M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_0 S_S_ S_S_ S_S# G S_M_0 M S_M_ Y S_M_ 0 S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_0 L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_0 L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_0 V S_M_ S_M_0 S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_WE# F

9 GMH-NTIG(LG) 0 IV@ SP@.VSUS Power consumption reference to Intel antiga chipset ES Volume. Section 0 GM TP 0.~W GS TP ~W PM TP W UG.0V_XG Intel check list(rev 0.) No description for V_SM bulk P Intel R(Rev 0.) 0U* Reserve near to power 0U* near to N Intel check list(rev 0.) 0U* near to power(v.0m). 0U* near to N Intel R(Rev 0.) 0U* near to power(v.0m). 0U* near to N ESR=m ohm 0 u/.v_ *u/.v_.u/0v_ V_SM(.V) R.0V Graphics core V_XG V_XG_NTF.m.0V_XG.0V_XG Voltage regulator is shared between the Graphics ore Rail, V_HPLL,V_MPLL,V_PEG_PLLV_PEG_PLL, V_SM_K, V_PLL, V_PLL, V_HPLL, V_SM, V_XF IV@ 0u/V_ R R0 IV@0/F_ IV@0/F_ P N H G F Y W V U T R P N H G F G0 H G F Y W V U T R P W W T Y E E Y E J G E Y H0 F0 E T T M L E J H G F Y V U N M U T J H V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_0/N V_SM_/N V_SM_/N V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_SENSE VSS_XG_SENSE POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V SM LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M0 V Y M0 V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF IV@.0V_XG.V Internal connect to power.u/0v_.0v 0 IV@0u/V_.0V_XG Place close to the GMH Intel check list(rev 0.) 0U* near to N(ESR=m ohm) Intel R(Rev 0.) 0U* near to power(v.0s). 0U* near to N.u/0V_ R R R0.u/.V_ IV@0_ IV@0_ IV@0_ 0 IV@0u/V_.u/.V_ IV@.u/.V_.u/.V_.0V Place close to the GMH IV&EV is/enable setting esign guide(table ) For INT VG diasble.v_xg power can connect to GN SP@ SP@u/0V_ SP@:IV Sutff uf EVstuff 0 ohm 0 u/0v_.u/0v_ u/0v_ IV@0u/.V_ *.u/.v_ IV@u/.V_.u/.V_ IV@.u/0V_ 0 u/.v_ 0u/V_ 0 IV@.u/0V_ avity apacitors IV@.u/0V_ UF G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_ J V_0 G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_ H V_0 F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_ F V_0 G V_ J V_ H V_ F V_ T V_ NTIG_PM V ORE POWER V NTF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_.0V M L K J H G E Y W U M0 L0 K0 H0 G0 F0 E Y0 W0 V0 U0 L K J H G E Y W V L K L K K K K V V_NTF 0.m_EV 0.m_IV ME Engine 0.m Total Max=.m. Route V_XG_SENSE and VSS_XG_SENSE differentially. V_XG_SENSE PU to VGFX_ORE_INT with 0ohm and VSS_XG_SENSE P with 0ohm for Intel suggest NTIG_PM N Power Status and max current table(/) POWER PLNE S0 S S/S Voltage I(max) V(EXT_VG) O X X.0V m V(INT_VG) O X X.0V m Note V_XG O X X.0V 00m Graphics ore V_SM(00) O O X.VSUS (RII-). V_SM(Standby) O O X.VSUS m Self Refresh during S (See N ES Rev:.0 Section 0. for max current) (See N ES Rev:.0 Section. for voltage) Quanta omputer Inc. PROJET : ZR Size ocument Number Rev GMH V,NTF Monday, pril, 00 ate: Sheet of

10 If RT have Flicker issue IV&EV is/enable setting STUFF. ohm GMH-NTIG(LG) 0 V_RT_TV_ R V_V_RT_ Power consumption reference to Intel IV@0_ 0 antiga chipset ES Volume. Section 0 IV@.u/0V_ SP@.0u/V_ *IV@0u/.V_ External Graphics IV@ IV&EV is/enable setting SP@:INT use 0.0U (GMH Integrated Graphics isable) EV@ EXT use 0 ohm VSYN_RT GN 0 0UH, 0% R V G 0. R_max = 0. SP@:INT use 0.U.V V_RT_ GN SP@ IV@0_ 0 EXT use 0 ohm.0v m V_LVS GN FS-0.0V L IV@0uH m IV@.u/0V_ SP@.0u/V_ IV@0u/.V_ UH m V_TX_LVS GN 0.0V_VP_GMH.0V V_LVS GN VTT_ U R *short00 VTT_ T IV@0u/.V_ SP@.u/0V_.0V V_TV GN V_RT VTT_ U.m for PLL_/ ESR= m.v V_RT VTT_ T V_Q GN VTT_ U m VTT_ T.u/.V_.u/.V_.u/.V_.u/.V_ 0u/V_ V G GN V G VTT_ U0 VSS G VTT_ T0 ESR= m ohm V_PLL/ always keep to.0v USE same GN plane V_XG GN VTT_ U 0 0UH, 0% (If no use IV dynamic core power) VTT_0 T 0. R_max = 0. V_XG_NTF GN.0VM_PLL VTT_ U F V_PLL VTT_ T.0V L0 IV@0uH m.0vm_pll VTT_ U L V_PLL VTT_ T.0VM_HPLL VTT_ U V_HPLL VTT_ T SP@.u/0V_.0VM_MPLL VTT_ U IV@0u/.V_ E V_MPLL VTT_ T ESR= m.v_txlvs VTT_ V.0V.V VTT_0 U J V_LVS VTT_ V m.m VTT_ U.V J VSS_LVS VTT_ T.0V R *short00 SP@000p/0V_ u VTT_ V.0V VTT_ U.m.V R *short00 V_PEG_G.0VM_XF R *short00.0v.u/.v_.u/0v_ V_PEG_G.0V.0V.0V 0m.m. nh, 0. nh,.u/0v_ u/0v_ *0u_ R-00.V.0VM_PEGPLL, R_max= m V_PEG_PLL 0m ESR = 0 m R UH, Rdc = L KP0HST. V_PEG_PLL m Max rated current = 0 m.v for Teenah use(00m) 0 0.uH, 0%,,.0V R 0_.0VM SM R0 V_SM_.VSUS_V_SM_K R_max=0.0 P0 R0 *short00 V_SM_.VSUS 0 0 N0.0VM_MPLL_R R 0./F_ V_SM_ R V_SM_ POWER u/.v_.u/.v_ u/0v_ P /F_ R.VSUS_SMK_R 0u/.V_ V_SM_ N.u/0V_ 0 V_SM_ T V_SM_ R u/.v_.u/0v_ V_SM_ P V_SM_.V.m for V_TV_.m for V_TV_.m for V_TV_ Total.m.V V_TV always keep 0.U/0.0U/0U to.v.v m.v R *short00.v.m for RT m for TV F 0@00 MHz, %..V R_max=0 m m V L IV@KP0HST. R no 0U heck list need min 0U~00U for V_TV_ R IV@0u/.V_ IV@0_.V 0m F 0@00 MHz, %. R_max=0 m L KP0HST..0V IV@.u/0V_ IV&EV is/enable setting SP@:INT use 0.U EXT use 0 ohm SP@.u/0V_.u/0V_.V 0.m R *short00 SP@:INT use 0.0U EXT use 0 ohm SP@.0u/V_.0u/V_.0V R-00 m R : 0 ohm heck list :.nh.0v.0vm SM_K *.u/0v_ u/.v_ V_Q share to TV and RT R0 *short00.0v.m.u/0v_.u/0v_ V_RT_TV_ V_H.V_TV.V_Q.0VM_MH_PLL.0VM_PEGPLL P N P N N M M M L M L M L M L F M L V_TV V_TV V_HPLL V_PEG_PLL NTIG_PM RT PLL LVS PEG SM V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_H V_TV V_Q V_LVS_ V_LVS_ TV H LVS K TV/RT XF SM K MI HV PEG VTT V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ VTTLF V_XF_ V_XF_ V_XF_ V_TX_LVS V_HV_ V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_MI_ V_MI_ V_MI_ V_MI_ VTTLF VTTLF VTTLF F H0 G0 F0 K V U V U U H F H G L VTTLF VTTLF VTTLF IV&EV is/enable setting.v_txlvs SP@:INT use 000pf EXT use 0 ohm.v 0.m.0V m.0v_v_peg.u/.v_.0v m.u/.v_.u/0v_ SP@000p/0V_.V.m R0 *IV@u/.V_ V R 0_.u/0V_.u/.V_ 0 u/.v_ IV@0_.0V_S R 0u/.V_.0V Internal connect to power.u/.v_.v.0v *short00 H.0V.0V 0u/.V_ R no 0U heck list need min 0U~00U for V_Q.u/0V_ F MHz, %,.0V 0m L KP0HST..0u/V_ MOIFY Power Net Name V_XG_# V_XG_NTF_# V_PEG_G V_PLL V_PLL V_SM_# antiga(v).0v.v.0v.0v.0v.0vm_pegpll_r R0 0u/.V_ ESR=0m ohm /F_.u/0V_.u/0V_.V IV&EV is/enable setting R IV@0_.V_LVS.V 0.m SP@:INT use U EXT use 0 ohm SP@u/0V_ V_HPLL V_MPLL V_SM_K_# V_PEG_PLL V_XF_# V_HPLL V_PEG_PLL.0V.0V.0V.0V.0V.0V.0V Quanta omputer Inc. PROJET : ZR Size ocument Number Rev GMH POWER Monday, pril, 00 ate: Sheet of 0

11 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Monday, pril, 00 ZR Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Monday, pril, 00 ZR Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Monday, pril, 00 ZR GMH-NTIG(LG) VSS VSS NTF VSS S N UJ NTIG_PM VSS VSS NTF VSS S N UJ NTIG_PM VSS_ G VSS_0 W VSS_0 U VSS_0 P VSS_0 N VSS_0 H VSS_0 F VSS_0 VSS_0 R VSS_0 M VSS_0 J VSS_ G VSS_ 0 VSS_ 0 VSS_ W0 VSS_ T0 VSS_ J0 VSS_ G0 VSS_ Y0 VSS_ N0 VSS_0 K0 VSS_ F0 VSS_ 0 VSS_ 0 VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_0 R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_0 K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_0 VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G0 VSS_0 V0 VSS_ T0 VSS_ J0 VSS_ E0 VSS_ 0 VSS_ H VSS_ VSS_ G VSS_0 VSS_ M VSS_ N VSS_ VSS_ M0 VSS_ F VSS_ H VSS_ Y VSS_ L VSS_00 E VSS_0 VSS_0 Y VSS_0 U VSS_0 N VSS_0 J VSS_0 E VSS_0 VSS_0 N VSS_0 J VSS_0 G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_0 Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J0 VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_0 L0 VSS_NTF_ V0 VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_0 E N_ N_ VSS_0 R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_0 F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_0 H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_00 L VSS_ J N_ VSS UI NTIG_PM VSS UI NTIG_PM VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_0 VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_0 R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_0 VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_0 J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_0 G VSS_ VSS_ G0 VSS_ 0 VSS_ V0 VSS_ N0 VSS_ H0 VSS_ E0 VSS_ T VSS_ M VSS_0 J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_0 VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_00 M VSS_0 E VSS_0 P VSS_0 L VSS_0 J VSS_0 F VSS_0 VSS_0 H VSS_0 VSS_0 Y VSS_0 U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_0 H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_0 H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_0 G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_0 H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_0 R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_0 W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_0 J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_0

12 0 VRT IHM(LG). Ohm pull up to.v for GLN_OMPI/O is required, no matter intel LN is used or not. Z_SIN0 ST_LE# ST H ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN O (ST) ST_RXP ST_TXN ST_TXP p/0v_ p/0v_ Internal pull-down resistors that are always enabled R R Internal VRM enabled for VccSus_0, VccSus_, VccL_, VccLN_0 and VccL_0. V_S R.V R Y.KHZ R0 T T 0K/F_ 0K/F_.0u/V_.0u/V_.0u/V_.0u/V_ R 0M_ M/F_ LK_KX LK_KX RT_RST# SRT_RST# SM_INTRUER# IH_INTVRMEN LN00_SLP 0K_ IH_GPIO./F_ H_IT_LK_R H_SYN_R H_RST#_R H_SIN H_SIN H_SOUT_R ST_TXN0_ ST_TXP0_ ST_TXN_ ST_TXP_ U RTX RTX RTRST# F0 SRTRST# INTRUER# INTVRMEN LN00_SLP E GLN_LK LN_RSTSYN F LN_RX0 G LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 F H_IT_LK H H_SYN E H_RST# F H_SIN0 G H_SIN H H_SIN E H_SIN G G GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# J ST0RXN H ST0RXP F ST0TXN G ST0TXP H STRXN J STRXP G STTXN F STTXP IHM REV.0 RT LP LN / GLN PU IH G H_OK_EN#/GPIO E H_OK_RST#/GPIO ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRSTP# PSLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS K K L K K J J N J J E J F E G L F F H G G H J G F H J E0 F0 H_FERR#_R T T H_THERMTRIP_R H J J ST_RIS_PN H STIS L<0." T LRQ0/# : Internal PU R.K_ V R _ R R R./F_ 0K_./F_ V LK_PIE_ST# LK_PIE_ST L0, L, L,.0V L, LFRME#, GTE0 H_0M# H_PWRG H_IGNNE# H_INIT# H_INTR RIN# H_NMI H_SMI# H_STPLK# H_THERMTRIP_RR R *_ R R *_ R _ *0_ Layout note: PRSTP#, aisy hain (S>Power>N>PU) IH_PRSTP#,, H_PSLP#.0V PM_THRMTRIP#,.0V Intel IHM R _ H_FERR# No use Thermal trip S side still PU ohm.(serial R use 0ohm) Use Thermal trip can share PU for PU and S side(nd Serial R use. ohm) PU L<" JSLQ0T0 H udio R *EV@_ MXM_SOUT_HMI R *IV@_ H_SOUT_HMI H_SOUT_R R _ Z_SOUT_UIO Weak integrated P on the H_SOUT pin. *0p/0V_ R *EV@_ R *IV@_ H_IT_LK_R R _.000 MHz is output from the IHM. *0p/0V_ R For EMI H_IT_LK_R *0p/0V_ MXM_IT_LK_HMI H_IT_LK_HMI IT_LK_UIO 0 *0p/0V_ RT VPU VRT_ 0MIL Pjt: TZ0 Ons: TZ0 T 0MIL VRT 0 R 0K_ u/0v_ SRT_RST# G *SHORT_ P R *EV@_ R *EV@_ MXM_SYN_HMI MXM_RST#_HMI R0 *IV@_ *0p/0V_ *_ R *IV@_ H_SYN_HMI H_RST#_HMI H_SYN_R R _ H_RST#_R R _ Z_SYN_UIO Z_RST#_UIO Weak integrated P on the H_SYN pins *0p/0V_ H_SIN R *EV@0_ MXM_SIN_HMI H_SIN R *IV@0_ H_SIN_HMI South ridge Strap Pin (/) Pin Name Strap description Sampled onfiguration PU/P R K_ VRT_ 0MIL RT_N0 Q *MMT0 RT_N0 R u/0v_ R *K_ VPU R *.K/F_ 0 u/0v_ 0K_ RT_RST# G *SHORT_ P H_OK_EN/ GPIO Flash escriptor Security Override Strap PWROK 0 = The Flash escriptor Security will be overridden. = The security measures defined in the Flash escriptor will be in effect This strap should only be enabled in manufacturing environments using an external pull-up resistor. N0 T_ONN R0 *0K/F_ STLE# PI Express Lane Reversal (Lanes -) PWROK Internal PU hange type TP H_SOUT XOR hain Entrance XOR hain Entrance /PI Express* Port onfig bit (Port -) PWROK PWROK IH_TP 0 0 H_SOUT 0 0 escription RSV IH_TP IH_TP R *K_ Enter XOR hain Normal opration(efault) H_SOUT_R R0 *K_ V Set PIE port config bit Quanta omputer Inc. PROJET : ZR Size ocument Number Rev IHM HOST ate: Monday, pril, 00 Sheet of

13 IHM(LG) INT# INT# INT# INT# U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H J E J PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IHM REV.0 REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO F G F F E F E R E J F R H K F G REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# IRY# PIRST# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# PLT_RST# INTE# INTF# INTG# INTH# T T T PME# internal PU K~K PIRST# PLT_RST# PLK_IH WLN GLN PIE_RXN PIE_RXP PIE_TXN PIE_TXP GLN_RXN GLN_RXP GLN_TXN GLN_TXP PLE NER IH WITHIN 00 MIL 0 T T T.u/0V_.u/0V_.u/0V_.u/0V_ PIE_TXN_ PIE_TXP_ GLN_TXN_S GLN_TXP_S SPI_LK_S SPI_S0# SPI_S# SPI_MOSI SPI_MISO USO#0 USO# USO# USO# USO# USO# USO# USO# USO# USO# USO#0 USO# S_USIS U N PERN MI0RXN N PERP MI0RXP P PETN MI0TXN P PETP MI0TXP L PERN MIRXN L PERP MIRXP M PETN MITXN M PETP MITXP J PERN MIRXN J PERP MIRXP K PETN MITXN K PETP MITXP G PERN MIRXN G PERP MIRXP H PETN MITXN H PETP MITXP E PERN MI_LKN E PERP MI_LKP F PETN F PETP MI_ZOMP MI_IROMP PERN/GLN_RXN PERP/GLN_RXP USP0N PETN/GLN_TXN USP0P PETP/GLN_TXP USPN USPP SPI_LK USPN SPI_S0# USPP F SPI_S#/GPIO/LGPIO USPN USPP SPI_MOSI USPN E SPI_MISO USPP USPN N O0#/GPIO USPP N O#/GPIO0 USPN N O#/GPIO US USPP P O#/GPIO USPN M O#/GPIO USPP N O#/GPIO USPN M O#/GPIO0 USPP M O#/GPIO USPN N O#/GPIO USPP N O#/GPIO USP0N P O0#/GPIO USP0P P O#/GPIO USPN USPP G USRIS G USRIS# PI-Express SPI irect Media Interface V V U U Y Y W W T T F F W W Y Y W W V V U U U U MI_IROMP_R R MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PIE_IH# LK_PIE_IH./F_ USP0- USP0 USP- 0 USP 0 USP- USP USP- USP USP- USP USP- USP USP- USP.V EXT-US ardreader EXT-US LUETOOTH Wireless M/ US Port MER R./F_ IHM REV.0 L<0.",void routing next to clock/high speed signals. V South ridge Strap Pin (/).u/0v_ Pin Name Strap description Sampled onfiguration PU/P REQ# TRY# STOP# EVSEL# V INT# INT# SERR# INTE# V 0 0 RN.K_0PR RN.K_0PR V V REQ# FRME# REQ# INT# INTF# INTG# PLT_RST# USO# USO# USO# USO#0 V_S 0 RN 0K_0PR U TSH0FU R 00K_ USO# USO# USO# USO# PLTRST#,,,0, V_S H_SYN GNT# / GPIO GNT# / GPIO GNT# / GPIO SPI_MOSI PI Express Port onfig bit 0 (Port -) PI Express Port onfig bit (Port -) ESI Strap(Server Only) Top-lock Swap Override Integrated TPM Enable PWROK PWROK PWROK PWROK LPWROK 0 = efault = Setting bit 0 0 = Setting bit = efault 0 = MI for ESI-compatible = efault 0 = "top-block swap" mode = efault 0 = INT TPM disable(efault) = INT TPM enable GNT# SPI_MOSI R0 R *K_ *0K_ V_S LOK# REQ0# V 0 RN.K_0PR V IRY# PERR# INT# INTH# USO# USO# USO# USO#0 RN 0K_PR V_S GNT0# SPI_S# / GPIO / LGPIO oot IOS Selection 0 oot IOS Selection PWROK LPWROK PI_GNT#0 0 SPI_S# 0 oot Location SPI PI LP(efault) GNT0# SPI_S# R R *K_ *K_ Quanta omputer Inc. PROJET : ZR Size ocument Number Rev IHM PIE / PI / US Monday, pril, 00 ate: Sheet of

14 V_S R R R R R R R R R R R R0 R V R R R R R R R R R0 R R V_S R R R R0 0K_ 0K_.K_.K_ 0K_ 0K_ 0K_ 0K_ 0K_.K_ *0K_ 0K_ 0K_.K_.K_.K_ 0K_ *0K_ *0K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *00/F_ 0K_ 0K_ SM_LK_ME SM_T_ME PLK_SM PT_SM RI# IH_GPIO0 SYS_RST# SM_LERT# PIE_WKE# PM_TLOW# NSWON# IH_GPIO IH_GPIO LKRUN# SERIRQ THERM_LERT# E_SI# HMI_SET STLKREQ# MH_IH_SYN# KSMI#_IH LI#_IH PM_STPPI# PM_STPPU# IH_GPIO R_WKE# IH_PWROK IHM(LG) PWRTN : ms of internal debounce logic on this pin and internal PU K TPM Physical Presence for itpm. Stuff R HMI SET HMI,,,,,, PLK_SM PT_SM SYS_RST# PM_SYN# PM_STPPI# PM_STPPU# LKRUN#,, PIE_WKE# SERIRQ THERM_LERT# :(/) SF issue:when imt is not implemented, IHM SMus and SMLink should be connected together to support slave mode onnect SMLINK0 to SMLK and SMLINK to SMT (dd R,R for debug use), KSMI# LI# E_SI# STLKREQ# PSPK MH_IH_SYN# IH_TP T T T T T T T S S PLK_SM PT_SM IH_GPIO0 SM_LK_ME SM_T_ME RI# SYS_RST# SM_LERT# PM_STPPI# PM_STPPU# LKRUN# PIE_WKE# E0 M THERM_LERT# J VR_PWRG_LKEN KSMI#_IH G LI#_IH H HMI_SET G IH_GPIO IH_GPIO OR_I0 E OR_I K PNEL_I F OR_I J STLKREQ# L R_WKE# E IH_GPIO G IH_GPIO F MI_TERM_SELH IH_GPIO M MH_IH_SYN# J IH_TP H0 J0 J U G SMLK SMT E LINKLERT#/GPIO0/LGPIO SMLINK0 SMLINK F R SUS_STT#/LPP# G SYS_RESET# M PMSYN#/GPIO0 SMLERT#/GPIO STP_PI# E STP_PU# L 0 RI# LKRUN# WKE# SERIRQ THRM# VRMPWRG TP IHM REV.0 SM ST GPIO locks SYS GPIO Power MGT GPIO GPIO GPIO GPIO LN_PHY_PWR_TRL/GPIO ENERGY_ETET/GPIO GPIO GPIO GPIO0 SLOK/GPIO GPIO GPIO STLKREQ#/GPIO SLO/GPIO STOUT0/GPIO STOUT/GPIO GPIO GPIO/LGPIO SPKR MH_SYN# TP TP TP0 TP MIS GPIO ontroller Link ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST0# L_RST# MEM_LE/GPIO GPIO0/SUS_PWR_K GPIO/_PRESENT WOL_EN/GPIO H F E 0 H F P E G 0 G0 M R 0 R R F F F 0 ST[x]GP pins if unused require.-k to 0-k pull-up to Vcc_ or.-k to 0-k pull-down to ground OR_I PNEL_I0 IH_GPIO IH_GPIO IH_PWROK PM_TLOW# PM_LN_ENLE_R PM_RSMRST#_R L_VREF0_S L_VREF_S IH_GPIO0 IH_GPIO IH_GPIO R R R T T0 T T T T T T0 R R R0 ZS efault not support IMT. So this interface follow R/hecklist PU only R R 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ V M_IH LKUS_ SUS#, SUS#, PM_PRSLPVR, NSWON# *short00 *0_ PM_RSMRST#_R K_PWRG MPWROK, L_LK0 L_T0 L_RST#0 V_S For EMI(EMI) L_VREF_S V M_IH LKUS_ <hecklist ver0.> If integrated LN is not used LN_RST# tie it to GN.N serial R from RSMRST#. If Intel LN is used with Wake On LN, tie LN_RST# to RSMRST# and N 0ohm. L_PWROK must not assert after PWROK asserts for IMT. L_PWROK to the N and S should be connected to existing PWROK inputs on the N and S on a platform with no IMT L VREF *0p/0V_ *0p/0V_ R */F_ R *_ R0 *_ VREF R connect to V_S hecklist connect to V(iMT reserve) R *.K/F_ 00 *.u/0v_ L_VREF0_S <hecklist ver0.> The IHM ontroller Link VREF circuit is required only if Intel MT is to be supported. V R.K/F_ R /F_.u/0V_ R 0K_ HMI_SET R No HMI V_S R *0K_ E_SI# IH PWROK Resume RST PM_RSMRST#_R Q RSMRST# M/ I V I0=0 -->ZK,I0= -->ZR I=0 -->UM,I= -->iscrete V V V V R 0K_ PNEL_I R0 0K_ IH_GPIO R 0K_ IH_GPIO Follow HEK LIST V. V_S 0 *.u/0v_ IH_PWROK U TSH0FU R ELY_VR_PWRGOO need PU K to V. ZS PU at power side PWROK_E 00K_ ELY_VR_PWRGOO,,, PWROK_E R 0K_ R.K_ MMT0 R V V.K_ V_S Z INTEL FE (0/) "dd RSMRST# isolation (important!!! See ww Santa Rosa MoW)" efault stuff for Teenah(Interposer) chipset ZS Intel FE suggestion to add for to protect RT/MOS data from corruption when system encounters an abnormal power down sequence R R *0K_ *0K_ OR_I OR_I R R 0K_ 0K_ oard I R R0 EV@0K_ 0K_ OR_I OR_I0 R0 R IV@0K_ *0K_ I I I I0 -SMT,I=0 -->UM,I= -->iscrete 0 0 0/ South ridge Strap Pin (/) Pin Name Strap description Sampled onfiguration PU/P GPIO0 SPKR GPIO No Reboot MI Termination Voltage PWROK PWROK PWROK 0 = efault = No Reboot mode 0 = for desktop applications = for mobile applications Internal PU PSPK MI_TERM_SEL R R *K_ *K_ LK Enable VR_PWRG_K0# V V *.u/0v_ U0 VR_PWRG_LKEN NSZ0 R 00K_ 0 0 0/ 0 0 0/ 0 0 0/ 0 0 0/ Quanta omputer Inc. PROJET : ZR Size ocument Number Rev IHM GPIO Monday, pril, 00 ate: Sheet of

15 IHM(LG) Power consumption reference to Intel IH Family ES Rev. PER INTEL SUGGESTION: HNGE TO 00OHM & UF V V V_S V_S.V.V.V S0:m V S//:m R R.V VRT 0 Ohms@ 00 MHz, 00 L V.V m V m V S0:m S//:m ~.v.u_g.0v, Powered by V_0 in S0 R H 00/F_ H 00/F_ *short00.v m MOIFY LMPGSN. 0u/.V_ L L 0 u/.v_.v_ u/.v_ 0uH m.v_pll_ih 0 0u/.V_ u/0v_ VLN_ If use S M for LN function. nd support wake up need connect to relation power. uh m 0.u/0V_ S_VREF u/0v_ 0.u/0V_ VPU_IH_VREF_SUS.u/0V_.u/0V_.V m.v m.v m.u/.v_ 0 u/0v_ u/0v_.u/0v_.u/0v_ VLN_0_INT_IH 0.u/0V_.V_IH_GLNPLL_R 0u/.V_.u/.V_ E E E E E E F G H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J E F G H J E F G0 G H0 J0 G0 G J 0 E E UF VRT VREF VREF_SUS V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] VSTPLL V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] VUSPLL V [] V [] V [] V [] V [0] VLN_0[] VLN_0[] VLN_[] VLN_[] VGLNPLL VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ IHM REV.0 VGP RX TX US ORE GLN POWER ORE VPSUS VPUS VP_ORE PI V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] VH VSUSH VSUS_0[] VSUS_0[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VL_0 VL_ VL_[] VL_[] E F L L L L L L M M P P T T U U V V V V V V R W Y G J 0 F0 G 0 F G G J J K J J F F E F T T T T T T U U V V W W Y Y T G G.V_IH_VMIPLL.0u/V_ V_H_IO_IH V_VSUSH.0V_IH_MI 0.u/.V_ TP_VSUS_0_IH_ TP_VSUS_0_IH_ TP_VSUS IH_ VSUS INT_IH VL_0_INT_IH VL INT_IH VL_ 0.u/0V_.u/0V_.u/0V_ 0.u/0V_.u/0V_.0u/V_ *u/0v_ R.u/0V_ T T T If use S M for LN function. nd support wake up need connect to relation power..0v m.0v 0.u/0V_.V m L uh m 00 m, 0% 0u/.V_ 0 u/.v_.u/0v_.u/0v_.u/0v_.u/0v_.0u/v_ *.u/0v_ L.0V.V S0:m S//:m *short00 00 MHz, 0..u/.V_.V 0m.0V m V V_S.V S0:m S//:m V.V.0V m.0v EV@0_ V.V /.V m IV@0_.V V_S IV@0_.VSUS.V /.V S0:m S//:m VSUS_0 power by V_0 in S0 / VSUS_ in S/S/S VSUS_ power by V in S0 / VSUS_ in S/S/S.u/0V_.u/0V_ NQ00T-00Y-N 00m.u/0V_ R R.u/0V_ R R EV@0_ VL_0 power by V_0_ in S0 VL_ power by V in S0 Impact IHM VH and VSUSH supply.v/.v Support INT HMI H interface. These power only support.v.evice must to meet. NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. 0 E E E E E E E0 E E E E E F F F F H F F F F F G G G G0 G G G G H H H H H H H H H H J J J J 0 E E E E E E E E F F F G G G G G G G G H H H H UE VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] IHM REV.0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[] VSS_NTF[] H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J.V 0m.V_ MOIFY.u/.V_.V m V R0 *short00 VGLN_ Quanta omputer Inc. PROJET : ZR Size ocument Number Rev IH POWER Monday, pril, 00 ate: Sheet of