JOURNAL OF APPLIED SCIENCES Electronics and Information Engineering LDPC. LDPC. Design of LDPC Coder-Decoder Based on Cyclic Shift Matrices

Μέγεθος: px

Εμφάνιση ξεκινά από τη σελίδα:

Download "JOURNAL OF APPLIED SCIENCES Electronics and Information Engineering LDPC. LDPC. Design of LDPC Coder-Decoder Based on Cyclic Shift Matrices"

Γαλήνη Βλαβιανός
5 χρόνια πριν
Προβολές:

1 JOURNAL OF APPLIED SCIENCES Electronics and Information Engineering Vol. 27 No. 2 Mar : (2009) LDPC : DVB-S2 WiMAX LDPC LDPC ( ) ( ) LDPC. Altera EP2S /8, 6/8, 5/8, 4/8, 3/8 5 LDPC. 80 Mbit/s. : LDPC : TN : A Design of LDPC Coder-Decoder Based on Cyclic Shift Matrices GUAN Wu, DONG Ming-ke, XIANG Hai-ge School of Electronics Engineering and Computer Science, Peking University, Beijing , China Abstract: In this paper, the LDPC codes used in DVB-S2 and WiMAX are analyzed. A universal structure based on cyclic shift matrices is presented for these codes. A partially parallel decoder is designed with a universal storage resource reusing architecture and serial operation processors. This decoder has been implemented on an Altera EP2S60 platform, and can work for bit code length at rates 7/8, 6/8, 5/8, 4/8 and 3/8. Test results show that its code throughput can approach 80 Mbit/s. Keywords: low density parity check (LDPC) codes, decoder, cyclic shift matrices LDPC [1-2] DVB-S2 [3], CMMB [4], WiMAX [5], DTMB [6]. DVB-S2 WiMAX LDPC Lin [7] LDPC.. Mustafa [8] DVB-S2. DVB-S2 IRA-LDPC (irregular repeat-accumulate LDPC, LDPC ) WiMAX QC-LDPC (Quasi-cyclic LDPC LDPC ). LDPC FPGA LDPC [9]. LDPCLDPC. LDPC DVB-S2 WiMAX LDPC. DVB-S2 WiMAX LDPC LDPC : ; : : (No. 9140A JW02) : gxwu@pku.edu.cn xianghg@pku.edu.cn

2 ( ) ( ) DVB-S2 WiMAX LDPC FPGA [10]. 1 LDPC LDPC. 1 DVB-S2 CMMB IRA-LDPC (CMMB ) [3-4]. IRA-LDPC M NM = mp, N = np. 1 M M p 1 1 p 1 p 1 M/p. (1) 1 M = 12, N = 24, p = 4; 0, 4, 8 1 3, 5 7, , 4, (1) M M. M M 0, M/p, 2M/p,, (p 1)M/p, 1, M/p + 1, 2M/p + 1,, (p 1)M/p + 1,, M/p 1, M/p + (M/p 1), 2M/p + (M/p 1),, (p 1)M/p + (M/p 1) 1 M N. p 1 1 p 1 p 1 M/p. (2) (1) (2) p 1 p 1 p 1 M/p 0, M/p, 2M/p,, (p 1)M/p, 1, M/p + 1, 2M/p + 1,, (p 1)M/p + 1,, M/p 1, M/p + (M/p 1), 2M/p+(M/p 1),, (p 1)M/p+(M/p 1) p p,. (3) (2) (3)

3 2 : LDPC 119 LDPC 2 LDPC QC-LDPC WiMAX DTMB [5-6]. QC-LDPC (3) 1 1. LDPC LDPC 1 1. DVB- S2 WiMAX LDPC. (1) (3)LDPC. 3 LDPC. 2 LDPC LDPC N = np M = mp mnp p [9] ( ) ( ) m (n ) (check node unit ) p m m. n (variable node unit, VNU). p VNU 1 2p. [9] ( ) ( ) 2. 2 p 1 p. ρ ρ. p VNU. mρ nλ (λ ); VNU 1 mρ + nλ. VNU VNU VNU 1 ( ) ( ) m (n ) Figure 1 Architecture for decoding row(column) by row(column) per block and block with block parallelly VNU VNU 2 ( ) ( ) Figure 2 Architecture for decoding block by block and block-row(column) with block-row(column) parallelly 1. 1 Table 1 Comparisons of the two decoding architectures [9] ( ) ( ) m (n ) 1 p p ( ) ( ) nλ mρ ( ) ( ) VNU

4 λ ρ p p LDPC1 nλ mρ. 2.2 LDPC.. p p 1 p. p ( ) 1 1 p. (3) (x, y) x y 1(3) 2. 2 Table 2 Example for the universal storage resource reusing architecture 1 ( ) 2 ( ) (0,1) (1,2) (2,3) (3,0) (3,0) (0,1) (1,2) (2,3) (0,6) (1,7) (2,4) (3,5) (4,0) (5,1) (6,2) (7,3) (0,7) (1,4) (2,5) (3,6) (6,0) (7,1) (4,2) (5,3) (0,9) (1,10) (2,11) (3,8) (5,0) (6,1) (7,2) (4,3) (0,12) (1,13) (2,14) (3,15) (9,0) (10,1) (11,2) (8,3) (0,23) (1,20) (2,21) (3,22) (2,4) (3,5) (0,6) (1,7) (4,0) (5,1) (6,2) (7,3) (1,4) (2,5) (3,6) (0,7) (4,2) (5,3) (6,0) (7,1) (8,4) (9,5) (10,6) (11,7) (4,3) (5,0) (6,1) (7,2) (11,4) (8,5) (9,6) (10,7) (4,11) (5,8) (6,9) (7,10) (10,4) (11,5) (8,6) (9,7) (4,12) (5,13) (6,14) (7,15) (3,8) (0,9) (1,10) (2,11) (4,16) (5,17) (6,18) (7,19) (5,8) (6,9) (7,10) (4,11) (8,3) (9,0) (10,1) (11,2) (10,8) (11,9) (8,10) (9,11) (8,4) (9,5) (10,6) (11,7) (9,8) (10,9) (11,10) (8,11) (8,5) (9,6) (10,7) (11,4) (0,12) (1,13) (2,14) (3,15) (8,6) (9,7) (10,4) (11,5) (4,12) (5,13) (6,14) (7,15) (8,10) (9,11) (10,8) (11,9) (4,16) (5,17) (6,18) (7,19) (8,11) (9,8) (10,9) (11,10) (8,16) (9,17) (10,18) (11,19) (8,16) (9,17) (10,18) (11,19) (1,20) (2,21) (3,22) (0,23) (8,20) (9,21) (10,22) (11,23) (8,20) (9,21) (10,22) (11,23) p

5 2 : LDPC p = 4 p. 5 p (3) 0 (p 1). p ROM. ROM. LDPC p ROM [11] ( d ) v i v ij = u 0i + u ki u ji (4) k=1 3 u 0i u ki v ij d i. ACC(4) SUB REG FIFO Sum u ji. Init ACC ShiftNum u ji. Init ShiftNum ShiftNum=d v i ACC Sum u 0i u ki (d v i 1) u kiinit ShiftNum FIFO Init Sum REG FIFO SUB REG Sum FIFO u ji v ij Sum d i. u 0i u ki ACC Init Sum u ji FIFO ShiftNum REG 3 SUB Figure 3 Architecture of a universal VNU [11] u ji = [ dc j k=1 ] d c j sgn(v kj ) sgn(v ij ) min v kj (5) k=1,k i 4 v kj u ji. CMP1 v kj Min&SubMin v ij SgnSum REG FIFOv ij ShiftNum. CMP2 REG Min FIFO Min FIFO u ji SubMin u ji Min u ji REG SgnSum FIFOs ij. Init CMP1 ShiftNum v ij s ij. v kj CMP1 Init v ij s ij Min& SubMin SgnSum FIFO ShiftNum REG 4 CMP2 Figure 4 Architecture of a universal d i v ij u ji

6 [11]. 2.4 LDPC N = np M = mp p p ROM 2. ROM. ROM u ki. Rotation p ROM p CxInfo p p VNU p InvRotation ROM p d i DecBit 1. p. 1 p Rotation InvRotation.. CxInfo VNU VNU 0 1 DecBit InvRotation u ki Addr Data Rotation 0 d 0,0 d 0,1 d 0,p-1 1 d 1,0 d 1,1 d 1,p-1 2 d 2,0 d 2,1 d 2,p-1 VNU 3 d ROM 3,0 d 3,1 d 3,p-1 p-1 4 d 4,0 d 4,1 d 4,p p-1 5 d 5,0 d d 5,1 5,p-1 u 0i d i v ij 5 Figure 5 Architecture of a universal LDPC decoder p. ROM LDPC. ROM LDPC LDPC. v kj u ji 3 7 Altera EP2 S60F484C4 [10] /8, 6/8, 5/8, 4/8, 3/8 LDPC. LDPC Quartus / bit ALUT / 3 FPGA Table 3 FPGA synthesis report (68%) / bit / (22%) / MHz / (Mbit s 1 ) FPGA LDPC 6. [10]. 7/8, 6/8, 5/8, 4/8, 3/8, LDPC 3.82, 2.69,1.91,1.55,1.34 db 1 E 6 [10] 0.2 db. BER MR-Hard-7/8 MR-Hard-6/8 MR-Hard-5/8 MR-Hard-4/8 MR-Hard-3/8 MR-S oft-7/8 MR-S oft-6/8 MR-S oft-5/8 MR-S oft-4/8 MR-S oft-3/ (E b /N 0 )/db 6 LDPC Figure 6 BER performance of the universal LDPC decoder 4 DVB-S2 WiMAX LDPC. LDPC LDPC. AlteraEP 2S60 F1020C /8, 6/8, 5/8, 4/8, 3/8 5 LDPC.

7 2 : LDPC Mbit/s. : [1] Mackay D J C, Neal R M. Near Shannon limit performance of low-density parity-check codes [J]. Electronics Letter, 1996, 32(18): [2] Chung S Y, Forney G D Jr, Richardson T J, Urbanke R L. On the design of low-density paritycheck codes within db of the Shannon limit [J]. IEEE Communications Letters, 2001, 5(2): [3] ETSI EN Second generation framing structure, channel coding and modulation system for broadcasting, interactive services[s] News Gathering and Other Broadband Satellite Applications, [4] 1 [S] Mobile multimedia broadcasting part 1: framing structure, channel coding and modulation for broadcasting channels [S]. [S.l.]: Chinese Standard, 2006.(in Chinese) [5] IEEE Std e. IEEE standard for local and metropolitan area networks part 16: air interface for fixed and mobile broadband wireless access systems, amendment 2: physical and medium access control layer for combined fixed and mobile operation in licensed bands [S] [6] [S] Framing structure, channel coding and modulation for digital television terrestrial broadcasting system [S]. [S.l.]: Chinese Standard, 2006.(in Chinese) [7] Lin Zhichu, Yang Zhixing, Pan Changyong. A new design method of multi-rate quasi-cyclic LDPC codes [C]// Communications, Circuits and Systems Proceedings, 2006: [8] Mustafa E, Sun F W, Lee L N. An innovative lowdensity parity-check code design with near-shannonlimit performance and simple implementation [J]. IEEE Transaction on Communications, 2006, 54(1): [9]. LDPC [J]. 2006, 2: Yang Zhixing, Lin Zhichu, Wang Jun. Design of semiparallel decoder for quasi-cyclic LDPC codes [J]. Video Engineering, 2006, 2: (in Chinese) [10]. LDPC [J]. 2009, 37(6). Qiao Hua, Guan Wu, Dong Mingke, Xiang Haige. Research on multi-rate LDPC Codes [J]. Journals on Electronics, 2009, 37(6). (in Chinese) [11] Chen J H, Tanner R M, Jones C, Li Y. Improved min-sum decoding algorithms for irregular LDPC codes [C]//International Symposium on Information Theory, : ( : )

Σχετικά έγγραφα

Protograph-based LDPC decoder applied to magnetic recording channel

Protograph-based LDPC decoder applied to magnetic recording channel 25 6 Vol. 25 No. 6 2013 12 Journal of Chongqing University of Posts and Telecommunications Natural Science Edition Dec. 2013 DOI 10. 3979 /j. issn. 1673-825X. 2013. 06. 016 LDPC FPGA 1 2 2 2 1. 400065