Design Method of Radix Converters (4)

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1 THE INTITUTE OF ELECTRONIC, INFORMATION AND COMMUNICATION ENGINEER TECHNICAL REPORT OF IEICE. (4) RN y yy y yy RN (residue number system: ), RN,, RN, FPGA,,, FPGA. Design Method of Radi Converters (4) RN to binary Converters ukihiro IGUCHI y and Tsutomu AAO yy y Deartment of Comuter cienece, Meiji University yy Deartment of Comuter cienece and Electronics, Kyushu Institute of Technology Abstract In digital signal rocessing, RN (residue number system) is often used for high-seed comutation. In such cases, radi converters are necessary. This aer resents design methods of radi converters from residue numbers into binary numbers. We have develoed an automatic design system for RN to binary converters. Various radi converters were designed to comare their erformance. Key words Radi converter, residue number system, multile valued logic, FPGA. 1.,, [9].,, (Residue Number ystem, RN) [] [5], [8], [9], [14]., RN [1]., AD(Analog Digital: ),, 18 RN, [], [4], [1].,,,, 1 ο 15, (Chinese remainder theorem, CRT) [1] [], [1].,,,, CRT,, Carry ave Adder (CA), [], [1], [14]., AND-OR,,, CRT, RN, FPGA,. (Residue Number ystem, RN). 1 [14] ( RN ), X n (m 1, m,:::, m n), (r1, r,:::, r n).1 X m i q i, r i (i =1; ;:::;n)., X = q i mi ri r i, [;m i 1] ri = X(mod mi). X n (n > = ) (m 1, m,:::, m n), (r1, r,:::, r n) =(X (mod, X m1) (mod, :::;X m) (mod ). mn) X RN(m 1, m,:::, m n), Xrns(m1 ;m;:::;mn) = ( 1,,:::, n) RN(; 5; ), 1rns(;5;) = (1 (mod ; ) 1 (mod ; 5) 1 (mod )=(; ; 5) ).. M = nq m i RN M. RN(; 5; ) RN, M = 5 = 15., [,14] 1

2 . RN 1 z 1 RN.. 1, AD X n n z z n Z DA, RN,, (X ± ) (mod m) =(X (mod m) ± (mod m) ) (mod m) (.1) (X ) (mod m) =(X (mod m) (mod m) ) (mod m) (.). X =1, =5. RN(; 5; ), 1rns(;5;) =(; ; 5), 5rns(;5;) =(; ; 5). 1 X : (X )rns(;5;) = (1 5)rns(;5;) =(; ; )., (( ) (mod ) ; ( ) (mod 5) ; (5 5) (mod )=(; ; ), ) X : (X )rns(;5;) =(1 5)rns(;5;) =(1; ; )., (( ) (mod ) ; ( ) (mod 5) ; (5 5) (mod )=(1; ; ), ) (mod =1. ) X : (X )rns(;5;) = (1 5)rns(;5;) = (; ; 4)., (( ) (mod ) ; ( ) (mod 5) ; (5 5) (mod )=(; ; 4). ), ( X (mod, mi) i =1;:::;n ).,, RN,, RN,, RN [9],, RN,. RN RN.1..1(a), 1 AD X., RN, n n X (mod mi), X, RN ( RN ) RN, DA(Digital Analog),,..1(b), AD, AD RN, RN, AD, 8 14, AD AD X.1 1 y 1 y n y n RN 14, RN RN, RN X RN(m 1,m,:::,m n), X rns(m1 ;m;:::;mn) =( 1,, :::, n)., X ~ = ( 1; ;:::; ) 1. ( 1,, :::, n), ~ RN-, -RN.1 RN(,4).1. RN, ( 1, ). n z 1 z z n Z DA, ~ = ( ; ; 1; ). (m 1;m ) = (; 4), 1 =[; ], =[; ] d,. RN-.1 ( ) [1] X rns(m1 ;m;:::;mn) =( 1; ;:::; n). (1; ;:::; n), i f; 1;:::;mi 1g X. X =( nx M i(ffi i)(mod mi) ) (mod M) : Q n 1 M = mi, Mi = M=mi, ffi =(M i ) (mod, mi) m i. RN(,5,) M = 5 = 15. M 1 = M= = 5, M = M=5 = 1, M = M= = 15. ff 1 =, 1 i, i

3 .1 Xrns(;4) Binary Decimal d d d d d d d d d d d d d d d d d d d d RN(,4)- ff = ff =1., X = ff 1 = m 1 =, ( 5) (mod ) = (mod =1 ) RN-, RN Mied RN, [14]., RN-, 1 RN-, RN, ( CRT ),,,,. RN- P 1, n dlog mie., Q n dlog M e,, M = mi., dlog n m ie P n dlog mie [bits].1(a) RN(,5,), 8 [bits]..., RN-. CRT,,, (mod M )..1(b) RN(,5,)-., 1,, [; ], [; ], [; ],,, 1, f; ; 14g, CRT = ( ) (mod M) = 1 [, ] [, 4] [, ] 1 1 (mod M) [, ] [, 4] 1 ( ) (mod 15) (a) (mod M) 15 [, ] = ( ) (mod M), M = 15. A B A B M - M (a) (b) (b) RN [,14] (mod M) [,14] MB MB M UM UM ((( 1) (mod M) 1) (mod M) 15) (mod M), 1 ( 1) (mod, M) f; 5; g M, M..(a)., A B<M A B M, ( A B<M) A B, ( A B > = M) A B M,.(a),.(b) M,,,...., M,, M

4 , CRT, 1;:::; n,,,.4. RN(,5,)-.(a), , , ,,,,.(b),, =, 5 1 = 4,, HDL (Hardware Descrition Language),,,,,,.,.(c),.(b),.(d).(c).(a),.(d),, FPGA,.. 4 RN-, M (q ) ( ) q. q. P P n ( Mi(ffi i) (mod mi) ) (mod M) = n Mi(ffi i) qm. q.1 q, 1, ;:::; n, CRT,, M, M,:::, qm, CRT,, D ( ) (mod 15) D. RN- AND, OR.5 RN(,5,)-, s 15 =(s > = 15), s 1 =(s > = 1), s = s 15 =( 1 > = ) ( > = 5) _ ( > = ) ( > = ) _ ( > = 4) ( > = ) _ ( 1 > = 1) ( > = ) _ ( 1 > = 1) ( > = 1) ( > = 1) _ ( 1 > = 1) ( > = ) _ ( 1 > = ); s 1 =( 1 > = 1) ( > = ) ( > = ) _ ( 1 > = 1) ( > = 4) ( > = 4) _ ( 1 > = ) ( > = 5) _ ( 1 > = ) ( > = 1) ( > = ) _ ( 1 > = ) ( > = ) ( > = ) _ ( 1 > = ) ( > = ) _ ( > = 1) _ ( 1 > = ) ( > = 4); EL =(s 1; μs 1 s 15):..5 s ,, 1, (; ; ) (; 4; ) > = 15 ( 1; ; )= (; ; 5) > = 15 (T: True), ( 1 > = ) ( > = ) ( > = 5) 1 [; ] ( 1 > = ) = 1 4

5 1 F 1 F F 1 F 1 F F 4 F 5 T F F T 4 F 4 1 F 4 T 1 F 1 F 1 T 1 1 F T 1 T T > 15 ( 1 > )( > ) ( > 5) = ( > ) ( > 5) ( > ) ( > ) ( > 4) ( > ) ( 1 > 1) ( > ) ( 1 > 1)( > 1) ( > 1) ( 1 > 1) ( > ) ( 1 > ), ( > = ) ( > = 5) ( 1; ; )= (; ; 5) (; ; ), (; ; 5) > = 15, > = 15, (; ; ), ( > = ) ( > = ), ( > = 4) ( > = ), ( 1; ; )= (; 4; ), (1; ; ).5 s , PLA (Programmable Array Logic) [11], ffl (AND), (OR) 4. FPGA FPGA (Field Programmable Gate Array) RN-,. Verilog HDL,,.(d) ( 4.1 ) Verilog HDL, RN- AND-OR, Verilog HDL RN- 1 1 >= 1 1 >= >= 1 >= >= >= 4 >= 1 >= >= >= 4 >= 5 >= AND OR s 1 s.5 RN-, don t care, don t care Altera FPGA (Field Programmable Gate Array) Cyclone II 4.1., Cyclone II trati II, 4.1 Design, rns 5, m 1 =, m = 5, m =. Range M = m 1 m m n In Out rns 5 =8 In =8, [; 14] Out =.,, LE (Logic Element), LE trati II ALUT Delay, 4.1 Range LE 4.. Cyclone II Range LE, rns8 19 rns 19 1 Range LE, 9 59, rns19 Range rns1 1 1 Range LE 1. Range, 5., RN-, RN(,5,), FPGA,, 5

6 TART 14 Altera Cyclone II (EPC5FC) 1 Verilg HDL 1 Verilg HDL Quartus II Ver. FPGA Bit File TOP 4.1 RN- 4.1 RN- Altera FPGA Design Range In Out LE(ALUT) Delay[ns] FPGA rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns A rns (1114) 48. B rns (15455) 5.5 B A: Cyclone II (EPC5FC) B: trati II (EP18F158C5),,, ( ) FPGA,, [1] M. Ciet, M. Neve, E. Peeter, and J.-T. Quisquater, Parallel FPGA imlementation of RA with residue number systems, Can side- #Logic Elements Range Range Logic Element channel threats be avoided?, MIDWET, Aril. [] R. Conway and J. Nelson, Fast converter for moduli RN using new roerty of CRT, IEEE Trans. Comut., Vol. 48, No. 8, Aug [] P. V. Ananda Mohan, Residue Number ystems: Alogrithms and Architectures, Kluwer Acadeic Publ. (). [4] J. P. Deschams, G. J. A. Bioul, and G. D. utter, yntehesis of Arithemetic Circuits, FPGA, AIC, and Embedded ystems, Wiley, March. [5] M. Honda, M. Kameyama, and T. Higuchi, Multile-valued VLI image rocessor based on residue arithmetic and its evaluation, IE- ICE Trans. Electron., Vol. E-C, No., , March 199. [] C. H. Huang, A fully arallel mied-radi conversion algorithm for residue number alications, IEEE Trans. Comut., vol.,. 98-4, 198. [] K. Ishida, N. Homma, T. Aoki, and T. Higuchi, Design and verification of arallel multiliers using arithmetic descrition language: ARITH, 4th International ymosium on Multile-Valued Logic, Toronto, Canada, May 4,.4-9. [8] M.A.oderstrand, W.K.Jenkins, G.A.Jullien and F.J.Taylor Ed., A new scaling algorithm in symmetric residue number system based on multile-valued logic in residue number system arithmeitc, in Modern Alications in Digital ignal Processing, IEEE Press, 198. [9] I. Koren, Comuter Arithmetic Algorithms, nd Edition, A. K. Peters, Natick, MA,. [1] D. Olson, and K. W. Current, Hardware imlementation of sulementary symmetrical logic circuit structure concets, th IEEE International ymosium on Multile-Valued Logic Portland, Oregon, May -5,. [11] T. asao, witching Theory for Logic ynthesis, Kluwer Academic Publishers, [1],,, Vol. J8-A, No.9, e [1] untzu,, Third-century AD. [14] F. J. Taylor, Residue arithmetic: A tutorial with eamles, IEEE Comuter,. 5-, Vol. 1, May 1984.