FPGA. Variations and BTI-induced Aging Degradation on Commercial FPGAs. Shouhei ISHII and Kazutoshi KOBAYASHI, 3 FPGA JST, CREST

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1 THE INSTITUTE OF ELECTNICS, INFORMATION AND COMMUNICATION ENGINEERS TECHNICAL REPORT OF IEICE. FPGA BTI, JST, CREST FPGA BTI FPGA 9nm 6nm FPGA FPGA FPGA (5 C)8 C 3, BTIFPGA Variations and BTI-induced Aging Degradation on Commercial FPGAs Abstract Shouhei ISHII and Kazutoshi KOBAYASHI, Graduate School of Science & Technology, Kyoto Institute of Technology JST, CREST In this paper, we focus on problems concerning variations and degradation on FPGAs which has become dominant due to scaling and quantitatively estimate the degradation of FPGAs by BTI. We show the relationship between variation and degradation. To measure degradation of 9nm and 6nm FPGAs, we map ring oscillators on FPGAs and measure standard deviation of oscillation frequency. As for degradation of FPGAs, we measure variations of oscillation frequency for 3, seconds at the room temperature (5 C) or 8 C. Key words BTI, FPGA, Variation, Degradation. [] FPGA (Field Programmable Gate Array) FPGA BTI (Bias Temperature Instability) BTI pmos nmos [] (Dynamic) (Static) BTI [3] Altera 9nm FPGA Cyclone II 6nm FPGA Cyclone IV FPGA FPGA 3 FPGA FPGA FPGA FPGA (Ring Oscillator) FPGA. FPGA FPGA Altera 9nm FPGA Cyclone II 6nm FPGA Cyclone IV FPGA FPGA Logic Array Logic Array Block (LAB) LAB LAB Logic Element (Logic Cell

2 IOE ENABLE Logic Array Block IOE Logic Array Logic Array IOE Logic Element SEL[:] 3 DEMUX 3 MUX OUT Logic Array Block IOE FPGA 4 DEMUX MUX dataa Logic Element Start datab datac Look-Up Table (LUT) Carry Chain combout D regout datad CK uartus IIConfiguration (sof) labclk LE sof IN DIV:DIV D CK x4 DIV D CK OUT sof FPGA 3 ) LE FPGA Cyclone II Cyclone IV LE LE 9nm FPGA 88 6nm FPGA (DIV:Divider) 3 4 DEMUX (Demultiplexer) MUX (Multiplexer) Configuration (FPGA ) 4 Enable High 4 DEMUX MUX DEMUX End 5 FPGA 4 FPGA 4. 3 FPGA 5 FPGA

3 . 3. FPGA FPGA Altera uartus II qsf (uartus II Settings File) qsf Verilog VHDL FPGA sof (SRAM Object File) qsf Perl qsfsof. 3. sof GPIO (General Purpose Input/Output) FT45RL (USB ) GPIO FPGA PC 3GHz 3 4 () 4 ( 8 ) DIV 3 3 = 4, 94, 967, FPGA GPIO ( ) %6.53% 6 4 ENABLE 4 ENABLE D-FF RESET GPIO = D-FF D-FF 4 OUTERSELOUTENABLECOUNTOUT CLEAR 6 OUTERSELOUTENABLECOUNTOUTCLEAR FPGA 4 ENABLED-FF GPIO FPGA. 4 GPIO FPGA GPIO FPGA FT45RL 8 GPIO ENABLE DEMUX SEL[:] 3 6 FPGA Cyclone II JTAG 3 MUX CLEAR x8 CLEAR DIVx6 x6 3 COUNTOUT[3:] OUT OUTENABLE FT45RL FPGA MUX USB Blaster DIVx4 GND Configuration FPGA GND GPIO GPIO + - PC OUTERSEL[:] GND FPGAGPIOPC GPIO GPIO Port (DB DB7) GND FT45RL 8 GPIO Port FPGA USB FT45RL PC PC PC FT45RL FPGA FPGAGPIOPC 7 FPGA (SEL[]SEL[]) ENABLE (ENABLE) D-FF (CLEAR) (OUTERSEL[]OUTERSEL[]) ENABLE (OUTENABLE) (COUNTOUT[] COUNTOUT[3]) GPIO FPGA FPGA GPIO 4 GPIO Windows 3. FPGA BTI FPGA BTI (5 )8 BTI 3

4 8 DC 4 FPGA 6nm PFGA GPIO FPGA 4., 3 4. FPGA. 3.,. 3. 9nm 6nm FPGA 6 9nm FPGA 448 6nm FPGA 44 9nm FPGA 6nm FPGA 3 FPGA 8, 9 dataa dataa datab datab Logic Element (LE) Verilog 6 mask LUT FF datab datab LUT 6 Lut mask uartus II Verilog LE 6nm FPGA LUT mask datab data_a EN data_a EN data_b data_b LUT LUT SEL[] data_c SEL[] data_c SEL[] data_d SEL[] data_d 8 dataa 9 datab () [GHz] dataa(6nm FPGA).8 datab(6nm FPGA).5 datac(6nm FPGA). datad(6nm FPGA) dataa(9nm FPGA).8 datab(9nm FPGA).4 datac(9nm FPGA) datad(9nm FPGA) 9nm FPGA [GHz] [%] [] [].45.7 [] [3] nm FPGA [GHz] [%] [] [] [] [3] datab 9nm FPGA 6nm FPGA 9, 3 9nm 6nm FPGA.5% FPGA [3] [3] LUT mask [] [] mask % 3 LUT mask [] [3] % LUT mask 9nm 6nm FPGA %,, 4

5 Probability density 5 5 Theoretical curve Measurement Count number Room Temperature 8 degrees.36 3 Time[s] 4 5 9nm FPGA 3 9nm FPGA Probability density Theoretical curve Measurement Count number 6nm FPGA [] [] [] [3] 3 DC 3 DC 4. FPGA BTI 3 FPGA BTI =3,75 ( 8.5 ) 9nm 6nm FPGA 6nm FPGA 8 9nm FPGA 3 6nm FPGA Room Temperature 8 degrees Time[s] 6nm FPGA 4 3,s[%] [%] 9nm FPGA().85. 9nm FPGA(8 C) nm FPGA(:) nm FPGA(:8 C) nm FPGA(:) nm FPGA(:8 C) , () 4 6nm FPGA 6nm FPGA 9nm FPGA 4 6nm FPGA % (6nm FPGA(: ) Fitting ) 4. 3 V th t n [4] V th at n () f V th [5] f 5

6 Room Temperature 8 degrees Time[s] 6nm FPGA 5 () a, n, f a n f 9nm FPGA() nm FPGA(8 C) nm FPGA(:) nm FPGA(:8 C) nm FPGA(:) nm FPGA(:8 C) f = f αt n + f at n + f () n n /6 /4 [], [6]t n n 5 5 n LE 6nm FPGA /6 /4 fitting n 6nm FPGA 5. FPGA BTI FPGA Altera 9nm Cyclone II 6nm Cyclone IV FPGA LUT 6 LUT mask Verilog LUT mask LUT mask LUT mask FPGA 9nm FPGA 3%6nm FPGA 4.7%LUT mask 9nm 6nm FPGA % FPGA (5 C) 8 C 3, 6nm FPGA f = at n + f n ( ) 6nm FPGA n (8nm, nm) FPGA [] A. W. Strong, E. Y. Wu, R.-P. Vollertsen, J. S. G. LaRosa, I. Stewart E. Rauch and T. D. Sullivan: Reliability Wearout Mechanisms in Advanced CMOS Technologies, A JOHN WILEY & SONS, INC. (9). [] K. Kang, K. Kim, A. E. Islam, M. A. Alam and K. Roy: Characterization and estimation of circuit reliability degradation under NBTI using on-line IDD measurement, Proceedings of the 44th annual Design Automation Conference, DAC 7, New York, NY, USA, ACM, pp (7). [3] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu and Y. Cao: The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 8,, pp (). [4] E. A. Stott, J. S. Wong, N. P. Sedcole and P. Y. K. Cheung: Degradation in FPGAs: Measurement and Modelling, FPGA (Eds. by P. Y. K. Cheung and J. Wawrzynek), ACM, pp (). [5],, (). [6] K. Ramakrishnan, S. Suresh, N. Vijaykrishnan and M. Irwin: Impact of NBTI on FPGAs, VLSI Design, 7. Held jointly with 6th International Conference on Embedded Systems., th International Conference on, pp (7). 6