Co-decode algorithm of network coding with hardware logic

HTML
DOWNLOAD

Μέγεθος: px

Εμφάνιση ξεκινά από τη σελίδα:

Download "Co-decode algorithm of network coding with hardware logic"

Σαῦλος Μαυρογένης
8 χρόνια πριν
Προβολές:

1 33 7 Vol.33 No Journal on Communiations July NetFPGA NetFPGA TN762 A X(2012) Co-deode algorithm o network oding with hardware logi LI Hui 1, ZHANG Ming-long 1, CHEN Fu-xing 1, HOU Han-xu 1, PAN Kai 1, WANG Wei 1, YUAN Hu-sheng 2, SUN Tao 2 (1. Shenzhen Key Lab o Cloud Computing Tehnology and Appliation, Shenzhen Graduate Shool, Peking University, Shenzhen , China; 2. Network & Inormation Center o Shenzhen University Town, Shenzhen , China) Abstrat: Pratial general oder and deoder o network oding (NC) with HDL (hardware desription language) logi or wire-speed nodes was presented. The NC oders applied random linear network oding (RLNC) and the deoders reovered the original pakets by Cramer s rule. The strutures and algorithms o NC oder and deoder were designed in detail and implemented in HDL with NetFPGA boards. Comparing with traditional stored-and-orward mehanism, network emulations showed that networks with wire-speed NC oder and deoder nodes ould ahieve the apaity bound o max-low min-ut theorem, and the end-to-end delay was guaranteed on a small onstant. Key words: network oding; oder; deoder; NetFPGA 1 [1] [2] Bhattad [3] [4] CB A, A A Foundation Items: The National Basi Researh Program o China (973 Program) (2012CB315904); The National Natural Siene Foundation o China ( ); Basi Researh o Shenzhen ( A, A); Shenzhen Industry ( A); The Natural Siene Foundation o Guangdong Provine ( )

2 2 33 NetFPGA [5,6] [7] [8] [8] m t S 1, S 2,, S m X 1, X 2,,X m R i (i=1,2,,n) P 1,P 2,,P m X 1,X 2,,X m P1 = a1 X1 + a2 X 2 + L am X P2 = b1 X1 + b2 X 2 + L bm X M P = h X + h X + L h X m m m m m (1) 1~ 3 [9~11] S k (k=1,2,,8) n R i (i=1,2,,n) 1 8 n [8] 2 8 n

3 7 3 E j (j=1,2,,8) 8 S (n,x 1) S n X (X>0) 1 S(1, x) in( E j ) = j = 1, 2,,8 2 S(2, y) GF(256) (α β) E j S(1, x) = ( α β ) = α S(1, x) + β S(2, y) (2) S(2, y) (1) 3 S 0 S 1 R 0 R 1 ei 4 3 G = (V, E) S i V (i = 1, 2,, m)r j V (j = 1, 2,, n) IP IP IP IP MNCP IP IP IP IP 254 MNCP MNCP MNCP IP MNCP MNCP 4 MAC IP MNCP 4 MNCP IP IP IP [2] MNCP 3(a) e 2 S(0, x) (α S(0, x)+ β S(1, y)) α e 1 0 S(0, x) O( e) = ( αe βe ) α β S (1, y) S(0, x) = ( αe + βeα ββe ) S(1, y) ( α e α ) S ( 0, x) β S ( 1, y) = + + (3) ( α β α ) + β e e MNCP

4 S(0, x) O( ) = ( α β ) α β S (1, y) S(0, x) = ( β α α + ββ ) S(1, y) = β α S + α + β β S (4) ( 0, x ) ( ) ( 1, y) i 1 0 αe β 0 0 e α β S(0, x) O( i) = 0 0 α β 0 1 S(1, y) α β ( αeαi βeααi βiβ α α βi β βiβ ββeαi ) = S S (0, x) (1, y) ( α α β α α β β α ) ( α β β β β β β α ) = + + S + e i e i i (0, x) + + S (5) i i e i (1, y) R 0 2 P K P = β αs( 0, ) + ( α + ββ x ) S ( 1, y ) K = ( αeαi + βeααi + βiβ α ) S(0, x) + (6) ( α βi + β βiβ + ββeα i ) S(1, y) MNCP 1 IP MNCP 1 1 IP 1) or do 2) i ( IP ) then 3) 4) else i ( IP IP ) then 5) IP MNCP 6) else 7) (2) 8) 5 MNCP 9) 4 10) 11) end i MNCP 5 MNCP [8](0010) 2 4byte MNCP MNCP MNCP byte MNCP 01 MNCP 10 IP GF(256) MNCP i (5) α i α e α i + α α i + β α α + β β + β α i MNCP 6 MNCP (4bit) (4bit) (16 bit) (2bit) (6bit) 1 2 (4bit) (4 bit) 8 (12bit) (4bit) (12bit) (8bit) (12bit) (12bit) (8bit) 5 MNCP

5 7 5 MAC α αeβ β = α + β α e e (9) α α β β β e h k w t α = g, α = g, β = g, β = g, v β = g e e e g α = g + g h+ w+ t h v+ k (10) [2,12] = (a) R 0 (6) β α α + ββ 0 α α + β α α + β β α α β + β β β + β β α e i e i i i i e i αeβiα + αeβiβ β + αα βeβi 0 (7) α e α + α e β β + α α = T T P(T 0)=1 P(T=0) F2 8 ( 0 ) P(T=0) αeβiα + αeβi β β + αα βeβi = 0 (8) αeα + αeβ β = αα βe α P(T=0)=1/255 P(T 0)=0.996 NetFPGA 2 2 (CAM) CAM (1) (1) (1) d 0 a b P d P X t K b a = Y d t = K d a b a b (6)(7)

6 6 33 S = S = (0, x) α + β β α β + β β β + β β α i i e i P K β α α + β β α α + β α α + β β α α β + β β β + β β α (1, y) e i e i i i i e i P K β α α α + β α α + β β α e i e i i β α α + β β α α + β α α + β β α α β + β β β + β β α e i e i i i i e i 7 MNCP MNCP N DP C DP P N 1) while (P N 0) do 2) i (C DP ) then 3) C DP = N DP ; 4) N DP = N DP + 1; 5) Return to 2); 6) else i () then 7) ; 8) P N = P N 1; 9) C DP = N DP ; 10) N DP = N DP + 1; 11) Return to 1); 12) else 13) ; 14) ; 15) P N = P N 1; 16) C DP = N DP ; 17) N DP = N DP + 1; 18) Return to 1); 19) end i 20) end while 7 3 Verilog NetFPGA IP MAC 125MHz FPGA CAM 64

7 7 7 IXIA Optixia XM12 IPv4 3(a) % IPv4 500Mbit/s HDL IPv4 [1] AHLSWEDE R, CAI N, LI S Y, et al. Network inormation low[j]. IEEE Trans on Inormation Theory, 2000, 46(4): [2] CHOU P A, WU Y, JAIN K. Pratial network oding[a]. Allerton Conerene on Communiation, Control, and Computing, Montiello[C] [3] BHATTAD K, RATNAKAR N, KOETTER R, et al. Minimal network oding or multiast[a]. Proeedings o International Symposium on 8 IPv ms IPv4 500Mbit/s 10ms 9 IPv4 Inormation Theory[C] [4] KIM M, MEDARD M, AGGARWAL V, O REILLY U, et al. Evolutionary approahes to minimizing network oding resoures[a]. IEEE INFOCOM[C] [5] [6] GIBB G, LOCKWOOD J, NAOUS J, et al. NetFPGA an open platorm or teahing how to build gigabit-rate network swithes and routers[j]. IEEE Transations on Eduation, 2008,51(3): [7] SUNDARARAJAN J K, MEDARD M, KIM M J, et al. Network oding in a multiast swith[a]. IEEE INFOCOM[C] [8] ZHANG M L, LI H, LI Y N, LI S Y R. Hardware prototyping o network oding in HDL[A]. The 6th International Conerene on Wireless Communiations, Networking and Mobile Computing[C] [9] CHEKURI C, FRAGOULI C, SOLJANIN E. On average throughput and alphabet size in network oding[j]. IEEE Transations on Inormation Theory, 2006, 52(6): [10] FRAGOULI C, SOLJANIN E. Network oding appliations[j]. Foundations and Trends in Networking, 2007, 2(2): [11] FRAGOULI C, SOLJANIN E. Network oding undamentals[j]. Foundations and Trends in Networking, 2007, 2(1): [12] FRAGOULI C, WIDMER J, BOUDEC J Y L. Network oding: an instant primer[j]. ACMSIGCOMM Computer Communiation Review arhive, 2008, 36(1):63-68

Σχετικά έγγραφα

Quick algorithm f or computing core attribute

24 5 Vol. 24 No. 5 Cont rol an d Decision 2009 5 May 2009 : 100120920 (2009) 0520738205 1a, 2, 1b (1. a., b., 239012 ; 2., 230039) :,,.,.,. : ; ; ; : TP181 : A Quick algorithm f or computing core attribute