Εργαστήριο Οργάνωσης Η/Υ Δαδαλιάρης Αντώνιος dadaliaris@uth.gr
Σχόλια: - - This is a single line comment - - There is no alternative way to write multi-line comments Αναγνωριστικά: Τα αναγνωριστικά στη VHDL μπορούν να περιέχουν γράμματα, αριθμούς και κάτω πάυλες. Ένα αναγνωριστικό πρέπει πάντοτε να ξεκινάει με κάποιο γράμμα. Ένα αναγνωριστικό δεν μπορεί να περιέχει δύο συνεχόμενες κάτω παύλες. Η VHDL είναι case insensitive. A4, next_state, NextState, dff_enable sig#5, _a, 7seg, my var
Δεσμευμένες Λέξεις: abs configuration impure null rem type access in of report unaffected after disconnect if inertial return units alias downto inout open rol all else is or ror use and label others select variable end library on severity wait array entity linkage package signal assert exit literal port shared while attribute loop postponed sla out with begin for procedure sll xnor block function mod sra xor body generate nand pure srl generic new range subtype bus group next then case guarded nor register to when not reject constant transport architecture until elsif file map process component buffer record
Αριθμοί: integers: 0, 1234, 98E7,... real: 0.0, 1.23456 or 9.87E6 base 2: 2#101101# Χαρακτήρες: 'A',...'Z', '0', '1',... Strings: "0011", "some_string",...
operator description operand 1 operand 2 result a ** b exponentiation integer integer integer abs a absolute value integer integer not a negation boolean / bit / bit_vector boolean / bit / bit_vector a * b multiplication integer integer integer a / b division integer integer integer a mod b modulo integer integer integer a rem b remainder integer integer integer + a identity integer integer - a negation integer integer
operator description operand 1 operand 2 result a + b addition integer integer integer a - b subtraction integer integer integer a & b concatenation 1D array 1D array 1D array a sll b shift left logical bit_vector integer bit_vector a srl b shift right logical bit_vector integer bit_vector a sla b shift left arithmetic bit_vector integer bit_vector a sra b shift right arithmetic bit_vector integer bit_vector a rol b rotate left bit_vector integer bit_vector a ror b rotate right bit_vector integer bit_vector
operator description operand 1 operand 2 result a = b equal to any any boolean a /= b not equal to any any boolean a < b less than any any boolean a <= b less than or equal to any any boolean a > b greater than any any boolean a >= b greater than or equal to any any boolean a and b and boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector a or b or boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector a xor b xor boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector a nand b nand boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector a nor b nor boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector a xnor b xnor boolean / bit / bit_vector boolean / bit / bit_vector boolean / bit / bit_vector
overloaded operators description operand 1 operand 2 result abs a absolute signed signed a + b arithmetic ops... signed signed signed a - b arithmetic ops... signed signed signed a * b arithmetic ops... unsigned unsigned unsigned a / b arithmetic ops... unsigned unsigned unsigned a mod b arithmetic ops... unsigned unsigned unsigned a rem b arithmetic ops... signed signed / integer signed - a negation signed signed
function description operand 1 operand 2 result shift_left(a, b) shift left unsigned / signed natural type of 1st operand shift_right(a, b) shift right unsigned / signed natural type of 1st operand rotate_left(a, b) rotate left unsigned / signed natural type of 1st operand rotate_right(a, b) rotate right unsigned / signed natural type of 1st operand resize(a, b) resize array unsigned / signed natural type of 1st operand std_match(a, b) compare unsgned / signed / std_logic / std_logic_vector type of 1st operand boolean to_integer(a) convert unsigned / signed integer to_unsigned(a, b) convert natural natural unsigned to_signed(a, b) convert integer natural signed
1. Για ποιό λόγο χρησιμοποιούμε packages κατά την συγγραφή κώδικα VHDL; 2. Τί περιλαμβάνει το πακέτο std_logic_1164 που χρησιμοποιείται στα παραπάνω παραδείγματα; 3. Ποιά είναι η βασική διαφορά μεταξύ του τύπου std_logic και του τύπου bit; 4. Εξηγείστε την λειτουργία των τελεστών sll, srl, sla, sra, ror, rol. Δώστε ένα παράδειγμα για κάθε έναν από τους παραπάνω τελεστές. 5. Ποιοί από τους τύπους δεδομένων του πακέτου std_logic_1164 δεν θέλουμε να εμφανιστούν κατά την διαδικασία της προσομοίωσης και γιατί;