LAr ROD boards TM - TBM - CarteP3 Pierre Matricon LAL - Orsay October 2002 matricon@in2p3.fr
Connections between the ROD boards TBM Crate Busy Trigger Timing Control CarteP3 Configuration TM to ROS 8 FEBs ROD TTC Busy
9 LVDS 5 LVDS TM 48V=>3V LVDS drivers RP2 Clock Configuration memory EPC2 TQFP 144 VJD 100A TQFP 144 VJD 100A TQFP 144 VJD 100A 4 mezzanine Link Source Cards RP3 FPGA TQFP 144 VJD 100A Deserialiser DS90CR484T FIFO in FPGA FPGAs configuration : 1. VME > TBM > TMbus > EPC2 2. PC > TBM > TMbus > EPC2 3. PC > TM > FPGA matricon@in2p3.fr
TM : test with the TM-Tester board 1 link is tested at a time TM under test CPU TM-Tester (TBM proto) VME interface Transmit Receive Compare
TBM/TM-Tester Link Destination Card 37 7 VME64x interface A Configuration memory EPC2 FIFO E Hardware diagnostic Clock F Serialiser 5 9 B FIFO 48 VJD 100A LVDS Multiplexer D Link 1 Link 2 Link 3 Link 4 > A software tool will be useful > Until this tool is available, simple hardware diagnostic will be performed with a PC matricon@in2p3.fr
TBM : TTC distribution Trigger Timing Control ST HFBR23T DS90LV001 DS90LV110T or FPGA TTC TTCrx LVDS Buffer DS90LV001 ROD : TTC receiver ROD
ROD : Busy Generation TBM : Busy control by VME ROD VME interface Busy Logic Crate Busy FPGA OR(Busy #6...Busy #21) Reset FIFO History FIFO Enable register ROD Busy* Simulated Busy register OR OR AND Busy register 1 OR Busy register 2 Crate Busy*
TBM : Functionalities for the TM modules VME interface TMbus for configuring the TM components > A software tool will be necessary for configuring the FPGAs through VME > Until this tool is available, one will use a PC connected to TBM
CP3 TBM ROD modules TM modules Power supply taps Crate Address 4.5 mm thick PCB (2.8, 3.4, 3.7, 4.0, 4.6, 4.9, 5.2, 5.8, 6.3, 6.4) holes isolated Rear view.................................................................................................... 01 02 04 05 06 07 08 09 10 11 12 13 14 15 17 18 19 21 20 +48V 0V Electrolytic capacitances R100
CP3 : TTC and Busy LVTTL TTC06-21 Busy06-21 LVDS.................................................................................................... 01 02 04 05 06 07 08 09 10 11 12 13 14 15 17 18 19 21 20 Front view TBM
CP3 : TMbus TMTDO (LVDS) TMTRST*, TMEN*, TMA0-4 (7 LVTTL).................................................................................................... 01 02 04 05 06 07 08 09 10 11 12 13 14 15 17 18 19 21 20 Front view TBM 100Ω 100Ω TMTCK, TMTMS, TMTDI, ROCK (4 LVDS) 100Ω 100Ω
CP3 : Crate address and RGA pins CRA0 CRA1 CRA2 CRA3 CRA4 Slot RGA4* RGA3* RGA2* RGA1* RGA0* 1 GndROD 2 GndROD 3 GndROD GndROD 4 GndROD 5 GndROD GndROD 6 GndROD GndROD 7 GndROD GndROD GndROD 8 GndROD 9 GndROD GndROD 10 GndROD GndROD 11 GndROD GndROD GndROD 12 GndROD GndROD 13 GndROD GndROD GndROD 14 GndROD GndROD GndROD 15 GndROD GndROD GndROD GndROD GndROD 17 GndROD GndROD 18 GndROD GndROD 19 GndROD GndROD GndROD 20 GndROD GndROD 21 GndROD GndROD GndROD
ROD - TM interface From ROD Data Link Full To ROD Reset Test CTRL Write Clock LR OC-TM controls Link Down OC-TM status 9 LVDS links 5 LVDS links
TM : RP2 RP3 pin allocation TM RP2 z a b c d 1 2 3 4 SL1_1+ SL1_2+ 5 SL1_1- SL1_2-6 SL1_3+ SL1_4+ 7 SL3_3- SL1_4-8 SL3_5+ SL1_6+ 9 SL3_5- SL1_6-10 SL1_7+ SL1_8+ 11 SL1_7- SL1_8-12 SL1_9+ SL1_10+ 13 SL1_9- SL1_10-14 SL1_11+ SL1_12+ 15 SL3_11- SL1_12- SL1_13+ SL1_14+ 17 SL1_13- SL1_14-18 SL2_1+ SL2_2+ 19 SL2_1- SL2_2-20 SL2_3+ SL2_4+ 21 SL2_3- SL2_4-22 SL2_5+ SL2_6+ 23 SL2_5- SL2_6-24 SL2_7+ SL2_8+ 25 SL2_7- SL2_8-26 SL2_9+ SL2_10+ 27 SL2_9- SL2_10-28 SL2_11+ SL2_12+ 29 SL2_11- SL2_12-30 SL2_13+ SL2_14+ 31 SL2_13- SL2_14-32 TM RP3 z a b c d 1 ROCK+ 2 ROCK- 3 TMTCK+ 4 SL3_1+ TMTCK- SL3_2+ 5 SL3_1- TMTMS+ SL3_2-6 SL3_3+ TMTMS- SL3_4+ 7 SL3_3- TMTDI+ SL3_4-8 SL3_5+ TMTDI- SL3_6+ 9 SL3_5- TMTDO+ SL3_6-10 SL3_7+ TMTDO- SL3_8+ 11 SL3_7- GndROD SL3_8-12 SL3_9+ TMTRST* SL3_10+ 13 SL3_9- GndROD SL3_10-14 SL3_11+ TMEN* SL3_12+ 15 SL3_11- GndROD SL3_12- SL3_13+ TMA0 SL3_14+ 17 SL3_13- TMA1 SL3_14-18 SL4_1+ TMA2 SL4_2+ 19 SL4_1- TMA3 SL4_2-20 SL4_3+ TMA4 SL4_4+ 21 SL4_3- GndROD SL4_4-22 SL4_5+ RGA0 SL4_6+ 23 SL4_5- RGA1 SL4_6-24 SL4_7+ RGA2 SL4_8+ 25 SL4_7- RGA3 SL4_8-26 SL4_9+ RGA4 SL4_10+ 27 SL4_9- GndTM SL4_10-28 SL4_11+ GndTM SL4_12+ 29 SL4_11- GndTM SL4_12-30 SL4_13+ GndTM SL4_14+ 31 SL4_13- GndTM SL4_14-32 +48V +48V GndT M
CP3 : Pin assignments J3/RJ3 Slot 05 z a b c d 1 TTC06+ CRA0 CRA1 Busy06* 2 TTC06- CRA2 CRA3 GndROD 3 TTC07+ CRA4 TMTCK+ Busy07* 4 TTC07- TMTCK- GndROD 5 TTC08+ TMTMS+ Busy08* 6 TTC08- TMTMS- GndROD 7 TTC09+ TMTDI+ Busy09* 8 TTC09- TMTDI- GndROD 9 TTC10+ TMTDO+ Busy10* 10 TTC10- TMTDO- GndROD 11 TTC11+ GndROD Busy11* 12 TTC11- TMTRST* GndROD 13 TTC12+ GndROD Busy12* 14 TTC12- TMEN* GndROD 15 TTC13+ GndROD Busy13* TTC13- TMA0 GndROD 17 TTC14+ TMA1 Busy14* 18 TTC14- TMA2 GndROD 19 TTC15+ TMA3 Busy15* 20 TTC15- TMA4 GndROD 21 TTC+ GndROD Busy* 22 TTC- GndROD 23 TTC17+ Busy17* 24 TTC17- GndROD 25 TTC18+ Busy18* 26 TTC18- GndROD 27 TTC19+ GndT M Busy19* 28 T T C19- GndT M GndROD 29 TTC20+ GndT M Busy20* 30 TTC20- GndT M GndROD 31 TTC21+ GndT M Busy21* 32 T T C21- +48V +48V GndT M GndROD J3/RJ3 SlotXX (Slots 06-21) z a b c d 1 TTCXX+ BusyXX* 2 TTCXX- GndROD 3 TMTCK+ 4 SL3_1+ TMTCK- SL3_2+ 5 SL3_1- TMTMS+ SL3_2-6 SL3_3+ TMTMS- SL3_4+ 7 SL3_3- TMTDI+ SL3_4-8 SL3_5+ TMTDI- SL3_6+ 9 SL3_5- TMTDO+ SL3_6-10 SL3_7+ TMTDO- SL3_8+ 11 SL3_7- GndROD SL3_8-12 SL3_9+ TMTRST* SL3_10+ 13 SL3_9- GndROD SL3_10-14 SL3_11+ TMEN* SL3_12+ 15 SL3_11- GndROD SL3_12- SL3_13+ TMA0 SL3_14+ 17 SL3_13- TMA1 SL3_14-18 SL4_1+ TMA2 SL4_2+ 19 SL4_1- TMA3 SL4_2-20 SL4_3+ TMA4 SL4_4+ 21 SL4_3- GndROD SL4_4-22 SL4_5+ RGA0 SL4_6+ 23 SL4_5- RGA1 SL4_6-24 SL4_7+ RGA2 SL4_8+ 25 SL4_7- RGA3 SL4_8-26 SL4_9+ RGA4 SL4_10+ 27 SL4_9- GndTM SL4_10-28 SL4_11+ GndTM SL4_12+ 29 SL4_11- GndTM SL4_12-30 SL4_13+ GndTM SL4_14+ 31 SL4_13- GndTM SL4_14-32 +48V +48V GndT M
Octobre Novembre Décembre Janvier Février Mars Pierre Éric Schematics CP3 TM TBM Henri Layout CP3 TM TBM Industry Fab CP3 TM TBM LAL Cabling CP3 TM TBM Pierre Éric Design FPGA Pierre Procurements Pierre Éric Bernard Debugging CP3 TM TBM