Microelectronic Circuit Design Fourth Edition - Part II Solutions to Exercises

Microelectronic Circuit Design Fourth Edition - Part II olutions to Exercises CHAPTER 6 NM 0.8V 0.4V 0.4 V NM H 3.6V.0V.6 V Page 94 V 0% V + 0. ΔV [ ].4 V [ ].4 V.6V + 0. 0.6 (.6) 0.6V 0.9 0.6 (.6) Checking : V 0% V H 0.9 ΔV V 90% V H 0. ΔV [ ] 0.8 V [ ] 0.8 V 0.6V 0. 0.6 (.6).6V + 0.9 0.6 (.6) Checking : V 90% V + 0.9 ΔV V 50% V H + V 0.6.6.6 V t r t 4 t 3 3 ns t f t t 5 ns Page 95 At P mw : PDP mw ns At P 3 mw : PDP 3mW ns At P 0 mw : PDP 0mW ns pj 3 pj 40 pj Page 97 Z ( A + B) ( B + C) AB + AC + BB + BC AB + BB + AC + BB + BC Z AB + B + AC + B + BC B( A +) + AC + B( C +) B + AC + B Z B + B + AC B + AC 08//0

I DD P 0.4mW V DD.5V 60 µa R V V DD.5V 0.V I DD 60µA A W.6x0 4 A 0 4 V.5 0.6 0. 0. V W 4.44 4.4 kω Page 30 I DD V V DD 3.3V 0.V R 0kΩ 3.4µA 3.4x0 6 A 6x0 5 A W 3.3 0.75 0. V 0. V W.09 Page 303 R 0.5V on R on + 8.8kΩ.5V R on.84 kω W 0 4.5 0.60 0.5 W (.84kΩ).98 6.6kΩ R on.03 6x0 5 3.3 0.75 0. 6.6 kω V 3.3V 0.0 V 6.6kΩ +0kΩ V K n R A Page 305 K n R 6x0 5 Ω V V V.03 NM H 3.3 0.75+.0x0 5 6.30 V 3.3.63 ( 6.30) 6.30.45 V NM 0.75+ 6.30 3.3 3 6.30 0.38 V 08//0

Using MATAB : fzero(@(vh) ((vh -.9-0.5* sqrt(0.6))^ - 0.5(vh + 0.6)), ) ans.5535 fzero(@(vh) ((vh -.9-0.5* sqrt(0.6))^ - 0.5(vh + 0.6)), 4) ans 3.70 [ ] V 3.6 V H V H 5 0.75 + 0.5 V H + 0.6 0.6 fzero(@(vh) (5-0.75-0.5* (sqrt(vh + 0.6) - sqrt(0.6)) - vh), ) ans 3.6 ( a) 80x0 6 A 00x0 6 A V W 0.646 V V TN 0.6 + 0.5.5 + 0.6 0.6.55 0.60 0.5 0.5 V W 80x0 6 A 00x0 6 A W (.5 0.5 0.646) V W V (b) 80x0 6 A 00x0 6 A W.55 0.60 0. V 0. V W 0.63 V V TN 0.6 + 0.5.+ 0.6 0.6 80x0 6 A 00x0 6 A W V (.5 0. 0.63) V W Page 3 The high logic level is unchanged : V H. 60x0 6 A 50x0 6 A W. 0.75 0. V 0. V W V TN 0.75 + 0.5.+ 0.6 0.6 60x0 6 A 50x0 6 0.78 V A V W ( 3.3 0. 0.78) V W 0.55 6.0 8.89 0.5 9.6 0.40.44.8.96 3 08//0

Using MATAB : fzero(@(vh) ((vh -.9-0.5* sqrt(0.6))^ - 0.5(vh + 0.6)), ) ans.5535 γ 0 V TN 0.6V V H.5-0.6.9 V I DD 0 for v O V H 0 00x0 6.9 0.6 V V 00x0 6 (.5 V 0.6) 0 6V 6.8V + 3.6 0 V 0.35V I DD 00x0 6.9 0.6 0.35 0.35 78 µa Checking : I DD 00x0 6 (.5 0.35 0.6) 77 µa Page 39.44V V TN.5+ 0.5 0. + 0.6 0.6 W 60.6x0 6 00x0 6 3.3 0.6 0. 0. W 60.6x0 6 00x0 6 W ( 0.44) W 0.585.7.7 Page 30 I D 00x0 6..5 0.6 0. 0. 79.9 µa which checks. Page 3 The PMO transistor is still saturated so I D 44 µa, and V H.5 V. 5 44x0 6 00x0 6.5 0.6 V V V 0.58 V Page 36 Place a third transistor with W. in parallel with transistors A and B. The W/ ratio of the load transistor remains unchanged : W.8 4 08//0

Place a third transistor in series with transistors A and B. The new W/ ratios of transistors A, B and C are W ABC The W/ ratio of the load transistor remains unchanged : W Page 333 M is saturated for all three voltages. I DD 40x0 6. The voltages can be estimated using the on - resistance method. 3mV 64.4mV For the 000 case, R ona 80.µA For the 000 case, R one 64.4mV 80.µA For the 00 case, R onc 804 Ω. 03mV 3mV 80.µA 3. 6.66..8 [.5 ( 0.6) ] 80. µa 844 Ω R onb 64.4mV 80.µA 804 Ω 3mV 64.4mV 886 Ω R ond 80.µA 844 Ω The voltage across a given conducting device is I D R on. mall variations in R on are ignored. ABCDE Y (mv) (mv) 3 (mv) I DD (ua) ABCDE Y (mv) (mv) 3 (mv) I DD (ua) 00000.5 V 0 0 0 0000.5 V.5 V 0 0 0000.5 V 0 0 0 000.5 V.5 V 0 0 0000.5 V 0 0 0 000.5 V.5 V.5 V 0 000.5 V 0 0 0 00 00 30 64 80. 0000.5 V 0.5 V 0 000.5 V.5 V.5 V 0 000 30 0 64 80. 00 30 30 64 80. 000.5 V.5 V.5 V 0 00.5 V.5 V.5 V 0 00 30 64 64 80. 0 00 83 64 80. 0000.5 V 0 0 0 000 30 64 0 80. 000.5 V 0 0 0 00 30 64 0 80. 000.5 V 0 0 0 00 30 64 64 80. 00.5 V 0 0 0 0 0 43 80. 000.5 V 0.5 V 0 00 30 64 64 80. 00 30 0 64 80. 0 66 3 3 80. 00 00 64 30 80. 0 0 64 87 80. 0 4 43 80. 65 3 3 80. 5 08//0

5V 80µA P av Page 335 P D 0 - F.5V 0.00 mw x0 4 W 00 µw or 0.00 mw x0 4 W 0.0 W or 0 mw 3x0 6 Hz P D 0 - F(.5V ) 3.x0 9 Hz Page 336 The inverter in Fig. 6.38(a) was designed for a power dissipation of 0. mw. To reduce the power by a factor of two, we must reduce the W/ ratios by a factor of. W W 4.7.36.68 3.36 4mW To increase the power by a factor of, we must increase the W/ ratios by a factor of 0. 0.mW W 0.8 36. W 0. 44.4 To reduce the power by a factor of three, we must reduce the W/ ratios by a factor of 3. W.8 0.603 W 3.33. W 6.66. 3.66 3 3 A BCD 6 08//0

t r.rc. 8.8x0 3 Ω ( x0 3 F).7 ns ( x0 3 F) 3.97 ns τ PH 0.69RC 0.69 8.8x0 3 Ω v O ( t) V F ( V F V I )exp t v O ( τ PH ) V H 0.5 V + V H.5.5.35 V RC.35 0. ( 0..5)exp τ PH τ PH RC ln0.5 0.69RC RC v O ( t ) V H 0. V H + V.5+ 0.3.7 V.7 0. ( 0..5)exp t t RC ln 0.9 RC v O ( t ) V + 0. V H + V 0. + 0.3 0.43 V 0.43 0. ( 0..5)exp t t RC ln 0. RC t f t t RC ln 0.+ RC ln0.9 RC ln 9.RC Page 343 3.7.37x0 3 Ω t f (.5x0 3 F).9 ns τ PH.(.37x0 3 Ω) (.5x0 3 F) 0.7 ns (.5x0 3 F) 5.8 ns τ PH 0.69( 8.8x0 3 Ω) (.5x0 3 F) 4.97 ns t r. 8.8x0 3 Ω τ P Page 346 0.7 ns + 4.97 ns T Nτ P0 40.84 ns 80 ns f T 0 9 s.5 MHz 80ns 7 08//0

For our Psuedo NMO inverter with V 0. V, C " τ PH.R on C. ox W " W µ n C ox ( V V G TN ). µ n V G V TN ( 50x0 9 m) ( 00cm m) τ PH. 0.606 ps 500cm V s V 3.3 0.85 τ PH.R on C. 0.4µ p V G V TN τ P Page 349 0.606 ps +.63ps 00cm m ( 5cm V s) 3. 0.85. 50x0 9 m.6 ps The PMO transistor is saturated for v O V. P av I DD 40x0 6.5V (.7mA).4 mw P D 5x0 F.5V 0.V We must increase the power by a factor of 0 pf 5pF V.63ps 3.7 ns 8, ns [.5 ( 0.6) ].7 ma 3. mw x0 9 s so the W/ ratios must also be increased by a factor of 8. W 8 3.7 90 W 8 47.4 379 P D 0x0 F.5V 0.V 06 mw 0 9 s 8 08//0

CHAPTER 7 Page 370 ( a) K p 40x0 6 0 800 µa V K 0 n 00x0 6 000 µa ma.00 V V.09 V.3 V ( b) V TN 0.6 + 0.5.5 + 0.6 0.6 ( c) V TP 0.6 0.75.5 + 0.7 0.7 Page 37 a For v I V, V GN V TN 0.6 0.4V and V GP V TP.5+ 0.6 0.9V M N is saturated for v O 0.4 V. M P is in the triode region for v O.6 V..6 V v O.5 V ( b) M P is saturated for v O.6 V. 0.4 V v O.6 V ( c) M N is in the triode region for v O 0.4 V. M P is saturated for v O.6 V. 0 v O 0.4 V W P K n W K p N.5 0 5 Page 373 Both transistors are saturated since V G V D. K n ( V V GN TN ) K p ( V V GP TP ) K n K p V TN V TP V GN V GP v I V DD v I v I V DD 0K p ( V GN V TN ) K p ( V V GP TP ) 0( V GN V TN ) V GP + V TP 4 v I 0.6 v I.73 V 0 v I 0.6 K p ( V V GN TN ) 0K p ( V GP V TP ) ( V GN V TN ) 0( V GP + V TP ) v I 0.6 0( 4 v I 0.6) v I.37 V 9 08//0

W K n K R W K p N P K n K p.5 ( V K V + V DD R TN TP ) + 3K R K R (.5 0.6 0.6) (.5 ) + 3(.5) V IH K V V + V R DD TN TP K R V IH.5 (.5.5( 0.6) 0.6).V.5 ( V O K + R )V IH V DD K R V TN V TP (.5+ )..5.5 0.6 K R.5 V I K V R ( V + V DD TN TP ) K R K R + 3 (.5 ).5+ 3.5.5 0.6 0.6 V I ( V K V + V DD R TN TP ) K R (.5.5( 0.6) 0.6) 0.90V.5 + 0.6 0.74V ( V OH K + R )V I + V DD K R V TN V TP (.5+ )0.90 +.5.5( 0.6) + 0.6.38V NM H V OH V IH.38..6 V NM V I V O 0.90 0.74 0.78 V Page 376 0 F ymmetrical Inverter : τ P.R onn C. 0 4.5 0.6 Ω 3.6 ns Page 377 ymmetrical Inverter : R onn τ P.C 0 9 s. 5x0 F W N ' R onn K n ( V G V TN ) 67 0 4.5 0.6 67Ω 3.5 W P.5 W N 78.8 0 08//0

The inverters need to be increased in size by a factor of 80ps 50ps.. W. 3.77 4. W. 9.43 0.6 N W N 3.77 3.3 0.75 3.43 3.3 0.5 Page 380.4C τ PH.4R onn C K n V G V TN.4C τ PH.4R onp C K p V G V TN.4C τ PH.4R onn C K n V G V TN.4C τ PH.4R onp C K p V G V TN P W.4C K n (.5 0.6).6 C K n.4c K p (.5 0.6).6 C K p.4c K n ( 3.3 0.75) 0.94 C K n P 9.43 3.3 0.75 8.59 3.3 0.5.4C K p ( 3.3 0.75) 0.94 C K p Page 38 The inverter in Fig. 7. is a symmetrical design, so the maximum current occurs for v O v I V DD. Both transistors are saturated : i 0-4 DN.5 0.6 Checking : i DP 4x0-5 5 (.5 0.6) 4.3 µa Page 38 ( a) PDP CV DD 5 ( b) PDP CV DD 0 3 F 3.3V 5 5 0 3 F(.5V ) 0.3 pj 30 fj 5 ( c) PDP CV DD 0 3 F.8V 5 5 0. pj 0 fj 0.065 pj 65 fj 4.3 µa 08//0

Remove the NMO and PMO transistors connected to input E, and ground the source of the NMO transistor connected to input D. The are now 4 NMO transistors in series, and W 4 8 W 5 N P Page 39 There are two NMO transistors in series in the AB and CD NMO paths, and three PMO transistors in the ACE and BDE PMO paths. Therefore : W 4 W W 3 5 5 N ABCD N E Page 396 (a) The logic network for F AB + C is P C B A P CV DD f ( 50x0 F) ( 5V ) ( 0 7 Hz).5 mw 08//0

50 pf β 3.6 τ P 3.6τ o + 3.6τ o 63.τ o 50 ff z e ln z ln z z e ln z ln z e 50 pf 7 β.683 50 ff,.68,.683 7.0,.683 3 9.3,.683 4 5.8,.683 5 39,.683 6 373 A o 46 A o A o 594 A o A 6 + 3.6 +0 + 3.6 +00 + 36 A 7 +.68 + 7.0 +9.3 + 5.8 +39 + 373 Page 40 From the figure, 0/ devices give a maximum R on of 4 kω. The W/ ratios must be 4 times larger in order to reduce the maximum R on to kω. W 4 0 40 3 08//0

CHAPTER 8 ( a) N 8 0 7 0 048 segments ( b) N 30 9 0 048 segments Page 4 a N 8 0 8 68,435,456 ( b) I DD 0.05W 3.3V 5. ma Current/cell 5.mA 8 cells 56.4 pa Reverse the direction of the substrate arrows, and connect the substrates of the PMO transistors to V DD. Page 46 M A : At t 0 +, V G V TN 4 V and V D.5V, so transistor M A is operating in the triode region. i 60x0 6 5.5.5 43 µa M A : At t 0 +, V G V D, so transistor M A is operating in the saturation region. V TN + 0.6(.5 + 0.6 0.6).59V i 60x0 6 5.5.59 4.8 µa Page 48 M A : At t 0 +, V G V D, so transistor M A is operating in the saturation region. i 60x0 6 5 480 µa M A : At t 0 +, V G V D, so transistor M A is operating in the saturation region. i 60x0 6 ( 5 ) 480 µa 4 08//0

a At t 0 +, V G V TN 3-0.7.3 V and V D.9 V, so transistor M A is operating in the triode region. i 60x0 6 3 0 0.7.9.9 54 µa 50x0 ( b) 5 F From Table 6.0 : t f 3.7R on C 3.7 60x0 6 3 0.7 V C V B V TN V C 3 0.7 + 0.5 V C + 0.6 0.6 n CV q 5x0 5 F.89V.60x0 9 C Page 43 ( a) ΔV V V C B C B + C C.9 0.95 49C C C C +.34 ns [ ] V.89 V V C C.95 x 0 5 electrons V 9.0 mv ΔV V C V B C B C C + 3 0.7.3 V 0 0.95 V 9.0 mv 49C C + C C C ( b) τ R C 5 ff on 5kΩ 0.3 ns or τ R C C on C C 5kΩ( 5 ff) 0.5 ns + C B 49 + Page 434 At t 0 +, V G V TN 3-0 - 0.7.3 V and V D.5 V, so transistor M A is operating in the triode region. i D 60x0 6 3 0.7.5.5 79 µa 5 08//0

In setting the drain currents equal, we see that the change in W/ cancels out, and the voltages remain the same. i D 5 60x0-6.33 0.7 59.5 µa P D ( 59.5µA) ( 3V ) 0.357 mw As a check, the current should scale with W/ : i D 5 ( 3.5µA ) 58.8 µa Equating drain currents: 5x0-6.5 V O 0.6.4V O + 0.9V O.746 0 V O.V i D 5x0-6.5. 0.6 Checking : 60x0-6. 0.6 Page 488 R on 60x0-6 V O 0.6 5.6 µa P D ( 5.6µA) (.5V ) 78.0 µw 5.6 µa 3.8 kω τ 3.8kΩ( 5 ff) 0.595 ns 60x0 6 ( 3.3 ) Page 440 For all possible input combinations there will be two inverters and 3 output lines in the low state..0 mw P D 5 0.mW Page 44 W.8.63. 6 08//0

For a 0 - V input, all transistors will be on and the input nodes will all discharge to 0 V. For the 3- V input, the nodes will all charge to 3 V as long as V TN V. γ.58 V TN 0.7 + 0.5 3 + 0.6 0.6 0.7 + γ 3 + 0.6 0.6.6 V. Thus the nodes will all be a 3 V. The output will drop below V DD /. For the PMO device, V G V TP The PMO transistor will be saturated. For the NMO device, V G V TP Assume linear region operation. 40x0-6 5.+ 0.7 00x0-6 V O.4V O + 0.6 0 V O 68.6 mv.9 0.7 V O V O 3.9 0.7 0.4V..9 0.7.V. 7 08//0

i C exp 0.V.98 x 0 3 i C 0.05V CHAPTER 9 i C exp 0.3V.63 x 0 5 i C 0.05V i C exp 0.4V 8.89 x 0 6 i C 0.05V Page 464 The current must be reduced by 5 while the voltages remain the same. I EE 300µA 5 Page 465 I B I E β F + I B3 R C 4.4µA kω 60 µa R C 5( kω) 0 kω I B3 9.9µA 4.4 µa I B 4 07µA 5.0 µa 8.84 mv << 0.7 V I B 4 R C 5.0µA( kω) 0. mv << 0.7 V Page 467 V H 0 0.7 0.7 V V 0 0.mA kω 0.7V +.0V V REF 0.7V. V 0.9 V ΔV -0.7V - (.V ) 0.4 V Page 469 NM H NM 0.4V 0.4 0.05V + ln 0.05 0.07 V 8 08//0

P 3.3V 0.3mA + 0.mA.65 mw P 3.3V 0.357mA + 0.mA.84 mw NM H NM 0.6V 0.6 0.05V + ln 0.05 0.0 V From the graph, the VTC slope is - for V I.08 V, V OH 0.7 V and V IH 0.9 V, V O.8 V. NM H 0.7 0.9 0.0 V. NM.08 (.8) 0.0 V The voltages remain the same. Thus the currents must be reduced by a factor of 3, and the resistor values must be increase by a factor of 3. - - - R EE Page 47.7V ( 5.V ) 7.5 kω I E 0.0mA For all inputs low : I EE ΔV V H V REF For an inputs high : I EE 0.7 ( 5.).7.4V ( 5.V ) 0. ma R C 0.4V.90 kω 8 kω 0.mA V kω 99µA 0.7 ( ) 0.3 V ΔV 0.6 V R C 0.6V.00 kω 99µA 0.7 0.7 ( 5.).7 Based upon analysis above, R C 0.6V.85 kω 35µA Page 473 For all inputs low : I EE ΔV V H V REF Page 474 R E V V E EE 0.3mA 0.7 ( 5.).7 V kω 35µA R 0.6V C.85 kω 35µA V kω 99µA 0.7 ( ) 0.3 V ΔV 0.6 V R C 0.6V.00 kω 99µA 0 0.7 ( 5.V ) 0.3 V 5.0 kω ma 9 08//0

( a) For I E 0, v O 5. V. b For I E 0, v O - 5.V Page 476 The transistor's power dissipation is P V CB I C + V BE I E 5V.55mA 50 + 0.7V.55mA 5 The total power dissipation in the circuit is P V CC I C + V EE I E 5V.55mA 50 + 5V.55mA 5 4.3 mw 5.3 mw 3.7 5 For v O 3.7V, I E 3.7 60 µa. 300 5000 0.7 ( 5) At the Q - point, I E 0.7 3.7 ma 300 5000 The transistor's power dissipation is P V CB I C + V BE I E 5V 3.7mA 50 + 0.7V 3.7mA 5 - - - ( a) 4V 5.V ( b) I E 5.V 3kΩ.73 ma I E 0kΩ 0kΩ + R E R E 3.00 kω 4 ( 5. ) 3000 Page 478 Increase the value of each resistor by a factor of 0. 7.8 mw 0kΩ 0kΩ +5kΩ.08 V 4 0000 0 I 4 5. E 3000 Page 48 R C ΔV 0.6V I EE 0.5mA. kω τ P 0.69(.kΩ) ( pf).66 ns P 5.V ( 0.5+ 0.+ 0.)mA 3.64 mw PDP 6.0 pj 4 + 3.47 ma 0000 0 08//0

R C R C 0 V 0.4V I EE 0.5mA 800 Ω P I V EE EE 0.5mA.8V PDP.4mW 50 ps 70 fj I EF I EE 50 µa P I V EE EE 0.5mA(.8V ) 0.70 mw.40 mw V H 0 V 0. V V Bias 0. V V BH 0.7 V B 0.9 V V BiasB 0.8 V V AH.4 V A.6 V V BiasA.5 V V EE V AH 0.7V 0.7V.4 0.7 0.7.8 V V EE.8 V V H 0 V, V 0.4 V, : The C - level bias is V BiasC V + V H Using the level shifter in Fig. 9.7, V BH 0.7 V B. V V BiasB 0.9 V V AH.4 V A.8 V V BiasA.6 V V EE V emittera 0.7V 0.7.8 V V EE.8 V 0. V Page 488 For v O V H, I C 0, and P 0. P V DD I DD 5V.43mA Increase R by a factor of 0 : R 0 kω Page 490 0. Γ exp 48. I B 0 A + 0.058 0 α R 0. 0. + 6 Page 49 I B 0A 0 + 0kΩ. 0 0. 54.6 0 0. 48. 48. 6 54.6. ma.59 A 3.34 A β FOR 0 A 3.34 A 3.00 08//0

Γ exp 0.5 403 I B 0 A + 0.05 0 0 0. 403 403 0.769 A V T.38x0 3 73 +50 0.05 + 36.5 mv V.60x0 9 CEMIN 36.5mV ln mv 0.05 Γ exp 0. 54.6 α R 0.5 0.05 + 0.5 5 40 + I B 0mA 0.5( 54.6) 40 5.08 ma β FOR 0mA.08mA 9.4 54.6 08//0

ns 6.4ns ln ma I BR.5mA 40.7 I BR.69 i CMAX V CC V CE β F 5 0 500.5mA Q X Q F i F τ F.5mA 0.5ns 0.65 pc Q X >> Q F ma I BR 0.064mA I BR I BR 5.49 ma.5ma 6.4ns ma 6.0 pc 40.7 Page 495 5 0.95 For v I V 0.5 V : i I 4000.0 ma V V + V BE CEAT Using the value of V CEAT in Fig. 9.3, V BE 0.5+ 0.04 0.9 V A better estimate is V CEAT 5mV ln + 0. mv V BE 0.5+ 0.00 0.6 V Page 496 For v I V H 5 V : i IH 5.5 4000.75 ma V 0.8 V BE 0.875mA + (.4mA) 3 Using Eq. (5.9), V BEAT 0.05V ln 0 5 A 40 + 0.79 V 3 Page 499 5V - N (kω)β R I B.5V I B 5.5 4000 0.875mA 3.5V β R 5(kΩ) 0.875mA 0(kΩ) 0.875mA Page 500 5.5 I B + 0.4 β 3.5V R 0. 4000.63 ma.43ma + N (.0mA) 8.3(.63mA) N 7 3 08//0

v I V and v O 0 : I B 4 5 V B 4 600 5 600 I 4 0.7 0.7 3 I 5.4 ma 5 ( 3+ 0.7 + 0.7) I B 4 0.375 ma I 4I B 4 5.4 ma 600 V CE 5 30ΩI C V O 5V 30Ω 5.4mA 5 ( 0 + 0.7 + 0.7).5 ma I 4I B 4 9.3 ma 600 3.7 0.70 V Oops! - the transistor is not in the forward - active region. Assume saturation with V CEAT 0.5V. 600 5 0.8 + 0.7 + 3.0 I I B + I C 30 5 0.5+ 0.7 + 3 + 9.6 ma Page 53 a BiCMO NAND gate : Replace the CMO NOR - gate with a two - input CMO NAND - gate, and connect its output to the bases of Q 3 and Q 4. ( b) BiNMO NAND gate : Replace the input CMO NOR - gate with a two - input CMO NAND - gate, and connect M 6 and M 7 in series instead of parallel. 4 08//0