Protograph-based LDPC decoder applied to magnetic recording channel

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Άργος Βικελίδης
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1 25 6 Vol. 25 No Journal of Chongqing University of Posts and Telecommunications Natural Science Edition Dec DOI /j. issn X LDPC FPGA low density parity check LDPC 2 LDPC TDMP turbo decoding message passing Min - Sum MHz Mbit /s LDPC LDPC TN47 A X Protograph-based LDPC decoder applied to magnetic recording channel ZHOU Jian 1 LV Yibo 2 HONG Shaohua 2 WANG Lin 2 1. Key Lab of Mobile Communication in Chongqing CQUPT Chongqing P. R. China 2. School of Information Science and Engineering Xiamen University Fujian P. R. China Abstract Using random expansion algorithm the hardware implementation of conventional protograph-based LDPC low density parity check decoders has difficulty with wiring and data transmission which results in the improvement of resource consumption and decrease in throughput. In this paper an easy-hardware-implementation quasi cyclic protographbased LDPC code is obtained by the use of a two-step lifting procedure and we also propose a protograph-based LDPC decoder for magnetic recording channels. Utilizing the normalized Min-Sum algorithm based on the TDMP Turbo decoding message passing layered decoding scheme the proposed decoder has a partially parallel architecture. Moreover an early termination strategy is also proposed to reduce the latency and power consumption of the decoder. The proposed LDPC decoder is evaluated on a Xilinx Spartan 6 FPGA field programmable gate array platform and the results indicate that the proposed decoder requires low resource and can be utilized for multiple protograph-based LDPC codes. Key words magnetic recording channel protograph-based LDPC code quasi cyclic expansion early termination strategy low resource consumption 0 low density parity check LD- PC 1 2 LDPC LDPC 3 additive white Gaussian Turbo noise AWGN LDPC AWGN @ qq. com Foundation Item The National Natural Science Foundation of China

2 6 LDPC FPGA 789 PR AR3A LDPC 2 IARA1 AR3A AR4JA 2 LDPC 2 LDPC 2 B IA1 4 1 IARA2 B IA2 LDPC B IA1 = PR partial response PR 4 B IA1 AR3A IARA B IA2 = LDPC LDPC PEG progressive edge growth LDPC MHz Mbit /s LDPC 5 pre-lifting 1 LDPC Tanner PEG B 2 1 B LDPC LDPC 2 N N LDPC PR LDPC lifting PEG PR 2 AWGN AR4JA AR3A PR PR H 4AR3A IARA2 N H AWGN puncturing PR 2

3 PEG /2 512 BPSK binary phase shift keying Min-Sum 4 extended class IV PR channel EPR k t TDMP turbo variable-to-check VTC decoding message passing 8 L k t = S k t -1 k -1 - R t H = 1 /2 + 1 /4 + 1 /16 Fig. 1 Parity check matrix H after two steps quasi cyclic expansion 3 2 TDMP H Fig. 2 Performance comparison between random expansion and quasi cyclic expansion 1. 3 TDMP TDMP 1 2 H N 32 H 48 2 memory TDMP IARA2 vc v cv 1 S v a posteriori probability APP R cv check-to-varible CTV 2 k t R k t cv = α n N c \v sgn L k t nc min n N c \v L k t 2 2 α Min- Sum α S k t v = L k t + R k t vc cv nc H 2 TDMP FPGA 1

6 LDPC FPGA 791 4 PR H ROM TDMP ROM 2 RAM 2 H 32 RAM 16 4 32 5 4 5 RAM SISO 3 central RAM controller input 2.

4 6 LDPC FPGA PR H ROM TDMP ROM 2 RAM 2 H 32 RAM RAM SISO 3 central RAM controller input 2. 2 RAM 6 bit bit Min-Sum address generator network CTV 2 recovery SISO RAM CTV H bit CTV 22 bit early termination checking 5 bit 7 bit 3 bit output Fig. 3 3 Overall architecture of decoder % CTV RAM CTV SISO RAM SISO SISO SISO SISO 4 4 PEG 2 ROM H ROM RAM CTV ROM VTC 2

5 CTV CTV VTC 2 CTV 4 Recovery RAM 4 Fig stages pipeline architecture of SISO 5 4 Fig. 5 Inside architecture of 4 inputs comparator Turbo LDPC PR Turbo 9-10 H H C T = 0 LDPC 80% H Turbo

6 6 LDPC FPGA AR3A IARA1 IARA2 PR FPGA 3 7 PR BER IARA2 IARA1 AR3A FPGA Xilinx Spartan6 XC6SLX150 Verilog ISE11. 4 ModelSim6. 5 SE 1 / LDPC 3. 1 BER PR Turbo PC C 7 IARA1 IARA2 AR3A PCI7300A PC FPGA Fig. 7 Performance comparison between IARA1 code IARA2 code and AR3A code 6 IARA2 PR FPGA BER 3. 2 Turbo 8 FPGA 15 6 bit MHz bit Mbit /s Fig. 6 Performance comparison between floating point simulation and fixed point simulation

7 LDPC FPGA Tab. 1 Comparison of FPGA implementation among different LDPC decoders Decoder Proposed Filp Flops ALUTs BRAMs Code length Rate 1 /2 1 /2 7 /8 1 /2 Frequency / MHz Throughput /Mbit s ZHANG Kai HUANG Xinming WANG Zhongfeng. LDPC 2 High-throughput layered decoder implementation for quasi-cyclic LDPC codes J. IEEE Journal on Selected Ar- FPGA LDPC eas in Communications TDMP Min-Sum 11 KIM S SOBELMAN G E. A reduced-complexity architecture for LDPC layered decoding schemes J. IEEE Transactions on Very Large Scale Integration VLSI Systems Mbit /s 12 ZHANG T PARHI K K. A 54 Mbps 3 6 -regular FP- LDPC LDPC GA LDPC decoder C / /IEEE Workshop on Signal Processing Systems SIPS. s. l. IEEE Press GALLAGER R G. Low-density parity-check codes J. Information Theory IRE Transactions on THORPE J. Low-density parity-check LDPC codes constructed from protographs R. s. l. IPN Progress Report JPL RICHARDSON T J URBANKE R L. Multi-edge type LDPC codes R. Pasadena California California Institute of Technology FANG Yi CHEN Pingping WANG Lin et al. Design of protograph LDPC codes for partial response channels J. IEEE Transactions on Communications MITCHELL D G M SMARANDACHE R COSTELLO D J. Quasi-cyclic LDPC codes based on pre-lifted protographs C / /Information Theory Workshop ITW. Paraty IEEE Press MITCHELL D G M SMARANDACHE R COSTELLO D J. Constructing good QC-LDPC codes by pre-lifting protographs C / /Information Theory Workshop ITW. Lausanne IEEE Press XIAO Hua BANIHASHEMI A H. Improved progressiveedge-growth PEG construction of irregular LDPC codes J. IEEE Communications Letters MANSOUR M M. A turbo-decoding message-passing algorithm for sparse parity-check codes J. IEEE Transactions on Signal Processing SHIH Xinyu ZHAN Chengzhou LIN Chenghung et al. An mm 2 52 mw multi-mode LDPC decoder design for mobile WiMAX system in μm CMOS process J. IEEE Journal of Solid-State Circuits TAN Taiqiu LI Yubai WU Chang. Low-complexity high-performance LDPC decoder for CMMB C / / 2nd International Conference on Information Science and Engineering ICISE. Hangzhou IEEE Press WANG Zhongfeng CUI Zhiqiang. Low-complexity highspeed decoder design for quasi-cyclic LDPC codes J. IEEE Transactions on Very Large Scale Integration VL- SI Systems @ qq. com

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