Discrete/UMA /Muxless Schematics Document AMD LIANO CPU FS1

Transcript

1 iscrete/um /Muxless chematics ocument M LINO PU F M GPU Manhattan(Park/Madison M) and Vancouver(eymour/Whistler M) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. over Page ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

2 Line Out INT.PKR O T T H T U.0 (0 parts or port if U.0 do not used) GPP X port U. ( parts) T ( parts) INT RT INT LK GEN HW MONITOR PI.,,9,0,, Mini U lue Tooth U amera 9 LP U M Liano PU X PI EXPRE GRPHI(Muxless Lan ~Lan) R ( F socket W ) X PI EXPRE GRPHI(iserete only Lan0 ~Lan) 0/ MHz -Pin ufpg P(PI EXPRE Lan0~Lan),, GPP X port P0 P X Port R HMI 0/ MHz,,,,,, P EP UMI-Link Panel 9 X L TRVI 9 P 9 INT MI FH RT 0 odec HUON-M 9 ZLI LX Integrated isplay 9 LN PIE x MI In U.0 (parts) Giga LN M U.0 x.0 PIE x,u x PIE x,u x U.0 x,u x K ENE K9 Touch Pad 9 INT. K 9 Mini ard WLN IO MXI MXL0 0 (iserete only) LP EUG ONN. JE0- Project code:9.m0.00 TXFM 9 RJ 9 M/M Pro/x /MM/ in Madison/Park Whistler/eymour TI Mini-ard IM WWN U.0 PORT,,,, R VRM M/G/G,9,90,9.Park/eymour (Mxb*)=>M.Park/eymour(MXb *) =>G.Madison/Whistler(Mxb*)=>G.Madison/Whistler(Mxb*)=>G TOP V GN OTTOM P TKUP YTEM / RT9 INPUT TOUT YTEM / RT0 V_ V_ RT90 9 V_ RT90 V_0 RT0 9 V_ OUTPUT V_(.) V_() V_() RT0 V_ 0_0(.) YTEM / RT INPUT HRGER Q INPUT TOUT PU / IL INPUT TOUT V_(.) V_VG_0 V_0 (00m) VG_ORE OUTPUT HG_PWR V.0 UP+V V 00m VN 0~.V OUTPUT RT V_ V_ V_0(.) V_VG_0 0, OUTPUT V_ORE_0 0~.V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock iagram ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

3 trapping REQUIRE YTEM TRP UE this pin to determine INT/EXT LK E_PWM PH GPO99 PI_LK RT_LK LK_PI_LP PI_LK LP_LK0 LP_LK PULL HIGH LP ROM EFULT llow PIE GEN EFULT _PLU Mode ILE EFULT UE EUG TRP non_fusion LOK mode ENLE E LKGEN ENLE (Use Internal) EFULT PULL LOW PI ROM Force PIE GEN _PLU Mode ENLE IGNORE EUG TRP EFULT Fusion LOK mode EFULT ILE E EFULT LKGEN ILE (Use External) U Table PIE Routing Pair U evice U.0 EXT(For W ebug) WLN N WWN T G IM ard N N ard Reader U.0 port U.0 EXT U.0 EXT N LNE0 LNE LNE LNE LNE0 LNE LNE LNE PU LN WWN LN FH Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Table of ontent ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

4 PUF OF LN WWN WLN UMI_FH_PU_RX0P UMI_FH_PU_RX0N UMI_FH_PU_RXP UMI_FH_PU_RXN UMI_FH_PU_RXP UMI_FH_PU_RXN UMI_FH_PU_RXP UMI_FH_PU_RXN V_0 PIE_RXP0 PIE_RXN0 PIE_RXP PIE_RXN PIE_RXP PIE_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP9 PEG_RXN9 PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN P_ZVP R0 9RF-GP PI EXPRE P_GFX_RXP0 9 P_GFX_RXN0 Y P_GFX_RXP Y P_GFX_RXN W P_GFX_RXP W P_GFX_RXN W P_GFX_RXP W9 P_GFX_RXN V P_GFX_RXP V P_GFX_RXN U P_GFX_RXP U P_GFX_RXN U P_GFX_RXP U9 P_GFX_RXN T P_GFX_RXP T P_GFX_RXN R P_GFX_RXP R P_GFX_RXN R P_GFX_RXP9 R9 P_GFX_RXN9 P P_GFX_RXP0 P P_GFX_RXN0 N P_GFX_RXP N P_GFX_RXN N P_GFX_RXP N9 P_GFX_RXN M P_GFX_RXP M P_GFX_RXN L P_GFX_RXP L P_GFX_RXN L P_GFX_RXP L9 P_GFX_RXN P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP 9 P_GPP_RXN P_GPP_RXP P_GPP_RXN P_GPP_RXP P_GPP_RXN F P_UMI_RXP0 F P_UMI_RXN0 E P_UMI_RXP E P_UMI_RXN E9 P_UMI_RXP E P_UMI_RXN P_UMI_RXP P_UMI_RXN INE UMI-LINK GPP GRPHI P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP9 P_GFX_TXN9 P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GFX_TXP P_GFX_TXN P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_GPP_TXP P_GPP_TXN P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP P_UMI_TXN P_UMI_TXP P_UMI_TXN P_UMI_TXP P_UMI_TXN K P_ZVP P_Z INE.00. GTXP0 I 0 UVKX-GP PEG_TXP0 GTXN0 I 0 UVKX-GP PEG_TXN0 Y GTXP I 0 UVKX-GP PEG_TXP Y GTXN I 0 UVKX-GP PEG_TXN Y GTXP I 0 UVKX-GP PEG_TXP Y GTXN I 0 UVKX-GP PEG_TXN W GTXP I 0 UVKX-GP PEG_TXP W GTXN I 0 UVKX-GP PEG_TXN V GTXP I 09 UVKX-GP PEG_TXP V GTXN I 0 UVKX-GP PEG_TXN V GTXP I UVKX-GP PEG_TXP V GTXN I UVKX-GP PEG_TXN U GTXP I UVKX-GP PEG_TXP U GTXN I UVKX-GP PEG_TXN T GTXP I UVKX-GP PEG_TXP T GTXN I UVKX-GP PEG_TXN T GTXP I_PX UVKX-GP PEG_TXP T GTXN I_PX UVKX-GP PEG_TXN R GTXP9 I_PX 9 UVKX-GP PEG_TXP9 R GTXN9 I_PX 0 UVKX-GP PEG_TXN9 P GTXP0 I_PX UVKX-GP PEG_TXP0 P GTXN0 I_PX UVKX-GP PEG_TXN0 P GTXP I_PX UVKX-GP PEG_TXP P GTXN I_PX UVKX-GP PEG_TXN N GTXP I_PX UVKX-GP PEG_TXP N GTXN I_PX UVKX-GP PEG_TXN M GTXP I_PX UVKX-GP PEG_TXP M GTXN I_PX UVKX-GP PEG_TXN M GTXP I_PX 9 UVKX-GP PEG_TXP M GTXN I_PX 0 UVKX-GP PEG_TXN L GTXP I_PX UVKX-GP PEG_TXP L GTXN I_PX UVKX-GP PEG_TXN PIE_TXP0_ PIE_TXN0_ UVKX-GP UVKX-GP PIE_TXP_ G PIE_TXN_ UVKX-GP G PIE_TXP_ UVKX-GP PIE_TXN_ 0 UVKX-GP F UMI_TX0P_ UVKX-GP F UMI_TX0N_ UVKX-GP F UMI_TXP_ UVKX-GP F UMI_TXN_ UVKX-GP E UMI_TXP_ 9 UVKX-GP E UMI_TXN_ 0 UVKX-GP UMI_TXP_ UVKX-GP UMI_TXN_ UVKX-GP K P_Z R0 9RF-GP PIE_TXP0 PIE_TXN0 PIE_TXP PIE_TXN PIE_TXP PIE_TXN UMI_PU_FH_TX0P UMI_PU_FH_TX0N UMI_PU_FH_TXP UMI_PU_FH_TXN UMI_PU_FH_TXP UMI_PU_FH_TXN UMI_PU_FH_TXP UMI_PU_FH_TXN GTXP0 GTXN0 GTXP GTXN GTXP GTXN GTXP GTXN LN WWN WLN UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX 9 UVKX-GP UM_PX 0 UVKX-GP 0 - PEG_TXP[0..] PEG_TXN[0..] PU_HMI_T PU_HMI_T# PU_HMI_T PU_HMI_T# PU_HMI_T0 PU_HMI_T0# PU_HMI_LK PU_HMI_LK# PEG_TXP[0..] PEG_TXN[0..] PEG_RXP[0..] PEG_RXN[0..] PEG_RXP[0..] PEG_RXN[0..] Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU_PIE(/) ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

5 M 0 M M M M M M M M M 9 M 0 M M M M M M 0 M M M M0 M M M M M M M M M M M M M M M Q0 M Q#0 M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# M IM0_KE0 M IM0_KE M IM0_OT0 M IM0_OT M IM0_#0 M IM0_# M R# M # M WE# V_ M RT# M EVENT# M_VREF_Q_PU M_ZVIO R0 9RF-GP PU MEMORY HNNEL U0 M_0 R0 M_ R M_ P M_ P M_ N M_ N M_ N0 M_ N M_ M M_9 U M_0 M M_ L M_ M_ L M_ L0 M_ U M_NK0 U M_NK L M_NK E M_M0 J M_M E M_M F M_M M_M M_M 9 M_M M_M G M_Q_H0 H M_Q_L0 G M_Q_H H M_Q_L J M_Q_H H M_Q_L E M_Q_H E M_Q_L E M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L M_Q_H M_Q_L T M_LK_H0 T M_LK_L0 R M_LK_H R M_LK_L H M_KE0 H M_KE Y M_OT0 M_OT V M_#0 M_# V M_R# W M_# W M_WE# H M_REET# T M_EVENT# W0 M_VREF W M_ZVIO INE OF M_T0 E M_T J M_T H M_T J M_T H M_T F M_T F M_T E M_T H M_T9 F M_T0 E9 M_T J9 M_T G M_T H M_T H9 M_T F9 M_T H0 M_T F M_T J M_T9 H M_T0 G0 M_T E0 M_T G M_T H M_T G M_T E M_T G M_T G M_T F M_T9 H M_T0 E M_T F M_T M_T M_T M_T M_T E M_T M_T M_T9 M_T0 Y M_T M_T Y M_T 0 M_T M_T M_T M_T M_T 9 M_T9 9 M_T0 M_T M_T 0 M_T Y9 M_T M_T M_T M_T Y M_T M_T9 M_T0 Y M_T M_T M_T Y M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M 0 M M M M M M M M M 9 M 0 M M M M M M 0 M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# M IM0_KE0 M IM0_KE M IM0_OT0 M IM0_OT M IM0_#0 M IM0_# M R# M # M WE# M M0 M M M M M M M M M M M M M M M Q0 M Q#0 M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M RT# M EVENT# PU MEMORY HNNEL T M_0 P M_ P M_ N M_ N M_ M M_ M M_ M M_ M M_ L M_9 U M_0 L M_ K M_ W M_ K M_ K M_ U M_NK0 T M_NK K M_NK M_M0 M_M M_M M_M F M_M G M_M H M_M M_M M_Q_H0 M_Q_L0 E M_Q_H M_Q_L E M_Q_H M_Q_L M_Q_H M_Q_L G M_Q_H G M_Q_L G M_Q_H F M_Q_L G M_Q_H G M_Q_L H M_Q_H G M_Q_L R M_LK_H0 R M_LK_L0 P M_LK_H P M_LK_L J M_KE0 J M_KE W M_OT0 Y M_OT V M_#0 Y M_# V M_R# V M_# V M_WE# J M_REET# T M_EVENT# INE OF M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T9 M_T0 M_T M_T M_T E 0 0 E E E G H F G G F H E E H E0 H0 0 F9 E E H G0 G9 F G G G F E F M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q PU_VREF_Q INE.00. INE.00. R_VREF_ R00R00-P 0 U0VKX-GP M_VREF_Q_PU LYOUT: place them close to PU V_ 0 RN0 KP0VKX-GP 090- RNKJ--GP M EVENT# M EVENT# Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU_R(/) ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

6 V V oot Voltage (V/GN) L0 N =.090.P PU_LERT# V_0 V_ V_0 V_ V_0 V_ V_ V_ V_ RN0 RN0 R KRJ--GP 090- Power V_ PU_LERT#_Q R 00RJ--GP R 00RJ--GP R 00RJ--GP R 00RJ--GP RN RNKJ--GP RNKJ--GP RNKJ-GP RN0 R 00RJ--GP RNKJ-GP V_ PU_I PU_I PU_THERMTRIP#_VIO PU_LERT# PU_TRT# PU_TI PU_TM PU_TK PU_REQ# H_PUPWRG_E H_PUPWRG_E PU_V_R PU_V_R PU_PROHOT# PU_RT# PU_RT# oot Voltage (open) PH_TEMP_LERT# 9, MHz 00MHz LV_L0P_TRVI LV_L0N_TRVI EP VG output from FH PU_LKP PU_LKN IP_LKP IP_LKN PU_THERMTRIP#_VIO PU_VN_RUN_F_L PU_VN_RUN_F_H V_0 PU_PROHOT#_ PU_V_RUN_F_L PU_V_RUN_F_H V_ PU_THERMTRIP#_VIO_Q PU_P_TXP0_PU PU_P_TXN0_PU P_TX0P_R P_TX0N_R P_TXP_R P_TXN_R P_TXP_R P_TXN_R P_TXP_R P_TXN_R V_0 V_ PU_TI PU_TO PU_TK PU_TM PU_TRT# PU_R PU_REQ# H_THERMTRIP#,, PU_TI PU_TO PU_TK PU_TM PU_TRT# PU_R PU_REQ# PU_RUN_F_L PU_VP_F_H PU_VIO_U_F_H PU_VR_F_H PU_I P_TX0P P_TX0N P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN PU_V_R PU_V_R RN0 PU_I LK PU_I T PU_RT_L_UF R 0RJ--GP RN0J--GP PU_RT#_R PU_RT# R9 0R00-P PU_PWRG_R,,,9 H_PUPWRG_E R0 0 change to short pad 0R00-P PU_PROHOT# R 0R00-P 0 - PU_THERMTRIP#_VIO PU_LERT# H_PROHOT# R 0 - KRJ--GP Q0 PM90--GP R 0KRJ--GP.090.L0 N =.090.P PU_PROHOT# Q PM90--GP.090.L0 N =.090.P R 0RJ--GP R0 0KRJ--GP Q0 UM_PX 0 UVKX-GP UM_PX 0 UVKX-GP 0 - R 0KRJ--GP 09- PM90--GP PU exceeds to l PU_PROHOT#_VIO TRVI LV Panel UM_PX UVKX-GP UM_PX 9 UVKX-GP UM_PX 0 UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP UM_PX UVKX-GP R9 0KRJ--GP R 0KRJ--GP R 0R00-P R9 0R00-P TP0 TP TP H_PUPWRG_E V_ F F E E K K J J H H G G H H H H H G F0 E0 0 G H E K L0 N =.090.P PU P0_TXP0 P0_TXN0 P0_TXP P0_TXN P0_TXP P0_TXN P0_TXP P0_TXN P_TXP0 P_TXN0 P_TXP P_TXN P_TXP P0_HP P_TXN P_HP P_HP P_TXP P_HP P_TXN P_HP P_HP LKIN_H LKIN_L P_LON P_IGON IP_LKIN_H P_VRY_L IP_LKIN_L P_UX_Z V V TET TET9 I TET0 I TET TET REET# TET PWROK TET TET PROHOT# TET THERMTRIP# TET9 LERT# TET0 TET TI TET TO TET TK TET TM TET_H TRT# TET_L R TET_H REQ# TET_L TET0_H RV#E TET0_L RV#K TET RV# TET_H TET_L TET _ENE VP_ENE FR VN_ENE MTIVE# VIO_ENE V_ENE THERM VR_ENE THERM INE.00. V_0 H_PUPWRG_ NLOG/IPLY/MI V_0 R 0R00-P 0 - G IPLY PORT 0 IPLY PORT ENE RV JTG TRL ER. LK R 0KRJ--GP Q0 INE IPLY PORT MI. TET V_ OF P0_UXP P0_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN P_UXP P_UXN R0 0KRJ--GP E E J J H H G G F F E J H G F 0 G0 H0 H 9 E9 G9 H9 H G F E F0 G H0 H9 K K K 0 Y 0 E R 0KRJ--GP H_PUPWRG Q PM90--GP --GP P_UXP P_UXN ML_LK 9,, P0_HP P_HP PU_LEN PU_IGON PU_LPWM P_UX_Z PU_TET9_NLOGIN PU_TET_NHIFTEN PU_TET_P0 PU_TET_P PU_TET_P PU_TET_P PU_TET_PLLTET PU_TET9_PLLTET0 PU_TET0_NLK PU_TET_NEN PU_TET_NHIFTEN PU_TET_NLK PU_TET_H_YPLK_H PU_TET_L_YPLK_L NTTIN_H NTTIN_L M_TET NTTOUT_H NTTOUT_L TET PU_LEN PU_P_UXP_PU PU_P_UXN_PU 0 0 R 0RF--GP PU_IGON UVKX-GP UM_PX_LV UVKX-GP UM_PX_LV UVKX-GP UM_PX UVKX-GP UM_PX P_HP TP TP0 TP TP PU_TET_PLLTET PU_TET9_PLLTET0 V_ PU_LEN_Q TP TP9 FR LLOW_TOP R 00KRJ--GP UM_PX_EP UM_PX_EP.090.L0 N =.090.P R UM_PX_EP 00KRJ--GP P0_HP PU_IGON_Q V_0 V_ R UM_PX_EP KRJ--GP.090.L0 N =.090.P TP0 TP R0 KRJ--GP Q09 PM90--GP UM_PX_EP V_0 R 00KRJ--GP V_0 Q0 PM90--GP UM_PX_EP R9 KRJ--GP UM_PX_EP PU_P_UXP_PU 9 ep PU_P_UXN_PU 9 LV_HP_TRVI 9 LV LV_HN_TRVI 9 P_UXP_R 9 RT P_UXN_R 9 PH_HMI_LK_R PH_HMI_T_R PU_I TET R KRJ--GP UM_PX_EP L_KLT_EN_R 9,0 V_ V_ PU_LPWM HMI [M HMI desing guidance] trap define PU :Enable HMI P:isable HMI LV_V_EN_R 9,0 0 - G --GP Q0 R 00RJ--GP R 00RJ--GP UM_PX R KRJ--GP LV_HN_TRVI LV_HP_TRVI 0 - PU_LPWM_Q V_ V_ 9,9 R KRJ--GP UM_PX Q0 PM90--GP.090.L0 N =.090.P R 00KRJ--GP R 00KRJ--GP PU_P_UXP_PU PU_P_UXN_PU P_UXP P_UXN PU_TET_H_YPLK_H M_TET PU_TET9_NLOGIN PU_TET_NHIFTEN PU_TET_NHIFTEN PU_TET9_PLLTET0 PU_TET_PLLTET PU_TET_NEN PU_TET0_NLK PU_TET_NLK PU_TET_L_YPLK_L LLOW_TOP V_UX_ R FR 0KRJ--GP [M FE Frank]: this is electrical key do not allow power to turn on if this pin is still "L" F package is open pin in the furtur,fr will have this pin tied to if the wrong processor is plugged the socket This is more of a problem on desktop platforms V_ (changing PUs) V_0 R P_HP0_ 0RJ--GP UM_PX R 0KRJ--GP 9,9 ML_T 9,, R KRJ--GP UM_PX P_HP0_ V_0 9 HP_ P_HP_R V_VG_0 EP_HP_PWR R HP 0KRJ-L-GP UM_PX V_VG_0 V_ R9 P_HP 0KRJ-L-GP.090.L0 N =.090.P R 00KRJ--GP PU_LPWM_TRVI 9, 0 - R 0RJ--GP L_KLT_TRL_R 9,0 UM_PX_EP R 00KRJ--GP UM_PX R9 RJ--GP I_EP R9 0RJ--GP R9 0RJ--GP EP_HP EP_HP_ET R0 R9 0RJ--GP UM_PX RN0 RNKJ-GP R 0RJ--GP 9RF-GP R0 0RJ--GP RN0 RNKJ--GP R 0RJ--GP.090.L0 N =.090.P UM_PX Q0 PM90--GP R 0KRJ--GP UM_PX RN09 RNKJ-GP RN0 R90 0RJ--GP R9 0RJ--GP UM_PX V_0 V_ R0 0KRJ--GP P0_HP P_HP EP_HP_ET Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU_ontrol&ebug(/) Q0 PM90--GP ize ocument Number Rev ustom JE0_ ate: Friday, pril 0, 0 0 heet of RNKJ--GP R KRJ--GP

7 PU_V OF PU PU_V for V(W PU) V V T V V T0 for V(W PU) V V T E V V U F V V U 0 09 V F F G H V V U9 V V V: V V V V V V0 0UF X H V V V H V V W 0.UF X 0nF X 0pF ap for EMI requirment J V V W K V V W K V V W L V V W L V V W9 L9 V V Y M V V Y M V V Y0 M0 V V Y M V V Y N V V Y N V V Y N9 V V Y0 P V V P V V for VN(W PU) P0 V V P V V for VN(W PU) R V V R V V PU_VN R9 V V E T V PU_VN INE 0P0VJN-GP 0UVKX-GP U0VKX-GP 0UVKX-GP 0UVKX-GP 0UVKX-GP 0P0VJN-GP 0UVKX-GP 0UVKX-GP U0VKX-GP 0UVKX-GP 0UVKX-GP 0UVKX-GP 0UVKX-GP J9 VN VN K J0 VN VN K J VN VN K 0 9 J 0UVKX-GP VN VN K J VN VN K J VN VN K K9 VN VN K K0 VN VN L VN: 0UF X 0.UF X 0pF ap for EMI requirment for VIO(W PU). for VIO(W PU) V_ 0P0VJN-GP U0VKX-GP 0UVKX-GP U0VKX-GP 0UVKX-GP 0P0VJN-GP 0P0VJN-GP 0UVKX-GP V_ VIO: 0UF X 0.UF X.uFUF X 0pF ap for EMI requirment. for VP(W/W) UVKX-GP U0VKX-GP 0UVKX-GP U0VKX-GP U0VKX-GP 0P0VJN-GP U0VKX-GP V_0 VIO R VIO R VIO R VIO T0 VIO T VIO T VIO U VIO U VIO U VIO V0 VIO V VIO V VIO W VIO W VIO W VIO Y VIO Y VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO G H J K0 K K L L L M0 M M N N N P0 P P 9 0 UVKX-GP U0VKX-GP 0P0VJN-GP UVKX-GP UVKX-GP U0VKX-GP 0UVKX-GP V_0 G VP_ VP_ G VP_ VP_ VP: G VP_ VP_ G VP_ VP_ 0 0UF X 0.uF X V_0 G VR VR 0pF ap for EMI requirment G VR VR V_0 G VR VR G9 VR VR for VR(W). for VR(W) 0. for V(W/W) V_0 0P0VJN-GP U0VKX-GP U0VKX-GP 0UVKX-GP 0UVKX-GP V V E F INE 00P0VKX-GP V_ 0P0VJN-GP UVKX-GP U0VKX-GP UVKX-GP 0P0VJN-GP 0P0VJN-GP UVKX-GP U0VKX-GP U0VKX-GP Wistron orporation VR:.UF X 0.uF X 0pF ap for EMI requirment F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ecoupling between processor and IMMs across VIO and plit 0P0VJN-GP 0P0VJN-GP U0VKX-GP U0VKX-GP 0 PU_Power(/) JE0_ ize ocument Number Rev ate: Friday, pril 0, 0 heet of 0

8 PUE OF E E0 E F9 F F F F F0 F F F F G G G G G G9 G G G J J J J0 J J K9 L L L0 M9 M M9 N N N0 N P9 P P9 R R R0 R T9 INE T T9 U U U0 U V9 V V9 W W W0 W W W W Y9 Y E E E E E E9 E E E E F F F9 F F F F F0 F F F F G0 H H H H H H9 H H H INE.00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU_(/) ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

9 P_RT# R9 0RJ--GP UM_PX_LV V_0 V_0 P_VIO 0 om change y edwin P_VIO UM_PX_LV L90 GK00T-0Y-GP nd =.00. UVKX-GP UVKX-GP UM_PX_LV P_VIOX UM_PX_LV L90 GK00T-0Y-GP nd =.00. UVKX-GP UVKX-GP UM_PX_LV R90 0KRJ--GP UM_PX_LV P_W_OUT P_V P_VRX UM_PX_LV UM_PX_LV L90 L90 GK00T-0Y-GP IN-UH-9-GP.R nd =.R.0E nd = UM_PX_LV UVKX-GP UVKX-GP UM_PX_LV P_RT# 9 UVMX-GP 9 0UVKX-GP LV_HN_TRVI LV_HP_TRVI LV_L0P_TRVI LV_L0N_TRVI,9 P_VIOX, P_HP0_ P_P# PWMI: 0~00KHz, 0~00% duty cycle UM_PX_LV R9 PU_LPWM_TRVI_R PU_LPWM_TRVI 0RJ--GP R909 0KRJ--GP P_RT# P_P# P_VRX 9 U0VKX-GP UM_PX_LV P_I_FG P_VIO UM_PX_LV 9 0 P_W_OUT U90 UXN UXP GN RX0P RX0N VRX RT# P# HP I_FG VIOX VIOX P_V GN 9 N# N# T0N T0P T0N T0P VIO T0N T0P 0 TK0N 9 TK0P PWMI W_OUT GNX V TETMOE GPIO0 RLV_FG RLV_ /M L/ML REXT RLV_MP GN 9 0 P_VIO T0N T0P N# N#.0.0 VIO N# UM_PX_LV ENPV/I_R 0 PWMO 9 ENLT V L PQFNGTR-0-GP P_RLV_MP P_REXT L/ML /M P_RLV_ P_RLV_FG P_RLV_LNK 99 U0VKX-GP UM_PX_LV LV_V_EN_R L_KLT_TRL_R L_KLT_EN_R P_VIO LV_T0# 9,9 LV_T0 9,9 LV_T# 9,9 LV_T 9,9 LV_T# 9,9 LV_T 9,9 LV_LK# 9,9 LV_LK 9,9 UM_PX_LV 9 U0VKX-GP 0RJ--GP 0RJ--GP 0RJ--GP 0 - LV_V_EN_R,0 L_KLT_TRL_R,0 L_KLT_EN_R,0 0 - R99 R90 R9 LV T_R 9 LV LK_R 9 PH.K V_0_TRVI on page:9 ingle Link LV ingle Link LV LV_V_EN 0,,9,9 L_KLT_TRL 0,9,9 L_KLT_EN 0,,9,9 R90: LV output swing control.99k for default swing, change the value for swing adjust UM_PX_LV R90 K99RF-L-GP R90 K99RF-L-GP UM_PX_LV TP90 9 U0VKX-GP P_V 9 0UVKX-GP UM_PX_LV 9 UVKX-GP 9 0UVKX-GP UM_PX_LV UM_PX_LV 90 U0VKX-GP V_0 0 UM_PX_LV R9 P_I_FG KRJ--GP UM_PX_LV R90 P_VIO KRJ--GP default setting RN90 RNKJ--GP UM_PX_LV Q90 L/ML ML_LK,, UM_PX_LV I_FG: Initial code loading selection, internal pull-down ~0K L: Hardware self configuration M: No initial code loading, external I control is expected H: Load initial code from external EEPROM through ML/M L: Hardware self configuration /M N00KW-GP.N0.F nd =.M0.0F ML_T,, R9 P_RLV_ KRJ--GP R9 UM_PX_LV P_VIO KRJ--GP 0 om change y EMI RLV_: LV selection, internal pull-down ~0K L: off M: +/- 0.% central spreading H: +/- % central spreading L: off R9 P_RLV_FG KRJ--GP UM_PX_LV R9 P_VIO KRJ--GP RLV_FG: LV color depth and data mapping selection, internal pull-down ~0K L: -bit LV, VE mapping M: -bit LV, JEI mapping H: -bit LV, both VE and JEI mapping H: -bit LV, both VE and JEI mapping Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TRVI ize ocument Number Rev JE0_ Friday, pril 0, 0 ate: heet of 9 0

10 00 HH-0--GP K UM_PX U00 V_0,9 LV_V_EN_R,,,9 _RT# 00 HH-0--GP K UM_PX R0 0KRF-GP UM_PX LV_V_EN_ 00 U0VKX-GP UM_PX N# V GN Y NVPX-GP.V.00H UM_PX LV_V_EN_Y R09 0RJ--GP UM_PX LV_V_EN 9,,9,9 00 HH-0--GP K L_KLT_EN_ UM_PX U00 N# GN V Y V_0 R0 0KRJ--GP UM_PX V_0,9 L_KLT_EN_R R0 00KRF-L-GP UM_PX 009 U0VKX-GP UM_PX NVPX-GP.V.00H UM_PX G Q00 N00K--GP.N0.J N =.N0.0 UM_PX LV_EQ_TRL_R R0 0R00-P LV_EQ_TRL R0 0R00-P LV_TRL_OE,9 L_KLT_TRL_R,9 L_KLT_EN_R R00 0-0RJ--GP KLT_TRL_ UM_PX 0 U0VKX-GP UM_PX R0 0RJ--GP LV_TRL_ UM_PX R00 0RJ--GP V_EN_U UM_PX 00 HH-0--GP K L_TRL_ UM_PX R00 00KRJ--GP UM_PX L_TRL_Q V_0 U00 UM_PX V GN Y NZ0MX-NL-GP.Z0.G V_0 U00 V 00 UM_PX HH-0--GP L_TRL_R L_TRL_U GN Y K 00 U0VKX-GP UM_PX NZ0MX-NL-GP.Z0.G UM_PX R00 00KRJ--GP UM_PX 00 U0VKX-GP UM_PX U00 OE V GN UM_PX Y HGGW-GP.G.0H L_TRL_OE U00 OE V GN UM_PX Y HGGW-GP.G.0H V_0 V_0 L_KLT_TRL_Y R0 0RJ--GP UM_PX L_KLT_TRL 9,9,9 R009 0RJ--GP UM_PX L_KLT_EN 9,,9,9 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet 0 of 0

11 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

12 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

13 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

14 0V_0 0UVKX-GP KP0VKX-GP R_VREF_ 9 UVKX-GP M RT# 09-0V_0 0 UVKX-GP can't stuff load too large let system abnormol at boot UVKX-GP Place these caps close to VTT and VTT. UVKX-GP U0VKX-GP KP0VKX-GP UVKX-GP Intel HR channel & RT tied toghter M have to separate channel & M 0 9 NP 0 NP M 9 NP NP M 9 M 9 0 R# M R# M 9 WE# M WE# M 9 # M # M 90 M 0# M IM0_#0 M 9 # M IM0_# M 9 9 M 0 0 0/P KE0 M IM0_KE0 M KE M IM0_KE M M 9 0 K0 M IM0_LK_R0 M 0 0 K0# M IM0_LK_R#0 M M 9 0 / K M IM0_LK_R 0 K# M IM0_LK_R# M M 0 M0 M M0 M M M M Q0 Q0 M M M M Q Q M M M M Q Q M M M M Q Q M M M M Q 0 Q M M M Intel HR M tied to GN M Q Q M M M M still following previous design M Q Q M Q Q 00 PH_MT,, M Q 0 Q L PH_MLK,, M Q9 Q9 V_0 M Q0 9 Q0 EVENT# M EVENT# M Q Q M Q Q VP 99 0_IM0 M Q Q 0_IM0 M Q 9 Q 0 _IM0 _IM0 M Q 0 F0 0 0 Q M Q 9 U0VKX-GP Q M Q Q N# M Q Q N# V_ M Q9 R0 R0 Q9 N#/TET M Q0 0 0 change to short pad Q0 0R00-P 0R00-P M Q Q V M Q 0 Q V M Q Q V M Q Q V M Q 9 Q V M Q Q V M Q 9 9 Q V M Q 9 Q V M Q9 99 Q9 V9 M Q0 00 Q0 V0 M Q 0 0 Q V M Q 9 0 Q V M Q Q V M Q Q V M Q Q V M Q 0 Q V M Q Q V 0 - M Q 0 Q V M Q9 F0 Q9 M Q0 Q0 M Q 9 Q PH_MT M Q R0 0RJ--GP Q PH_MLK M_T M Q 9 Q 9 R0 0RJ--GP M_LK M Q Q M Q Q PH_MT M Q Q 9 0P0VJN-GP PH_MLK M Q 0 Q 0 0P0VJN-GP M Q Q M Q9 Q9 M Q0 Q0 M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q 9 M Q 9 Q M Q9 9 Q9 M Q0 0 Q0 0 M Q Q M Q 9 F0 Q M Q 9 Q M Q#0 0 Q0# M Q# Q# M Q# Q# M Q# Q# V_ M Q# Q# M Q# Q# OIMM EOUPLING M Q# 9 Q# 9 M Q# Q# M Q0 Q0 0 F0 0 0 M Q 9 Q M Q Q M Q Q M Q Q M Q Q M Q Q M Q Q M IM0_OT0 OT0 M IM0_OT 0 OT 9 R_VREF_ VREF_ Layout Note: VREF_Q Place these aps near U0VKX-GP 9 M RT# 0 O-IMM. REET# V_0 0 VTT 0 0 VTT 0 U0VKX-GP U0VKX-GP H =mm M TNR TYPE R-0P--GP.00. nd =.00.P9 rd =.00. U0VKX-GP U0VKX-GP U0VKX-GP U0VKX-GP 0UVKX-GP U0VKX-GP U0VKX-GP 0UVKX-GP 0U0VZY-GP 0UVKX-GP 0UVKX-GP 0U0VZY-GP 0UVKX-GP 0 0UVKX-GP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev JE0_ Friday, pril 0, 0 ate: heet of 0

15 M M RT# U0VKX-GP R_VREF_ 0V_0 UVKX-GP U0VKX-GP Place these caps close to VTT and VTT. 0 -abine avid M M 0 M can't stuff load too large let system abnormol at boot UVKX-GP 9 0 UVKX-GP UVKX-GP U0VKX-GP UVKX-GP M IM0_OT0 M IM0_OT M RT# F0 Intel HR channel & RT tied toghter M have to separate channel & U0VKX-GP F0 U0VKX-GP M 0 M M M M M M M M M 9 M 0 M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q R_VREF_ 0V_0 H = mm /P / 0 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q OT0 OT VREF_ VREF_Q REET# VTT VTT TNR TYPE NP NP R# WE# # 0# # KE0 KE K0 K0# K K# M0 M M M M M M M NP NP L VP 99 0 N# N# N#/TET R-0P--GP.00.Z nd =.00.M rd =.00.X EVENT# V V V V V V V V V9 V0 V V V V V V V V _IM _IM V_ M R# M WE# M # M IM0_#0 M IM0_# M IM0_KE0 M IM0_KE M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# V_0 V_ 0_IM _IM M M0 M M M M M M M M 0 -abine avid M M 0 change to short pad M M Intel HR M tied to GN M M M still following previous design PH_MT,, PH_MLK,, M EVENT# 0 U0VKX-GP U0VKX-GP 0 U0VKX-GP F0 Layout Note: Place these aps near O-IMM. O-IMM is placed farther from the Processor than O-IMM 0 0U0VZY-GP U0VKX-GP V_0 Intel HR channel address is 0 M channel address is 0 OIMM EOUPLING 0 0U0VZY-GP U0VKX-GP 0 0UVKX-GP U0VKX-GP 0 0UVKX-GP R0 0KRJ--GP R0 0R00-P 0 0UVKX-GP 0 0U0VZY-GP U0VKX-GP 09 0UVKX-GP 0 0UVKX-GP U0VKX-GP F0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R-OIMM ize ocument Number Rev JE0_ Friday, pril 0, 0 ate: heet of 0

16 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

17 0,,,9 _RT# UMI_FH_PU_RX0P UMI_FH_PU_RX0N UMI_FH_PU_RXP UMI_FH_PU_RXN UMI_FH_PU_RXP UMI_FH_PU_RXN UMI_FH_PU_RXP UMI_FH_PU_RXN V_0 IP_LKP IP_LKN PU_LKP PU_LKN LK_PIE_VG LK_PIE_VG# WLN LK_PIE_WLN LK_PIE_WLN# G LK_PIE_WWN LK_PIE_WWN# LN LK_PIE_LN LK_PIE_LN# GPP LK port evice 0 New ard WLN WWN LN X X X X X Part of 00 change bom by siv FHE V_0 V_0 PIE_RT#_ E R _RT#_R PIE_RT# PILK0 F 0P0VKX-GP F PI_LK RJ--GP _RT# PILK/GPO _RX0P_ PILK/GPO F 0 UVKX-GP E0 G PI_LK_R R RJ--GP LK_PI_LP,, R R 0 _RX0N_ UMI_TX0P PILK/GPO UVKX-GP E PI_LK_R 0KRJ--GP 0KRJ--GP _RXP_ UMI_TX0N PILK/M_O/GPO9 F R 0R00-P PI_LK 09 UVKX-GP I_UM 0 _RXN_ UMI_TXP UVKX-GP _RXP_ UMI_TXN PIRT# UVKX-GP PX_UPPORT dgpu_prnt# _RXN_ UMI_TXP UVKX-GP 9 _RXP_ UMI_TXN UVKX-GP 0 J _RXN_ UMI_TXP 0/GPIO0 UVKX-GP UMI_TXN /GPIO L UVZY-GP R R /GPIO G 0KRJ--GP 0KRJ--GP UMI_PU_FH_TX0P UMI_RX0P /GPIO L PX PX UMI_PU_FH_TX0N H UMI_RX0N /GPIO UMI_PU_FH_TXP J UMI_RXP /GPIO UMI_PU_FH_TXN 9 L UMI_RXN /GPIO VRM_00_900 UMI_PU_FH_TXP Y N UMI_RXP /GPIO dgpu_prnt# UMI_PU_FH_TXN Y N UMI_RXN /GPIO -abin avid PX_UPPORT UMI_PU_FH_TXP Y J UMI_RXP 9/GPIO9 for W Jin define ZP_O_upport UMI_PU_FH_TXN Y9 L UMI_RXN 0/GPIO0 L PU_PIE_LRP /GPIO R0 F9 M PU_PIE_LRN PIE_LRP /GPIO 90RF-GP F J V_0 R09 PIE_LRN /GPIO K V_0 KRF--GP /GPIO V N GPP_TX0P /GPIO 0 - V GPP_TX0N /GPIO G9 W0 M R9 GPP_TXP /GPIO W GPP_TXN /GPIO J0 R 0KRJ--GP L 0KRJ--GP GPP_TXP 9/GPIO9 00MHz GPP_TXN 0/GPIO0 K Zero O VRM_00_900 GPP_TXP /GPIO N ebug trap ZP_O_upport GPP_TXN /GPIO G E /GPIO PI_ GPP_RX0P /GPIO R0 PI_ E R 0KRJ--GP GPP_RX0N /GPIO PI_ W GPP_RXP /GPIO F PI_ PX 0KRJ--GP 900MHz V H R GPP_RXN /GPIO GPU_PWROK_ PI_ Non Zero O V GPP_RXP /GPIO H 0RJ--GP GPU_PWROK,9,9 W GPP_RXN 9/GPIO9 W GPP_RXP 0/GPIO0 W E GPP_RXN /GPIO E0# N J R R0 E# PIE_RT#_ RJ--GP LK_LRN E# N0 PLT_RT#,,,, V_0 KRF--GP F LK_LRN E# FRME# G0 K9 EVEL# G0 V_0 V_0 folloiwng Intel HR netname 0 - EXT clock_gen PIE_RLKP IR# L0 0P0VKX-GP G F0 PIE_RLKN TR# R 0R00-P FHIP_LKP_R PR E0 R H R FHIP_LKN_R IP_LKP TOP# 0R00-P T M9 R IP_LKN PERR# H R 0KRJ--GP ERR# For TRVI H G 0KRJ--GP IP_LKP REQ0# H G IP_LKN REQ#/GPIO0 LT_TP# connection is just 00- F R FHPU_LKP_R REQ#/LK_REQ#/GPIO GPIO Muxless support for chipset automation purpose. 0R00-P T M FHPU_LKN_R PU_LKP REQ#/LK_REQ#/GPIO TP0 R 0R00-P T It is an automatic test for PU_LKN GNT0# FHGFX_LKP_R GNT#/GPO PE_GPIO0 PE_GPIO0 ->VG_REET PE_GPIO 9 PE_GPIO ->VG_PowerEnable M validation team only I_PX R I_PX R 0RJ--GP 0RJ--GP J0 FHGFX_LKN_R LT_GFX_LKP GNT#/_LE/GPO K9 K GPIO LT_GFX_LKN GNT#/LK_REQ#/GPIO TP0 9 LKRUN# PM_LKRUN# 0 - H H9 NEW GPP_LK0P LOK# H GPP_LK0N PM_LKRUN# F R LK_MINI_R INTE#/GPIO 0R00-P J E checklist:no PU Res R9 LK_MINI#_R GPP_LKP INTF#/GPIO 0R00-P K GPP_LKN INTG#/GPIO Integrated Resistor PU0K LK_R INTH#/GPIO T_O_# G R0 0RJ--GP F LK_R# GPP_LKP G R 0RJ--GP F GPP_LKN R 0R00-P LN_LK_R E R LN_LK#_R GPP_LKP 0R00-P E LPLK0_R R9 GPP_LKN LPLK0 RJ--GP LP_LK0, LPLK LP_0 LP_LK M GPP_LKP L0 LP_ LP_0,, M GPP_LKN L LP_,, LP_ L LP_ LP_,, M 9 GPP_LKP L LP_,, M GPP_LKN LFRME# LP_FRME#,, LKREQ# LRQ0# N E GPP_LKP LRQ#/LK_REQ#/GPIO9 0 N E9 INT_ERIRQ GPP_LKN ERIRQ/GPIO INT_ERIRQ 00 bom change R GPP_LKP 0 0P0VJN-GP R GPP_LKN G K_X LLOW_TOP M_TIVE# N E GPP_LKP PROHOT# PU_PROHOT# R GPP_LKN PU_PG E H_PUPWRG_E,,,9 G LT_TP# F PU_RT# PU_RT# J M_M_M_O R0 X0 G K_X 0MR-GP K_X X-KHZ-GPU 0 change to short pad.000. M_X G K_X M_X K_X N =.000. R0 PH_ULK_K _ORE_EN H 0R00-P M_X RTLK F INTRUER_LERT# RT_LK F M_X INTRUER_LERT# K_X VT_RT_G E TP0 RT_UX_ PI EXPRE INTERFE LOK GENERTOR PI LK PI INTERFE PU PLU LP 0 P0VJN-GP R0 MRJ--GP X0 XTL-MHZ-0-GP.000. N = R =.000. M_X M_X L = pf Freq tolertance :+/- 0ppm 0 P0VJN-GP.HUM.M0 G0 GP-OPEN 0 UVZY-GP 0 UVKX-GP L = pf Freq tolertance :+/- 0 ppm Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev ustom JE0_ 0 P0VN-GP ate: Friday, pril 0, 0 heet of 0

18 V_ V_0 RN0 R 0KRJ--GP R 0KRJ--GP LK T integrated PU R 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R9 0KRJ--GP M_LK M_T E_I# E_WI# PM_PWRTN# PIE_WKE# U_O# have not use O function in JE0 Project VG_P integrated PU (FH Rev. updated) 0 integrated PU R R RN0KJ--GP RN0 RNKJ--GP RN0 0KRJ--GP 0KRJ--GP RN0KJ--GP H_0GTE H_RIN# H_IN0 H_OE_ITLK H_OE_RT# hecklist suggestion do not stuff by default R 00KRJ--GP integrated PU is not supported when the pin if configured for U O (FH Rev. updated) 9 base on M suggestion, PM_RMRT# M define two function pin on same pin in R PM_RMRT# ,, make sure Travis_EN# function first so confrim function work nornally or not on GPIO,if work nornally, IO can re-programming pin to GPIO (R,stuff R) and change Travis_EN# to GPIO in the furtur keep Gevent# for PIE_RT used LK_PIE_WWN_REQ# LK_PIE_WLN_REQ# H_OE_ITLK H_OE_OUT 9 H_IN0 H_OE_YN H_OE_RT#,9,, PM_LP_#, PM_LP_#,9 PM_PWRTN# FH_PWRG H_THERMTRIP# V_0 PIE_LK_LN_REQ# E_WI# T_O_PRNT# O Q,, M_LK M_T PEG_LKREQ# PIE_WKE# Function Name Integrated Resistor External Resistor G0IN H_0GTE.K PU 0K PU._0 KRT# PME# H_RIN# E_I#.K PU 0K PU 0K PU._0 0K PU._ THRIPTRIP# H_THERMTRIP# 0K PU 0K PU._ PIE_RT# Gevent FH_PIE_RT# MEM_Hot# 0K PU 0K PU Gevent E_WI# 0K PU 0K PU._ WKE# PIE_WKE# 0K PU 0K PU._ U_O0# U_O# U_O# Gevent# Gevent# 0 - H_PKR R0 U_O0# U_O# U_O# T_O_PRNT# O_ 0 U0VKX-GP 0R00-P 0K PU 0K PU 0K PU 0K PU 0K PU U_O# U_O# 0K PU Gevent# E_WI# 0K PU 0K PU._0 U_O# U_O# 0K PU 0 change to short pad TP0 0 change to short pad TP0 TP0 R H_0GTE 0R00-P R H_RIN# 0R00-P E_I# 0-0R00-P R9 0R00-P 0R00-P 0-0RJ--GP R 0KRJ--GP 0 - R R R0 0RJ--GP ZERO O R0 RJ--GP R0 RJ--GP E0 0P0VJN-GP R0 RJ--GP R0 RJ--GP TP0 LP_MI# E_MI#.K PU 0K PU._ GPIO T_O_#.K PU ERIRQ INT_ERIRQ.K PU 0K PU._0 LK_REQ0 LK_PIE_NEW_REQ#.K PU LK_REQ LK_PIE_WLN_REQ#.K PU LK_REQ LK_PIE_WWN_REQ#.K PU LK_REQ PIE_LK_LN_RQ#.K PU LK_REQG PEG_LKREQ#.K PU R0 E0 0P0VJN-GP TP0 PM_PWRTN#_R R09 0R00-P FH_TET0 FH_TET FH_TET E_0M#_R E_K_RT#_R E_I# PIE_WKE# FH_THERMTRIP# W_PWRG PIE_LK_LN_RQ#_R LK T LK_PIE_WWN_REQ#_R LK_PIE_WLN_REQ#_R R 0RJ--GP VG_P FH_GPIO H_PKR_R H_ITLK H_OUT H_IN0 H_YN H_RT# LKREQG# U_O# E_WI# T_O_PRNT#_R R W T W J N T9 T0 V9 E G9 R9 T U K V R0 F9 U G E E F H G F T R G G J G V W Y V0 F M R T P F P J T Y Y Y E K9 J9 J 0 F E0 F0 E 0 J H G K 9 9 FH PIE_RT#/PI_PME#/GEVENT# RI#/GEVENT# PI_#/GE_TT/GEVENT# LP_# LP_# PWR_TN# PWR_GOO TET0 TET/TM TET G0IN/GEVENT0# KRT#/GEVENT# LP_PME#/GEVENT# LP_MI#/GEVENT# LP_P#/GEVENT# Y_REET#/GEVENT9# WKE#/GEVENT# IR_RX/GEVENT0# THRMTRIP#/MLERT#/GEVENT# W_PWRG RMRT# LK_REQ#/T_I0#/GPIO LK_REQ#/T_I#/GPIO MRTVOLT/T_I#/GPIO0 LK_REQ0#/T_I#/GPIO0 T_I#/FNOUT/GPIO T_I#/FNIN/GPIO9 PKR/GPIO L0/GPIO 0/GPIO L/GPIO /GPIO LK_REQ#/FNIN/GPIO LK_REQ#/FNOUT/GPIO IR_LE#/LL#/GPIO MRTVOLT/HUTOWN#/GPIO R_RT#/GEVENT#/VG_P GE_LE0/GPIO PI_HOL#/GE_LE/GEVENT9# GE_LE/GEVENT0# GE_TT0/GEVENT# LK_REQG#/GPIO/OIN/ILEEXIT# LINK/U_O#/GEVENT# U_O#/IR_TX/GEVENT# U_O#/IR_TX0/GEVENT# U_O#/IR_RX0/GEVENT# U_O#/_PRE/TO/GEVENT# U_O#/TK/GEVENT# U_O#/TI/GEVENT# U_O0#/PI_TPM_#/TRT#/GEVENT# Z_ITLK Z_OUT Z_IN0/GPIO Z_IN/GPIO Z_IN/GPIO9 Z_IN/GPIO0 Z_YN Z_RT# P_T//GPIO P_LK/E/L/GPIO PI_#/GE_TT/GPIO PK_T/GPIO9 PK_LK/GPIO90 PM_T/GPIO9 PM_LK/GPIO9 KO_0/GPIO09 KO_/GPIO0 KO_/GPIO KO_/GPIO KO_/GPIO KO_/GPIO KO_/GPIO KO_/GPIO KO_/GPIO KO_9/GPIO KO_0/GPIO9 KO_/GPIO0 KO_/GPIO KO_/GPIO KO_/X0/GPIO KO_/X/GPIO KO_/X/GPIO KO_/X/GPIO.HUM.M0 V_UX_ R 0KRJ--GP _PGOO_ H UIO R 00KRJ--GP EMEE TRL Q PI / WKE UP EVENT GPIO U O U MI U. ULK/M_M_M_O U.0 U.0 L/GPIO9 /GPIO9 L_LV/GPIO9 _LV/GPIO9 E_PWM0/E_TIMER0/GPIO9 E_PWM/E_TIMER/GPIO9 E_PWM/E_TIMER/WOL_EN/GPIO99 E_PWM/E_TIMER/GPIO00 N00KW-GP.N0.F nd =.M0.0F PM_RMRT# Part of U_ROMP U_FP/GPIO U_FN U_F0P/GPIO U_F0N U_HP U_HN U_HP U_HN U_HP U_HN U_H0P U_H0N U_H9P U_H9N U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_HP U_HN U_H0P U_H0N U_LRP U_LRN U TXP U TXN U RXP U RXN U TXP U TXN U RXP U RXN U TXP U TXN U RXP U RXN U TX0P U TX0N U RX0P U RX0N KI_0/GPIO0 KI_/GPIO0 KI_/GPIO0 KI_/GPIO0 KI_/GPIO0 KI_/GPIO0 KI_/GPIO0 KI_/GPIO0 R KRJ--GP G 9 H H H H H0 G0 K0 J G F K K E0 F0 0 0 H9 G9 F E E E E F F G H G J H J K H9 G9 G G E H J H K K F F E F U_ROMP U_LRP U_LRN L T LK T R R RMRT#_K V_V_POK R9 KRF-GP U0_P U0_M U0_P U0_M U0_P U0_M U_PP 9 U_PN 9 U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP0 U_PN0 U KRF--GP U KRF--GP U0_TXP0 9 U0_TXN0 9 U0_RXP0 9 U0_RXN0 9 LK T E_PWM V_ U0_TXP U0_TXN U.0 ext port U0_RXP U0_RXN U0_TXP U0_TXN U.0 ext port U0_RXP U0_RXN U0_TXP U0_TXN U.0 on board port U0_RXP U0_RXN Pair WLN L T LK T U.0 EXT(For W ebug) N WWN T U U PORT U PORT evice G IM ard U.0 ccd.0 U.0 on board port U.0 ext port U.0 ext port If not used MU or GPIO,P 0K V_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev ustom JE0_ Friday, pril 0, 0 ate: heet of 0 RN0 RN0 RN0KJ--GP RN0KJ--GP

19 FH Part of st T H T O E-T nd T H T_TXP0 T_TXN0 T_RXN0 T_RXP0 T_TXP T_TXN T_RXN T_RXP K9 M9 L0 N0 N L H0 J0 J H M K H J N L L N J H T_TX0P T_TX0N T_RX0N T_RX0P T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP T_TXP T_TXN T_RXN T_RXP R GE LN _LK/LK_/GPIO _M/LO_/GPIO _#/GPIO _WP/GPIO _T0/TI_/GPIO _T/TO_/GPIO _T/GPIO9 _T/GPIO0 GE_OL GE_R GE_MK GE_MIO GE_RXLK GE_RX GE_RX GE_RX GE_RX0 GE_RXTL/RXV GE_RXERR GE_TXLK GE_TX GE_TX GE_TX GE_TX0 GE_TXTL/TXEN GE_PHY_P GE_PHY_RT# GE_PHY_INTR L N J H K M H J 9 W0 H F E G F9 G E 9 W9 GE_OL GE_R GE_MIO GE_RXERR GE_PHY R90 0KRJ--GP V_ RN90 RN0KJ--GP N9 L K M L9 N L L H H T_TXP T_TXN T_RXN T_RXP N#L9 N#N N#L N#L N#H N#H ERIL T PI ROM PI_I/GPIO PI_O/GPIO PI_LK/GPIO PI_#/GPIO ROM_RT#/PI_WP#/GPIO VG_RE VG_GREEN VG_LUE V V V T V L0 L M9 R90 0RF--GP UM_PX R90 0RF--GP UM_PX R90 0RF--GP UM_PX RT_RE 9 RT_GREEN 9 RT_LUE 9 J J N#J N#J VG_HYN/GPO VG_VYN/GPO9 M N0 RT_HYN 9 RT_VYN 9 V_ R90 0KRJ--GP RN90 PU_TLERT# GPIO FH_U.0PORT_EN# M_THRM_FH V_0 0, PH_TEMP_LERT# R90 KRF--GP R90 9RF--GP T_O_PWRGT T_LE# T_LP T_LN [checklist]: Integrated lock Mode => Left unconnected GPIO FH_U.0PORT_EN# M_THRM_FH R9 PU_TLERT# 0RJ--GP F T_LRP F T_LRN F G T_T#/GPIO T_X T_X H FNOUT0/GPIO M FNOUT/GPIO J FNOUT/GPIO K FNIN0/GPIO N FNIN/GPIO L FNIN/GPIO HW MONITOR K TEMPIN0/GPIO K TEMPIN/GPIO K TEMPIN/GPIO M TEMPIN/TLERT#/GPIO.HUM.M0 VG MINLINK VG VG /GPO0 VG L/GPO VG RET UX_VG_H_P UX_VG_H_N UXL ML_VG_L0P ML_VG_L0N ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_LP ML_VG_LN ML_VG_HP/GPIO9 VIN0/GPIO VIN/GPIO VIN/TI_/GPIO VIN/TO_/GPIO VIN/LO_/GPIO9 VIN/LK_/GPIO0 VIN/GE_TT/GPIO VIN/GE_LE/GPIO N#G N#H0 N# N#G N#L M N K HUON REET V V9 U T T T9 T R R0 P9 P 9 N M L N P P M M G H0 G L UXL PW_LR# GPIO U_HP GPIO GPIO9 GPIO0 VIN_VR GPIO RT T 9 RT LK 9 R90 UM_PX RF-GP P_UXP_R P_UXN_R 0 GPIO M M V_0 R9 P_TX0P_R 00RF-L-GP-U P_TX0N_R P_TXP_R P_TXN_R P_TXP_R P_TXN_R V_VN 0_R P_TXP_R R90 P_TXN_R 0KRJ--GP V_ R9 0KRJ--GP 9 R9 0KRJ--GP P_HP_R U_HP V_ R99 0KRJ--GP R9 0KRJ--GP RN0KJ--GP RN90 RN0KJ--GP GPIO0 GPIO GPIO GPIO9 V_ VIO.V.V MEM_V H L MEM_V on't are H VRM IZE M G Vram size (GPIO) Vram size (GPIO) 0 0 G 0 PW_LR# undfine 0 R9 0KRJ--GP R909 0KRJ--GP VIN_VR 09- If not used HWM or GPIO,P 0K G90 GP-OPEN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev ustom JE0_ ate: Friday, pril 0, 0 heet 9 of 0

20 V_0 V_0 0m 00m VN LK V_VPPL_Y_0 0m H VPL Y VN LK V_VPL_ML_0 0m H 0m V Q00 VPL VN LK m J U O00-GP VPL ML VN LK 0 ohm 00m V_0 V_VN 0_R 0m K 0 T VN VN LK V_VPL_U_ m L 0 U0VKX-GP L UVKX-GP U0VKX-GP UVKX-GP R09 L00 VPL U_ VN LK V_VPL_U_ m M U0VKX-GP 0RJ-0-U-GP VPL_.V_PIE VPL U_ VN LK m N H9 LMG-GP VPL PIE VN LK m N G.000.E 0 0 LO_P V_0 V_0 R00 0RJ--GP VPL T VN LK P nd =.00.0 U0VKX-GP U0VKX-GP 0 UVKX-GP M 0m V_0 LO_P VN PIE L00 VN PIE Y V 0 ohm 00m VPL VPL VN PIE m E V_0 PY00T-0Y-N-GP VN PIE m Y UVKX-GP U0VKX-GP U0VKX-GP UVKX-GP 0UVKX-GP V_ L00 VN ML VN PIE.000. V VPL_.V_T VN ML VN PIE UM_PX V LMG-GP UVKX-GP U0VKX-GP VN ML VN PIE F V.000.E 0 0 VN ML VN PIE UM_PX G nd =.00.0 U0VKX-GP U0VKX-GP m 0 VIO GE_ VN T m V_ R0 VN T UM_PX Y0 U00 VN T VN T m 09 U0VKX-GP U0VKX-GP UVKX-GP VR GE_ VN T UVKX-GP IN OUT VR GE_ VN T GN V_ET VN T 0 0 HN# ET VN T m 9 VIO_GE_ VN T 0 0 G9TU-GP VIO_GE_ VN T F R0 9K9RF-L-GP 0 ohm V_ V_U_ V_ Vout=.0*(+R/R) L00 0m G 0m H0KF-T0-GP VN U_ VIO N H 0- VN U_ VIO.00. L9 J 0 0 N = VN U_ VIO M 0 0 K U0VKX-GP UVKX-GP UVKX-GP UVKX-GP 0UVKX-GP VN U_ VIO V U0VKX-GP U0VKX-GP K9 VN U_ VIO V If support U.0 or LN wake-up, pls tie to.v_ M9 VN U_ VIO Y otherwise, tie to.v_0 M0 VN U_ VIO Y N9 VN U_ VIO L00 0 ohm 00m W N0 V_ VN U_ V_ M 0 ohm 00m L009 LMG-GP VN U_ N m VXL_.V.000.E 0 0 VN U_ VXL G M R0 LMG-GP nd =.00.0 U0VKX-GP U0VKX-GP VN U_ 0RJ--GP V_ E VN_.V_U 0mU 90m nd =.00.0 VN U_ VR N0 U VR_V V_ R0 VN U_ VR M0 L0 R0 V_ 0RJ--GP VR_.V_ VR_.V_U m T 0m V_VPPL_Y_ RJ--GP 0 ohm 00m LMG-GP VR U_ VPL Y_ J T UVKX-GP V_.000.E VR U_ R00 nd =.00.0 U0VKX-GP m V_VN_HWM_ 0RJ--GP VN HWM_ m M P VN U_ M VN U_ N VN U_ VIO_Z_ m V_ P VN U_ P VN U_ 09 0 ohm 00m ohm U VN_.V_U_ mn UVKX-GP VR U_ L00 N V_U_ V_VPL_U_ VR U_ V_ P L0 PY00T-0Y-N-GP VR U_ M VR U_.000. LMG-GP onfrim.000.e R0 nd U U = RJ--GP odec power use.v,vio_z have to tied to.v U0VKX-GP U0VKX-GP Non U U0VKX-GP U0VKX-GP UVKX-GP POWER U odec power use.v,vio_z have to tied to.v If use.v_ power,have to add LO for it extra 00 0UVKX-GP U0VKX-GP 00 U0VKX-GP U0VKX-GP 00 U0VKX-GP UVKX-GP U0VKX-GP U0VKX-GP 00 U0VKX-GP U0VKX-GP E9 0 G FH VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP VIO PIGP.HUM.M0 MIN LINK GE LN PI/GPIO I/O ERIL T PI EXPRE LKGEN I/O U U ORE 0.V_ I/O Part of VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ VR_ T T T0 U U V V V0 Y 00 UVKX-GP 00 UVKX-GP UVKX-GP 009 U0VKX-GP V_0 00 U0VKX-GP U0VKX-GP VN LK U0VKX-GP U0VKX-GP VN LK_ G R09 0KRF--GP.000. V_0 0KRF--GP UVKX-GP If support U.0 wake-up, tie to.v_ If no, tie to.v_0, If no U.0, tied to GN 0 ohm 00m 0 ohm 00m 0 ohm 00m 0 ohm 00m V_0 V_VPL_ML_0 R0 0R00-P 0 UVKX-GP V_0 0 U0VKX-GP UM_PX UM_PX L0 LMG-GP.000.E nd =.00.0 V_0 V_VPPL_Y_0 V_ V_VN_HWM_ L0 L0 LMG-GP LMG-GP.000.E.000.E nd = nd = U0VKX-GP U0VKX-GP U0VKX-GP 0 U0VKX-GP V_VN 0_R 0 U0VKX-GP UM_PX HW Montior Not implemented or HW Montior balls not used GPIO => ecoupled cap not used HW Montior Not implemented or HW Montior balls used as GPIO => ead not used 0 U0VKX-GP V_ L0 LMG-GP.000.E nd =.00.0 V_ L00 LMG-GP.000.E nd =.00.0 V_VPPL_Y_ If support U.0, tie to.v_ otherwise, tie to.v_0 0 U0VKX-GP 09 U0VKX-GP V_ U V_VPL_U_ L0 LMG-GP.000.E nd = U0VKX-GP If U.0 wake-up is supported, tie to.v_ If no, tie to.v_0, If no U.0, tie to GN 0 U U0VKX-GP R0 0RJ--GP Non U Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev JE0_ Friday, pril 0, 0 ate: heet of 0 0

21 I =. REQUIRE TRP V_0 V_ V_ R:PU.V_UX_ checklist:pu.v_ no support PLU funciton,pu.v_ REQUIRE YTEM TRP UE this pin to determine INT/EXT LK 0KRJ--GP R0 R0 0KRJ--GP R0 0KRJ--GP R0 0KRJ--GP 0KRJ--GP R0 0KRJ--GP R0 PULL HIGH PULL LOW E_PWM PH GPO99 LP ROM EFULT PI ROM PI_LK llow PIE GEN EFULT Force PIE GEN RT_LK _PLU Mode ILE EFULT _PLU Mode ENLE LK_PI_LP UE EUG TRP IGNORE EUG TRP EFULT PI_LK non_fusion LOK mode Fusion LOK mode EFULT LP_LK0 ENLE E ILE E EFULT LP_LK LKGEN ENLE (Use Internal) EFULT LKGEN ILE (Use External) PI_LK,, LK_PI_LP PI_LK, LP_LK0 LP_LK E_PWM RT_LK LP ROM implemented checklistsuggestion: no PU or P required (integrated PU 0K) R: do not stuff PU Res R 0KRJ--GP 0KRJ--GP R 0KRJ--GP R 0KRJ--GP R R R R9 0KRJ--GP KRF-GP KRF-GP EUG TRP PI_ PI_ PI_ PI_ PI_ R0 R0 R09 R09 R0 R0 R R R PULL HIGH PI_ UE PI PLL (EFULT) PI_ isable IL UTORUN (EFULT) PI_ UE F PLL (EFULT) PI_ UE EFULT PIE TRP (EFULT) PI_ isable PI MEM OOT (EFULT) KRJ--GP KRJ--GP KRJ--GP KRJ--GP KRJ--GP PULL LOW YP PI PLL Enable IL UTORUN YP F PLL UE EEPROM PIE TRP Note: FH has K internal PU FOR PI_[:] Enable PI MEM OOT Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

22 FH Part of 9 E E E E9 F F9 F F F F F9 F F F9 G G G H H H9 J J9 J0 J J J K K K K L L L L L L M M M M N N N N N P P P0 P P P R R R R T T T N K H N_HWM XL PL_Y GROUN PL_ N_ NQ_ IO_ EFUE T T U U U U0 U U0 U V V V W W W W Y Y Y 0 E E E E F F F F G0 G H H H H9 H H H H J J J9 K K L M M N N N N T L K N R.HUM.M0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HUON-M(/) ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

23 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

24 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

25 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

26 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Reserved ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

27 , 0,,,9 _RT# LP_LK0 9 F0 UVZY-GP KOL TP0,, INT_ERIRQ LP_FRME# PM_LKRUN#,, LP_0,, LP_,, LP_,, LP_ TP > H_RIN# H_0GTE K_EEP FN_PWM FN_TH KOL[0..] KOL KROW[0..] TPLK TPT P_RT# _TFULL RT_E# INT_ERIRQ LP_FRME# LP_LK0 PM_LKRUN# LP_0 LP_ LP_ LP_ ERT# EI#_K KOL0 KOL KOL KOL KOL KOL KOL KOL KOL KOL9 KOL0 KOL KOL KOL KOL KOL KOL KOL KROW0 KROW KROW KROW KROW KROW KROW KROW G_PRE# U0 ERIRQ LFRME# PILK LKRUN# L0 L L L ERT# KRT# I# G0 PIRT# PWM0 PWM FNPWM0 FNPWM FNF0 FNF KO0 KO KO KO KO KO KO KO KO KO9 KO0 KO KO KO KO KO KO KO KI0 KI KI KI KI KI KI KI PLK PT PLK PT PLK PT V V V V_0 V 9 V 9 V GN 9 GN GN GN GN_0 GN 9 L0 0 L 0 0 GPXIO0 GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO9 GPXIO0 GPXIO GPXIO0 GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO GPXIO T_L T_ FN_ E_LV_V_EN _I P_VER_ T_TYPE E_PI_WP# _ENLE _OFF E_GPXIO09 G_LE E_GPXIO _IN# E_GPXIO0 E_GPXIO HRGER_TYPE E_GPXIO V_UX_ L H0KF--GP V_UX_ E_V E_GN T_L 9,0 T_ 9,0 ML_T,9, ML_LK,9, R9 0RJ--GP _EN 9 G_EN _I 0 UVZY-GP PU_THRM E_PI_WP# 0 U_PWR_EN#, MP_MUTE# 9 PM_PWRTN#,9 _ENLE,9 RMRT#_K _OFF WLN_TET_LE T_IN# 9 _IN# 0 TP UVZY-GP PH_TEMP_LERT#,9 V PWRG, TP UVZY-GP E_GN TP LV_V_EN 9,0,9,9 0 change to short pad R 0R00-P 0 UVZY-GP LON_OUT 9 HRGER_TYPE V_UX_ T/HRGER PU-Temp/VG Temp ; PH.k on PU side TP TP09 TP0 0 - V_UX_ R 0KRJ--GP E_GN T_TYPE E_GN IRETE# V_UX_ T_TYPE /(PIN) PULL-LOW REITOR PULL-HIGH REITOR VOLTGE W N/ 00.0K.V 90W 00.0K N/ 0V 0W 0.0K 00.0K 0.V 0W 0.0K 00.0K 0.V 0W.0K 00.0K 0.V Reserved.0K 00.0K.0V Reserved.9K 00.0K.V P VERION /(PIN) PULL-LOW REITOR PULL-HIGH REITOR VOLTGE - Reserved Reserved Reserved W 90W 00.0K 00.0K 00.0K 00.0K 00.0K 00.0K 00.0K R0 00KRF-L-GP R0 00KRF-L-GP IRETE# High: UM Low: iscrete, PX 0.0K 0.0K.0K.0K.9K.K 00.0K R0 UM 00KRF-L-GP R0 I_PX 00KRF-L-GP.0V.V.V.V.0V.V.V Model I R0 00KRF-L-GP E_GN V_UX_ 0 - R 00KRF-L-GP _IN# V_UX_ 0 - R 00KRF-L-GP E_GPXIO R09 0RJ--GP 0 0P0VKX-GP G0 GP-OPEN K_PWRTN# 9, 0 PI_LK_R E_I# TP9 R RJ--GP TP0 TP, 0,9,, WIFI_RF_EN LUETOOTH_EN 0 0, 9,0,9,9 9 L_KLT_EN RIGHTNE HG_ON# LI_LOE# PM_LP_# TOP_HG# PM_LP_# TY_LE Y_THRM 0 change to short pad 0 --GP EI#_K.000.K N =.000.F, E_WI# E_I# TOP_HG# E_GPIO0 E_GPIO0 E_GPIO LUETOOTH_EN E_PI_LK_ HG_ON# EWI#_K PURE_HW_HUTOWN# R 0R00-P R 0RJ--GP GPIO GPIO GPIO GPIO0 GPIO0 GPIO0 PWM GPIO9 GPIO GPIO GPIO PILK GPIO9 GPIO0 GPIO K9QF-0-GP.09.0G R 0KRJ--GP EWI#_K EI#_K PI# 0 MOI MIO 9 9 GPIO0 90 GPIO GPIO GPIO 0 GPIO 9 GPIO 9 GPIO GPIO GPIOE VR E_PI_#_ E_PI_O_ E_PI_I_ PROHOT_E Model I WIRELE_LE IRETE# PURE_HW_HUTOWN#_Q Q0 MMT90--GP VR 09 UVKX-GP UHRGER_ P_PWM_K 0RJ--GP R E R RJ--GP R RJ--GP R 0R00-P U0VKX-GP ERT# 0- HRGE_LE E_Tx E_Rx 0 UVKX-GP TP WLN_LE_OFF# PWRLE PURE_HW_HUTOWN# PI_0#_R 0 PI_I_R 0 PI_O_R 0 R TP0 00KRF-L-GP U0VKX-GP V_UX_ R 0KRJ--GP 0- PU_LPWM_TRVI,9 0 Prevent IO data loss solution R 0KRJ--GP P0VJN-GP U0 GN REET# V R 00KRJ--GP V_UX_ 0- P_VER_ V_UX_ PH_ULK_K E_GN E GPIO standard PH/PL T_L T_ T_IN# R0 KRF-GP R0 00KRF-L-GP Value PN 0K.00.L 0K.0.L.K..L.9K.9.L.K..L K.00.L K.00.L K RN0 RNKJ--GP R 00KRJ--GP.0.L V_UX_ T_ T_L V_0 Q0 N00KW-GP.N0.F nd =.M0.0F V_0 RN0 RNKJ--GP T,9 T L,9.T90. nd =.090.F rd =.090.R V_0 G90L9TUF-GP.0090.I ERT# R 0KRJ--GP HG_ON# TOP_HG# RN0 V_UX_ PROHOT_E E_GPIO0 High ctive Q0 G R G 0KRJ--GP _ENLE R0 0KRJ--GP _OFF RN00KJ--GP R KRJ--GP R0 00KRJ--GP H_PROHOT#_E N00K--GP.N0.J N =.N0.0 R9 0R00-P H_PROHOT# 0- G_PRE# R NON G 0KRJ--GP FN_TH V_0 R 0KRJ--GP E Proceted:KV E_Rx R 0KRJ--GP w/ G: PU 0K to V_0 ; w/o G: P 0K GN Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. K NPE9 ize ocument Number Rev JE0_ Friday, pril 0, 0 ate: heet of 0

28 00- V_0 J IN Over temperature threshold setting by external resistor divider Floating= o; GN=90o; V=9o V_0 V_0 R0 NT-00K--GP R 00RJ--GP 0 0UVKX-GP 09- V_0_thermal U0VKX-GP Layout notice : oth XN and XP routing 0 mil trace width and 0 mil spacing..090.l0 N =.090.P Q0 PM90--GP P00_XP 9 90P0VJN-GP P00_XN J 0- close to U0 V_0_thermal 00P0VKX-GP THERM_Y_HN#.ystem ensor, Put on palm rest.h/w T hutdown R0 0KRJ--GP R09 0KRJ--GP U0 V XP XN OTZ P00E0-GP TR TL GN J.000. J FN_TH Y_THRM PU_THRM 0 UVKX-GP R0 0RJ--GP FN_TH_ U0VKX-GP 0 HH-0PT-GP.R00.F 0 change to short pad nd =.R00.HH FN_PWM_R FN_PWM R0 rd =.R00.0F 0R00-P FN_TH_ R9 V_0 FN_V *Layout* mil 0-09 U0VKX-GP R0 0KRJ--GP FN_V 0 HH-0PT-GP.R00.F nd =.R00.HH rd =.R00.0F 0 00P0VKX-GP 0R00-P For PWM FN FN E-ON--GP 0.F0.00 nd = 0.F0.00 rd = 0.F.00 VG Thermal sensor P00 V_UX_ V_0, PURE_HW_HUTOWN# 0 TPT-GP.000.T nd =.T. rd =.T. R 0KRJ--GP U0VKX-GP Q0 N00K--GP THERM_Y_HN# G V_0.N0.J N =.N0.0 E Proceted:KV R 00KRJ--GP 0 - Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal P00 ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet of 0

29 V_0 P# 9 U0VKX-GP 0 - R9 0RJ-0-U-GP U90 EN N# GN VIN VOUT G909-TU-GP.0909.FF N =.099.F R9 00RJ--GP EP V_0 U_GN U_GN LOE TO PIN U_GN 0-9 0U0VKX-GP H_OE_OUT H_OE_ITLK H_OE_OUT H_IN0 P#=0 Power down PK mp P#= Power up PK mp IGITL U90 (include thermal pad) L_V 90 P0VJN--GP 0-90 U0VKX-GP U_GN 9 U0VKX-GP LOE TO PIN 9 U0VKX-GP LOE TO PIN V_0 U_P U_N PVEE HP_OUT_R_U HP_OUT_L_U 0 - R9 U_HP_JK_R RJ--GP R9 U_HP_JK_L RJ--GP 0 - EP V_0 U_PK_R+ U_PK_R- U_PK_L- U_PK_L+ 0 - V_0 V_0 R9 0R00-P 9 GN PIFO EP PV PK-OUT-R+ PK-OUT-R- P P PK-OUT-L- 0 PK-OUT-L+ 9 PV V.00.0 LX-V-GR-GP U_HP_J# H_OE_ITLK 0 - R9 RJ--GP R9 0R00-P V 90 P0VJN-GP P# GPIO0/MI-T GPIO/MI-LK P# T-OUT 0 - Z_ITLK_UIO_+ 9_TIN LK T-IN V-IO 9 YN 0 REET# PEEP P N PVEE HPOUT-R/PORT-I-R HPOUT-L/PORT-I-L MI-VREFO-L MI-VREFO-R MI-VREFO LO-P VREF V 0 9 VREF LO_P_UIO MIV MI-VREFO MI-VREFO 9 UIP_P_EEP U_GN MIV 0 - V_0 0 - V_0 L_V U_HP R9 0RJ--GP U_HP_J_R# H_OE_YN H_OE_RT# 909 P0VJN-GP NLOG 0 - ENE_ LINE-L/PORT-E-L LINE-R/PORT-E-R MI-L/PORT-F-L MI-R/PORT-F-R ENE_ JREF 9 MONO-OUT 0 MI-L/PORT--L MI-R/PORT--R LINE-L/PORT--L LINE-R/PORT--R pilt by GN L_ENE_ LIN-L_PORT- LIN-R_PORT- MI-L_PORT- MI-R_PORT- L_ENE_ MI-L_PORT- MI-R_PORT- JREF LOE TO PIN9 U_GN 9 U0VKX-GP G R909 0KRF-L-GP U_GN 90 0UVMX-GP LOE TO PIN 9 LOE TO PIN 9 UVKX-GP UIP_P_EEP UIO_EEP R90 0KRF-L-GP 9 U0VKX-GP 9 U0VKX-GP 90 U0VKX-GP 99 U0VKX-GP R90 0KRF-L-GP OMO_MI_J# 9 U0VKX-GP 9 U0VKX-GP 9 U0VKX-GP 9 00P0VJN-GP 9 U0VKX-GP U_GN 9 0UVKX-GP Q90 N00K--GP.N0.J N =.N U0VKX-GP R90 9KRF-L-GP U_GN 0 - INT_MI_R U_MI_L U_MI_R U_HP_J# EXT_MI_J# U_MI_L U_MI_R 9 00P0VKX-GP 90 0UVMX-GP U_GN V_0 LOE TO PIN and P0VKX-GP INT_MI_R OMO_MI_R 9 00PVKX-GP P# 90 U0VKX-GP OMO_MI R90 0KRF--GP RN90 R90 KRJ--GP RN90 RNKJ--GP-U RN90 RNKJ--GP RNKJ--GP R99 0R00-P OMO_MI 90 0U0VKX-GP 0UVMX-GP U_GN 0-9 V_0 LOE TO PIN9 and 90 OMO_MI_Q U_GN INT_MI_L_R 9 MI_IN_L MI_IN_R K_EEP H_PKR MIV Ref voltage is.v becasue Vgs(th)concern cann't use N0 for desing 90 W--GP.000.Q nd =.000.K U_GN U_GN ate: Friday, pril 0, 0 heet 9 of MI_GN 0-90 U0VKX-GP 9 TVL GP MIV U_GN Q90 Max Vgs(th).V G OMO_MI_J# OMO_MI PM_LP_#,,, MP_MUTE# K_PWRTN#, Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. UIO OE(L) JE0_ ize ocument Number Rev R9 0RJ--GP 99 U0VKX-GP --GP R9 KRJ--GP R99 KRF-GP R9 0RJ--GP 9 U0VKX-GP 9 U0VKX-GP G90 GP-LOE G90 GP-LOE 90 --GP.000.K N =.000.F

30 (lanking) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MP ize ocument Number Rev JE0_ ate: Friday, pril 0, 0 heet 0 of 0

31 0 change to short pad V_ V_LN_ R0 0R00-P V_0 V_LN_,,,, PLT_RT# _T0/X_0/M_0 _T/X_/M T/X_/M T/X_/M T/X_/M T/X_/M T/X_/M T/X_/M_ 0 change to short pad L0 VL_G 0R00-P UVKX-GP E0 E0 E0 E0 U0VKX-GP U0VKX-GP L0 GK00T-0Y-GP.00.0 nd =.00. L0 0R00-P U0VKX-GP R 0R00-P UVKX-GP 9 U0VKX-GP V_LN_0 _T0/X_0/M_0 _T/X_/M T/X_/M T/X_/M_ U0VKX-GP U0VKX-GP U0VKX-GP PIE_RXP0 PIE_RXN0 PIE_TXP0 PIE_TXN0 V_LN_ V_LN_ GPHY_PLLV PIE_PLLV 0 UVKX-GP P0VJN-GP P0VJN--GP 9 UVKX-GP R 00RJ--GP 0 UVKX-GP V_LN_0 0 U0VKX-GP LN_XO_R X0 LN_XI V_LN_ U0VKX-GP U0VKX-GP,, PIE_WKE# PIE_LK_LN_REQ# R0 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R0 0R00-P XTL-MHZ-0-GP.000. N = R = U0VKX-GP U0VKX-GP LK_PIE_LN LK_PIE_LN# R KRJ--GP R LN_X0 00RF-L-GP VL_G VL_G VL_G GPHY_PLLV PIE_PLLV PIE_RXP0 PIE_RXN0 LN_RT M_R_T0 M_R_T M_R_T M_R_T M_R_T M_R_T M_R_T M_R_T VMINPRNT R KRJ--GP M_TET R KRJ--GP M_TET L=pF Freq tolertance:+/-0ppm 0 09 U0VKX-GP U0VKX-GP P0VJN--GP U0VKX-GP U0VKX-GP LN_R R9 KRF-GP 0 U0VKX-GP V V 9 VL VL VL 0 9 XTLO XTLI TET TET R V_LN_ 09- GPHY_PLLVL PIE_PLLVL 9 PIE_PLLVL PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N WKE# LK_REQ# PERT# PIE_REFLK_P 0 PIE_REFLK_N R_T0 R_T R_T R_T R_T R_T R_T R_T U0 VMIN_PRNT MX0KMLG-GP..M0 VO/VIO VO/VIO VO/VIO VO_R 0 GN 9 TR_N 9 TR_P 0 TR_N TR_P TR_N TR_P TR0_N TR0_P 0 LOW_PWR P00LE#_ERILO TRFFILE#_ERILI LK_P000LE# O_LINKLE# LN_V LN_V JE0-HR change to version P/N:..M0 I_EET #_EELK LOW_PWR M_GPIO0 M_000LE# LN_FLH_I/EET M_LINKLE# M_#/EELK V_LN_ LN MI Off-Page MI- 9 MI+ 9 MI- 9 MI+ 9 MI- 9 MI+ 9 0M/00M/G_LE# LN_T_LE# M /X_WE# M_X_# MI0-9 MI0+ 9 R0 0RJ--GP M_X_E#/M_IN#.R0.0 V_LN_ nd =.R.0E rd =.R0.0P L0 V_LN R IN-UH-9-GP V_LN_ 0 change to short padv_ln_ V_LN_ L0 IV_G 0R00-P U0VKX-GP R0 0 change to short pad KRJ--GP L0 LN_FLH_I/EET XTLV_G IV_G M_#/EELK IVH 0R00-P U0VKX-GP 0 change to short pad R0 KRJ--GP L0 XTLV_G LN_V XTLVH 0R00-P U0VKX-GP VH VH GPIO_LR_OUT GPIO_0 _ETET/X_WE# R_ILE/X_ETET# M_IN#/X_E# 9 R_LX R_VF R_VP R_V U0VKX-GP 0M/00M/G_LE# 9 LN_T_LE# 9 0 change to short pad TP0 R09 0M/00M/G_LE# 0R00-P R 0R00-P 0M/00M/G_LE# R 0R00-P R 0R00-P _/X_WE# X_# X_E#/M_IN# M_GPIO0 00- R M_GPIO0 0KRJ--GP LOW_PWR VO_R LOM JE0_ ate: Friday, pril 0, 0 heet of 0 V_LN_ R0 KRJ--GP 0 change to short pad for version M_X_RE# V_R_0 VO_R GPIO_/MEI_ENE/X_RE# 9 R 0R00-P X_RE# R R_WP#/X_WP# X_WP#/_WP# M_X_LE R 0RJ--GP R_LE/R_U_PWR/X_LE 0 0R00-P X_LE M_X_R/ R_LK/X_RY_Y# R 0R00-P _LK/X_R/# M_X_LE R_M/X_LE R 0R00-P _M/X_LE/M_ 09- E0 UVKX-GP U0VKX-GP R 0R00-P U0VKX-GP 0 0UVKX-GP U0VKX-GP UVKX-GP R 0R00-P X_LE 000 V.9 version can't use LO 09- Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev R0 KRJ--GP R0 KRJ--GP U0VKX-GP U0VKX-GP