Product Selection Guides

table of contents February 203 Zynq -7000 All Programmable SoCs... 2 7 Series FPGAs... 3 Virtex -6 FPGAs... 6 Spartan -6 FPGAs... 7 Virtex-5 FPGAs... 8 CPLD Products... 0 Configuration Storage Solutions... ISE Design Suite...3 Aerospace & Defense...4 Automotive... 23 Xilinx Boards and Kits... 28 Xilinx IP Cores, Reference Designs, and Instructor Led Training Courses... 3 Xilinx Productivity Advantage... 32

Zynq -7000 All Programmable SoCs Processing System Programmable Logic Speed Grades Packages Zynq -7000 All Programmable SoC Device Name Z-700 Z-7020 Z-7030 Z-7045 Part Number XC7Z00 XC7Z020 XC7Z030 XC7Z045 Processor Core Processor Extensions Maximum Frequency L Cache L2 Cache On-Chip Memory External Memory y Support () External Static Memory Support () DMA Channels Peripherals Peripherals w/ built-in DMA () Security (2) Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only) Xilinx 7 Series Programmable Logic Equivalent Programmable Logic Cells (Approximate ASIC Gates (3) ) Look-Up Tables (LUTs) Flip-Flops Extensible Block RAM (# 36 Kb Blocks) Programmable DSP Slices (8x25 MACCs) Peak DSP Performance (Symmetric( y FIR) ) PCI Express (Root Complex or Endpoint) Agile Mixed Signal (AMS) / XADC () Security (2) Commercial (0C to 85C) Extended (0C to 00C) Industrial (-40C to 00C) Artix -7 FPGA 35,200 80 00 GMACs 800 MHz Dual ARM Cortex -A9 MPCore with CoreSight NEON & Single / Double Precision Floating Point for each processor 32 KB Instruction, 32 KB Data per processor 52 KB 256 KB DDR3, DDR2, LPDDR2 2x Quad-SPI, NAND, NOR 8 (4 dedicated to Programmable Logic) 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO 2x AXI 32b Master, 2x AXI 32b Slave, 4x AXI 64b/32b Memory AXI 64b ACP 6 Interruptst t GHz 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO AES and SHA 256b Decryption and Authentication for Secure Boot Artix -7 FPGA 06,400 220 276 GMACs Kintex -7 FPGA 28K Logic Cells (~430K) 85K Logic Cells (~.3M) 25K Logic Cells (~.9M) 7,600 53,200 240 KB (60) 560 KB (40) 78,600 57,200,060 KB (265) 400 593 GMACs Kintex -7 FPGA 350K Logic Cells (~5.2M) 28,600 437,200 2,80 KB (545) 900,334 GMACs Package Type (4) CLG225 () CLG400 CLG400 CLG484 FBG484 FBG676 FFG676 FBG676 FFG676 FFG900 Size (mm) 3x3 7x7 7x7 9x9 23x23 27x27 27x27 27x27 27x27 3x3 Pitch (mm) 0.8 0.8 0.8 0.8.0.0.0.0.0.0 Processing System User I/Os (excludes DDR dedicated I/Os) (5) 32 54 54 54 54 54 54 54 54 54 Multi-Standards and Multi-Voltage SelectIO TM Interfaces (.2V,.35V,.5V,.8V, 2.5V, 3.3V) 54 00 25 200 00 00 00 00 00 22 Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces (.2V,.35V,.5V,.8V) 63 50 50 50 50 50 Gen2 x4 2x 2 bit, MSPS ADCs with up to 7 Differential Inputs AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration - -2, -3 -, -2 Gen2 x8 Serial Transceivers 4 4 4 8 8 6 Maximum Transceiver Speed (Speed Grade Dependant) N/A N/A N/A N/A 6.6 Gb/s 6.6 Gb/s 2.5 Gb/s 6.6 Gb/s 2.5 Gb/s 2.5 Gb/s XMP087 (v.6.) Notes:. Z-700 in CLG225 has restrictions on PS peripherals, Memory interfaces and I/Os. Please refer to the Technical Reference Manual for more details. 2. Security block is shared by the Processing System and the Programmable Logic. 3. Equivalent ASIC gate count is dependent of the function implemented. The assumption is Logic Cell = ~5 ASIC Gates. 4. Devices in the same package are pin-to-pin compatible. FBG676 and FFG676 are also pin-to-pin compatible. 5. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface. 6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information. 2

Virtex -7 fpgas Logic Resources Memory Resources Clocking I/O Resources Embedded IP Resources Speed Grades Footprint Compatible Footprint Compatible Footprint Compatible Footprint Compatible Package (5) Part Number EasyPath Cost Reduction Solutions () XC7V585T XC7V2000T XC7VX330T XC7VX45T XC7VX485T XC7VX550T XC7VX690T XC7VX980T XC7VX40T XC7VH580T XC7VH870T XCE7V585T XCE7V2000T XCE7VX330T XCE7VX45T XCE7VX485T XCE7VX550T XCE7VX690T XCE7VX980T XCE7VX40T 9,050 305,400 5,000 64,400 75,900 86,600 08,300 53,000 78,000 90,700 36,900 582,720,954,560 326,400 42,60 485,760 554,240 693,20 979,200,39,200 580,480 876,60 728,400 2,443,200 408,000 55,200 607,200 692,800 866,400,224,000,424,000 725,600,095,200 6,938 2,550 4,388 6,525 8,75 8,725 0,888 3,838 7,700 8,850 3,275 795,292 750 880,030,80,470,500,880 940,40 28,620 46,52 27,000 3,680 37,080 42,480 52,920 54,000 67,680 33,840 50,760 8 24 4 2 4 20 850,200 700 600 700 600,000 900,00 600 650 408 576 336 288 336 288 480 432 528 288 32,260 2,60,20 2,60 2,800 2,880 3,600 3,600 3,360,680 2,520 3 4 4 2 2 2 3 3 4 2 3 36 36 56 28 48 80 80 72 96 48 72 GTZ 28.05 Gb/s Transceivers 8 6 Area Slices Logic Cells CLB Flip-Flops Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each) Total Block RAM (Kb) CMTs ( MMCM + PLL) Maximum Single-Ended I/O Maximum Differential I/O Pairs DSP48E Slices PCI Express Gen2 PCI Express Gen3 Agile Mixed Signal (AMS) / XADC Configuration AES / HMAC Blocks GTX 2.5 Gb/s Transceivers (2) GTH 3. Gb/s Transceivers (3) Commercial Extended (4) Industrial Flip chip, fine pitch BGA (.0 mm ball spacing) -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2-2L, -3-2L, -2G -2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L -2L, -2G -2L, -2G -2L, -2G -, -2 - -, -2 -, -2 -, -2 -, -2 -, -2 - - FFG57 35 x 35 mm 0, 600 (20, 0) 0, 600 (0, 20) 0, 600 (0, 20) 0, 600 (20, 0) 0, 600 (0, 20) FFG76 42.5 x 42.5 mm 00, 750 (36, 0) 50, 650 (0, 28) 0, 700 (28, 0) 0, 850 (0, 36) FHG76 45 x 45 mm 0, 850 (36, 0) FLG925 FFG58 45 x 45 mm 35 x 35 mm Virtex-7 FPGAs Optimized for Highest System Performance and Capacity (.0V, 0.9V) (.0V, 0.9V) 0, 200 (6, 0) Available User I/O: 3.3V SelectI/O TM Pins,.8V SelectI/O Pins (GTX, GTH Transceivers) 0, 350 (0, 48) 0, 350 (48, 0) 0, 350 (0, 48) 20 0, 350 (0, 48) FFG926 45 x 45 mm 0, 720 (0, 64) 0, 720 (0, 64) FLG926 45 x 45 mm 0, 720 (0, 64) 8 24 (.0V) 2 8.8V SelectIO Pins (GTH, GTZ) FFG927 45 x 45 mm 0, 600 (0, 48) 0, 600 (56, 0) 0, 600 (0, 80) 0, 600 (0, 80) FFG928 45 x 45 mm 0, 480 (0, 72) FLG928 45 x 45 mm 0, 480 (0, 96) FFG930 45 x 45 mm 0, 700 (24, 0) 0, 000 (0, 24) 0, 900 (0, 24) FLG930 45 x 45 mm 0, 00 (0, 24) Ceramic flip chip, fine pitch BGA (.0 mm ball spacing) HCG55 35 x 35 mm 400 (24, 8) HCG93 45 x 45 mm 600 (48, 8) 650 (48, 8) HCG932 45 x 45 mm 300 (48, 8) 300 (72, 6) XMP084 (v4.6) Notes:. EasyPath solutions provide a fast and conversion-free path for cost reduction. 2. 2.5 Gb/s support in "-3E", "-2GE" speed/temperature grade; 0.325 Gb/s support in "2C", "-2LE", and "-2I" speed grade. 3. 3. Gb/s support in "-3E". "-2GE" speed grade;.3 Gb/s support in "2C", "-2LE" and "-2I" speed/temperature grades. 4. -2G only applies to Stacked Silicon Interconnect devices and supports 2.5G GTX, 3.G GTH, 28.05G GTZ with -2 fabric. 5. Leaded package options ("FFxxxx"/"FLxxxx"/"FHxxxx"/"HCxxxx") available for all packages. 3

Kintex -7 fpgas Kintex-7 FPGAs Optimized for Best Price-Performance (.0V, 0.9V) Part Number XC7K70T XC7K60T XC7K325T XC7K355T XC7K40T XC7K420T XC7K480T EasyPath Cost Reduction Solutions () XCE7K355T XCE7K40T XCE7K420T XCE7K480T Slices 0,250 25,350 50,950 55,650 63,550 65,50 74,650 Logic Resources Logic Cells CLB Flip-Flops 65,600 62,240 326,080 356,60 406,720 46,960 477,760 82,000 202,800 407,600 445,200 508,400 52,200 597,200 Memory Resources Maximum Distributed RAM (Kbits) Block RAM/FIFO w/ ECC (36Kbits each) Total Block RAM (Kbits) 838 35 4,860 2,88 325,700 4,000 445 6,020 5,088 75 25,740 5,663 795 28,620 5,938 835 30,060 6,788 955 34,380 Clock Resources CMTs ( MMCM + PLL) 6 8 0 6 0 8 8 I/O Resources Maximum Single-Ended I/O Maximum Differential I/O Pairs 300 44 400 92 500 240 300 44 500 240 400 92 400 92 DSP48E Slices 240 600 840,440,540,680,920 Embedded Hard IP Resources PCI Express (2) Agile Mixed Signal (AMS) / XADC Configuration AES / HMAC Blocks GTX 2.5 Gb/s Transceivers 8 8 6 24 6 32 32 Commercial -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 Speed Grades Extended -2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 Industrial -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 Package (4) Dimensions (mm) Available User I/O: 3.3V SelectIO TM Pins,.8V SelectIO Pins (GTX Transceivers) FBG484 23 x 23 85, 00 (4) 85, 00 (4) Footprint Compatible FBG676 FFG676 27 x 27 27 x 27 200, 00 (8) 250, 50 (8) 250, 50 (8) 250, 50 (8) 250, 50 (8) 250, 50 (8) 250, 50 (8) Footprint Compatible FBG900 3 x 3 350, 50 (6) 350, 50 (6) FFG900 3 x 3 350, 50 (6) 350, 50 (6) FFG90 3 x 3 300, 0 (24) 380, 0 (28) 380, 0 (28) FFG56 35 x 35 400, 0 (32) 400, 0 (32) FBG.0mm Lidless flip-chip; FFG:.0mm Flip-chip fine-pitch XMP085 (v3.5) Notes:. EasyPath solutions provide a fast and conversion-free path for cost reduction. 2. Hard block supports PCI Express Base 2. specification at Gen and Gen2 data rates. Gen3 supported with soft IP. 3. Leaded package options ("FBxxx" or "FFxxx") available for the following Kintex-7 devices: XC7K60T, XC7K325T, XC7K355T, XC7K40T, XC7K420T, XC7K480T 4. Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information. 4

Artix -7 fpgas Logic Resources Memory Resources Clock Resources CMTs ( MMCM + PLL) 3 3 4 4 3 3 4 4 6 0 Maximum Single-Ended I/O 26 26 300 300 26 26 300 300 300 500 I/O Resources Maximum Differential I/O Pairs 54 54 72 72 54 54 72 72 44 240 Embedded Hard IP Resources Speed Grades Footprint Compatible Footprint Compatible (2), (3) Package Dimensions CPG236 CSG325 CSG484 Artix -7 FPGAs Optimized for Lowest Cost and Lowest Power Applications (.0V, 0.9V) Artix-7 SL FPGAs Artix-7 SLT FPGAs Artix-7 T FPGAs Advance Advance Part Number XC7A20SL XC7A35SL XC7A50SL XC7A75SL XC7A20SLT XC7A35SLT XC7A50SLT XC7A75SLT XC7A00T XC7A200T Slices 2,500 5,42 8,200,94 2,500 5,42 8,200,94 5,850 33,650 Logic Cells 6,000 32,909 52,480 7,642 6,000 32,909 52,480 7,642 0,440 25,360 CLB Flip-Flops 20,000 4,36 65,600 89,552 20,000 4,36 65,600 89,552 26,800 269,200 Maximum Distributed RAM (Kbits) 208 453 688 974 208 453 688 974,88 2,888 Block RAM/FIFO w/ ECC (36Kbits each) 30 65 95 25 30 65 95 25 35 365 Total Block RAM (Kbits),080 2,340 3,420 4,500,080 2,340 3,420 4,500 4,860 3,40 (mm) 0 x 0 DSP48E Slices PCI Express () Agile Mixed Signal (AMS) / XADC Configuration AES / HMAC Blocks GTP Transceivers (6.6 Gb/s Max Rate) 5 x 5 9 x 9 Commercial Extended Industrial 60 20 80 240 60 4 4 8 8 8 6 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 -, -2 48, 52 08, 08 48, 52 08, 08 Available User I/O: 3.3V SelectI/O HR I/O, 3.3V SelectI/O HD I/O Pins (GTP Transceivers) 44, 56 44, 56 CPG237 0 x 0 48, 52 () 48, 52 () CSG326 5 x 5 08, 77 (4) 08, 77 (4) 08, 77 (4) 08, 77 (4) CSG485 9 x 9 08, 08 (4) 08, 08 (4) 26, 08 (6) 26, 08 (6) FGG677 27 x 27 44, 56 (8) 44, 56 (8) CSG324 5 x 5 20 (0) FTG256 7 x 7 70 (0) 20 80 240 240 740 Available User I/O: 3.3V SelectI/O HR I/O Pins (GTP Transceivers) SBG484 9 x 9 285 (4) FGG484 23 x 23 285 (4) FBG484 23 x 23 285 (4) FGG676 27 x 27 300 (8) FBG676 27 x 27 400 (8) FFG56 35 x 35 500 (6) XMP086 (v4.2) CPG: 0.5mm Wire-bond chip-scale; CSG: 0.8mm Wire-bond chip-scale; FTG:.0mm Wire-bond fine-pitch; SBG: 0.8mm Lidless flip-chip; FGG:.0mm Wire-bond fine-pitch; FBG.0mm Lidless flip-chip; FFG:.0mm Flip-chip fine-pitch Notes:. Supports PCI Express Base 2. specification at Gen and Gen2 data rates. 2. Leaded package option available for all packages. 3. Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families. 5

Virtex -6 fpgas 6

SPARTAN -6 fpgas 7

Virtex -5 fpgas 8

Virtex -5 fpgas 9

CPLD PRODUCTS 0

CONFIGURATION SOLUTIONS

CONFIGURATION SOLUTIONS 2

DESIGN TOOLS ISE DESIGN SUITE ISE Design Suite Device Support ISE WebPACK Tool ISE Design Suite Logic Edition Embedded Edition DSP Edition System Edition ISE Design Suite Comparison Table ISE WebPACK Tool (Device Limited) Logic Edition Embedded Edition DSP Edition System Edition Virtex FPGAs Kintex FPGAs Artix FPGAs Virtex-4 FPGAs Virtex-4 FPGAs ISE Foundation Tools with ISE Simulator (ISim) LX: XC4VLX5, XC4VLX25 LX: All PlanAhead Design Analysis Tool SX: XC4VSX25 SX: All ChipScope Pro Logic Analyzer FX: XC4VFX2 FX: All ChipScope Pro Serial I/O Toolkit Embedded Development Kit (EDK) * * * Virtex-5 FPGAs Virtex-5 FPGAs Software Development Kit (SDK) LX: XC5VLX30, XC5VLX50 LX: All System Generator for DSP LXT: XC5VLX20T - XC5VLX50T LXT: All * Device Limited to Zynq-7000 EPP Z700, Z7020, Z7030 devices only FXT: XC5VFX30T SXT: All Virtex-6 FPGAs XCLX75T Virtex-7 FPGAs None FXT: All Virtex-6 FPGAs All Virtex-7 FPGAs All Kintex-7 FPGAs Kintex-7 FPGAs XC7K70T, XC7K60T All Artix-7 FPGAs: XC7A00T, XC7A200T Artix-7 FPGAs: All Targeted Stand-Alone Products Software Development Kit (SDK) ChipScope Pro and ChipScope Pro Serial I/O Toolkit Embedded Development Kit (EDK) System Generator for DSP Usage Embedded software developers who do not require ISE tools Lab Environments ISE WebPACK Tool Users Zynq Extensible Zynq-7000 EPP: Processing Platform XC7Z00, XC7Z020, XC7Z030 Zynq-7000 EPP: All Spartan FPGAs Spartan-3 FPGAs XC3S50 - XC3S500 Spartan-3A FPGAs All Spartan-3AN FPGAs All Spartan-3A DSP FPGAs XC3SD800A Spartan-3E FPGAs All Spartan-6 FPGAs XC6SLX4 - XC6SLX75T XA (Xilinx Automotive) Spartan-3 FPGAs All XA (Xilinx Automotive) Spartan-6 FPGAs All Spartan-3 FPGAs: All Spartan-3A FPGAs: All Spartan-3AN FPGAs: All Spartan-3 DSP FPGAs: All Spartan-3E FPGAs: All Spartan-6 FPGAs: All XA (Xilinx Automotive) ISE Design Suite Operating System Support ISE Design Entry and Implementation Tools ISE Simulator (ISim) CoolRunner XPLA3 CoolRunner-II CPLDs All ISE WebPACK ChipScope Pro and ChipScope Pro Serial I/O Toolkit Embedded Development Kit (EDK) and Platform Studio XC9500 Series All (Except 9500XV Family) Software Development Kit (SDK) System Generator for DSP XMP075 (v3.0) -Bit* ows XP Professional 32/64- Windo it* ows 7 Professional 32/64-B Windo ows Server 2008 Windo 2/64-bit 2/65-bit Red H Hat Enterprise Linux 5 WS3 Red H Hat Enterprise Linux 6 WS3 -bit Linux Enterprise 32/64 SUSE *US and Japanese: Full Support. Chinese: Limited Support. 3

Zynq -7000Q All Programmable SoCs Processing System Programmable Logic Zynq -7000Q All Programmable SoC Device Name Z-7020 Z-7030 Z-7045 Part Number XQ7Z020 XQ7Z030 XQ7Z045 Processor Core Processor Extensions Maximum Frequency L Cache L2 Cache On-Chip Memory External Memory Support Dual ARM Cortex -A9 MPCore with CoreSight NEON & Single / Double Precision Floating Point for each processor 733 MHz 32 KB Instruction, 32 KB Data per processor 52 KB 256 KB DDR3, DDR2, LPDDR2 External Static Memory Support 2x Quad-SPI, NAND, NOR DMA Channels 8 (4 dedicated to Programmable Logic) Peripherals 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Peripherals w/ Built-in DMA 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO Security () AES and SHA 256b Decryption and Authentication for Secure Boot Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only) 2x AXI 32b Master, 2x AXI 32b Slave, 4x AXI 64b/32b Memory AXI 64b ACP 6 Interrupts Kintex -7Q FPGA 25K Logic Cells (~.9M) 78,600 57,200,060 KB (265) 400 x4 Gen2 2x 2 bit, MSPS ADCs with up to 7 Differential Inputs Xilinx 7 Series Programmable Logic Equivalent Artix -7Q FPGA Kintex -7Q FPGA Programmable Logic Cells (Approximate ASIC Gates (2) ) 85K Logic Cells (~.3M) 350K Logic Cells (~5.2M) Look-Up Tables (LUTs) 53,200 28,600 Flip-Flops 06,400 437,200 Extensible Block RAM (36 Kb Blocks) 560 KB (40) 2,80 KB (545) Programmable DSP Slices (8x25 MACCs) 220 900 PCI Express (Root Complex or Endpoint) x8 Gen2 Analog Mixed Signal (AMS) / XADC Security () AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration Speed Grades Packages Q-Temp ( 40 C to 25 C) Industrial ( 40 C to 00 C) Package Type (3) CL400 CL484 - -, -2 RB484 (5) RF676 RF676 Size (mm) 7x7 9x9 23x23 27x27 27x27 Pitch (mm) 0.8 0.8.0.0.0 Processing System User I/Os (excludes DDR dedicated I/Os) (4) 54 54 54 54 54 Multi-Standards and Multi-Voltage SelectIO TM Interfaces (.2V,.35V,.5V,.8V, 2.5V, 3.3V) 25 200 00 00 00 Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces (.2V,.35V,.5V,.8V) 63 50 50 Serial Transceivers 4 4 8 Maximum Transceiver Speed (Speed Grade Dependent) N/A N/A 6.6 Gb/s 0.325 Gb/s 0.325 Gb/s XMP092 (v.0) Notes:. Security block is shared by the Processing System and the Programmable Logic. 2. Equivalent ASIC gate count is dependent of the function implemented. The assumption is Logic Cell = ~5 ASIC Gates. 3. Devices in the same package are pin-to-pin compatible. 4. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface. 5. RB484 is a ruggedized version of FB484 (4-corner lid added). 6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information. 4

Virtex -7Q T Defense-Grade fpgas Virtex-7Q T FPGAs Part Number XQ7V585T XQ7VX330T XQ7VX485T XQ7VX690T XQ7VX980T Logic Resources Memory Resources Clock Resources I/O Resources Embedded Hard IP Resources Speed Grades Slices () Logic Cells (2) CLB Flip-Flops Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each) Total Block RAM (Kb) Mixed Mode Clock Managers (MMCM) Maximum Single-Ended I/O (3) Maximum Differential I/O Pairs DSP48E Slices PCI Express Gen 2 Interface Blocks PCI Express Gen 3 Interface Blocks Analog Front End (XADC) / SysMon Blocks Package Dimensions (mm) RF57 Configuration AES / HMAC Blocks GTX 0.325 Gb/s Transceivers (4) GTH.3 Gb/s Transceivers (5) Extended Temp (0 to +00 C) Industrial Temp ( 40 to +00 C) Military Temp ( 55 to +25 C) 35 x 35 9,050 5,000 75,900 08,300 53,000 582,720 326,400 485,760 693,20 979,200 728,400 408,000 607,200 866,400,224,000 6,938 4,388 8,75 0,888 3,838 795 750,030 28,620 27,000 37,080 52,920 54,000 8 850 408 4 700 336 4 700 336,260,20 2,800 3,600 3,600 3 36-2L -, -2-0, 600 (20, 0) 2 28-2L -, -2-0, 600 (0, 20) 4 28-2L -, -2 -,470 20,000 480 3 36 -, -2 0, 600 (0, 20) RF76 42.5 x 42.5 00, 750 (36, 0) 50, 650 (0,28) 0, 700 (28,0) 0, 850 (0,36) RF930 45 x 45 0, 700 (24,0) 0, 000(0,24) 0,900 (0,24) XMP09 (v.0) Notes:. A single Virtex-7 FPGA CLB comprises two slices, with each containing four 6-input LUTs and eight Flip-Flops, for a total of eight 6-LUTs and 6 Flip-Flops per CLB. 2. Virtex-7 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture. 3. Refer to data sheet for details on I/O standards support. 4. 0.325 Gb/s support in -2 speed grade. 5..3 Gb/s support in -2 speed grade. 6. This is preliminary product information, subject to change. Please contact A&D Marketing for the latest information. Available User I/O: 3.3V SelectIO Pins,.8V SelectIO Pins (GTX, GTH Transceivers),500 8 900 432 3 24-2L - 5

Kintex -7Q T Defense-Grade fpgas Kintex-7Q T FPGAs Part Number XQ7K325T XQ7K40T Slices 50,950 63,550 Logic Resources Logic Cells 326,080 406,720 CLB Flip-Flops 407,600 508,400 Maximum Distributed RAM (Kb) 4,000 5,663 Memory Block RAM/FIFO w/ ECC (36 Kb each) 445 795 Resources Total Block RAM (Kb) 6,020 28,620 Clock Resources Mixed Mode Clock Managers (MMCM) 0 0 I/O Resources Maximum Single-Ended I/O 500 500 Maximum Differential I/O Pairs 240 240 DSP48E Slices 840,540 Embedded PCI Express () Hard IP Analog Front End (XADC) / SysMon Blocks Resources Configuration AES / HMAC Blocks GTX 0.325 Gb/s Transceivers 6 6 Extended Temp (0 to +00 C) -2L -2L Speed Grades Industrial Temp ( 40 to +00 C) -, -2 -, -2 Military Temp ( 55 to +25 C) - - Package RF676 RF900 Dimensions (mm) 27 x 27 3 x 3 250, 50 (8) 350, 50 (6) Notes:. Supports PCI Express Base 2. specification at Gen and Gen2 data rates. 2. This is preliminary product information, subject to change. Please contact A&D Marketing for the latest information. Available User I/O: 3.3V SelectIO Pins,.8V SelectIO Pins (GTX Transceivers) 250, 50 (8) 350, 50 (6) XMP090 (v.0) 6

Artix -7Q T Defense-Grade fpgas Artix-7Q T FPGAs Part Number XQ7A00T XQ7A200T Slices 5,850 33,650 Logic Resources Logic Cells 0,440 25,360 CLB Flip-Flops 26,800 269,200 Maximum Distributed RAM (Kb),88 2,888 Memory Block RAM/FIFO w/ ECC (36 Kb each) 35 365 Resources Total Block RAM (Kb) 4,860 3,40 Clock Resources Mixed Mode Clock Managers (MMCM) 6 0 I/O Resources Maximum Single-Ended I/O 285 400 Maximum Differential I/O Pairs 37 92 DSP48E Slices 240 740 Embedded PCI Express () Hard IP Analog Front End (XADC) / SysMon Blocks Resources Configuration AES / HMAC Blocks GTP 5.4/ 6.6 Gb/s Transceivers 4 8 Speed Grades Industrial Temp ( 40 to 00 C) -, -2 -, -2 Military Temp ( 55 to 25 C) - - Package (2) Dimensions (mm) Available User I/O: 3.3V SelectIO Pins (GTP Transceivers) Notes: CS324 FG484 5 x 5 23 x 23 20 (0) 285 (4) RB484 (3) 23 x 23 285 (4) RB676 (3) 27 x 27 400 (8) RS484 (4) 9 x 9 285 (4). Supports PCI Express Base 2. specification at Gen and Gen2 data rates. 2. Design migration is available within the Artix-7Q family for like packages, but is not supported between other 7 Series families. (CS: 0.8 mm wire-bond chip-scale. FG:.0 mm wire-bond fine-pitch.) 3. RB484 & RB676 are ruggedized versions (4-corner lid added) of FB484 and FB676 packages. (FB:.0 mm flip-chip bare-die.) 4. RS484 is a ruggedized version (4-corner lid added) of SB484 package. Feasibility of this lid is in process. (SB: 0.8 mm flip-chip bare-die.) 5. This is preliminary product information, subject to change. Please contact A&D Marketing for the latest information. XMP089 (v.0) 7

Spartan -6Q Defense-Grade fpgas 8

Virtex -5Q Defense-Grade fpgas 9

Virtex -4Q, VIRTEX-II PRO XQ, and VIRTEX-II XQ Defense-Grade fpgas 20

Virtex -5QV, VIRTEX-4QV, VIRTEX-IIXQR, And VIRTEX-XQR Defense-Grade fpgas 2

XILINX AEROSPACE and DEFENSE SOLUTIONS 22

XA Zynq -7000 All Programmable SoCs Processing System Device Name Part Number Processor Core Processor Extensions Maximum Frequency L Cache L2 Cache On-Chip Memory External Memory Support () External Static Memory Support () DMA Channels Peripherals Peripherals w/ built-in DMA () Security (2) Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only) Xilinx 7 Series Programmable Logic Equivalent Programmable Logic Cells (Approximate ASIC Gates (3) ) Look-Up Tables (LUTs) Flip-FlopsFlops XA Zynq -7000 All Programmable SoC Z-700 Z-7020 XA7Z00 Dual ARM Cortex -A9 MPCore with CoreSight NEON & Single / Double Precision Floating Point for each processor 667 MHz 32 KB Instruction, 32 KB Data per processor 52 KB 256 KB DDR3, DDR2, LPDDR2 2x Quad-SPI, NAND, NOR 8 (4 dedicated to Programmable Logic) 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO AES and SHA 256b Decryption y and Authentication for Secure Boot Artix -7 FPGA 28K Logic Cells (~430K) 7,600 2x AXI 32b Master, 2x AXI 32b Slave, 4x AXI 64b/32b Memory AXI 64b ACP 6 Interrupts XA7Z020 Artix -7 FPGA 85K Logic Cells (~.3M) 53,200 35,200 06,400 Programmable Logic Extensible Block RAM (# 36 Kb Blocks) 240 KB (60) 560 KB (40) Speed Grades Packages Programmable DSP Slices (8x25 MACCs) Peak DSP Performance (Symmetric FIR) Agile Mixed Signal (AMS) / XADC () Security (2) Industrial (-40C to 00C) Automotive (-40C to 25C) 80 74 GMACs 2x 2 bit, MSPS ADCs with up to 7 Differential Inputs AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration - 220 204 GMACs Package Type (4) CLG225 () CLG400 CLG400 CLG484 Size (mm) Pitch (mm) 3x3 0.8 Processing System User I/Os (excludes DDR dedicated I/Os) (5) 32 54 54 54 Multi-Standards and Multi-Voltage SelectIO TM Interfaces (.2V,.35V,.5V,.8V, 2.5V, 3.3V) Notes:. Z-700 in CLG225 has restrictions on PS peripherals, Memory interfaces, and I/Os. Please refer to the Technical Reference Manual for more details. 54 2. Security block is shared by the Processing System and the Programmable Logic. 3. Equivalent ASIC gate count is dependent of the function implemented. The assumption is Logic Cell = ~5 ASIC Gates. 4. Devices in the same package are pin-to-pin compatible. 5. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface. 6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information. 7x7 0.8 00-7x7 0.8 25 9x9 0.8 200 XMP088 (v.0) 23

SPARTAN -6 LX and LXT fpgas 24

SPARTAN -3 and SPARTAN-3E fpgas 25

SPARTAN -3A and SPARTAN-3A DSP fpgas 26

XA9500XL and COOLRUNNER -II FAMILIES 27

XILINX BOARDS AND KITS 28

XILINX IP CORES, REFERENCE DESIGNS, AND INSTRUCTOR LED TRAINING COURSES 3

XI LI NX PRODUCTIVITY ADVANTAG E 32

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