25 6 Vol. 25 No. 6 2013 12 Journal of Chongqing University of Posts and Telecommunications Natural Science Edition Dec. 2013 DOI 10. 3979 /j. issn. 1673-825X. 2013. 06. 016 LDPC FPGA 1 2 2 2 1. 400065 2. 361005 low density parity check LDPC 2 LDPC TDMP turbo decoding message passing Min - Sum 183. 9 MHz 63. 3 Mbit /s LDPC LDPC TN47 A 1673-825X 2013 06-0788-07 Protograph-based LDPC decoder applied to magnetic recording channel ZHOU Jian 1 LV Yibo 2 HONG Shaohua 2 WANG Lin 2 1. Key Lab of Mobile Communication in Chongqing CQUPT Chongqing 400065 P. R. China 2. School of Information Science and Engineering Xiamen University Fujian 361005 P. R. China Abstract Using random expansion algorithm the hardware implementation of conventional protograph-based LDPC low density parity check decoders has difficulty with wiring and data transmission which results in the improvement of resource consumption and decrease in throughput. In this paper an easy-hardware-implementation quasi cyclic protographbased LDPC code is obtained by the use of a two-step lifting procedure and we also propose a protograph-based LDPC decoder for magnetic recording channels. Utilizing the normalized Min-Sum algorithm based on the TDMP Turbo decoding message passing layered decoding scheme the proposed decoder has a partially parallel architecture. Moreover an early termination strategy is also proposed to reduce the latency and power consumption of the decoder. The proposed LDPC decoder is evaluated on a Xilinx Spartan 6 FPGA field programmable gate array platform and the results indicate that the proposed decoder requires low resource and can be utilized for multiple protograph-based LDPC codes. Key words magnetic recording channel protograph-based LDPC code quasi cyclic expansion early termination strategy low resource consumption 0 low density parity check LD- PC 1 2 LDPC LDPC 3 additive white Gaussian Turbo noise AWGN LDPC AWGN 2013-06-07 2013-10-23 909032790@ qq. com 61271241 Foundation Item The National Natural Science Foundation of China 61271241
6 LDPC FPGA 789 PR AR3A LDPC 2 IARA1 AR3A AR4JA 2 LDPC 2 LDPC 2 B IA1 4 1 IARA2 B IA2 LDPC 1 2 1 0 0 B IA1 = 0 2 1 1 1 0 1 2 1 1 PR partial response PR 4 B IA1 AR3A IARA1 5 2 1 2 1 0 0 B IA2 = 0 1 1 2 1 4 0 1 2 1 1 LDPC 2 1. 2 LDPC PEG progressive edge growth LDPC 5 2 1 183. 9 MHz 63. 3 Mbit /s LDPC 5 pre-lifting 1 LDPC 5-6 2 Tanner PEG 7 4 12 20 B 2 1 B LDPC LDPC 2 N N LDPC 1 2 0 1. 1 PR LDPC lifting PEG PR 2 AWGN AR4JA AR3A PR PR H 4AR3A IARA2 N 128 2 H 1 1 1 AWGN puncturing PR 2
790 25 2 2 PEG 2 560 1 /2 512 BPSK binary phase shift keying Min-Sum 4 extended class IV PR channel EPR4 2 2 0 1 k t TDMP turbo variable-to-check VTC decoding message passing 8 L k t = S k t -1 k -1 - R t 1 1 2 H 0. 812 5 = 1 /2 + 1 /4 + 1 /16 Fig. 1 Parity check matrix H after two steps quasi cyclic expansion 3 2 TDMP H Fig. 2 Performance comparison between random expansion and quasi cyclic expansion 1. 3 TDMP TDMP 1 2 H N 32 H 48 2 memory TDMP IARA2 vc v cv 1 S v a posteriori probability APP R cv check-to-varible CTV 2 k t R k t cv = α n N c \v sgn L k t nc min n N c \v L k t 2 2 α Min- Sum α S k t v = L k t + R k t vc cv nc 3 4 1-3 3 H 2 TDMP FPGA 1
6 LDPC FPGA 791 4 PR H ROM TDMP ROM 2 RAM 2 H 32 RAM 16 4 32 5 4 5 RAM SISO 3 central RAM controller input 2. 2 RAM 6 bit 1-3 8 bit Min-Sum address generator network CTV 2 recovery SISO RAM CTV H 4 5 8 bit CTV 22 bit early termination checking 5 bit 7 bit 3 bit output Fig. 3 3 Overall architecture of decoder 2. 1 41. 07% CTV RAM CTV SISO RAM 2 2. 3 4 SISO 1-3 32 SISO SISO 3 4 4 SISO 4 4 PEG 2 ROM H ROM 1 1 1 RAM CTV ROM VTC 2
792 25 4 5 3 CTV CTV VTC 2 CTV 4 Recovery RAM 4 Fig. 4 4 4 stages pipeline architecture of SISO 5 4 Fig. 5 Inside architecture of 4 inputs comparator 32 2. 4 32 Turbo LDPC PR Turbo 9-10 H H C T = 0 LDPC 80% H Turbo
6 LDPC FPGA 793 7 AR3A IARA1 IARA2 PR FPGA 3 7 PR BER IARA2 IARA1 AR3A 4 9-10 3 FPGA Xilinx Spartan6 XC6SLX150 Verilog ISE11. 4 ModelSim6. 5 SE 1 /2 2 560 LDPC 3. 1 BER PR Turbo PC C 7 IARA1 IARA2 AR3A PCI7300A PC FPGA Fig. 7 Performance comparison between IARA1 code IARA2 code and AR3A code 6 IARA2 PR FPGA BER 3. 2 Turbo 8 FPGA 15 6 bit 183. 9 MHz 352 8 bit 6 8 160 11 183. 9 1024 352 8 + 160 63. 3Mbit /s 4 4 1 024 1 12-13 14 6 Fig. 6 Performance comparison between floating point simulation and fixed point simulation
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