ΗΜΥ 408 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Εαρινό Εξάµηνο 2016 ΔΙΑΛΕΞΗ 2: Technology and Historical Progress of FPGAs ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Επίκουρος Καθηγητής ΗΜΜΥ (ttheocharides@ucy.ac.cy) Some slides adopted from Digital Integrated Circuits, Rabbey et. al.
p-n Junctions q A junction between p-type and n-type semiconductor forms a diode. q Current flows only in one direction p-type n-type anode cathode ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.2 Θεοχαρίδης, ΗΜΥ, 2016
The MOS Transistor Polysilicon Aluminum ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.3 Θεοχαρίδης, ΗΜΥ, 2016
nmos Transistor q Four terminals: gate, source, drain, body q Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal Source Gate Drain Polysilicon SiO 2 n+ n+ p bulk Si ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.4 Θεοχαρίδης, ΗΜΥ, 2016
nmos Operation q Body is commonly tied to ground (0 V) q When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 0 D ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.5 Θεοχαρίδης, ΗΜΥ, 2016
nmos Operation q When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S 1 D ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.6 Θεοχαρίδης, ΗΜΥ, 2016
pmos Transistor q Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Polysilicon Source Gate Drain SiO 2 p+ p+ n bulk Si ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.7 Θεοχαρίδης, ΗΜΥ, 2016
Power Supply Voltage q GND = 0 V q In 1980 s, V DD = 5V q V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power q V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, (0.5 is typical today!) ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.8 Θεοχαρίδης, ΗΜΥ, 2016
Transistors as Switches q We can view MOS transistors as electrically controlled switches q Voltage at gate controls path from source to drain g = 0 g = 1 nmos g d s d s OFF d s ON pmos g d s d s ON d s OFF ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.9 Θεοχαρίδης, ΗΜΥ, 2016
CMOS Inverter A 0 1 Y V DD A Y A Y GND ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.10 Θεοχαρίδης, ΗΜΥ, 2016
CMOS Inverter A Y 0 1 0 A Y V DD OFF A=1 Y=0 ON GND ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.11 Θεοχαρίδης, ΗΜΥ, 2016
CMOS Inverter A Y 0 1 1 0 A Y V DD ON A=0 Y=1 OFF GND ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.12 Θεοχαρίδης, ΗΜΥ, 2016
CMOS Inverter N Well The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.13 Θεοχαρίδης, ΗΜΥ, 2016
CMOS Process ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.14 Θεοχαρίδης, ΗΜΥ, 2016
A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ Dual-Well Trench-Isolated CMOS Process ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.15 Θεοχαρίδης, ΗΜΥ, 2016
Circuit Under Design V DD V DD M2 M4 V in V out V out2 M1 M3 ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.16 Θεοχαρίδης, ΗΜΥ, 2016
Its Layout View ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.17 Θεοχαρίδης, ΗΜΥ, 2016
Advanced Metallization ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.18 Θεοχαρίδης, ΗΜΥ, 2016
Advanced Metallization ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.19 Θεοχαρίδης, ΗΜΥ, 2016
3D Perspective Polysilicon Aluminum ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.20 Θεοχαρίδης, ΗΜΥ, 2016
Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.21 Θεοχαρίδης, ΗΜΥ, 2016
Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Die Lead frame Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. Polymer film ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.22 Θεοχαρίδης, ΗΜΥ, 2016
Package Types ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.23 Θεοχαρίδης, ΗΜΥ, 2016
Multi-Chip Modules ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.24 Θεοχαρίδης, ΗΜΥ, 2016
History of Computing Devices Source: MIT Digital Logic Course Xilinx Education webpage ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.25 Θεοχαρίδης, ΗΜΥ, 2016
Design Spectrum Source: RUSSELL TESSIER AND WAYNE BURLESON Reconfigurable Computing for Digital Signal Processing: A Survey, JVLSISP, 2001 ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.26 Θεοχαρίδης, ΗΜΥ, 2016
Design Alternatives q Decreasing performance; Increasing flexibility ASIC Application Specific Integrated Circuits - Custom Design - Cell Based Design Mask Programmable Gate Arrays Structured ASICs FPGA/FPLD ASIC type Custom mask layers Custom logic cells Full-custom All Some Semicustom/Cell-based All None MPGA Some None Structured ASIC Some None FPGA None None Further Reading: Online Textbook ASICs by Smith - Chapter 1 ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.27 Θεοχαρίδης, ΗΜΥ, 2016
Disadvantage of ASICs ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.28 Θεοχαρίδης, ΗΜΥ, 2016
FPGA vs ASIC Source: Xilinx ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.29 Θεοχαρίδης, ΗΜΥ, 2016
Time to Market Pressure ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.30 Θεοχαρίδης, ΗΜΥ, 2016
As a side note: NRE and unit cost metrics q Costs: Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system total cost = NRE cost + per-product cost unit cost * # of units = total cost / # of units = (NRE cost / # of units) + unit cost Example NRE=$2000, unit=$100 For 10 units total cost = $2000 + 10*$100 = $3000 per-product cost = $2000/10 + $100 = $300 Amortizing NRE cost over the units results in an additional $200 per unit ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.31 Θεοχαρίδης, ΗΜΥ, 2016
Break Even Analysis: ASICs vs FPGAs q A 10,000-gate design to demonstrate how to find the break-even point and cost of ownership for an FPGA vs an ASIC. Basic break even cost = NRE + engineering + (units*price) (1) q Gate arrays or ASICs have a much higher development cost than do FPGAs. q Because of higher component price, FPGAs have traditionally been used in lower volume applications. q FPGAs have no NRE charges, and their design cycles are short. ASIC = $25,000 NRE+$79,000 engineering and tools+ (X units* $13). (1) FPGA = 0 NRE+$25,000 engineering and tools+ (X units*$39). (2) Solving (1) and (2), X=79,000/26=3038 units. Further Reading: http://www.edn.com/archives/1995/051195/10df4.htm ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.32 Θεοχαρίδης, ΗΜΥ, 2016
ASIC vs. FPGAs q You need 32 weeks or eight months to production to develop an ASIC. In contrast, an FPGA takes only 11 weeks or 2.75 months to production. q Because an FPGA is the faster approach to designing and delivering custom logic, the time lost building an ASIC is the difference between delivering the product with an FPGA (2.75 months) and delivering it with an ASIC (eight months), or 5.25 months, in this example. If the market for the product is three years or 36 months, the lost revenue from developing a gate array would be: Lost revenue = [5.25(3*18-5.25)/2.18^2)*100] = 39.49%. ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.33 Θεοχαρίδης, ΗΜΥ, 2016
Re-Spinning q Currently, roughly 30% of designs are re-spun. Using this number and assuming another $25,000 NRE charge, the probable cost of a re-spin is: q Re-spin cost = [(17 weeks*$3000 engineering per week) +NRE]*re-spin potential q ASIC total cost = 25,000+79,000+7819020+ 22800 + (X units*13). q Additional 17 weeks delay in time to market.. ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.34 Θεοχαρίδης, ΗΜΥ, 2016
Reasons for Respin Found On First Spin ICs/ASICs: - Functional Logic Error ###################### 43% - Analog Tuning Issue ########## 20% - Signal Integrity Issue ######### 17% - Clock Scheme Error ####### 14% - Reliability Issue ###### 12% - Mixed Signal Problem ##### 11% - Uses Too Much Power ##### 11% - Has Path(s) Too Slow ##### 10% - Has Path(s) Too Fast ##### 10% - IR Drop Issues #### 7% - Firmware Error ## 4% - Other Problem # 3% - Overall 61% of New ICs/ASICs Require At Least One Re-Spin Source: Aart de Geus, Chairman & CEO of Synopsys ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.35 Θεοχαρίδης, ΗΜΥ, 2016
More Designs Embracing FPGAs Source: Gartner Group ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.36 Θεοχαρίδης, ΗΜΥ, 2016
Programmable Logic Share Source: Xilinx ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.37 Θεοχαρίδης, ΗΜΥ, 2016
FPGA Gate Counts ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.38 Θεοχαρίδης, ΗΜΥ, 2016
FPGA Evolution Source: Xilinx ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.39 Θεοχαρίδης, ΗΜΥ, 2016
FPGA technology vs ASIC ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.40 Θεοχαρίδης, ΗΜΥ, 2016
Current FPGA Architectures ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.41 Θεοχαρίδης, ΗΜΥ, 2016
FPGA Application Domains q Started as Prototyping platforms q Hardware Accelerators q Reconfigurable multi-function systems q Specialized Applications Aerospace and space - Mars Rover Military Applications Missiles q Signal Processing q Embedded Systems ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.42 Θεοχαρίδης, ΗΜΥ, 2016
Gate Array ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.43 Θεοχαρίδης, ΗΜΥ, 2016
Gate Array vs. Standard-Cell ASIC q AND gates ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.44 Θεοχαρίδης, ΗΜΥ, 2016
Programmable Logic - History q PROM first programmable logic Address lines serve as logic inputs and data lines as logic output Logic functions are inefficient as logic functions rarely use all product terms D0 D2 Source: http://jingwei.eng.hmc.edu/~rwang/e85/lectures/digital_logic/node12.html ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.45 Θεοχαρίδης, ΗΜΥ, 2016
PLA Programmable Logic Arrays q Programmable wired AND followed by programmable wired OR q Inputs to AND plane can be normal or complementary input generates product terms q OR sum of products Consider Implementing F=A B C +A BC +AB C +AB C+ABC PLA problems q Two levels of programmability leads to Poor performance Difficult to manufacture ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.46 Θεοχαρίδης, ΗΜΥ, 2016
Programmable Array Logic (PALs) q Programmable wired AND plane and fixed wired OR plane Source: Brown and Rose, IEEE Design and Test, 1996 ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.47 Θεοχαρίδης, ΗΜΥ, 2016
Simple Programmable Logic Devices (SPLDs) q PLAs and PALS Programmable logic plane structure size increases rapidly with increase in number of inputs q Complex PLDs Programmably interconect multiple SPLDs Altera MAX series pioneered such devices q FPGAs ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.48 Θεοχαρίδης, ΗΜΥ, 2016
Programmable Technologies ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.49 Θεοχαρίδης, ΗΜΥ, 2016
Xilinx FPGA Toolflow Source: Xilinx ΗΜΥ408 Δ02 Τεχνολογική Αναδροµή.50 Θεοχαρίδης, ΗΜΥ, 2016