ZO3 SYSTEM BLOCK DIAGRAM

ZO SYSTM LOK IGRM TV-OUT TFT L Panel WXG RT P P P INT or V selector Resistor P LVS TV-out RT H (ST) MXM P P PI-xpress X TV-out LVS VG ST0 M Sg ufpg Turion ual-ore/ Sempron Single-ore n-vidia MP P,,, HT LINK ual hannel R / MHz US.0 PU Thermal Sensor luetooth US Port x P P P PI-xpress LI P PU Fan RII SO-IMM 0 SO-IMM P P US Mini ard / WLN P VOR(ISL) P V/.V (TPS0) ISHRG.V P P P New ard.v/.vm/.v/.v SMR_VRF/ SMR_VTRM VG-ore (MX ).V P TTRY SLT TTRYHRGR (ISL) P P P O (PT) P Int MI PT zalia P,,,0,, LP X'TL.KHZ PI us X'TL.MHZ ardreader ontroller PI- LN PHY Realtek RTL P X'TL M udio mplifier P zalia udioontroller RealTek L P X'TL.K (WPLG) Ricoh R P0 Transformer P MI Jack P Line in P SPI ROM P P I Port P0 Media ard Reader P0 RJ/ P onnector Speaker P Phone Jack P M. P Touch Pad P Keyboard P PROJT : ZO Quanta omputer Inc. Size ocument Number Rev lock iagram Wednesday, pril, 00 ate: Sheet of 0

() HT_RX#[..0] HT_RX#[..0] () HT_TX[..0] () HT_RX[..0] HT_RX[..0] () HT_TX#[..0] HT_TX[..0] HT_TX#[..0] PROSSOR HYPRTRNSPORT INTRF VLT_x N VLT_x R ONNT TO TH LT_RUN POWR SUPPLY THROUGH TH PKG OR ON TH I. IT IS ONLY ONNT ON TH OR TO OUPLING NR TH PU PKG VLT_RUN U VLT_ VLT_ VLT_ VLT_0 VLT_ VLT_ VLT_ VLT_0.U_ HT_RX N HT_RX#P HT_RX M HT_RX#M HT_RX L HT_RX#M HT_RX K HT_RX#K HT_RX H HT_RX#H HT_RX0 G HT_RX#0H HT_RX F HT_RX# F HT_RX HT_RX# F HT_RX N HT_RX# N HT_RX L HT_RX# M HT_RX L HT_RX# L HT_RX J HT_RX# K HT_RX G HT_RX# H HT_RX G HT_RX# G HT_RX HT_RX# F HT_RX0 HT_RX#0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 T T V U V V Y W T R U U V U W W HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0.V_HT VLT_RUN L FJHS00_0 L0 FJHS00_0 0 ohm().u_.u_.u_.u_ 0P_ LYOUT: Place bypass cap on topside of board NR HT POWR PINS THT R NOT ONNT IRTLY TO OWNSTRM HT VI, UT ONNT INTRNLLY TO OTHR HT POWR PINS PL LOS TO VLT0 POWR PINS 0 0P_ VLT_RUN () HT_PU_UPLK () HT_PU_UPLK# () HT_PU_UPLK0 () HT_PU_UPLK#0 J K J J L0_LKIN_H L0_LKIN_L L0_LKIN_H0 L0_LKIN_L0 L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 Y Y Y W HT_PU_WNLK () HT_PU_WNLK# () HT_PU_WNLK0 () HT_PU_WNLK#0 () R _ R0 _ () HT_PU_UPTL0 () HT_PU_UPTL#0 HT_TLIN_P HT_TLIN_N P P N P L0_TLIN_H L0_TLIN_L L0_TLIN_H0 L0_TLIN_L0 L0_TLOUT_H L0_TLOUT_L L0_TLOUT_H0 L0_TLOUT_L0 T HT_PU_WNTL R HT_PU_WNTL# R R T T0 HT_PU_WNTL0 () HT_PU_WNTL#0 () thlon S Processor Socket PROJT : ZO Quanta omputer Inc. Size ocument Number Rev THLON HT I/F ate: Wednesday, pril, 00 Sheet of 0

V_VTT_SUS_PU IS ONNT TO TH V_VTT_SUS POWR SUPPLY THROUGH TH PKG OR ON TH I. IT IS ONLY ONNT ON TH OR TO OUPLING NR TH PU PKG.VSUS Processor R Memory Interface K/F_ M Q M Q () M Q[0..] M Q M_T M_T M Q[0..] () F M Q PU_M_VRF M Q M_T M_T F M Q M Q0 M_T M_T M Q0 M Q M_T0 M_T0 Y M Q 00 M Q M_T W R0 M_T M Q M Q M_T M_T Y M Q 000P_ M Q M_T K/F_ M_T F M Q M Q M_T M_T F M Q M Q M_T M_T F M Q M Q M_T M_T M Q.VSUS M Q M_T M_T F M Q SMR_VTRM M Q M_T M_T Y M Q M Q0 M_T M_T Y U M Q0 M Q M_T0 M_T0 W M Q R M Q M_T M_T W M Q./F_ M Q M_T M_T W M Q MMVRF VTT 0 0 M Q M_T M_T Y M Q VTT_SNS VTT 0 0 M Q M_T M_T M Q T Y0 VTT_SNS VTT 0 F M Q M_T M_T M Q VTT 0 F M Q M_T M_T M Q M_ZN VTT W0 F0 M Q M_T M_T 0 M Q M_ZP MMZN VTT 0 0 M Q M_T M_T F0 M Q MMZP VTT 0 M Q0 M_T M_T 0 M Q0 VTT 0 M Q M_T0 M_T0 Y0 M Q VTT 0 M Q M_T M_T M Q R M Q M_T M_T Y M Q () M S# V M0_S_L M0_LK_H Y M_LKOUT ()./F_ M Q M_T M_T W M Q () M S# J M0_S_L M0_LK_L M_LKOUT# () M Q M_T M_T W M Q () M S# V M0_S_L M0_LK_H M_LKOUT0 () M Q M_T M_T M Q () M S#0 T M0_S_L0 M0_LK_L F M_LKOUT0# () M Q M_T M_T M Q M Q M_T M_T M Q () M S# Y M0_S_L M0_LK_H F M_LKOUT () M Q M_T M_T Y M Q () M S# J M0_S_L M0_LK_L F M_LKOUT# () G M Q0 M_T M_T H M Q0 () M S# W M0_S_L M0_LK_H M_LKOUT () G M Q M_T0 M_T0 H0 M Q () M S#0 U M0_S_L0 M0_LK_L M_LKOUT# () M Q M_T M_T M Q M Q M_T M_T M Q () M_K H M_K M0_OT W M_OT () G M Q M_T M_T J M Q () M_K J M_K0 M0_OT0 W M_OT () G M Q M_T M_T H M Q () M_K J0 M_K M0_OT V0 M_OT () M Q M_T M_T F M Q () M_K0 J M_K0 M0_OT0 U M_OT0 () M Q M_T M_T F0 M Q () M [0..] M M M Q M_T M_T K M Q M [0..] () M M_ M_ J M M Q M_T M_T K0 M Q M M_ M_ J 0 V M M Q0 M_T M_T F M Q0 M M_ M_ W 0 K M M Q M_T0 M_T0 M Q M M_ M_ L L0 M M Q M_T M_T 0 M Q M 0 M_ M_ L R M 0 M Q M_T M_T M Q M M_0 M_0 U L M M Q M_T M_T M Q M M_ M_ L 0 L M M Q M_T M_T G M Q M M_ M_ M L M M Q M_T M_T G M Q M M_ M_ L M M M Q M_T M_T M Q M M_ M_ N M0 M M Q M_T M_T F M Q M M_ M_ N M M M Q M_T M_T M Q M M_ M_ N 0 M M M Q0 M_T M_T H M Q0 M M_ M_ N N M M Q M_T0 M_T0 M Q M M_ M_ P N M M Q M_T M_T M Q M 0 M_ M_ P R M 0 M Q M_T M_T H M Q M_0 M_0 T M Q M_T M_T M Q M Q M_T M_T M Q () M S# K M_NK M_NK K M S# () M Q M_T M_T H M Q () M S# R0 M_NK M_NK T M S# () G M Q M_T M_T H M Q () M S#0 T M_NK0 M_NK0 U M S#0 () M Q M_T M_T G M Q M Q M_T M_T H M Q () M RS# T0 M_RS_L M_RS_L U M RS# () M Q0 M_T M_T F M Q0 () M S# U0 M_S_L M_S_L V M S# () M_T0 M_T0 G () M W# U M_W_L M_W_L U M W# () M M M M M M M_M M_M Y M M R II: M/TRL/LK M M M_M M_M M M M M M_M M_M Y M M thlon S M M M_M M_M M M Processor Socket M M M_M M_M F M M M M M_M M_M M M M M0 M_M M_M M M0 () M M[0..] M_M0 M_M0 M M[0..] () Near PU L<00mil R M QS F M QS M QS# M_QS_H M_QS_H W M QS# M_LKOUT M_LKOUT0 M QS M_QS_L M_QS_L W M QS M QS# M_QS_H M_QS_H Y M QS# M QS M_QS_L M_QS_L W F M QS M QS# M_QS_H M_QS_H F M QS#.P_ M QS M_QS_L 0.P_ M_QS_L M QS M_LKOUT# M_LKOUT0# M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F M QS M_LKOUT M_LKOUT M QS# M_QS_H M_QS_H G M QS# M QS M_QS_L M_QS_L G M QS M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L M QS.P_.P_ M QS# M_QS_H M_QS_H G M QS# M_LKOUT# M_LKOUT# M QS0 M_QS_L M_QS_L G M QS0 M QS#0 M_QS_H0 M_QS_H0 G M QS#0 M_QS_L0 M_QS_L0 H To SOIMM socket (Far) U To SOIMM socket (near).u_.u_ SMR_VTRM.U_.U_.U_.U_.U_.U_ 0 000P_ 000P_ 000P_ 000P_ 0 0P_ 0 0P_ 0 0P_ 0P_ () M QS[0..] () M QS#[0..] M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# R: T thlon S Processor Socket M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS[0..] () M QS#[0..] () PROJT : ZO Quanta omputer Inc. Size ocument Number Rev THLON RII MMORY I/F ate: Wednesday, pril, 00 Sheet of 0

LYOUT: ROUT V TR PPROX. 0 mils WI (US x mil TRS TO XIT LL FIL) N 00 mils LONG. THLON ontrol and ebug PU_V_RUN PU_V_RUN.U_.U_ L LMPG0SN_ 00P_.V 0 00U-.V_ If M SI is not used, the SI pin can be left unconnected and SI should have a 00-Ω (±%) pulldown to VSS..VSUS R0 R0 *00_ *00_ R0 00_ PU_SI_R PU_SI_R () () VLT_RUN ORFV ORF- R R PU_V_RUN PU_HT_RST# PU_LL_PWROK PU_LTSTOP# PU_SI_R PU_SI_R./F_./F_ PU_HTRF PU_HTRF0 U F V F V RST_L PWROK F0 LTSTOP_L F SI F SI P HT_RF R HT_RF0 F V_F_H V_F_L THRMTRIP_L PROHOT_L VI VI VI VI VI VI0 PU_PRSNT_L PSI_L F H_THRMTRIP# H_PROHOT# PU_PRSNT# PSI#.VSUS R 00_ H_VI () H_VI () H_VI () H_VI () H_VI () H_VI0 () V.VSUS () PU_LK 00P_ T T PU_VIO_SUS_F_H PU_VIO_SUS_F_L PU_LKIN_S_P PU_LKIN_S_N W Y VIO_F_H VIO_F_L LKIN_H LKIN_L PSI_L is a Power Status Indicator signal. This signal is asserted when the processor is in a low powerstate. PSI_L should be connected to the power supply controller, if the controller supports skipmode, or diode emulation mode. PSI_L is asserted by the processor during the and S states. () HTPU_PWRG R0 *.K/F_ * U *NSZ0PX_NL PU_LL_PWROK () PU_LK# R /F_ 00P_ PU_RY PU_TMS PU_TK PU_TRST# PU_TI G0 F RY TMS TK TRST_L TI RQ_L TO 0 PU_RQ# PU_TO () HTPU_STOP# R00 0_.VSUS R 0_.VSUS 0 * U *NSZ0PX_NL PU_LTSTOP#.V V R R 0K_ K/F_ T T T T0 T PU_TST_H_YPSSLK_H PU_TST_L_YPSSLK_L PU_TST_PLLTST0 PU_TST_PLLTST PU_TST_P PU_TST_P PU_TST_P PU_TST_P0 PU_TST_SNSHIFTN PU_TST_THRM PU_TST_THRM G H0 F W W Y TST_H TST_L TST TST TST TST TST TST TST TST TST TST TST TST TST TST TST TST_H TST_L TST TST TST TST TST0 TST_H TST_L TST TST TST0 TST F J H F K PU_TST_H_FLKOUT_P R 0./F_ PU_TST_L_FLKOUT_N TST_L and TST_H differential pair should have an 0- differential trace routed to a termination resistor. These traces should be shorter than. inches. //// PU_TST_SNLK PU_TST_TSTUP PU_TST_SNSHIFTN PU_TST_SNN PU_TST0_SNLK PU_TST_SINGLHIN PU_TST_URNIN# T T T T0 () HTPU_RST# (,,) PWROK_ R0 *0_ R0 0_ * U *NSZ0PX_NL PU_HT_RST# PSI# Q MMT0 PWR_PSI# () P0 P N0 N R R P R RSV0 RSV RSV RSV RSV RSV RSV RSV MIS RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 H H G R W R H H.VSUS R 00_ H_PROHOT#.VSUS V PU_TST_THRM PU_TST_THRM 0 mil trace / 0 mil space.v R *0_ PU H/W MONITOR R Q MMT0 /F_ R 0_ 00P_ MIL V_THM _PROHOT# () MP_PROHOT# () ddress H U G V -LT XN SMT XP SMLK -OVT R 0K_ KSMT KSMLK Q0 V V R 0K_ N00 ().VSUS To S GPIO To FN MP_THRMIP# THRM_LRT# () PUFN#_ON ().V 00_ R H_THRMTRIP# V R0 R.K_ V *0_ R.K_ Q N00 Q *MMT0 Q N00.V R 0_ R *.K_ Q MMT0 MT_PU () MLK_PU () R *.K_ PWROK_ THRM_SYS_PWR () M NPT S SOKT Processor Socket.VSUS PU_TST_SINGLHIN R0 *00_ PU_TST_URNIN# R0 00_ PU_PRSNT# R K/F_ PU_TST_H_YPSSLK_H R 0/F_ PU_TST_SNN R0 00_ PU_TST_L_YPSSLK_L R 0/F_ PU_TST_PLLTST0 R 00_ PU_TST_PLLTST R 00_ R0 0_ R 0_ HTPU_RST# R 0_ R0 0_ PU_RQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO.VSUS V R 0K_ R 0_ Q MMT0 HT ONNTOR R K/F_ H_HTPU_RST# T T T T T T T.VSUS T N *SP-00-0-P-LV HT RSV RSV0 RQ_L RY 0 TK TMS TI TRST_L TO 0 V_PRO_IO_ V_PRO_IO_RST_L KY PROJT : ZO Quanta omputer Inc. Size ocument Number Rev THLON TRL & UG Wednesday, pril, 00 ate: Sheet of 0 0 0

PROSSOR POWR N GROUN V_OR V_OR VSS VSS J VSS VSS J V V V VSS VSS J0 V V V VSS VSS J G V_OR V V W VSS VSS0 J H V V Y VSS VSS J J V V J VSS VSS J J V V K VSS VSS K J V V L VSS VSS K K V V0 M VSS0 VSS K K0 VSS VSS K 0 V V P 0 0 K U-0V_ VSS VSS K U-0V_ U-0V_ U-0V_ U-0V_ U-0V_ U-0V_ V0 V T U-0V_ U-0V_ K V V U VSS VSS K L V V V.VSUS VSS VSS K L V VSS VSS0 L L V VSS VSS L L V_OR V VIO H VSS VSS L0 L V VIO J VSS VSS L M V VIO K VSS VSS L M V VIO K VSS0 VSS L M V VIO K VSS VSS L M0 VSS VSS M 0 V0 VIO K N.U_ VSS VSS M.U_.0U_ 0P_ V VIO L N V VIO M VSS VSS M N V VIO M VSS VSS0 M P V VIO0 M VSS VSS N P0 V VIO M VSS VSS N R V VIO N VSS VSS N0 R V VIO P VSS VSS N R V VIO P VSS0 VSS N R V VIO P VSS VSS P T V0 VIO P VSS VSS P T V VIO R VSS VSS P T V VIO T VSS VSS P T0 V VIO T VSS VSS00 P T V VIO0 T VSS VSS0 R T V VIO T VSS VSS0 R0 U V VIO U VSS VSS0 R U V VIO V VSS VSS0 R U V VIO V VSS0 VSS0 T U V VIO V VSS VSS0 T V V0 VIO V VSS VSS0 T V V VIO Y VSS VSS0 T V0 V VSS VSS0 T OUPLING TWN PROSSOR N IMMs VSS VSS0 T POWR VSS VSS U thlon S VSS VSS U PL LOS TO PROSSOR S POSSIL Processor Socket VSS VSS U VSS VSS U0 VSS0 VSS U.VSUS VSS VSS U F VSS VSS U F VSS VSS U F VSS VSS V F VSS VSS0 V F VSS VSS V 0 0 F.0U_ 0P_ VSS VSS V.U_.U_.U_.U_.U_.U_.U_.U_.0U_ 0P_ 0P_ F VSS VSS V F VSS VSS V F VSS0 VSS V H VSS VSS W H VSS VSS Y H VSS VSS Y H VSS VSS N J.VSUS VSS GROUN M Sg upg Top View U UF thlon S Processor Socket U-0V_ 0 U-0V_.U_.U_ F PROJT : ZO Quanta omputer Inc. Size ocument Number Rev THLON PWR & ate: Wednesday, pril, 00 Sheet of 0

M M M M 0 M QS M M M M Q M Q M Q M QS#0 M M Q M Q M Q M Q M M0 M Q M Q M Q M QS# M Q M Q M M M M M M Q0 M Q M Q M Q M Q M Q M Q M QS M M Q M Q M Q M QS# M M QS M M QS# M Q M Q M Q M Q M Q0 M QS M QS M Q M Q M Q0 M M Q0 M Q M QS# M QS M M M Q M Q M Q M Q M QS0 M Q M Q M Q M Q M Q MVRF_IM M QS M M M M M M M QS# M QS# MM_SMLK MM_SMT M Q M Q M QS# M M M Q M Q M Q M Q M Q M 0 M Q M Q M Q0 M M M M M M Q M Q M Q M QS# M QS0 M M M M Q0 M QS M M M Q M Q M QS# M QS M M M M Q0 M Q M Q M M0 M 0 M Q M Q M Q M Q M M M Q M Q M Q MM_SMLK M QS M Q M QS# M M Q M Q M Q M M M M M M Q M Q M Q M Q M QS# MM_SMT M M M Q M Q M Q0 M Q M QS# M M Q M Q M Q M M QS M QS M M Q M Q M Q M QS M Q M Q M Q M Q M QS# M QS#0 M M Q0 M Q0 M Q M QS# M M M Q M 0 M Q M Q0 M QS M M Q M Q M Q M Q MVRF_IM MVRF_IM M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M 0 M M M M M M 0 M S# M W# M S# M RS# M_K M_OT0 M S# M RS# M S# M S# M S#0 M S# MM_SMLK MM_SMT M M M M 0 M S# M M_K M_OT M_OT M_K M S#0 M S# M S# M M M M S#0 M M M M M M M M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M_K0 M S# M 0 M S# M_OT M S# M S#0 M W# M MSM_T () MSM_LK () V V.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VRF V V SMR_VTRM SMR_VTRM V.VSUS SMR_VTRM M [0..] () M_K0 () M_K () M RS# () M S# () M W# () M S#0 () M S# () M_OT0 () M Q[0..] () M_LKOUT0 () M_LKOUT0# () M_LKOUT () M_LKOUT# () M_OT () M S# () M S# () M S#0 () M QS#[0..] () M QS[0..] () M M[0..] () M_LKOUT () M_LKOUT# () M_LKOUT () M_LKOUT# () M_OT () M_K () M_K () M_OT () M [0..] () M S# () M S#0 () M S# () M QS#[0..] () M QS[0..] () M M[0..] () M RS# () M S# () M W# () M Q[0..] () M S# () M S# () M S# () M S# () M S#0 () M S# () Size ocument Number Rev ate: Sheet of R-II SOIMM* 0 Wednesday, pril, 00 Size ocument Number Rev ate: Sheet of R-II SOIMM* 0 Wednesday, pril, 00 Size ocument Number Rev ate: Sheet of R-II SOIMM* 0 Wednesday, pril, 00 (H=.) (H=.) RVRS RVRS RP X_ RP X_ 0 0 *0U-.V_ *0U-.V_ 0 0 RP X_ RP X_ 0 0 0U-.V_ 0 0U-.V_ 0 RP0 X_ RP0 X_ RP X_ RP X_ RP X_ RP X_ 0 0 RP X_ RP X_ U_ U_ * * RP0 X_ RP0 X_ R _ R _ RP X_ RP X_ 0 0 Q *N00 Q *N00 0 0 RP X_ RP X_ 0 0 R 0_ R 0_ 0U-.V_ 0U-.V_ *0U-.V_ *0U-.V_ * * RP X_ RP X_ RP X_ RP X_ R _ R _ RP X_ RP X_ 0 0 *0U-.V_ *0U-.V_ RP X_ RP X_ RP X_ RP X_ 0 0 Q *N00 Q *N00 R *0_ R *0_ SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TST 0 0 0 00 0 0 0 0 0 0 M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K K0 K 0 VRF RS 0 S W 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 Quanta omputer Inc. PROJT : ZO Quanta omputer Inc. PROJT : ZO RP X_ RP X_ RP X_ RP X_ * * RP *.KX_ RP *.KX_ R _ R _ RP X_ RP X_ RP X_ RP X_ R 0K_ R 0K_ 0 0 *0U-.V_ *0U-.V_ RP X_ RP X_ 0 0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TST 0 0 0 00 0 0 0 0 0 0 M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K K0 K 0 VRF RS 0 S W 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 0 0 RP X_ RP X_ R 0_ R 0_ * * RP X_ RP X_ R _ R _ R0 K/F_ R0 K/F_ RP X_ RP X_ RP X_ RP X_ 0 0 0 0 R 0_ R 0_.U_.U_ R _ R _ RP X_ RP X_ R K/F_ R K/F_.U_.U_ RP X_ RP X_ * * R _ R _ RP X_ RP X_ 0 0 RP X_ RP X_

MP Used UM Only MP Signal Name RG RST RG VRF _T0 TV RST TV VRF IFP_RST IFP_VPRO _T HPLUG_T HMI_RST HMI_VPRO _T_R HP_ROM_ST HPLUG_T_R MP Unused UM Only MP Signal Name RG RST RG VRF _T0 TV RST TV VRF IFP_RST IFP_VPRO _T HPLUG_T HMI_RST HMI_VPRO _T_R HP_ROM_ST HPLUG_T_R omponent *0K LV N *0K LV N K PULN 0K PULLHIGH 0K PULLHIGH.K PULN omponent 0K PULLHIGH 0K PULLHIGH K PULN 0K PULLHIGH 0K PULLHIGH.K PULN () HT_TX[..0] () HT_TX#[..0] () HT_PU_WNLK0 () HT_PU_WNLK#0 () HT_PU_WNLK () HT_PU_WNLK# () HT_PU_WNTL0 () HT_PU_WNTL#0 () MP_THRMIP# () MP_PROHOT#.V_HT R R 0/F_ 0/F_ HT_TX0 HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX0 HT_TX HT_TX HT_TX HT_TX HT_TX HT_TX#0 HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# HT_TX#0 HT_TX# HT_TX# HT_TX# HT_TX# HT_TX# PU_L_PV PU_L_ U0 F HT_MP_RX0_P H HT_MP_RX_P J HT_MP_RX_P K HT_MP_RX_P G HT_MP_RX_P L HT_MP_RX_P L HT_MP_RX_P J HT_MP_RX_P HT_MP_RX_P F HT_MP_RX_P H HT_MP_RX0_P L HT_MP_RX_P HT_MP_RX_P HT_MP_RX_P HT_MP_RX_P HT_MP_RX_P G HT_MP_RX0_N J HT_MP_RX_N K HT_MP_RX_N L HT_MP_RX_N F HT_MP_RX_N K HT_MP_RX_N K HT_MP_RX_N K HT_MP_RX_N HT_MP_RX_N G HT_MP_RX_N J HT_MP_RX0_N K HT_MP_RX_N HT_MP_RX_N HT_MP_RX_N HT_MP_RX_N HT_MP_RX_N J HT_MP_RX_LK0_P H HT_MP_RX_LK0_N L HT_MP_RX_LK_P K HT_MP_RX_LK_N H HT_MP_RXTL0_P G HT_MP_RXTL0_N HT_MP_RXTL_P HT_MP_RXTL_N M L :JMP0T00 :JMP0T0 MP_THRMIP# MP_PROHOT# THRMTRIP#/GPIO_(V) PROHOT#/GPIO_0(V_S) HT_MP_OMP_V HT_MP_OMP_ MP OF HT HT_MP_TX0_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX0_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX_P HT_MP_TX0_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX0_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_N HT_MP_TX_LK0_P HT_MP_TX_LK0_N HT_MP_TX_LK_P HT_MP_TX_LK_N HT_MP_TXTL0_P HT_MP_TXTL0_N HT_MP_TXTL_P HT_MP_TXTL_N LKOUT_00MHZ_P LKOUT_00MHZ_N HT_MP_RQ# HT_MP_STOP# HT_MP_RST# HT_MP_PWRG PU_SVRF LK00_TRM_ K K K L K K H L0 G F H F 0 J L L K L L J M0 H G J F G 0 F K J G H K0 J0 L M 0 G J HT_RX0 HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX0 HT_RX HT_RX HT_RX HT_RX HT_RX HT_RX#0 HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HT_RX#0 HT_RX# HT_RX# HT_RX# HT_RX# HT_RX# HTPU_RQ# PU_SVRF MP_TRM HT_RX[..0] () HT_RX#[..0] () HT_PU_UPLK0 () HT_PU_UPLK#0 () HT_PU_UPLK () HT_PU_UPLK# () HT_PU_UPTL0 () HT_PU_UPTL#0 () PU_LK () PU_LK# () HTPU_STOP# () HTPU_RST# () HTPU_PWRG () R 0_.V_HT 0 R0.K/F_ HTPU_RQ# MP_THRMIP# R K_ V V R *00_ atasheet error its should be. plane.vsus MP_THRMIP# R 00_ HTPU_STOP# R0 00_ HTPU_RST# R 00_ HTPU_PWRG R 00_ MP_PROHOT# R 00_ FOR UM ONLY () INT_RT_R () INT_RT_GRN () INT_RT_LU () INT_HSYN R IV@0_ INT_RT_R () INT_VSYN R IV@0_ INT_RT_GRN R /F_ R IV@0_ INT_RT_LU.0U_ R IV@0_ INT_TV_/R () INT_RT_LK R0 IV@0_ INT_TV_Y/G () INT_RT_T R IV@0_ INT_TV_OMP () INT_TV_/R () INT_TV_Y/G 0 IV@P_ () INT_TV_OMP R Y IV@MHZ IV@P_ /F_.0U_ RG RST RG VRF TV RST TV VRF TV_XTLIN TV_XTLOUT G H K G H H F RG R RG GRN RG LU RG HSYN RG VSYN RG RST RG VRF _LK0 _T0 TV R TV GRN TV LU TV RST TV VRF TV_XTLIN TV_XTLOUT S IFP_TX_P IFP_TX_N IFP_TX0_P IFP_TX0_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N 0 0 0 J J F0 F G0 G H H0 INT_TXLOUT INT_TXLOUT- INT_TXLLKOUT () INT_TXLLKOUT- () INT_TXLOUT0 () INT_TXLOUT0- () INT_TXLOUT () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT- () T T [LVS] : Remove,R for Nvidia suggest. V V : changed P value R R R0 V R0 R R V@.K_ INT_RT_T R R V@.K_ INT_LVS_IT T T0 *0K_ HP_ROM_SLK 0K_ HP_ROM_ST *0K LK_R 0K T_R.K_ HPLUG_T_R * HMI_VPRO *K/F_HMI_RST HMI_TX_P_R HMI_TX_N_R : Remove,R for Nvidia suggest. UNUS HMI ONLY HMI_TX0_P_R T HMI_TX0_N_R T HMI_TX_P_R T HMI_TX_N_R T HMI_TX_P_R T HMI_TX_N_R T HP_ROM_SLK HP_ROM_ST L _LK K _T L HPLUG_T K HMI_VPRO K HMI_RST L HMI_TX_P M HMI_TX_N IFP_VPRO IFP_RST FLT PNL _LK _T L_PNL_PWR L_KL_ON L_KL_TL GPIO_(V_S)/FRR/SYS_SRR/IGPU_GPIO_* GPIO_(V_S)/NFRR/SYS_PRR/IGPU_GPIO_* K HMI_TX0_P J HMI_TX0_N M0 HMI_TX_P L0 HMI_TX_N HPLUG_T K0 HMI_TX_P J0 HMI_TX_N MP 0 L J U T IFP_VPRO IFP_RST MP_GPIO MP_GPIO HPLUG_T R R R R0 *.0U_ *K/F_ INT_LVS_ILK () INT_LVS_IT () INT_LVS_IGON () INT_LVS_LON () L_KLT_TRL () *.K_ *.K_ K_ FOR VI IS NOT IMPLMNT V V FOR UM ONLY : Remove R,R PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MP(HT/VG/FLT_PNL) ate: Wednesday, pril, 00 Sheet of 0

[MXM] U0 () PG_RXP[:0] PG_TXP[:0] () PG_RXP0 F _PG_TXP0 PG_TXP0 PG_RXP P0_RX0_P P0_TX0_P F _PG_TXP PG_TXP PG_RXP P0_RX_P MP P0_TX_P _PG_TXP PG_TXP PG_RXP P0_RX_P OF P0_TX_P _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P F _PG_TXP PG_TXP PG_RXP P0_RX_P PI P0_TX_P F _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P 0 0 H _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P H _PG_TXP PG_TXP PG_RXP0 P0_RX_P P0_TX_P H _PG_TXP0 PG_TXP0 PG_RXP P0_RX0_P P0_TX0_P 0 K _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P K _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P F K _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P G J _PG_TXP PG_TXP PG_RXP P0_RX_P P0_TX_P H K _PG_TXP PG_TXP P0_RX_P P0_TX_P H () PG_RXN[:0] PG_TXN[:0] () PG_RXN0 G _PG_TXN0 PG_TXN0 PG_RXN P0_RX0_N P0_TX0_N F _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N 0 _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N 0 _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N F _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N F _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N 0 H _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N H _PG_TXN 0 PG_TXN PG_RXN0 P0_RX_N P0_TX_N H _PG_TXN0 PG_TXN0 PG_RXN P0_RX0_N P0_TX0_N K _PG_TXN PG_TXN P0_PRSNTX PG_RXN P0_RX_N P0_TX_N 0 K _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N F0 K _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N G0 J0 _PG_TXN PG_TXN PG_RXN P0_RX_N P0_TX_N H0 K0 _PG_TXN PG_TXN P0_RX_N P0_TX_N H P0_PRSNTX# P0_PRSNTX# R _ P0_RFLK_P P0_PRSNTX () LK_MXM R V P0_RFLK_N P0_RFLK_P P0_PRSNTX#/_LK U R *0K_ R _ P0_PRSNTX R0 *0K_ P0_PRSNTX# () LK_MXM# R0 P0_RFLK_N P0_PRSNTX#/_T U0 P0_PRSNTX R *0K_ Internal Pull-up P0_PRSNTX#/XP_N U P0_PRSNTX R *0K_ P0_PRSNTX# U R *0_ P0_PRSNTX () NT NM P0_PRSNTX MP (ISRT) MPM (GPU) N/ [NW R] () PI_RXP () PI_RXN () NW_LKRQ# () PP# NW_LKRQ# PP# L L0 W W P_RX_P P_RX_N P_LKRQ# P_PRSNT# P_TX_P P_TX_N P_RFLK_P P_RFLK_N M M T T PI_TXP_ PI_TXN_ LK_PI_NW R LK_PI_NW_#_R R _ R _ PI_TXP () PI_TXN () LK_PI_NW_ () LK_PI_NW_# () [NW R] LK_MXM LK_MXM# *0P_ *0P_ [TV] [MINI R] M P_RX_P M P_RX_N U P_LKRQ# U P_PRSNT# P_TX_P M P_TX_N M P_RFLK_P T P_RFLK_N T0 PI_TXP_ () PI_RXP N 0 P_RX_P P_TX_P M PI_TXP () PI_TXN_ () PI_RXN N PI_TXN () MINI_LKRQ# P_RX_N P_TX_N M LK_PI_MINI_R () MINI_LKRQ# U P_LKRQ# P_RFLK_P T R _ LK_PI_MINI () U LK_PI_MINI#_R P_PRSNT# P_RFLK_N T R _ LK_PI_MINI# () [MINI R] LK_PI_MINI LK_PI_MINI# LK_PI_NW_ LK_PI_NW_# *0P_ *0P_ *0P_ *0P_ :PIN U GO IRTLY N0 P_RX_P N P_RX_N R P_LKRQ#/GPIO_(V) U P_PRSNT# P P_RX_P P0 P_RX_N T P_LKRQ#/GPIO_(V) V P_PRSNT# P P_RX_P P P_RX_N U PF_LKRQ#/GPIO_(V) V0 PF_PRSNT# MP P_TX_P P_TX_N P_RFLK_P P_RFLK_N P_TX_P P_TX_N P_RFLK_P P_RFLK_N P_TX_P P_TX_N P_RFLK_P P_RFLK_N P_RST# P_RST# P_LK_OMP M0 M T T P P T T P P P R W0 W V P_OMP <00mil R PI_RST# () dd 0R resistor, The resistor should only be R *0_ stuffed for MP *.K/F_ PI_RST# () : Remove R for Nvidia suggest. Internal 0K to. MINI_LKRQ# NW_LKRQ# PP# R0 R0 R *0K_ *0K_ *0K_ V PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MP(PI-) ate: Wednesday, pril, 00 Sheet of 0

PI/LP PULL-UP (0,) [..0] (0,) 0# (0) # (0) # (0) # (0,) LKRUN# 0 0 0 0 U0 0 PI_0 PI_FRM# 0 PI_ MP PI_IRY# 0 PI_ OF PI_TRY# L PI_ PI_STOP# K PI_ PI_VSL# J PI_ PI_PR PI_ PI_PRR#/GPIO_(V)/RS_# PI_ PI_SRR# J PI_ PI_PM#/GPIO_0(V_S) H PI_ G PI_0 F PI PI_ PI_RQ0# PI_ PI_RQ# PI_ PI_RQ#/GPIO_0(V)/RS_SR# PI_ PI_RQ#/GPIO_(V)/RS_TS# PI_ PI_RQ#/GPIO_(V)/RS_SIN# G PI_ PI_ PI_GNT0# PI_ PI_GNT# J PI_ PI_GNT#/GPIO_(V)/RS_TR# PI_0 PI_GNT#/GPIO_(V)/RS_RTS# PI_ PI_GNT#/GPIO_(V)/RS_SOUT# K PI_ PI_ PI_INTW# L PI_ PI_INTX# G PI_ PI_INTY# J PI_ PI_INTZ# PI_ H PI_ PI_LK0 PI_ PI_LK F PI_0 PI_LK PI_ PI_LK PI_LK K PI_0# K PI_# F PI_# PI_LKIN K PI_# PI_RST# PI_RST# PI_LKRUN#/GPIO_(V) PI_RST# PI_RST0# J H K L J 0 G0 J0 M F0 H0 K0 L0 F L J K L K K J FRM# IRY# TRY# STOP# VSL# PR PRR# SRR# PI_PM# RQ0# RQ# RQ# RQ# RQ# GNT0# GNT# GNT# GNT# GNT# INT# INT# INT# INT# PI_LK R PI_LK PI_LK PI_LK PI_LK PI_LKIN PIRST# PIRST# IRST_R# PIRST_R# R _ R _ FRM# (0) IRY# (0) TRY# (0) STOP# (0) VSL# (0) PR (0) PRR# (0) SRR# (0) PI_PM# (0) RQ0# (0) T T T T0 GNT0# (0) T T T T INT# (0) INT# (0) T T PLK_PM (0) T T T L:match to within 000 = Length of PI feedback and onboard devices = R _ R _ T T IRST# () PIRST# (0) V V V TRY# PRR# VSL# RQ# IRY# FRM# SRR# STOP# RQ# RQ0# LKRUN# RQ# SRIRQ 0 0 0 PI_PM# RP.KX_0PR RP.KX_0PR RP.KX_0PR R R 0K_ INT# INT# INT# INT# LRQ# LRQ#0 RQ# L0 L L L *.K_ V V_S V V V (,,) (,,) (,,) (,,) L0 L L L R _ R _ R _ R _ L0_R L_R L_R L_R LP_0 LP_ LP_ LP_ LP LP_PWRWN#/GPIO_(V)/XT_NMI# LP_P# T (0,,,) LFRM# () LRQ#0 T (,0,,) SRIRQ (,,) LP_RST# R0 _ LFRM#_R LRQ#0 LRQ# SRIRQ R _ LP_RST# LP_FRM# LP_RQ0#/GPIO_0(V) LP_RQ#/GPIO_(V)/FNRPM LP_SRIRQ LP_RST# LP_LK0 LP_LK LP_LK R PI_LK_UG R R _ R _ R _ LP_LK_ () PI_LK_UG () PI_LK_UG () LOK YPSS V R R 0K_ *0K_ MP_TK T MP_TI U JTG_TK JTG_TI JTG JTG_TO JTG_TMS JTG_TRST# T T U MP_TO MP_TMS MP_TRST# R0 R0 *0K_ 0K_ T V 0 P_ P_ LP_LK_ PLK_PM P0 PKG_TST TST_MO_N P TSTMO_N R K_ P_ PI_LK_UG R MP P_ PI_LKIN MI solution PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MP(PI/LP/JTG) ate: Wednesday, pril, 00 Sheet of 0

() LN_TX0 () LN_TX () LN_TX () LN_TX () LN_TXLK () LN_TXTL.V_RMGT INT LFT US T () LN_RX0_R () LN_RX_R () LN_RX_R () LN_RX_R () LN_RXLK_R () LN_RXTL_R () () () () R R0 LN_TX0_R LN_TX_R J K R0 _ LN_TX_R L R _ LN_TX_R L R _ LN_TXLK_R H R _ LN_TXTL_R K R R H_ITLK () H_SIN0 () H_SIN USP- RN USP USP RN USP- USP0 USP0- USP USP- LN_RX0_R 0 LN_RX_R 0 LN_RX_R LN_RX_R F LN_RXLK_R G LN_RXTL_R J0./F_ MII_OMP_PV./F_ MII_OMP_ H_SIN U U U U U0 RGMII_TX0/MII_TX0 MP RGMII/MII_M RGMII_TX/MII_TX OF RGMII/MII_MIO RGMII_TX/MII_TX MII_RXR/GPIO_(V_S) RGMII_TX/MII_TX MII_OL/MI_T RGMII_TXLK/MII_TXLK MII_RS/MI_LK RGMII_TXTL/MII_TXN RGMII/MII_PWRWN#/GPIO_(V_S) RGMII/MII_INTR/GPIO(V_S) RGMII_RX0/MII_RX0 RGMII_RX/MII_RX RGMII_RX/MII_RX UF_MHZ RGMII_RX/MII_RX LN MII_RST# RGMII_RX/MII_RXLK RGMII_RXTL/MII_RXV MII_VRF MII_OMP_PV MII_OMP_ US0_P US0_N US_P US_N H H_ITLK H_OK_N#/GPIO_(V_S) H_OK_RST#/GPIO(V_S) H_ST_IN0/GPIO_(V_S) H_ST_OUT/GPIO_(V) H_ST_IN/GPIO_(V_S)/MGPIO_0 H_SYN/GPIO_(V) H_ST_IN/GPIO_(V_S)/MGPIO_ H_RST# US US_P US_N US_P US_N K0 L0 J G H0 U U V V L: GMII_MHZ_R should <00mil,P LN_RXR LN_OL LN_RS MII_PWRN LN_INT MII_MHZ_R MIIRST# RGMII_VRF MP_GPIO MP_GPIO R R R R T T H_SOUT H_SYN H_RST# USP () USP- () USP () USP- () *.K_ *0K_ R _.K/F_.K/F_ MLK () MIO () LN_INT () MII_MHZ () MIIRST# ().V_RMGT MINI R XT US(PJ) H H_SOUT H_SYN H_ITLK H_RST# MII_MHZ MIIRST# H_SOUT 0 H_SYN H_RST# 0 H_ITLK 0 R 0_ US PULL-OWN USP0 RN USP0- USP USP- RN USP RN USP- USP RN USP- : MI Solution R0 0P_ 0P_ 0P_ 0P_ : MI Solution KX_ KX_ KX_ KX_ R _ R _ R0 _ R _ R _ R _ R0 _ R0 _ 0P_ *.K_ USP RN USP- USP RN USP- USP RN USP- USP0- RN USP0 H_SOUT_O () H_SOUT_M () H_SYN_O () H_SYN_M () H_ITLK_O () H_ITLK_M () H_RST#_O () H_RST#_M () LN_RXR LN_OL LN_RS KX_ KX_ KX_ KX_ R R R0 *0K_ *0K_ *0K_ USP- RN USP USP RN USP- USP RN USP- KX_ KX_ KX_ KX_ *KX_ XT US(PJ) LUTOOTH INT LFT US USP USP- () USP W US_P US_P W USP () () USP- W US_N US_N W USP- () () () () ().K for MP only USP USP- % pull-down to for other MP models R.K/F_ USP USP- US_RIS_ W US_P W US_N US_P US_N US0_P US0_N US_P US_N T US_RIS_ US_P Y US_N Y US_P US_N US_P US_N US_O0#/GPIO_(V_S) T US_O#/GPIO_(V_S) T US_O#/GPIO_(V_S) T US_O#/GPIO_(V_S)/MGPIO_ T US_O#/GPIO_(V_S)/MGPIO_ T USP USP- USP0 USP0- USP USP- USP USP- USO#0 USO# USO# USO# USO# USO# USO# USO# USO#0 NW R RN0 R V_S 0KX_PR 0K_ MP STRPPING H_RST# (LN) 0 MII RGMII (FULT) H_SOUT_R, LFRM# (IOS) 00 LP (FULT) 0 PI IOS 0 SPI IOS RSRV (SPI) MP_SPKR (oot MO) 0 USR TL (FULT) SF TL V_S V V V R00 R0 R R R R R R 0K_ *0K_ *.K_.K_ *.K_.K_ *0K_ 0K_ H_RST# H_SOUT LFRM# (,,,) MP_SPKR (,) () ST_TXP0 () ST_TXN0 00.0U_.0U_ T T T T T T0 ST_TXP0_ ST_TXN0_ ST_TXP_ ST_TXN_ ST_TXP G ST_TXN G ST_TXP G ST_TXN G ST_0_TX_P ST_0_TX_N ST TX_P ST TX_N ST_0_TX_P ST_0_TX_N ST TX_P ST TX_N ST ST_0_RX_P ST_0_RX_N ST RX_P ST RX_N ST_0_RX_P ST_0_RX_N ST RX_P ST RX_N G G H H F F ST_RXP ST_RXN ST_RXP ST_RXN ST_RXP ST_RXN T T T T T T ST_RXP0 () ST_RXN0 () H_SYN_R (SIO LOK) 0.MHz (FULT) MHz SPI_O, SPI_LK (SPI LOK) 00 MHz 0 MHz 0 MHz MHz V V_S V_S R R R R R R *0K_ 0K_ 0K_ *0K_ *0K_ 0K_ H_SYN MP_SPI_O () MP_SPI_LK () (,) P[..0] (,) P[..0] P[..0] P[..0] :Z timing issue, modify to P P_ P_ R.K/F_ R *0M_ ST_THRM LK_KX LK_KX P0 P P P P P P P P P P0 P P P P P Y.KHz L ST_0_TX_P L ST_0_TX_N J ST TX_P J ST TX_N J F0 I_T_P0 L I_T_P K I_T_P K I_T_P K I_T_P J I_T_P L I_T_P L I_T_P J I_T_P K I_T_P L I_T_P0 J I_T_P J I_T_P L I_T_P K I_T_P G0 I_T_P H H ST_TRMP XTLIN_RT XTLOUT_RT MP PT RT ST_0_RX_P ST_0_RX_N ST RX_P ST RX_N ST_L#/GPIO_(V) I_R_P0 I_R_P I_R_P I_S_P# I_S_P# I_K_P# I_IOW_P# I_INTR_P I_RQ_P I_IOR_P# I_RY_P L_T_P/GPIO_(V) I_OMP_PV I_OMP_.V_VT RT_RST# L K K K G H J K J J0 H0 K L0 K0 F M K N M P0 P P PIOR#_R L_T_P I_OMP_V I_OMP_V_ R VRT R RTRST# VRT 0K_ V R _ R R ST_L# () K_ /F_ /F_ PS# () PS# () PK# () PIOW# () IRQ () PRQ () PIOR# () PIORY () V RT NOT: charger : RMOV R0 VPU 0MIL 0MIL VRT_ VRT_ R K_ 0 VRT RTRST# R R RT_HG RT_HG Q 0K_ 0K_ MMT0 N RT_ONN H00H.U_ U_ H00H R R RT_HG 0MIL M_.K/F_ SM_INTRUR# () G *SHORT_ P U_ VPU R.K_ R K_ PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MP(LN/H/US/H/RT) ate: Wednesday, pril, 00 Sheet 0 of 0

U0F (,,) PWROK_ () RSMRST# elay 0ms after S powerok T0 L PWRG PWRG_S MP OF PWRGOO PUV_N MPV_N/HTV_N MM_VL PU_VL MP_VL/HT_VL M N M M P HTV_N HT_VL PU_VRON () HWPG_.V (,) PU_ORPG (,) FOR SLP MO OR POWR IRIUT () PLK_SM SM_LK0 SM_LK/MSM_LK MSM_LK () () PT_SM G SM_T0 SMUS SM_T/MSM_T F MSM_T () SM_LRT#/GPIO_(V_S) F SM_LRT# : Mount Q, unmount R () GT0 () RIN# () NSWON# () PI_WK# () KSMI# () MP_LI# () _SI# T (0) MP_SPI_O Strap pin only (0) MP_SPI_LK _SI# U_ R _ MP_LI# R 0_ T T MIL_L# T T PWRTN# RSTTN# SIO_PM# RI# MP_GPIO P MP_GPIO N MP_GPIO_I0 R MP_GPIO_I M MP_GPIO_I M0 MP_GPIO0 MP_GPIO K K R0 P H P P M P M J K K M 0GT/GPIO_(V) PU LGY SPKR KRRSTIN#/GPIO_(V) INTRUR# PWRTN# PMU SLP_S# RSTTN# SLP_S# P_WK#/GPIO_(V_S) XT_SMI#/GPIO_(V_S) SUS_LK/GPIO_(V_S) LI# SLP_RMGT# SIO_PM#/GPIO_(V_S)/SPI_S LL# RI#/GPIO(V_S) THRM#/GPIO_(V) GPIO GPIO_(V_S)/PWRN_OK/SPI_S FNTL/GPIO_(V) GPIO_(V_S)/NMI/PS_LK0 FNTL0/GPIO_(V) GPIO_(V_S)/SMI#/PS_T0 FNRPM0/GPIO_0(V) GPIO_(V_S)/SI/INTR/PS_LK GPIO_(V_S)/INIT#/PS_T THRM_SI/GPIO_(V_S)/PWR_L# THRM_SI/GPIO_(V_S) SPI_I/GPIO_(V_S) THRM_SI0/GPIO_(V_S) SPI_O/GPIO_(V_S) SPI_S0/GPIO_0(V_S) MP_VI/GPIO_(V) SPI_LK/GPIO_(V_S) MP_VI/GPIO_(V) MP_VI0/GPIO_(V) GPIO_(V)/SUS_STT/LMTR_XT_TRIG# K L R R P P N0 K F F F SUSR# SUSR# R 0_ R SUS_LK_R T0 SLP_RMGT# R PM_T# MP_GPIO SW_MP_VI SW_MP_VI0 *K_ R 0_ THRM_LRT# () T R0 R MP_SPKR (0,) SM_INTRUR# (0) SUS# () SUS# () *K_ *0_ VOR.I VOR.I0 *0_.VSUS MP_GPIO R0 00_ MP_SI R 00_ MP_SI R 00_ confirm by n-vidia F 0/ H MP_GPIO H VOR.I_R T R0 0_ H VOR.I0_R R 0_ k pull-down to on SW_MP_VI0 R K_ VOR.I () VOR.I0 () R.V_S SLP_RMGT# : Mount Q0,Q,R,R, unmount RR VPU V_S R SUS# SLP_RMGT# R0 *0_ R K_ 0K_ O0 Q0 *0_.V_RMGT Q O0 R *0_.V_RMGT Q N00 P_ P_ XTL Y MHZ XTL H XTLIN H XTLOUT MP LOK UF_SIO_LK LKOUT_MHZ J K SIO_LK T T : changed P value PU LGY PULL-UP PMU PULL-UP M/ I for "/"/" GT0 RIN# R R *0K_ *0K_ V RSTTN# PI_WK# RI# R0 R R *0K_ *0K_ *0K_ V_S V_S SM/I PULL-UP PLK_SM PT_SM SM_LRT# MSM_LK MSM_T R R R R R.K_.K_.K_ *.K_ *.K_ V_S MP_GPIO PM_T# KSMI# NSWON# SIO_PM# R R0 R R0 R0 *0K_ *0K_ *.K_ *0K_ *0K_ R 0K_ R 0K_ R IV@0K_ MP_GPIO_I0 MP_GPIO_I MP_GPIO_I MSM_LK MSM_T R R.K_.K_ V R *0K_ R *0K_ R V@0K_ HyperTransport Link. V_HT Power Valid V.V MX: R0 M_ VPU R 0K_ V R 0K_ HT_VL I0 I I M/ 0 0 0 " 0 0 X 0 0 " 0 0 " U 0 X 0 " " U R VPU 0K_ HTV_N HTV_V Q N00 Q N00 Q0 O0.V_HT MX:. 0U-.V_.V_HT R 0K_ HT_VL_R U_ HT_VL_V# Q MMT0 : HNG P FROM 0.U TO U FOR LY HT_VL Q N00 PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MP(SM/GPIO/LK/PMU) ate: Wednesday, pril, 00 Sheet of 0

.V_UL.V_PLL_SP_SS.V_HMI.V_PLL.V_PLL_SP_V.V_RMGT.V_HT_PLL.V_R.V_PLL.V_RMGT.V_PLL_M_UL V_UL.V_P.V_P.V_HT_MP.V_SP_.V_SP_.V_PLL.V_PLL.V_PLL V.V_IFP.V_PLL_IFPP.V_PLLP.V_PLLP_SS.V_US_UL.V_SP_ V V.V_HT V.V_S.V.V.V.V_RMGT.V.V_HT.V_RMGT V V V_S.V.V.V_OR.V.V.V.V_HT.V_RMGT.V.V_OR V_S.V V.V V.V.V_OR Size ocument Number Rev ate: Sheet of MP(POWR/) 0 Wednesday, pril, 00 Size ocument Number Rev ate: Sheet of MP(POWR/) 0 Wednesday, pril, 00 Size ocument Number Rev ate: Sheet of MP(POWR/) 0 Wednesday, pril, 00.V_R m V m mil / 0mil mil / 0mil mil / 0mil 0m mil / 0mil.V_HMI V mil / 0mil 00m.V_PLLP m.v_us_ul.v_sp_ mil / 0mil mil / 0mil MP POWR PLN/ & YPSS.V_PLL_SP_V mil / 0mil.V_IFP mil / 0mil m m m mil / 0mil 00m.V_PLLP_SS mil / 0mil 0m 00m MP Unused UM Power mil / 0mil m 0m.V_P m.v_rmgt.v_ul.v_ifp.v_p V_UL 0m.V_PLL_IFPP.V_PLL_SP_SS mil / 0mil m 0m.V_HMI.V_PLL_M_UL m TR WITH / SPING : 0m.V_PLL mil / 0mil mil / 0mil 0m.V_SP_ omponent.v_pll_ifpp.v_pll MP Signal Name.V_HT_PLL mil / 0mil.V_RMGT m La Lb : reserv for.v power source : HNG TO 00, L HNG TO X0U0000, R HNG TO 00 L TI00U00_ L TI00U00_ 0 0 0 0.U_.U_ R 0_ R 0_ L TI00U00_ L TI00U00_ L *TI00U00_ L *TI00U00_.U_.U_.U_.U_ L TI00U00_ L TI00U00_.U_.U_ POWR MP OF PI- ST PU UM PI- ST LN US U0 MP POWR MP OF PI- ST PU UM PI- ST LN US U0 MP.V_P V.V_P W.V_P W.V_P V.V_P Y.V_P Y.V_P Y.V_P Y.V_P Y.V_P W.V_P W.V_P Y.V.V Y.V.V.V.V W.V 0.V.V V0.V0 V.V W0.V Y0.V Y.V V.V.V.V Y0.V U.V U.V0 W.V Y.V U.V.V V.V.V.V.V W.V.V_HT Y.V_HT Y.V_HT Y.V_P W.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_ 0.V_SP_ 0.V_SP_ 0.V_SP_ 0 0 H 00 0 Y 0 0 M 0 0 0 0 U 0 0 V R 0 N G Y F V M M F 0 H M F F M G L P 0 V L P.V_PLL_PU_HT.V_PLL_PU._PLL_ISP N.V_RG_.V_TV_ F.V_IFP.V_IFP.V_HMI H.V_IFP_HV.V_HMI_PLL_HV.V_PLL_P_SS P.V_PLL_P_SS P0.V_PLL_SP_V W.V_PLL_SP_SS V.V_PLL_SP_SS R.V_PLL_LG P.V_UL_RMGT N.V_UL_RMGT L.V_PLL_M_UL N.V_R V.V_R V.V_R W.V_R W.V_UL N.V_UL N.V_PLL_P R0.V_PLL_P R.V_PLL_P_SS U.V_PLL_P_SS U0.V_UL L.V_UL L.V J.V G.V F.V H.V_US_UL Y.V_US_UL Y.U_.U_ *U_ *U_ 0.U_ 0.U_ L TI00U00_ L TI00U00_ 0 0 0.U_ 0.U_ 0 0 0 0U-.V_ 0 0U-.V_ R *0_ R *0_ 0 0 U-0V_ U-0V_ L TI00U00_ L TI00U00_ 0 0 U_ U_ 0 0 *U_ *U_ R 0_ R 0_ *U_ *U_ R 0_ R 0_ U_ U_ 0 0U-.V_ 0 0U-.V_ 00 0U-.V_ 00 0U-.V_ *U_ *U_ U_ U_ R0 TI00U00_ R0 TI00U00_ R0 TI00U00_ R0 TI00U00_ U_ U_ L TI00U00_ L TI00U00_ U-0V_ U-0V_ 00.U_ 00.U_.U_.U_ L PY00T_ L PY00T_ U_ U_ 0 0 U_ U_ 0 U-0V_ 0 U-0V_ U_ U_ L 0_ L 0_ L *0_ L *0_ *U_ *U_ L 0_ L 0_ 0.U_ 0.U_ U-0V_ U-0V_ U_ U_ Quanta omputer Inc. PROJT : ZO Quanta omputer Inc. PROJT : ZO L PY00T_ L PY00T_ *U_ *U_ R TI00U00_ R TI00U00_ * * U-0V_ U-0V_ MP OF U0G MP MP OF U0G MP J J Y Y N M J 0 U N M R R U H M H T 0 R H R G G J R T 0 T J W M R V N M 0 F N L G H N R R 0 F H P V0 J N WUS_T0 0 WUS_T WUS_T Y0 WUS_T Y WUS_T W WUS_T W0 WUS_T W WUS_T V WUS_V WUS_VRF WUS STTUS WUS_T_N WUS_PLK WUS_PHY_RST# WUS_RX_N WUS_SRIL_T WUS_STOP WUS_TX_N M K 0 N H V L 0 J 0 N G G P T J J 0 U T0 M F J G F F 0 G M R G N0 N M M 0 V J L P H L M U U0 N 0 L J J 0 J G G0 V F 0 F0 0 V J F T J Y 0 T Y P J R N T WUS_PHY_TIV.U_.U_ U_ U_.U_.U_ * * *U_ *U_ 0 0 0.U_ 0.U_.U_.U_.U_.U_ 0 *U_ 0 *U_ 0U_ 0U_ 0U-.V_ 0U-.V_ * * *U_ *U_ U_ U_ L TI00U00_ L TI00U00_.U_.U_ 0 0.U_.U_ L 0_ L 0_.U_.U_ * *.U_.U_ 0 0U-.V_ 0 0U-.V_ L V@PY00T_ L V@PY00T_ * * U/.V_0 U/.V_0 L PY00T_ L PY00T_ U_ U_

VIN N N mp 0.mp.mp 0.mp.mp V V 0.V.V 0 0 0 0 0 0 0 0 0 0 00 0 PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN PWR PI-xpress LK_RQ# PX_RST# PX_RFLK# PX_RFLK PX_RX0# PX_RX# 0 PX_RX# 0 PX_RX# PX_RX# PX_RX# PX_RX# PX_RX# PX_RX# PX_RX# PX_RX0# PX_RX# PX_RX# PX_RX# PX_RX# PX_RX# PX_RX0 PX_RX PX_RX 0 PX_RX PX_RX PX_RX PX_RX PX_RX PX_RX PX_RX PX_RX0 PX_RX PX_RX PX_RX PX_RX PX_RX PX_TX0# PX_TX# PX_TX# 0 PX_TX# 00 PX_TX# PX_TX# PX_TX# PX_TX# PX_TX# 0 PX_TX# PX_TX0# PX_TX# PX_TX# PX_TX# 0 PX_TX# PX_TX# PX_TX0 0 PX_TX PX_TX 0 PX_TX 0 PX_TX PX_TX 0 PX_TX PX_TX PX_TX PX_TX PX_TX0 0 PX_TX PX_TX PX_TX PX_TX PX_TX 0 SPIF/I PRSNT# PRSNT# PG_RXN0 PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN0 PG_RXN PG_RXN PG_RXN PG_RXN PG_RXN PG_RXP0 PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP0 PG_RXP PG_RXP PG_RXP PG_RXP PG_RXP PG_TXN0 PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN0 PG_TXN PG_TXN PG_TXN PG_TXN PG_TXN PG_TXP0 PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP0 PG_TXP PG_TXP PG_TXP PG_TXP PG_TXP P0_PRSNTX_R PI_RST# () LK_MXM# () LK_MXM () PG_RXN[:0] () PG_RXP[:0] () PG_TXN[:0] () PG_TXP[:0] () N pin "" for S/PIF input.an unconnected to R R 0_ *0_ P0_PRSNTX () (,) (,) () V_LVS_LLK# () V_LVS_LLK () V_LVS_LTX#0 () V_LVS_LTX# () V_LVS_LTX# () V_LVS_LTX0 () V_LVS_LTX () V_LVS_LTX () V_LVS_VN () V_LVS_LON () V_LVS_LK () V_LVS_T () V_RT_HSYN () V_RT_VSYN () V_RT_R () V_RT_G () V_RT_ () V_RT_LK () V_RT_T () V_TV_Y/G () V_TV_/R MT V MLK LVS_ULK# 0 LVS_ULK LVS_UTX0# LVS_UTX# 0 LVS_UTX# LVS_UTX# LVS_UTX0 LVS_UTX LVS_UTX LVS_UTX LVS_LLK# 0 LVS_LLK 0 LVS_LTX0# LVS_LTX# 0 LVS_LTX# LVS_LTX# 0 LVS_LTX0 LVS_LTX LVS_LTX LVS_LTX LVS_PPN LVS_LN LVS_L_RGHT 0 _LK 0 _T VG_HSYN VG_VSYN VG_R 0 VG_GRN VG_LU _LK _T TV_Y/HTV_Y/TV_VS TV_/HTV_Pr () V_TV_OMP TV_VS/HTV_Pb LVS RT TV VI- VI VI- IGP & RSV VI LK# 0 VI LK 0 VI TX0# VI TX# VI TX# VI TX0 VI TX VI TX VI HP 0 _LK 0 _T Remove IGP/VI LK# IGP/VI LK IGP/VI TX0# 0 IGP/VI TX# IGP_/VI TX# IGP/VI TX0 0 IGP/VI TX IGP_VI TX VI HP/ IGP T IGP IGP T IGP T T IGP T IGP IGP T IGP T0 T IGP IGP T IGP T T RSV RSV RSV RSV RSV RSV R V@0_ () THRM_LRT_VG# R *V@0_ THRM# RUNPWROK MT_MXM MLK_MXM SM_T /TT# R *.K_ Q V@N00 SM_LK V@S PWROK_MXM () PWROK_ (,,) V IN (,) MXM_ONN_RVS R : for MXM power up sequence, use PWROK_ to MXM PWROK, Mount R V@.K_ Q V@N00 R V@.K_ VIN V 0 0 0 0 V@.U-V_ V@.U-V_ V@.U-V_ V@.U/V_ V@U_ V@ V.V.V V@0U-V_ V@ V@U_ V@ V@0U-V_ V@ MXM_ONN_RVS PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MXM Wednesday, pril, 00 ate: Sheet of 0

LVS SINGL_H () INT_TXLLKOUT- () INT_TXLLKOUT () INT_TXLOUT0- () INT_TXLOUT0 () INT_TXLOUT- () INT_TXLOUT () INT_TXLOUT- () INT_TXLOUT () V_LVS_LLK# () V_LVS_LLK () V_LVS_LTX#0 () V_LVS_LTX0 () V_LVS_LTX# () V_LVS_LTX () V_LVS_LTX# () V_LVS_LTX lose MXM ONN IV@0X_ RN IV@0X_ RN IV@0X_ RN IV@0X_ RN0 V@0X_ RN V@0X_ RN V@0X_ RN V@0X_ RN dison-- 0 Modify the LVS pin difinition TXLLKOUT- TXLLKOUT TXLOUT0- TXLOUT0 TXLOUT- TXLOUT TXLOUT- TXLOUT N TXLOUT0 L_ILK TXLOUT0- L_IT TXLOUT TXLOUT- 0 0 VIN_L TXLOUT TXLOUT- L_ON L_ON () RIGHTNSS TXLLKOUT 0 TXLLKOUT- 0 V (0) USP- L_V (0) USP 0 _PWR 0 _PWR ON0X_0 RIGHTNSS VIN.U-V_ R *0_ R 0_ R0 0_ VIN_L 000P-V_ L_KLT_TRL () _L_KLT_TRL () () V_LVS_LK () INT_LVS_ILK () V_LVS_T () INT_LVS_IT R R R R V R.K_ V@0_ L_ILK IV@0_ V R.K_ V@0_ L_IT IV@0_ L POWR V _PWR MR MOUL POWR V lose to ONN N R 0_ () () INT_LVS_IGON V_LVS_VN R R <demo circuit> restline suggest 00K G suggest 0K(ZS efault) IV@0_ Unstuff R for V_LVS_VN signal V@0_ ISP_ON R IV@0K_ U IN IN ON/OFF T0 OUT LV_ R 0_ 0U-.V_ 0.0U_ L_V 0U-.V_ Q 0U-.V_ *O 000P_ : unstuff Q, mount R for saving Q V R US UR'S SUGGSTION, *.K_ TI HNG FROM TO HIGH. onfirm by Joms Q *TU _POWRON () RT lose MXM ONN V NHW RTV N () V_RT_R () V_RT_G () V_RT_ () V_RT_HSYN () V_RT_VSYN R R R R R V@0_ V@0_ V@0_ V@0_ V@0_ SYS_VG_R SYS_VG_GRN SYS_VG_LU HSYN VSYN R 0/F_ R 0/F_ R0 0/F_ 0P_ 0P_ 0P_ L L L K0LL0_ K0LL0_ K0LL0_ 0P_ 0 0P_ RT_R RT_G RT_ 0P_ 0 RT_ONN T_ RTHSYN RTVSYN LK_ RTV RTVSYN *0P_ RTHSYN *0P_ () V_RT_LK R V@0_ RTLK LK_ 0P_ () V_RT_T () INT_RT_R () INT_RT_GRN () INT_RT_LU () INT_HSYN () INT_VSYN R R R R R R V@0_ IV@0_ IV@0_ IV@0_ IV@0_ IV@0_ RTT V V RTV.U_ : dd,, for MI solution U V_SYN V_ YP V_VIO SYN_OUT SYN_OUT SYN_IN SYN_IN VSYN HSYN VSYN HSYN L L LM0SN_ LM0SN_ RTVSYN RTHSYN R 0_ RTV RT_SNS# () T_ 0P_ () INT_RT_LK () INT_RT_T R0 R IV@0_ IV@0_ SYS_VG_R SYS_VG_GRN SYS_VG_LU VIO_ VIO_ VIO IN _IN _OUT _OUT 0 RTLK RTT LK_ T_ R R.K_.K_ V R.K_ R.K_ M00 TV Out (SVHS) MiniIN -pin R0 V@0_ SYS_TV_Y/G () V_TV_Y/G R V@0_ SYS_TV_/R () V_TV_/R R V@0_ SYS_TV_OMP () V_TV_OMP : hange L,L,L0 P/N L0 SYS_TV_/R R N0 K0LL0_ S_VIO L K0LL0_ TV-HROM TV-LUM SYS_TV_Y/G R Remove HMI () INT_TV_Y/G R IV@0_ 0/F_ P_ P_ P_ P_ 0/F_ () INT_TV_/R R IV@0_ () INT_TV_OMP R IV@0_ S Protect TV-OMP L K0LL0_ SYS_TV_OMP V V V R P_ P_ 0/F_ TV-OMP *0U TV-HROM *0U TV-LUM *0U PROJT : ZO Quanta omputer Inc. Size ocument Number Rev LVS/RT/TV-OUT/HMI Wednesday, pril, 00 ate: Sheet of 0

LN (0) LN_RXLK_R R _ LN_RXLK *P_ *P_.V_RMGT R R R R R 0_ (0) (0) *.K_ *.K_.K_.K_ MLK MIO LN_TXLY LN_RXLY LN_LK (0) (0) (0) (0) (0) LN_RX0_R LN_RX_R LN_RX_R LN_RX_R LN_RXTL_R.V_RMGT R 0_ R 0_ Q *N00.V_RMGT Q *N00 (0) (0) (0) (0) (0) (0) R _ LN_RX0 R _ LN_RX R _ LN_RX R _ LN_RX LN_RXLK R _ LN_RXTL LN_RXLY LN_TX0 LN_TX LN_TX LN_TX LN_TXLK LN_TXTL T *P_ Y *MHZ *P_ LN_TXLY LNPHY_MI0 LNPHY_MI0- LNPHY_MI LNPHY_MI- LNPHY_MI LNPHY_MI- LNPHY_MI LNPHY_MI- LN_TX# LN_RX# LN_GLINK0# LN_GLINK00# LN_GLINK000# MLK- MIO- LN_LK LN_GXTL LN_GXTL R *M_ 0 0 0 0 U m RX0 V0 RX V RX V RX V V RXLK V RX_TL RXLY V0 TX0 V TX TX TX TRL TXLK V0 TX_TL V TXLY V V MI0 MI0- MI V0 MI- MI MI- TRL MI MI- V0 V L_TX# V L_RX# V L_UPLX# L_LINK0# L_LINK00# ONFIG0 L_LINK000# ONFIG ONFIG MLK ONFIG MI/O ONFIG RS/ONFIG LK OL/ONFIG INT/ONFIG XTL ONFIG ONFIG RTL 0/00/000--LN PHY 0 0 PHYRST RST XTL.V_RMGT V_LN TRL V V V V V TRL V V V V 0 0 0 LN_FG0 LN_FG LN_FG LN_FG LN_FG LN_GRS LN_GOL LN_INT LN_FG LN_FG LNRST# LN_RST R LN_INT (0).K_ LN_FG0 LN_FG R.K_ LN_FG R.K_ LN_FG R0.K_ LN_FG R0.K_ PHY ddress:0000 LN_GRS LN_GOL LN_INT LN_FG LN_RS LN_OL LN_INT ONFIG LN_FG :RGMII/MII TO OPPR MIO LNRST# R R R R R0 R auto-na auto-na auto-na auto-na.k_ NVidia=.K Realtek=0K R R0 R 0_.K_.K_.K_.K_.K_.K_ *0K/F_ *R00.V_RMGT.V_RMGT dvertise ll apabilities, Prefer Slave.V_RMGT.V_RMGT.V_RMGT MIIRST# (0) (0) MII_MHZ R 0_ RTL.V_RMGT.V_RMGT :L HNG TO PY00T-00Y-N,(00) L PY00T-00Y-N V_LN. TRL.V_RMGT Q SK TRL.V_RMGT Q SK RJ- RINGL TIPL N RING TIP.V_RMGT 0 0 V m 0U-.V_ 0U-.V_ V 0U-.V_ 0m.V_RMGT.V_RMGT R 0_ R 0_ LN_LINKL# LN_V LN_V LN_TL# 0 L_GRN L_P_ L_ORNG L_YL L_P_ 0P_ 0 LN_MX0 LN_MX0- TX/0 TX-/0- Transformer NS0:GIGIT U LNPHY_V_0 LN_MT0 TT MT LNPHY_MI0 LN_MX0 T MX LNPHY_MI0- LN_MX0- T- MX- LNPHY_V_ LN_MT TT MT LNPHY_MI LN_MX T MX 0 LNPHY_MI- LN_MX- T- MX- LNPHY_V_ LN_MT TT MT L onfiguration L_LINK000 L_TX Set Register ontrol it= =LINK UP (NY SP) LINKING=TRNSMITTING OR RIVING : MI solution 0P-KV_0 0P-KV_0 TIPL RINGL LN_MX LN_MX LN_MX- LN_MX- LN_MX- LN_MX N FI_SP_HF_J RX/ N/ N/- RX-/- N/ N/- RJ-&RJ- LNPHY_MI T MX LN_MX LNPHY_MI- T- MX- LN_MX- LNPHY_V_ 0 LNPHY_MI TT T MT MX LN_MT LN_MX R 0_.0U_.0U_.0U_ LNPHY_MI- LN_MX- T- MX- NS0 0.0U_ : MI Solution R _ R00 _ R _ R _ LN_TX# LN_RX# LN_GLINK0# LN_GLINK00# LN_GLINK000# *R00 *R00 *R00 *R00 *R00 LN_TL# LN_LINKL# LNMT_G 000P-KV_0 R 0_ 0 0P_ : MI solution PROJT : ZO Quanta omputer Inc. Size ocument Number Rev RTL (GigaLN) Wednesday, pril, 00 ate: Sheet of 0

V_S (,) USON# U IN OUT IN OUT OUT N# - O# TPS0GNR R *.K/F_ USPWR 00U-.V_ 000P_ U VR_IRM-V0/TRI-P IRRX_ IR R R /F_ */F_ V_S V_S LI SWITH : H/W Solution V (0) (0) (0) (0) USP0- USP0 USP- USP R 0_ *RFM00M L R 0_ : Hanged to 00 R0 0_ *RFM00M L R0 0_ USPWR 00U-.V_ US M port USP0-_R USP0_R 0 USP-_R USP_R N SYUIN_US 0 000P_ N SYUIN_US LFT US LFT US IRRX_ IRRX_ Q Q *MMT0 O# V R0 0_ V_S R *.K_ Y *NSZPX V_S R *.K_ IRRX IRRX () S check MPLI# power VPU nda GPIO list have internal PU R *0K_ SS *SS R 0_ R 0_ 0 VSUS R *0K_ R 00K_ R V@0K_/IV@.K_ SS R0 V@0_ R IV@0_ Q TU L_ON () MP_LI# () LI# () LI# () V_LVS_LON () INT_LVS_LON () _FPK# () H h-tcbcdp PU H h-tcbcdp H h-tcbcdp H h-tcbcdp M H H H-TP H-TP LUTOOTH MOUL ONNTOR MXM VSUS V_S () T_POWRON# MINI ard FN : dd a Hole H0 H H0 h-cdp H-N H-N : dd MI solution (0) (0) () USP USP- T_L P *MIP : Mount MI solution H H H H H H0 h-tcbcdp h-tcbcdp h-tcbcdp h-tcbcdp h-tcbcdp h-tcbcdp H h-cd0p- H h-cd0p- H h-cdp- P0 P P *MIP *MIP *MIP R 0_ R 0_ H h-cd0p- H h-cdn H H-P- N T_ONN P *MIP P *MIP P *MIP T_POWR USP_R USP-_R T_L 0.P_ P *MIP P *MIP Q O 0 000P_ T_POWR 0U-.V_ 0 H H-P- H H-N H H-P- P *MIP P *MIP P *MIP H h-cd0p- H H-P- H h-cdp H H-P- H H-P H H-P-.P_ H h-cd0p- H H-P- H H-P- H h-cd0p- P *MIP PROJT : ZO Quanta omputer Inc. Size ocument Number Rev US/LUTOOTH//IR ate: Wednesday, pril, 00 Sheet of 0

MINI-ard VSUS V : Modify net to close device side. V L K0LM-T_ If M.P must N all debug R L0 K0LM-T_ R R0 VMINI WS_LKR : add 0 for MI request. () 0 0P_ PI_WK# VSUS R0 *.K_ (,0,,) SRIRQ () LRQ#0 (,,) LP_RST# () PI_LK_UG () () () () () () () PI_TXP PI_TXN PI_RXP PI_RXN LK_PI_MINI LK_PI_MINI# MINI_LKRQ# R 0_ R 0_ R 0_ R 0_ R 0_ SRIRQ_RR LRQ#0_RR WS_TR WS_LKR MINI_RQ_LK N PTp0 PTn0 PRp0 PRn0 RFLK RFLK- LKRQ# WK#.V 0.V L_WPN# L_WLN# L_WWN# 0 US_ US_- SM_T SM_LK 0.V.Vaux PRST# 0 0.V.V.V VMINI VSUSMINI 0_ R *0_ RF_L# 0 S RP 0X_ RP 0X_ R 0_ *00U-.V_ *0_ T RF_L# () USP (0) USP- (0) PT_SM () PLK_SM () PI_RST# () RF_N () LFRM# (,0,,) L (,,) L (,,) L (,,) L0 (,,) 0 VSUSMINI *.V 0 0 0.U_ Q *TU MINIPI ONN_WL Need reserve G pin define heck Footprint New card : dd R for NW card PP# () PP#_ R 0_ PP# N NW R'S POWR SWITH NW_V PI_WK# V_S R 0_ () () Q *TU () () () () PI_TXP PI_TXN PI_RXP PI_RXN LK_PI_NW_ LK_PI_NW_# () PP# () NW_LKRQ# (0) (0) USP USP- NW_V PRST# NW_VUX NW_.V NW_SMT NW_SMLK PUS# R 0_USP_R R 0_USP-_R 0 0 PTp0 0 PTn0 PRp0 PRn0 RFLK RFLK- PP# LKRQ#.V.V PRST#.VUX WK#.V.V SM_T SM_LK RSRV RSRV PUS# US_ US_- 0 U TPSPWG NW_V V.VIN.VOUT.VIN.VOUT V_S NW_VUX UXIN UXOUT.V NW_.V.VIN.VOUT.VIN.VOUT PI_RST# SYSRST# STY# PP# SHN# PP# PUS# PUS# RLKN PRST#_R PRST# R0 N 0 O# 0 PP# : ( Internal Pull Up, active low when card support PI ) PUS# : ( Internal Pull Up, active low when card support US ) SHN# : ( Internal Pull Up ).K/F PRST# 00P_ PT_SM PLK_SM Q N00 NW_V Q0 N00 RP0.KX_ NW_SMT NW_SMLK XPR-FOXONN V_S V.V NW_VUX NW_V NW_.V 0 0 00.U_.U_ PROJT : ZO Quanta omputer Inc. Size ocument Number Rev MINI PI- card & NW R Wednesday, pril, 00 ate: Sheet of 0

ST H TP SWITH N0 RXP RXN TXN TXP ST_RXN0_.0U_ ST_RXP0_.0U_ ST_TXP0 (0) ST_TXN0 (0) ST_RXN0 (0) ST_RXP0 (0) LFT# RIGHT# SW MISKI_SWITH_. SW SR_N# SR_LFT# SW MISKI_SWITH_. SW.V.V.V 0 V V V RSV V 0 V V ST-H.VST R HV *0_.0U_ V.0U_.VST HV *.U_ 0.U_ *.U_ R 0_ * V 00U-.V_ () () TPT TPLK SR_UP# TP ONN MI near N TPT TPLK MISKI_SWITH_. SW R R MISKI_SWITH_..K_.K_ L L0 P_ P_ : dd MI solution V SR_RIGHT# MISKI_SWITH_. SW MISKI_SWITH_. mil L KP0HST. TP_V V N LZ0-0MT 0. TPT_R LZ0-0MT 0. TPLK_R RIGHT# SR_RIGHT# SR_UP# SR_LFT# 0 SR_N# 0 LFT# TOUH_P_TP_P O (PT) (0,) P[..0] V V V V (0,) P[..0] R 0K_ R *0K_ R 0K_ R.K_ R.K_ IRQ P PRQ PIORY () () IRST# IL# TU Q R0 *0_ V R 0K_ (0) (0) (0) (0) R 0K_ PIOW# PIORY IRQ PS# 0 000P_ N IRST#_R P P P P P P P P0 PIOW# PIORY IRQ P P0 PS# V_O RSL R 0 0 0 0 0 0 0 0 0 0 P P P0 P P P P P PRQ PIOR# PK# PIG# R P PS# V_O PRQ (0) PIOR# (0) PK# (0) *0K_ PS# (0) 00mil V L 0_ 00U-.V_ V 0_ O_ONN PROJT : ZO Quanta omputer Inc. Size ocument Number Rev ST-H & PT-O ate: Wednesday, pril, 00 Sheet of 0

O(L) V L V_O INT MI array R 0_ O MI-VRFO-R MI-VRFO-L L_VRF R0 R 0U_.K_.K_ MI_R MI-VRFO MI_L O TI00G R 0U-.V_ *0_ V VN O U VN VIN 0U-.V_ *G-JTU VOUT J R *K_ N0 MI_INTL INT_MI *P_ O R.K_ MI-VRFO SPK OUT O O V_O SPIFO HP Jack R00 FRONT-L FRONT-R 0K/F_ L_JRF P L SPIF_OUT_ K00LL 0. 0 SURR-L SURR-R U FRONT-R MONO-OUT V SURR-L JRF SURR-R VSS N N N MI-LK P SPIFO V FRONT-L MI-//GPIO0 Sense MI-//GPIO N L VSS MI-VRFO-R ST-OUT GPIO IT-LK MI-VRFO 0 VSS LIN-VRFO ST-IN MI-VRFO-L V VRF SYN 0 VSS RST# V_O V PP LIN-R LIN-L MI-R MI-L -R 0 - -L MI-R MI-L N N Sense LIN-R LIN-L MI-R MI-L MI_INT_R MI_INT_L :hanged, to.u SNS.U_.U_ U-V_ U-V_ U_ U_ LIN-R_ LIN-L_ MI_R MI_L MI_INTL O(L) Power () () O IGVOL_N IGVOL_UP V_V Vo=.*(RR)/R=.V MI_L MI_R LIN-L_ LIN-R_ SPIFO SNS HPR HPL 0 0 O N 0 0 SW-0P R *K_ R 0_ R 0_ R 0_ 000P_ 000P_ 000P_ O O : add, for MI request. V_V R R R R R *0K_ 0K_ *0K_ *0K_ *0K_ R R R R R 0K_ *0K_ 0K_ 0K_ 0K_ O R *0K_ G_Lv G_Lv G_ttack G_ON/OFF G_Recovery G_Recovery R 0K_ V R0 0_.V R0 *0_ Z_V 0U-.V_ V 0U-.V_ 0 Z_SIN PP Z_V R0 _ H_RST#_O (0) H_SYN_O (0) H_SIN0 (0) G-attack-time selection G_ttack ( pin) ttack time ms ms G ON/OFF selection G_ON/OFF ( pin) G ON/OFF ON OFF G-recovery-time selection G_Recovery (0 pin) G_Recovery ( pin) Recovery Time.0 s.0 s.0 s.0 s G-on-level selection G_Lv ( pin) G_Lv ( pin) G ON Level Output Po (RL= ohm). dv. W.0 dv.0 W. dv 0. W.0 dv 0. W 0P_ R0 0_ 0P_ H_ITLK_O (0) V_V O V_O H_SOUT_O (0) : MI Solution : hange power to VSUS SP_STY ON/OFF & HP_STY ON/OFF.V SP_STY ( pin) SP_STY ( pin) SP_STY ON/OFF ON M N R0 *0_ M VSUS OFF R 0_ OFF RSV OFF (0) H_SOUT_M _SO RSV.V VSUS HP_STY ( pin) HP_STY ( pin) HP_STY ON/OFF (0) H_SYN_M R _ H_SIN_M _SYN ON (0) H_SIN _SI 0 OFF (0) H_RST#_M _RST# _LK H_ITLK_M (0) OFF OFF 0 R 0P_ 0_ FRONT-L U_ FRONT-L- SPK eep L L L L PP K0LL_ K0LL_ K0LL_ K0LL_ : MI Solution INSPKR-N INSPKRN INSPKL-N INSPKLN *P_ U_ P_ 00P_ *P_ R0 R0 K_ *P_ O 0K_ : MI Solution N SPKR_H. *P_ 0P_ MP_SPKR (0,) SPK () V () FRONT-R MP_MUT# MUT FUNTION P HP_MUT# *0U-.V_ R 0_ U_ 0U-.V_ FRONT-R- R V V R U U *0_ R R TSH0FU TSH0FU *0_ V_V O 0 U_ 0K_ 0K_ O U_ R R MUT_SPK MUT_HP 0 U_ G_Lv G_Lv G_ttack G_ON/OFF G_Recovery G_Recovery FRONT-L- 0K_ 0P_ PROUT-L FRONT-R- 0K_ 0P_ PROUT-R U_ V_O O U_ 0 U G_Lv G_Lv G_ttack G_ON/OFF G_Recovery G_Recovery SP_INL PROUT_L SP_INR PROUT_R VRFSP N N 0 V SP_STY SP_STY HP_STY HP_STY U_ V_P Panasonic _P 0 O V_HP N _SPL U_ Test _SPR Test Test Test P P P P_ V_SPR V_SPL P_ VSS_P SP_OUTL SP_OUTL SP_OUTL SP_OUTL SP_OUTR SP_OUTR SP_OUTR SP_OUTR HP_OUTL P P P P P P 0 VSS HP_INL 0 HP_INR HP_OUTR P 0 P P N HPINR U_ U_ INSPKL INSPKR- INSPKL- INSPKR- INSPKR INSPKL- INSPKL O INSPKR and R change from 0kohm to 0kohm HP HPL R 0K_.U_ HPINL R 0K_ SURR-L SURR-L R R P_ 0K_ 0K_ SURR-R HPR.U_ P -- ISOLT Richard 0/ -- Modify P to P_~ SURR-R PROJT : ZO Quanta omputer Inc. Size ocument Number Rev RLTK L & M Wednesday, pril, 00 ate: Sheet of 0

V U R : J0H R : J0H0 VSUS IN R RR RRR POWR 0 VSUS V_PI V_V 0 V_X V_X V_PI V_PI N 0U_.0U_.0U_ V_PI.0U_ 0U_ VSUS V_PI X_0/MS_0/S_0 ()S-V Q R V_PI X_/MS_/S_ ()S-T0 X_/MS_/S_ ()S-T 0 X_/MS_/S_ ()S-T ()X-V N00 0K_ Q V_RIN M_PWR_TRL_0# V_ROUT_ X_R#/LK ()S-T X_Z V_ROUT X_W#/MS_S/S_M ()S-LK ()X- X_R/#/S_WP# S_Z ()S-M ()X-R/ O0 0U_.0U_.0U_ V_ROUT X_R#/LK 0 V_ROUT X_R/#/S_WP# S- ()X-R X_#.0U_.0U_.U_.U_ V_ROUT S-WP ()X- 0 X_L V_ROUT ()X-L X_L 0mil V_X ()X-L V_X X_W#/MS_S/S_M M_PWR_TRL_0 V_M ()X-W X_WPO# ()X-WP R X_0/MS_0/S_0 (,) [..0] X_0/MS_0/S_0 ()MS-V (0)X-0 X_/MS_/S R.U_ X_/MS_/S R ()MS-T0 ()X- 0K_ X_/MS_/S R 0 0 X_/MS_/S R ()MS-T ()X-.0U_.0U_.0U_ X_/MS_/S_ 0 X_/MS_/S_ ()MS-T ()X- X_ X_R#/LK ()MS-T ()X- X_ MS_Z ()MS-SLK ()X- 0 X_ X_W#/MS_S/S_M ()MS-INS ()X- X_ VSUS ()MS-S ()X- U M_PWR_TRL_0 0 ()S/()MS/()X- SIO- IN N VSUS ()S/(0)MS/()X- SIO- 0 V_X 0 0 R_RR_TTN_R0-0-XX- IN VO 0 When HWSPN# is RQ# 0 *U_ *GTU GNT# INT#,# controlled by system, the R 0K_ pull-up resistor(r0) dose not need to apply. R 0/F_ PM_ISL 0 0 _SUS# V_X V_X 0 HWSPN# VSUS N X_0/MS_0/S_0 S-V PowerOnReset for Vccore MSN R 0K_ X_/MS_/S_ S-T0 X_/MS_/S_ S-T When GRST# is controlled by system, XN R 0K_ X_/MS_/S_ S-T X-V 0 R 00K_ X_R#/LK S-T X_Z the pull-up resistor(r0) and X_W#/MS_S/S_M S-LK X- X_R/#/S_WP# capacitor(0) do not need to apply. 0 UIO R *00K_ S_Z S-M X-R/ X_R#/LK PR 0 X_R/#/S_WP# S-/ X-R X_# () PR : pin pull-up can saving the # PR SL_R S-WP X- X_L () # # /# UIO S_R PROM, remove R, stuff R X-L X_L VSUS () # # /# UIO S-VSS X-L X_W#/MS_S/S_M () # PLK_PM 0# /# S-VSS X-W X_WPO# (,) 0# 0 PM_ISL /0# UIO S- X-WP R ISL X_0/MS_0/S_0 UIO 0 X_0/MS_0/S_0 MS-V X-0 X_/MS_/S R () RQ0# RQ# X_/MS_/S R MS-T0 X- 00K_ X_/MS_/S R () GNT0# SRIRQ (,,,) FRM# X_/MS_/S R MS-T X- 0 R GNT# UIO0/SRIRQ# X_/MS_/S_ () FRM# 0 GRST#_ IRY# FRM# X_/MS_/S_ MS-T X- X_ () IRY# TRY# X_R#/LK MS-T X- *_ IRY# X_ () TRY# VSL# TRY# MS_Z MS-SLK X- X_ () VSL# STOP# VSL# X_W#/MS_S/S_M MS-INS X- X_ () STOP# INT# () PRR# STOP# INT# MS-S X- 0 () PRR# 0 U_ SRR# PRR# () SRR# SRR# INT# INT# () 0 *P_ MS-VSS GRST#_ MS-VSS XG- PIRST# GRST# X- () PIRST# PIRST# () RT_V00 L U _V : changed P value K0HS0_ TPIS0 V_PHY R _XIN V_PHY 0 0_ V_PHY 0 R R0 XI 000P_ P_ V_PHY 0U_.0U_ Q.U_.0U_ Y TPIS0 X_/MS_/S R X_/MS_/S_ TPIS0./F_./F_.MHz TP0N X_/MS_/S_ TPN0 0 TP0P _XOUT TPP0 0 TP0N XO TPN0 0 *N00 TP0P TPP0 0 R *0K_ *L-M0-00JT P_ V X_ FIL0_PWR MIO X_ FIL0 MIO L X_ *.0U_ MIO X_ Q S LOS S TP0P L_TP0 MIO X_/MS_/S_ S_Z POSSIL TO TP0N L_TP0- RXT MIO 0 R 0 X_/MS_/S R *N00 RN 0X_ RXT MIO R X_/MS_/S R TP0P L_TP0 MIO RN 0X_ 0K/F_ X_0/MS_0/S_0 TP0N L_TP0- MIO0 0 VRF_PWR 00 X_WPO# VRF MIO0 X_W#/MS_S/S_M OMMON MO HOK MIO0 Q R0 R L.0U_ X_L X_/MS_/S R MIO X_L NR ONN. MIO X_# MIO0./F_./F_ S LOS S POSSIL TO X_R/#/S_WP# _OM MIO0 *N00 *L-M0-00JT R R and GUR S_Z X_Z VSUS R MIO00 0 R 0_ S MS_Z MIO0 0P_ S 0K_.K/F_ MS_S_LK X_R#/LK MIO0 R./F_ M_PWR_TRL_0 MIO0 TP_X_L# X_R#/LK should MIO0 T RSV MIO0 shield. N > ms >0 ns PROM L_TP0- L_TP0- RT_V00 0 0P_ L_TP0 MS_S_LK VSUS * NOT Use PROM : L_TP0 R0 : installed V R0,U,0 : NOT installed : MI Solution * Use PROM : R0,U,0 : installed GRST# R0 R _ONN R0 : NOT installed PRST# > 00 ns lose to ONN. 0K_ 0K_ U S_R S_Z MS_Z SL_R S 0 SL VSUS WP HWSPN# *0P_ *0P_ PROJT : ZO V PLK(MHz) PI_PM# () (,) PLK_PM R LKRUN# *0_ PLK_PM LKRUN# 0 PILK PM# LKRUN# PI / OTHR I/S TST Reduced external noise by F confirm VSUS Reserve MS UO card issue *L0 * : Remove U, PROONN-MXP0-0-00-N Quanta omputer Inc. Size ocument Number Rev R/(IN/) Wednesday, pril, 00 ate: Sheet of 0 0