QUANTA COMPUTER. Page Title of schematic page Rev. Date
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- Νικόλαος Αγγελοπούλου
- 7 χρόνια πριν
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Transcript
1 Page of schematic page Rev. ate Index lock iagram hange ist OK NRTOR PROSSOR /(MI&HOST&PI) PROSSOR /(R) PROSSOR /(POWR) PROSSOR /() PH / (MI&VIO) PH / (ST/P/zalia) PH / (PI/PI/K/US) PH / (PIO) PH / (POWR) R IMM RT/VS WN/XPRSS R WP & FSH ocking/00/tp/tpm/t H/O/amera/MI K/US/FN/Reset HMI onn/evel shift POWR PU OR (IS) POWR VPU&VPU(PM) POWR.VSUS/VTT_MM POWR V.0(OZN)- POWR V_FXOR(MX0) POWR V. POWR HRR (IS) 0 POWR(PTR IN / ONN) RU udio /Modem/uttom theros M * : No for HMI evel shift for HMI evel shift PS QUNT OMPUTR Page ist Size ocument Number Rev ustom TW Main oard ate: Monday, ugust, 00 Sheet of
2 TW lock iagram.mhz PU rrandale R 00/0.V UNUFFR R SOIMM P OK N ISRS0 R 00/0.V UNUFFR R SOIMM P P PIN (micro F-P) HMI RT ocking P P VI P P P-P S Puma Peak x N(Intel WiFi ink 00) Kilmer Peak x N(Imtel WiMX/WiFi ink 0) WN Module Intel : Puma peak/kilmer Peak theros : H or P # TMS VS R// TMS FI interface MI(X) MS RJ MS/S RU P0 N iga theros RM P # # PI PH Ibex Peak-M HM/HM zalia ink P ocking N Marvell 0 P # mm x mm P-P xpressard/ P # # M IOS M P0 US./.0 ST Port 0 ST Port TPM P.V P,MHZ MI. Jack P MOM P0 udio Jack P INT.SPKR. P igital MI Knowles SPM00HH P # # US Slot * P0 Finger Print TS P xpressard * P ST H * P ST O * P PU WP P lue Tooth TH. P amera ocking US HU P P TOUH P T/P SWITH P INT.K/ P0 SPI IOS M P PS/NUM/SR Wireless/WWN/T Power/Speep ight Sensor TOS TSFN P SM US Sensor IS P xpressard H MS/S US ON* harge PI- * P utton POWR Wireless SW.evel nvironment-related Substances Should NVR be Used..Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. P-SW/MUT-SW/O P
3 0 P-hange from no-mount to mount -P elete R 0 ohm. -P elete R 0 P-hange 0 from 0.u to U -P dd Q,R,R0,R,R for RMRST# 0 P- hange from U to 0.0U -P R change power from.vsus to RMPWR_PU 0 P-dd 0.0u -P R change value from.k/f to.k/f(for S power) -P R change value from K/F to 0/F.(For S) 0 P0-el R -P dd U,,R. (For S power) 0 P-hange r,r from no-mount -P U.F change to RMRST_PU# to mount -P mount 0UF(Reduce ripple) -P VQ power change to V._PU 0 P-hange RP from PR to 00 -P U.J U.H delete net "R_VRF_Q0""R_VRF_Q" x for MI issue. -P el R 0ohm 0 P-dd for leakage on mode -P0 Y change footprint -P0, change P to P(H000) 0 P0- hange Y pin define -P0 change R0-0 to use only sw00pt. (For VPU 0 P- dd R bypass option leakage) 0 dd ~ for S power reduction.0 -P hange WN PI port from port to port -P hange xpressard PI port from port to port 0 P- hange T_PRS# from IOP to PIO -P hange, from P to.p and pull up to RV -P U.F change to RMRST_NTR_PH. 0 P- Pull up to V for PIO -P R change from to RV 0 isolation power plan for H,H,F -P, change to TK MK00NJ(change footprint) -P dd 0U on net V_V. -P elete R,R,R0 0 ohm.(save cost) 000 hanged PR to 0K for OP function. -P elete R 0_.(save cost) -P Mount, uf. 000 lijah changed P to 000P. -P el R,R0,R,R 000 lijah added the V._PU_V0_PWR circuit -P change SMR_VRF_Q0 to SMVRF_MH sets. -P el R,R -P el SMVRF_MH net -P change SMVRF_MH to SMVRF_MH 0 P-hange to F. fuse -P hange SMR_VRF_Q to SMVRF_MH -P el R,R 0 P-dd R0 serial on IRQ_SRIRQ -P el,0(save cost) -P hange R,R from.k to.k(solve RT VVS) -P hange,, from no-mount to mount.(solve RT R,, oversheet issue) -P dd R 00k pull down for dispon -P dd R, R.K for SMUS -P dd R0 00K.(For idle mode save power) -P hange R0V-0 to SW00PT -P dd R,R 0ohm -P el R,R,R -P hange from no-mount to mount -P dd R 0K pull high to RV -P hange PR from no-mount to mount for pull high RV on PM_SYS_PWR -P,0,,,,,,,,, change from SW00PT to R0V-0. -P R no mount -P dd V_RST net -P hange R from mount to no-mount -P R change from.k/f to K/F.(For O current limit) -P el H_INTRRUPT net -P0 el R(save cost) -P Q, Q,R,R for MI and HP detect circuit. -P for mount for mount -P R,R,for MI-VRF -P dd for PSPK for -P dd R and R for HP and MI detect pin -P, change from PF to PF. -P el R -P hange from no-mount to mount -P hange from mount to no-mount -P dd close near. Power portion 000 hanged PR to.0k. 000 hanged PR0 to.0k. 000 hanged PR to K. 000 lijah changed PR from 0KR to.kr. 000 lijah deleted PR. 000 lijah changed P to 00pF. 000 lijah changed PR to.kr. 000 lijah changed PR to KR. 000 lijah changed P- and P-gnd to ISUM- for reboot issue. 000 lijah changed P- and P-gnd to ISUM- for reboot issue. 00 hanged PR from 0R to.r for vender asking. 00 hanged PU to ISHRZ-TR0 for states issues. 00 hanged PR to.kr for load line improving. 00 hanged PQ0, PQ to ON0 for H/W ripple and noise reducing. 00 hanged PR to 0.K for power-on issue. 00 dded P0 and reset circuit for power-on issue. 00 hanged PR to 0KR for OP. 00 dded V._PU, V._PU_V0_PWR and PQ for S Power saving. 00 dded P for timing. QUNT 00 hanged PR connecting with output capacitors OMPUTR for OP. hange ist 00 hanged PR to.kr for load line improving. Size ocument Number Rev 00 hanged PR to 0KR for IN signal improving. ustom 00 hanged PR from no-mount to mount TW Main oard Monday, ugust, 00 ate: Sheet of
4 / hange Y pin define for issue. U P_ K_XIN_ Y (.x.mm).mhz/0p/0ppm P_ elete R K_XOUT_ KN PU_STOP# X X KPWR/P#_. PU_STOP# PUT0_PR PU0_PR PUT_PR PU_PR OTT_PR OT_PR SRT_PR SR_PR 0 KIN_K_P () KIN_K_N () KIN_OT P () KIN_OT N () KIN_MI_P () KIN_MI_N () V elete R 0U/.V/XR_ V_K 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ VRF_. V_MHz VOTMHz_. VSR_. VPU_. KIN_ST_P () KIN_ST_N () V KN Q N00 V V.0 VRM_KN# () MNI P-N *0U/.V/XR_ (,,) PK_SM (,,) PT_SM VP_IO_K 0.U_ 0.U_ R_M_PH R /F_ M_PH () ISRSKFT STT_PR ST_PR 0 R 0K/F_ R 0K/F_ VSR_IO VPU_IO SK_. ST_. OTMHz MHz ST SR PU RF MHz_nonSS MHz_ss RF_/FS_.** Thermal P 0 *P_ R_M_PH PU_STOP# R0 R R 0K_ *0K/F_ 0K_ V.0 V FS PU Frequency Select Table PU SR RF MHz MHz MHz US MHz OT MHz 0(default) evel nvironment-related Substances Should NVR be Used..Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. QUNT OMPUTR OK NRTOR Size ocument Number Rev TW Main oard ate: Monday, ugust, 00 Sheet of
5 () FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () MI_TXN0 () MI_TXN () MI_TXN () MI_TXN () MI_TXP0 () MI_TXP () MI_TXP () MI_TXP () MI_RXN0 () MI_RXN () MI_RXN () MI_RXN () MI_RXP0 () MI_RXP () MI_RXP () MI_RXP () FI_FSYN0 () FI_FSYN () FI_INT () FI_SYN0 () FI_SYN FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP RRN PROSSOR (MI,P,FI) F H F 0 0 F0 F F U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] F MI_TX[] MI_TX[] MI_TX[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_FSYN[0] FI_FSYN[] FI_INT FI_SYN[0] FI_SYN[] rrandale MI Intel(R) FI PI XPRSS -- RPHIS P_IOMPI P_IOMPO P_ROMPO P_RIS P_RX#[0] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[0] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX#[] P_RX[0] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[0] P_RX[] P_RX[] P_RX[] P_RX[] P_RX[] P_TX#[0] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[0] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX#[] P_TX[0] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[0] P_TX[] P_TX[] P_TX[] P_TX[] P_TX[] K J J F F 0 J H H F F F 0 0 M M M0 K M J K H0 H F M M 0 M K M H K 0 F P_IROMP_R R XP_RISR0 R () V._PU_V0_PWR 0 dd 0.0u () RMRST_NTR () RMRST_NTR_PH RV./F_ 0/F_ U 0K/F_ TSH0FU H0K0 RMPWR_PU (,) MPWROK 0.0U_ () H_THRMTRIP# () H_PUPWR RMPWR_PU (,,,0,) PTRST# () H_PMSYN () PM_RM_PWR R R K/F_ R K/F_.VSUS R *0_ R K/F_ RMRST_PU# Q RMRST# () N00 R0 *0_ H_TRR# H_PURST# 0.U_ R 00K/F_ R R R R H_TRR# () H_PI R R H_PROHOT# H_PURST# Processor Pullups XP Signal XP_TMS XP_TI_R XP_PRQ# XP_TK 0/F_ 0/F_./F_./F_ H_OMP H_OMP H_OMP H_OMP0 H_THRMTRIP# R 0_ 0/F_ VTTPWROO M R R R R R.K/F_ RRN PROSSOR (K,MIS,JT) R 0/F_ U T OMP T T H K T N K P N N K M./F_ *_ *_ *_ *_ OMP OMP OMP0 SKTO# TRR# PI PROHOT# THRMTRIP# RST_OS# PM_SYN VPWROO_ VPWROO_0 SM_RMPWROK VTTPWROO TPPWROO.K/F_ (.0V) RSTIN# R T */F_ rrandale V.0 V.0 MIS THRM PWR MNMNT OKS R MIS JT & PM K K# K_ITP K_ITP# P_K P_K# P_RF_SSK P_RF_SSK# SM_RMRST# JT MPPIN XP_TI_R XP_TO_M XP_TI_M XP_TO_R R0 T0 F SM_ROMP[0] SM_ROMP[] M SM_ROMP[] N PM_XT_TS#[0] PM_XT_TS#[] PRY# PRQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] N P T P N P T T R R P N J K K J J H K H RMRST_PU# SM_ROMP_0 R SM_ROMP_ R SM_ROMP_ R FX_PROHOT# R 0K/F_ R 0K/F_ R *0_ R0 *0_ T XP_PRQ# XP_TK XP_TMS XP_TRST# K_PU_K () K_PU_K# () T T XP_TI_R XP_TO_R XP_TI_M XP_TO_M T T T T T T0 T T R 0_ R R0 0_ R T KOUT_MI () KOUT_MI# () PH_RFSSK () PH_RFSSK# () *0_ *0_ R 0_ XP_TI XP_TO 00/F_./F_ 0/F_ V.0 XP_TRST# PM_XTTS#0 () PM_XTTS# () R _ () PROHOT H_PROHOT# Q N00 V.0 R /F_ H_PROHOT# () () FX_VRHOT FX_PROHOT# Q *N00 H_THRMTRIP# R (,,,0,) PTRST# 0/F_ Q MMT0 V R 0K/F_ V U TSH0FU R 00K/F_ 0.U_ SHN# () Q N00 Scan hain (efault) PU Only MH Only STUFF -> R, R,R0 NO STUFF -> R,R STUFF -> R,R NO STUFF -> R0,R,R STUFF -> R,R NO STUFF -> R,R,R PROSSOR /(HOST&PI) Size ocument Number Rev. evel nvironment-related Substances Should NVR be Used. ustom TW Main oard. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. ate: Monday, ugust, 00 Sheet of QUNT OMPUTR
6 RRN PROSSOR (R). evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. PROSSOR /(R) ustom Monday, ugust, 00 TW Main oard Size ocument Number Rev ate: Sheet of QUNT OMPUTR M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M 0 M M M M M M M M M 0 M M M M M M M QS M QS M QS M QS0 M QS M QS M QS M QS M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M0 M M M M M M M M M M M M M M M M0 M M M M M M M M M M M M M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS0 M QS M QS M QS M QS M QS M QS M M M 0 M M M M M M M M M 0 M M M M M Q[:0] () M Q[:0] () M S0 () M S () M S () M S# () M RS# () M W# () M [:0] () M QS[:0] () M QS#[:0] () M M[:0] () M OT () M OT0 () M S# () M S#0 () M K () M K# () M K () M K0 () M K0# () M K0 () M [:0] () M QS[:0] () M QS#[:0] () M M[:0] () M OT () M OT0 () M S# () M S#0 () M K () M K# () M K () M K0 () M K0# () M K0 () M S0 () M S () M S () M S# () M W# () M RS# () R SYSTM MMORY U rrandale U Y Y P P F H M M N0 N F F H J M N H H K0 K N P R T Y W V V T Y U T U T V F0 F H0 K J 0 J J0 M M K N P H F K K F J J J0 J 0 K K K N M0 R M N T P M N M T T R P S_S[0] S_S[] S_S[] S_S# S_RS# S_W# S_K[0] S_K[] S_K#[0] S_K#[] S_K[0] S_K[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS[0] S_QS#[0] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] R SYSTM MMORY - U rrandale W R Y W V W V M M H K H R T H P R R R F H J M U V T V R T R R R R P R F P N F F F F H J J J J J K M K K M N F J K J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 S_S[0] S_S[] S_S[] S_S# S_RS# S_W# S_K[0] S_K[] S_K#[0] S_K#[] S_K[0] S_K[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[0] S_QS#[0] S_QS[] S_QS#[] S_QS[] S_QS#[] S_QS[] S_QS#[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[]
7 V_OR 0 F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P UF V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 PU OR SUPPY.V RI POWR POWR SNS INS PU VIS rrandale VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSPVR VTT_ST ISNS H H H H0 J J H H F F F F F Y0 W0 U0 T0 J J J J N K K K M M M N V_SNS J VSS_SNS J VTT_SNS VSS_SNS_VTT PU: RRN.0V () 0 0 VTT_ VTT_ PSI# V.0 PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI PM_PRSPVR 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V_ U/.V_ R 0_ R 0_ T T 0U/.V//SR=/H. 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ *0U/.V/XR_ U/.V_ U/.V_ U/.V_ PSI# () V.0 PU_VI0 () PU_VI () PU_VI () PU_VI () PU_VI () PU_VI () PU_VI () PM_PRSPVR () larksfiled VTT=. VTT_Select=ow rrandale VTT=.0 VTT_Select=High PU_IMON () V_OR V_OR 0 R 00_ R 00_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/V//SR=. 0U/V//SR=. VSNS () VSSSNS () / hange power consumption of VX to Please note that V_FX_OR U should be.0v in uburndale V_FXOR 0 U/.V_ U/.V_ 0 0U/.V/XR_ R R R R R0 R R 0U/.V/XR_ 0 K/F_ PU_VI0 K/F_ PU_VI *K/F_ PU_VI K/F_ PU_VI K/F_ PU_VI *K/F_ PU_VI K/F_ PU_VI For Turbo Mode R default VI[:0]=00000 PSI# default=0 PRSPVR default=. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. RRN PROSSOR (RPHIS POWR) () 0U/.V//SR=/H. *0U/.V//SR=/H. V.0 V.0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ T T T T R R R R P P P P N N N N M M M M K K K K J J J J H H H H R R R R R R R J J H K J J J H F VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ rrandale RPHIS *K/F_ *K/F_ K/F_ *K/F_ *K/F_ K/F_ *K/F_ R *K/F_ PM_PRSPVR R K/F_ R K/F_ PSI# R *K/F_ FI P & MI SNS INS POWR RPHIS VIs VX_SNS VSSX_SNS R -.V RIS.V.V V.0 / dd R V.0 V.0 FX_VI[0] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VR_N FX_PRSPVR FX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT0_ VTT0_0 VTT0_ VTT0_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VP VP VP R T M P N P M P N R T M J F Y W W U T T P N N H P0 N0 0 K0 J J0 J H H0 H M FX_VI0 () FX_VI () FX_VI () FX_VI () FX_VI () FX_VI () FX_VI () R.K/F_ R 0_ R0 0_ R 0_ Max V.0 V.0 (0.) V. U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V_ U/.V_ V_X_SNS () VSS_X_SNS () 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ U/.V/XR_.U/.V_.U/.V/XR_ U/.V_ QUNT OMPUTR ate: Monday, ugust, 00 Sheet of FX_VR_N (,) FX_PRSPVR () FXVR_IMON () V._PU 0U/.V//SR=/H. PROSSOR /(POWR) Size ocument Number Rev ustom TW Main oard
8 T0 T R R R R R R0 R R R R R R P0 P P P0 P P P N N N N0 N M M M M0 M M M M M M 0 K K K K0 K J J J0 J J J J J J H H H H H H0 H H H H H0 H H H H H 0 F F F UH VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 rrandale VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 K K K0 RRN PROSSOR () UI K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS VSS VSS 0 VSS VSS VSS VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS NTF VSS VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R RRN PROSSOR( RSRV, F) T T F0 T F T F T T T T T0 T T T T T T T T P J M J H U T J J U RSV RSV RSV RSV RSV RSV RSV RSV S_IMM_VRF S_IMM_VRF RSV RSV RSV RSV M0 F[0] M F[] P F[] F[] 0 F[] M F[] N F[] M F[] K F[] K F[] K F[0] J F[] N0 F[] N F[] J F[] J F[] J0 F[] K0 F[] H RSV_TP_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSRV RSV_NTF_ RSV_NTF_ RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ RSV RSV RSV RSV RSV RSV_NTF_ J J H K R RSV J RSV J RSV_NTF_0 RSV_NTF_ P T RSV_NTF_ T RSV_NTF_ R RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_0 KY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ P0 P T T P R T T P R R F J H R R RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ V V N W W N RSV_TP_ RSV_TP_ VSS P rrandale rrandale F0 R *.0K_ F R *.0K_ F - isplay Port Presence F Not applicable for larksfield Processor PI-press onfiguration Select F0 : Single P 0 : ifurcation enabled PI-press Static ane Reversal F : Normal Operation 0 : ane Number Reversed -> 0, ->,... F : isabled; No Physical isplay Port attached to mbedded iplay Port 0 : nabled; n external isplay port device is connected to the mbedded isplay port R *.0K_. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. QUNT OMPUTR PROSSOR /() Size ocument Number Rev ustom TW Main oard ate: Monday, ugust, 00 Sheet of
9 / Swap FI,MI US V.0_PH_IO V (,) MPWROK R R () NSWON# () HWP () PM_RM_PWR () SUS_PWR_N_K RV R R () PRSNT () MI_RXN0 () MI_RXN () MI_RXN () MI_RXN () MI_RXP0 () MI_RXP () MI_RXP () MI_RXP () MI_TXN0 () MI_TXN () MI_TXN () MI_TXN () MI_TXP0 () MI_TXP () MI_TXP () MI_TXP./F_ 0K/F_ IX PK-M (MI,FI,PIO) IX PK-M (VS,I) MIOMP HWP RSMRST# SUS_PWR_N_K NSWON# SYS_RST# *0_ N_RST#_R 0K_ PM_TOW# J W0 J0 0 0 F 0 H 0 H F T M 0 M P P U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI MI_ZOMP MI_IROMP FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_SYN0 FI_SYN System Power Management SYS_RST# SYS_PWROK PWROK R 0_ PM_MPWROK_R K MPWROK R *0K_ N_RST# RMPWROK RSMRST# SUS_PWR_K / PIO0 PWRTN# PRSNT / PIO TOW# / PIO WK# KRUN# / PIO SUS_STT# / PIO SUSK / PIO SP_S# / PIO SP_S# SP_S# SP_M# TP PMSYNH H J F W J F H J J Y P F H P K N J0 / modify remove R~R PI_WK# PI_KRUN# RSV_PP# FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_INT () FI_FSYN0 () FI_FSYN () FI_SYN0 () FI_SYN () IH_SUSK () PM_SP_S# () PM_SP_S# () PM_SP_S# () T T0 H_PMSYN () PI_KRUN# (,) T () RT_ () RT_ () RT_R (,) (,) (,) HSYN () VSYN () _KT_N () VS_VN () _KTT V R R R R () R_ROUT0- () R_ROUT- () R_ROUT- T () R_RK0- () R_RK0 () R_ROUT0 () R_ROUT () R_ROUT T VS_K VS_T 0K/F_ 0K/F_.K/F T () R_ROUT0- () R_ROUT- () R_ROUT- T00 () R_RK0- () R_RK0 () R_ROUT0 () R_ROUT () R_ROUT T00 R 0_ R 0_ R 0_ N_ N_ N_R U T _KTN T _V_N Y Y V P P T T V V Y V 0 Y V P P Y T U T V V _KTT K T _TR_K _TR_T V_I V_V V_VRFH V_VRF VS_K# VS_K K/F IRF_R _IRF RT_IRTN VS VS_T#0 VS_T# VS_T# VS_T# VS_T0 VS_T VS_T VS_T VS_K# VS_K VS_T#0 VS_T# VS_T# VS_T# Y VS_T0 T VS_T U0 VS_T T VS_T RT_U RT_RN RT_R RT K RT T Y RT_HSYN Y RT_VSYN RT IbexPeak-M(S v0.) igital isplay Interface SVO_TVKINN SVO_TVKINP SVO_STN SVO_STP SVO_INTN SVO_INTP SVO_TRK SVO_TRT J J F H T T HMI_TR_K HMI_TR_T P_UXN P_UXP J U HMI_HP P_HP P_0N P_0P P_N J P_P P_N 0 P_P 0 P_N W P_P HMI_T_# HMI_T_ HMI_T_# HMI_T_ HMI_T0_# HMI_T0_ HMI_K_# HMI_K_ R0 R P_XT_TR_K P_XT_TR_T _P_XT_T# _P_XT_T _P_XT_T# 0 _P_XT_T _P_XT_T0# _P_XT_T0 _P_XT_K# _P_XT_K HMI_HP () 0.U_ 0.U_ 0.U_ 0 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ HMI_TR_K () HMI_TR_T () 00K/F_ 00K/F_ 00K/F_ 00K/F_ (HMI.bps) V.0 HMI_T# () HMI_T () HMI_T# () HMI_T () HMI_T0# () HMI_T0 () HMI_K# () HMI_K () P_XT_TR_K () P_XT_TR_T () V.0 HMI M/ HMI_OK_HP_XT () 0.U_ P_XT_T# () 0.U_ P_XT_T () 0.U_ P_XT_T# () 0.U_ P_XT_T () 0.U_ P_XT_T0# () 0.U_ P_XT_T0 () 0.U_ P_XT_K# () 0.U_ P_XT_K () PM_RI# F RI# SP_N#/PIO F T IbexPeak-M(S v0.) VSUS R 0K/F_ P_TRK P_TRT Y R P_UXN R P_UXP V0 HMI_OK_HP_XT P_HP P_0N 0 P_0P 0 P_N F P_P H P_N P_P P_N P_P P_TRK P_TRT U0 U P_UXN P_UXP P_HP T P_0N J0 P_0P 0 P_N J P_P P_N F P_P H P_N P_P PI_KRUN# R PM_RI# R0 PM_TOW# R0 PI_WK# R0 SUS_PWR_N_K R NSWON# R0.K_ 0K/F_.K_ K/F_ 0K/F_ *0K/F_ V RV () RSMRST# (,,) WK# Q / elete U,R,R0,, RSMRST# RSMRST# buffer Min. 0ms R K/F_ RV_ON RSMRST# N00K PI_WK# Min. 0ms.V 0.V HMI_OK_HP_XT P_XT_TR_K P_XT_TR_T R0 *0 R0 *0 R0 *0 R R0 R0 / hange R0,R0,R0 to no-mount N VS I VS_K R00.K/F_ PH /(MI&VIO) Size ocument Number Rev. evel nvironment-related Substances Should NVR be Used. dd Int raphics disable ustom TW Main oard / tommy. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. ate: Monday, ugust, 00 Sheet of 00K_.K/F_.K/F_ N_ N_ N_R V VS_T R0 QUNT OMPUTR.K/F_ V V
10 VPU VPU H Topology RT R.K/F R.K/FVRT_ R Flash escriptor Security Overide ow : nable H_OK_N#: High: isable(efault) V R R R R0 No Reboot PSPK () H_K0 () H_K () H_SYN0 () H_SYN () H_RST#0 () H_RST# () H_SOUT0 () H_SOUT.K/F R0 R R.K/FVRT_ T T_ONN JT_TK R _ *0K_ *0K_ *0K_ *0K_ JT_TMS JT_TI JT_TO JT_RST# R R R R *0_ *0K/F_ H_OK_N# PSPK High = nable ow = isable (efault) R R R R R R R R Q0 MMT0 R0 K/F_ *P_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ can not use R0V-0 VPU VRT VRT_ *0K/F_ *0K/F_ *0K/F_ *0K/F_ H_K_R H_SYN_R H_RST#_R H_SO_R V VRT SW00PT H0H-0 R K/F_ / no mount H_SYN H_SO H_SO SPI_SI R R R M_ Weak internal pull-down. o not pull high. Sampled at rising edge of RSMRST#. Weak internal pull-down. o not pull high. Sampled at rising edge of RSMRST#. Weak internal pull-down. o not pull high. Sampled at rising edge of RSMRST#. INVRMN High = nable High () = Integrated VRM is enabled ow (0) = Integrated VRM is disabled Intel nti-theft Technology High = nable ow = isable (efault) U/.V/XR_ 0K/F_ 0K/F_ H_SYN:Internal pull low High: P VR.V ow : P VR.V SPI_S0 R J SHORT_ P U/.V/XR_ J SHORT_ P U/.V/XR_ (H000) 0 el R () PSPK () H_SIN0 () H_SIN /0 R change from 0K to.k () H_OK_N# R K/F_ RV VSUS V VRT P_ () KSMI# /0 : Move KSMI# to PIO R P_ Y.K/0PPM R WXVSSI IOS M IRQ_SRIRQ RT_RST# SRT_RST# H_K_R H_SYN_R H_SO_R H_OK_N# JT_TK JT_TMS JT_TI JT_TO JT_RST# SPI_K SPI_S# SPI_SI SPI_S0 VSUS R SPI_K SPI_SI. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. T IX PK-M (H,JT,ST) RNPK 0 0 F0 F H J0 M K K J J V Y Y V U RT_X RTX RT_X RTX RTRST# SRTRST# SM_INTRUR# INTRUR# 0K_ INVRMN INTVRMN High=Integrated SUS.V VRM is enable 0K/F_ R 0M_ U SPI_S# /S V.K_ O /HO /WP K I H_K H_SYN R 0_ PSPK P SPKR H_RST#_R 0 H_RST# T T 0.U_.K_ H_SIN0 H_SIN H_SIN H_SIN H_SO IbexPeak-M(S v0.) VSUS RT IH H_OK_N# / PIO H_OK_RST# / PIO JT_TK JT_TMS JT_TI JT_TO JT_RST# SPI_K SPI_S0# SPI_S# SPI_MOSI SPI_MISO SPI JT P ST FWH0 / 0 FWH / FWH / FWH / FWH / FRM# ST# RQ0# RQ# / PIO F ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPI ST0P / PIO STP / PIO IRQ_SRIRQ SRIRQ STIOMPO K K K K H H H H F F F F H H F F F F T Y V STOMP R R0 T T0 P_0 (,,) P_ (,,) P_ (,,) P_ (,,) P_FRM# (,,) IRQ_SRIRQ (,) (P/H ST/ N) R ST# () 0K/F_ 0K/F_ QUNT OMPUTR PH /(ST)./F_ V ST H 0 ST_RXN0 () ST_RXP0 () ST_TXN0 () ST_TXP0 () ST O ST_RXN () ST_RXP () ST_TXN () ST_TXP () V.0 Size ocument Number Rev ustom TW Main oard ate: Monday, ugust, 00 Sheet 0 of
11 () () () USO0# USO# USO# USO# PRR# VS# POK# SRR# V V PIRQ# PIRQ# STOP# PIRQ# PK_F PIRQ# RQ# RQ0# PIRQF# NT#/PIO : High : Internal pull-up ow : onfigures MI for SI compatible operation (for servers only. Not for mobile/desktops) SM US for 0 (OK/RM) PK_SM/PT_SM SO-IMM0 ddress X 0h SO-IMM 00 00X h ISRS h xpress ard V SM0_K V SM0_T RV V R R R R PK_MP PK_TPM PK_ Q N00 RP RP 0PR-.K 0PR-.K RP 0PR-.K.K_.K_.K_.K_ USO# USO# USO# USO# PIRQH# TRY# FRM# RQ# RQ# PIRQ# IRY# PIRQ# V V T T R _ R _ R _ R _ R R 0K/F_ RV PK_SM (,,) 0K/F_ PT_SM (,,) PIRQ# PIRQ# PIRQ# PIRQ# RQ0# RQ# RQ# RQ# NT0# NT# NT# PIRQ# PIRQF# PIRQ# PIRQH# PI_RST# SRR# PRR# IRY# VS# FRM# POK# STOP# TRY# T PI_PTRST# PK_MP_R PK R PK_F_R T V V IX PK-M (PI,US,NVRM) H0 N J 0 H 0 0 M M F M0 M J K F0 K M J K F J0 F M H J0 H H F M F K F H K K 0 H F M N P P P P (,,) U (,,) /0# /# /# /# PIRQ# PIRQ# PIRQ# PIRQ# PIRST# SRR# PRR# POK# PM# PTRST# MT MK PI RQ0# RQ# / PIO0 RQ# / PIO RQ# / PIO NT0# NT# / PIO NT# / PIO NT# / PIO PIRQ# / PIO PIRQF# / PIO PIRQ# / PIO PIRQH# / PIO IRY# PR VS# FRM# STOP# TRY# KOUT_PI0 KOUT_PI KOUT_PI KOUT_PI KOUT_PI IbexPeak-M(S v0.) RV RV NT# R0 NVRM US Q NV_#0 NV_# NV_# NV_# NV_QS0 NV_QS NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO N00 *K/F_ NV_ NV_ NV_ROMP NV_R# NV_WR#0_R# NV_WR#_R# NV_W#_K0 NV_W#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / PIO O# / PIO0 O# / PIO O# / PIO O# / PIO O# / PIO O# / PIO0 O# / PIO R swap override Strap/Top-lock Swap Override jumper ow = swap override/top-lock NT# Swap Override enabled High = efault R Y P V P P T T V J J Y U V Y Y V F H J N0 P0 J0 0 F M N H J F H M N J F F T () NV_ T NV_:MI termination voltage. Weak internal pull-up. o not pull low (P/H USN, N) US_IS USO0# USO# USO# USO# USO# USO# USO# USO# SM_T_M SM_K_M.K/F_.K/F_ PI_RQ_WN# R USP0- (0) USP0 (0) USP- (0) USP (0) USP- () USP () USP- () USP () USP- (0) USP (0) USP- () USP () USP- () USP () US Port0 USP- () USP () WIMX USP- () USP () T RV RV USO0# (0) USO# (0) USO# (0) US Port ocking US xpress ard US Port Finger Printer amera./f_ V. RV_UX 0K/F_ R R Q N00 (0) PI_RXN ard (0) PI_RXP Reader (0) PI_TXN (0) PI_TXP N PI_RQ_WN# WN K_PI_WN# K_PI_WN ard Reader (0) K_PI_R# (0) K_PI_R xpress ard () K_PI_XPRSS_R# () K_PI_XPRSS_R nti-theft Technology High = nable NV_ ow = isable ocking an WN xpress ard () () 0 hange RP from PR to 00 x for MI issue. ocking N R 0_ () K_PI_KN# R 0_ () K_PI_KN N () K_PI_N# () K_PI_N NV_ NT0# R K/F_ NT# R K/F_ oot IOS Strap NT0# NT# oot IOS ocation 0 0 * P 0 Reserved (NN) 0 PI SPI *.K_ () () () PI_RXN () PI_RXP () PI_TXN () PI_TXP () PI_RXN () PI_RXP () PI_TXN () PI_TXP () PI_RXN () PI_RXP () PI_TXN () PI_TXP () PI_RXN () PI_RXP () PI_TXN () PI_TXP (0) PI_RQ_K_N# PI_RQ_RU# PI_RQ_XPRSSR# () PI_RQ_N# 0 hange VSUS to V V V R R RP RP RP RP R R0 R R0 0 0K/F_ 0K/F_ 0X PI_PTRST# PI_TXN_ PI_TXP_ PI_TXN_ PI_TXP_ PI_TXN_ PI_TXP_ K_PI_WN#_R K_PI_WN_R PI_RQ_WN# K_PI_KN#_R K_PI_KN_R PI_RQ_K_N# 0X K_PI_R#_R M K_PI_R_R M PI_RQ_RU# N 0X K_PI_XPRSS_R#_R H K_PI_XPRSS_R_RH 0.U_ 0.U_ 0.U_ 0.U_ PI_RQ_XPRSSR# 0X 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ K_PI_N#_R K_PI_N_R PI_RQ_N# PI_RQ_RU# PI_RQ_K_N# PI_TXN_ PI_TXP_ PI_TXN_ PI_TXP_ PI_RQ P KRQ# PI_RQ_WN# PI_RQ_N# PI_RQ_XPRSSR# PI_RQ 0 0.U_ R IX PK-M (PI-,SMUS,K) 0 J0 F H W U0 T0 U V F H J W T U U V J J K K P M M U M M M J0 J H K K P RV U U TSH0FU *0_ PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP KOUT_PI0N KOUT_PI0P KOUT_PIN KOUT_PIP KOUT_PIN KOUT_PIP KOUT_PIN KOUT_PIP KOUT_PIN KOUT_PIP KOUT_PIN KOUT_PIP IbexPeak-M(S v0.) PI-* PIKRQ0# / PIO PIKRQ# / PIO PIKRQ# / PIO0 PIKRQ# / PIO PIKRQ# / PIO PIKRQ# / PIO KOUT_P N KOUT_P P P KRQ# / PIO SMus From K UFFR lock Flex P PH_PIO PIO0 SM0_K SM0_T SM_K_M0 SM_T_M0 PIO P KRQ# P KRQ# R 00K_ ontroller ink R R R R R0 R R PTRST# (,,,0,) SMRT# / PIO SMK SMT SM0RT# / PIO0 SM0K SM0T SMRT# / PIO SMK / PIO SMT / PIO _K _T _RST# P KRQ# / PIO KOUT_P N KOUT_P P KOUT_MI_N KOUT_MI_P KOUT_P_N / KOUT_K_N KOUT_P_P / KOUT_K_P KIN_MI_N KIN_MI_P KIN_K_N KIN_K_P KIN_OT_N KIN_OT_P KIN_ST_N / KSS_N KIN_ST_P / KSS_P R R0 RFKIN KIN_PIOOPK XT_IN XT_OUT XK_ROMP KOUTFX0 / PIO KOUTFX / PIO KOUTFX / PIO KOUTFX / PIO 0K/F_ 0K/F_.K/F_.K/F_.K/F_.K/F_ 0K/F_ 0K/F_ 0K/F_ RV Monday, ugust, 00 ate: Sheet of (TO ) H-T00 PIO If not used,.-k? to 0-k? pull-up to V. H J M 0 T T T H N N T T W P P F H H P J H H F T P T N0 PH_PIO SM0_K SM0_T PIO0 SM_K_M0 SM_T_M0 PIO SM_K_M SM_T_M P KRQ# KOUT_MI#_R KOUT_MI_R PH_RFSSK_R# PH_RFSSK_R RP0 PK_F XT_IN XT_OUT XK_ROMP XT_IN XT_OUT RV T0 T T T RP KIN_MI_N () KIN_MI_P () KIN_K_N () KIN_K_P () KIN_OT N () KIN_OT P () KIN_ST_N () KIN_ST_P () M_PH () R R R M QUNT OMPUTR PH /(PI) 0./F_ Y.P MHz/F/0ppm.P KOUT_MI# () KOUT_MI () PH_RFSSK# () PH_RFSSK () V.0 Size ocument Number Rev ustom TW Main oard 0X 0X *0_. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners.
12 0 P- Pull up to V for PIO () IHTSNSOR_INT# () T_PRS# 0 P- hange T_PRS# from IOP to PIO and pull up to RV SV_ST_UP I0 I I High = Strong (efault) I () SI# T_PRS# () RIT_TMP_RP# V V V RV R R R R R PH_PIO0 IX PK-M (PIO,VSS_NTF,RSV) PH_PIO SI# IHTSNSOR_INT# 0K/F_ T () RMRST_NTR_PH T R 0K/F_ RV R0 0K/F_ V () FP_PRS# R RP SW T T I0 I I *0K/F_ T 0K_ MI0 MI MI 0K/F_ 0K/F_ 0K/F_ 0KX RP IP(FHS-0F-T-V-T/R()) V Y J F0 K T F Y H0 V M V V P H F F 0 F F H H H H J J J J J J0 J J UF MUSY# / PIO0 TH / PIO TH / PIO TH / PIO PIO PIO V MIS N_PHY_PWR_TR / PIO PIO STP / PIO TH0 / PIO SOK / PIO PIO PIO PIO STP_PI# / PIO STKRQ# / PIO STP / PIO STP / PIO SO / PIO STOUT0 / PIO PIKRQ# / PIO PIKRQ# / PIO STOUT / PIO STP / PIO PIO VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ IbexPeak-M(S v0.) KX NTF PU IHTSNSOR_INT# R0 R0 R RSV M I *0K/F_ MI0 R0 *0K/F_ MI R0 *0K/F_ KOUT_PIN KOUT_PIP KOUT_PIN KOUT_PIP 0T KOUT_K0_N / KOUT_PIN KOUT_K0_P / KOUT_PIP MI PI RIN# PROPWR THRMTRIP# TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# R TP TP TP TP R H H F F U M M 0 T 0 0 W Y Y V V F M N J K K M N M0 N0 H T P 0 T0 R_K_PU_K# R_K_PU_K RIN# PH_THRMTRIP#_R PIO 0, PIO If not used,.-k to 0-k pull-up to V. PIO If not used,.-k to 0-k pull-up to V. PIO Weak internal pull-up. o not pull low. Sampled at rising edge of RSMRST# PIO T0 () PIO has internal pull up and control VRM. High : nable VRM(See H_SYN) ow : isable VRM(P VR=.0) 0K/F_ T0 T /0 elete R H_PI () PIO Intel M rypto Transport ayer Security (TS) cipher suite weak internal pull-down of 0 K which is enabled when PWROK is low. ow : with no confidentiality High : with confidentiality *0K/F_ 0K/F_ 0K/F_ V RP SI# RIN# () H_PUPWR () R _ T_PRS# T0 RIN# PH_PIO0 PH_PIO 0X R R00 R0 R0 R0 R0 K_PU_K# () K_PU_K () V.0 0K/F_ R _ 0K/F_ RV 0K/F_ 0K/F_ 0K/F_ 0K/F_ H_THRMTRIP# () V V. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. UI Y VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[0] H VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[] VSS[] VSS[] 0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] F F 0 0 F H H0 H0 H H H VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] IbexPeak-M(S v0.) VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] H H J K K K K 0 M M M0 N M M M M M M M N P P P0 P P P P P R R T T T T T T U0 U U U P V P V V0 V V0 V V V V V V V V V V V V V W W Y Y Y Y Y Y Y0 Y Y Y Y Y P Y Y Y P T T Y T M T M K K V UH VSS[0] 0 M U F Y H U F P N F F F F F H H H H H V H H H J J J0 J J J J J J T J K N K K K K M VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] IbexPeak-M(S v0.) K0 K K K K K K K K K K M M0 M M M M M0 M M M M M M M U0 M V M M 0 0 N N0 N P P P P P P R R T H T T T T T V V V0 V V0 V V V V V V V W W W F W W W0 W Y Y Y QUNT OMPUTR PH /(PIO) Size ocument Number Rev ustom TW Main oard ate: Monday, ugust, 00 Sheet of
13 UJ *U/.V/XR_ PH_VK (m) P VK[] P VK[] R0 0_ (0m) F VN[] /0 elete,dd R0 F VN[] 0.U_ Y0 PSUSYP V.0 (.) VM[] U/.V_ VM[] U/.V/XR_ VM[] Place near,v F VM[] F VM[] F VM[] V VM[] V VM[] V VM[] Y VM[0] Y VM[] Y VM[] 0.U_ 0U/.V//SR=/H. V_PH_PRTV PRT 0U/.V/XR_ U/.V/XR_ (m) V. U VVRM[] (m) V.0 V.0_PH_VP (M00NJ(0uH/00m/0.) VP[] VP[] R *0_ V.0_PH_VP (m) VP[] V.0 M00NJ(0uH/00m/0.) VP[] 0 0U/.V/XR_ V.0 H 0 U/.V/XR_ VIO[] J VIO[] H 0U/.V//SR=/H. VIO[] F VIO[] 0 U/.V/XR_ 0 U/.V/XR_ H VIO[] 0 U/.V/XR_ V.0 F VIO[] 0 0.U_V_PH_PSST V PSST 0 isolation power plan for H,H,F 0.U_V_PH_PSUS Y PSUS RV (m) P VSUS_[] U VSUS_[0] 0.U_ U0 VSUS_[] U VSUS_[] V V V_[] 0.U_ V V_[] Y V_[] V.0 (<m) T V_PU_IO[] 0.U_ U/.V/XR_ U V_PU_IO[] VRT (m) VRT 0.U_ 0.U_ IbexPeak-M(S v0.) U/.V/XR_ POWR lock and Miscellaneous RT PU PI/PIO/P ST PI/PIO/P US H VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VIO[] VRF_SUS VRF V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VSTP[] VSTP[] VIO[] VVRM[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VM[] VM[] VM[] VM[] VSUSH V V Y Y V U U U P P N N M M J J H H F F U V F K J M N P U K K 0 (m) (<m) 0 (<m) (m) V.0 U/.V/XR_ 0 0 hange 0 from 0.u to U V.0 (m) (m) RV (,) RV_ON V_VRF 0.U_ PH_VSTP RV_VRFSUS U/.V/XR_ (0.m) V 0 0.U_ 0.U_ 0 V.0 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ V.0 V. V U/.V/XR_ 0.U_ V.0 0 0U/.V/XR_ 0 RV U/.V/XR_ H T0 H 0 F F0 F H0 0 Y Y VPU H0H-0 R 0_ Q TU H0H-0 *U/.V/XR_ R 0K/F_ VPU Q N00 RV V V R M_ R 0_ R 00/F_ Q0 N00 VPU RV V.0 el R Q N00K-T- V.0 K VIO[] (0m) J *U/.V/XR_ VPXP PH_VPXP nable/isable internal VRM VVRM[..]. PIO V.0 (.) 0U/.V/XR_ 0.U_ V.0_PH_IO V. U/.V/XR_ (.0) 0U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ U/.V/XR_ 0.U_ 0.U_ V (m) hange from no-mount to mount High : nable (Internal pull High) VK[..], VSTP[..], VPXP, VFIP can remove /. ow : isable Straping V. or V. High : V. H_SYN ow : V. (Internal pull ow) F F F0 F H H H0 H J0 J N0 N N N N N J J T T U U V V W W H N0 N N T IX PK-M (POWR) U POWR VOR[] VOR[] VOR[] VOR[] VOR[] VOR[] VOR[] VOR[] VOR[] VOR[0] VOR[] VOR[] VOR[] VOR[] VOR[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] PH_VFIPJ (m) VFIP V.0 M VIO[] RT V OR VS PI * NN / SPI MI HVMOS FI IbexPeak-M(S v0.) V[] V[] VSS_[] VSS_[] VVS VSS_VS 0 F F H H VTX_VS[] P VTX_VS[] P VTX_VS[] T VTX_VS[] T V_[] V_[] V_[] VVRM[] VMI[] VMI[] T T U VPNN[] M VPNN[] K VPNN[] K0 VPNN[] K VPNN[] K VPNN[] K VPNN[] M VPNN[] M VPNN[] M VM_[] VM_[] VM_[] VM_[] M M P P V_VVS V._VTX_VS V (m) V.0_VMI V._VPNN (m) QUNT OMPUTR (m) 0.uH_ (m) MPSN V_V (m) V 0.U_ 0.0U_ 0U/.V/XR_ dd 0u hange from U to 0.0U el R 0.U_ 0.0u_ 0.0u_ 0U/.V/XR_ 0.U_ 0 U/.V/XR_ 0.U_ 0.U_ V 0.U_ U/.V/XR_ V. (<m) el R (m) V. el R0 V V. V.0 PH /(POWR) Size ocument Number Rev TW Main oard ate: Monday, ugust, 00 Sheet of
14 Place these aps near So-imm0.. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. Place these aps near So-imm. MMORY THRM SNSOR Themal I ddress PH SMUS Max.. Max.. (Max. 0.) (Max. 0.) (H=mm) (H=mm) 00 0 Nvidia raphics Thermal TP0 Write TP0 Read TOS TSFN TOS TSFN(lert) xt.raphics Thermal (M-) MT/MK: RM Thermal () H -Sensor WWN Thermal () / Sawp SMR_VRF_Q and Q0 / change ON from IMM to IMM0 el R,R0,R,R el R,R 0 dd ~ for S power reduction.0 R IMMx ustom Monday, ugust, 00 TW Main oard Size ocument Number Rev ate: Sheet of QUNT OMPUTR PT_SM PK_SM SMVRF_MH SMVRF_MH SMVRF_MH PK_SM PT_SM SMVRF_MH M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M M M M M M 0 M M 0 M M M M M M M M M 0 M M M M M M M M M 0 M M M M M M M QS# M M M M M M M QS# M QS0 M QS M M M QS M QS M QS M QS# M QS# M M M QS# M QS M QS# M M M M M QS# M QS M QS M M0 M QS#0 M M M QS# M QS# M QS# M M M QS# M QS# M QS M QS# M QS M QS#0 M QS M QS# M M M QS M M0 M M M QS0 M M M QS M QS M QS M M M M SMVRF_MH PM_XTTS#0 () RMRST# () PM_XTTS# () RMRST# () PK_SM (,,) PT_SM (,,) SMVRF_MH () MT (,,) MK (,,) KSMT () KSMK () KSMK () KSMT () M Q[:0] () M Q[:0] () M S () M S#0 () M S () M S# () M K0 () M K0# () M K () M K# () M K0 () M K () M S# () M RS# () M W# () M [:0] () M S0 () M K () M K0 () M K0# () M S () M S#0 () M RS# () M K () M K0 () M [:0] () M S# () M S () M S0 () M W# () M S# () M K# () M OT0 () M OT () M M[:0] () M QS[:0] () M QS#[:0] () M OT0 () M M[:0] () M OT () M QS[:0] () M QS#[:0] ().VSUS V VTT_MM VTT_MM V VTT_MM.VSUS VTT_MM.VSUS.VSUS V V V V V V.VSUS.VSUS V._PU 0U/.V/XR_ R 0K/F_ 0.U_ R 0K/F_ 0U/.V/XR_ *0U/.V//SR=/H. 0U/.V/XR_ R 0K/F_ 0U/.V/XR_ R 0K/F_ 0U/.V/XR_ Q N00 U/.V/XR_ Q N00 0 U/.V/XR_ U/.V/XR_ U/.V/XR_.U/.V_ 0.U/.V_.U/.V_.U/.V_.U/.V_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ R 0/F_ R 0K/F_ R 0/F_ R 0K/F_ 0.U_ 0 0P_ 0.U_ 0U/.V/XR_ 0U/.V/XR_ 0.U_ 0U/.V/XR_ 0.U_ 0U/.V/XR_ 0U/.V/XR_ U/.V/XR_ 0 0U/.V/XR_ U/.V/XR_ 0 0.U_ U/.V/XR_ 0U/.V/XR_ U/.V/XR_ U -P-F SMT Vs 0 SMK O.S. P-XXXX R SRM SO-IMM (0P) ON R-IMM /P /# 0 S0# S# K0 K0# K K# K0 K S# RS# W# S0 S S S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# V V V V V V V V V V0 V V V V V V V V VSP N N NTST VNT# RST# VRF_Q VRF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT QS# QS# P-XXXX R SRM SO-IMM (0P) ON R-IMM /P /# 0 S0# S# K0 K0# K K# K0 K S# RS# W# S0 S S S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# V V V V V V V V V V0 V V V V V V V V VSP N N NTST VNT# RST# VRF_Q VRF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT QS# QS# 0U/.V/XR_ *0U/.V//SR=/H. 0.U_ 0.U_ 0U/.V/XR_ 0U/.V/XR_ 0.U_ 0.U_ 0.U_ 0U/.V/XR_ 0U/.V/XR_ 0U/.V/XR_.U/.V_ 0.U_ 0.U_ 0.U_ 0.U_ 0 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_
15 RT ON 0.U_ 0.U_ R R RT-R.K/F_.K/F_ R R0 U.K/F_.K/F_ RT- RT-S POY SWITH 0. el 0, F RT- RT-HS V HPT RT-VS 0 RT-SK RT-SK (,) 0 IN OUT RT-S (,) IN OUT R (,) HSYN For MI V-SUY(00FR0SXXR) R./F_ RT-HS *0_ 0.U_ VSYN SYN_IN SYN_OUT R./F_ RT-VS SYN_IN SYN_OUT V RT_R RT_ RT_ 0 V 0.U/.V_ R /F_ 0P_ YP V_ R /F_ V V_VIO M00-0/IPZ 0P_ V_SYN R /F_ V VIO_ VIO_ VIO_ 0P_ K0HS0 K0HS0 K0HS0 HPT V 0P_ 0P_ 0P_ P_ P_ RT-R RT- RT- V 0.U/0V/XR SNS# Foxconn () RT_SNS SNS_N# (,) K_V_SNS# () MVHTFT U R 00K/F_ R 0K_ Q PTU V U0 Without ocking K_V_SNS# _SNS# ocking_insert# RT_SNS 0 M RT no Plug H H V S O_R () 0.U_ [ ehavior] M RT Plug in H => H => H S O_ () RT_SNS: H=> or =>H detect which one is inserting M RT plug out => H H H => S O_ () ocking_insert#: H=> detect which one is inserting () RT_R S O_VSYN () [RT SW] With ocking When ocking_insert# is low switching R to ocking RT () RT_ [SNS_N#] ll no Plug H RT_R () RT_ S Input for RT pin0, assert to high when RT M RT Plug in H => => H RT_ insert[no Request] () VSYN S M RT plug out => H H => RT_ S 0 (,) OK_INSRT# OK VI Plug in H => H H => IN VSYN S OK VI Plug out => H H => H IN: N 0-->S OK RT Plug H => H H => -->S PIV0S OK RT/VI Plug => H H => H SNS_N# () _KT_N U ISPON hange to () ISP_ON TSH0FU F. fuse POY SWITH. F H VS ON VS-HN(V-0SFY) RT/VS Size ocument Number Rev.evel nvironment-related Substances Should NVR be Used. ustom TW Main oard.purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. ate: Monday, ugust, 00 Sheet of R isplay On V 0.U_ 00K/F_ 0.U/V V V V V N V R0 0K/F_ ISPON R.K_ N N _KTT () 0P_ isp_on KTT ROUT () R_ROUT ROUT- R_ R_- () R_ROUT- R_- R_ 0 RK0 R_ R_K 0 R_RK0 () N VS enable RK0- R_- R_K- R_RK0- () V U V ROUT- ROUT () R_ROUT- R_ROUT () ROUT R_- R_ ROUT- 0.U_ () R_ROUT R_ R_- R_ROUT- () IN OUT () R_RK0- RK0- ROUT R_ROUT () RK0 R_K- R_ ROUT- IN () R_RK0 R_K R_- R_ROUT- () 0.U_ 0.0U_ () VS_VN ROUT0- ROUT0- ON/OFF 0.U_.U/.V/XR_ () R_ROUT0- R_ROUT0- () ROUT0 R_0- R_0- ROUT0 () R_ROUT0 0 R_0 R_0 0 R_ROUT0 () T0IU--T R 00K/F_ QUNT OMPUTR R 00K/F_
16 WN_RF_ON: ow : disable the radio. High : nable the radio. () PK_MP / add R,R for MI R 0_ () K_PI_WN R 0_ () K_PI_WN# WN_WK# R () PI_TXP () PI_TXN () PI_RXP () PI_RXN () PI_RQ_WN# () T_H_K_INT () H_T_INT 0K/F_ () WN_PWN RV_UX Q N00K RV_UX Q PTU T_H_K_INT WN_WK# VPU R 0K/F_ VPU Q N00 Mini PI- ard FOR W ON WK# (,,) Reserved Reserved Reserved Reserved.Vaux.Vaux PTp0 PTn0 PRp0 PRno Reserved/UIM_ Reserved/UIM_ RFK RFK- KRQ# T_HK T_T WK# R 0K_ MiniPI-FOX(S0-S0N-F) RV WNV *0.0U_.Vaux.V _WPN# _WN# _WWN# US_ US_- SM_T SM_K.V.Vaux PRST# W_IS# 0/UIM_VPP /UIM_RST /UIM_K /UIM_T FRM#/UIM_PWR.V.Vaux Q NTMFS S WN Power Q N00 RV_UX 0 T_H_K_INT R RV_UX 0.U_ R 00/F_ U/.V/XR_ PTRST# (,,,0,) P_0 (0,,) P_ (0,,) P_ (0,,) P_ (0,,) P_FRM# (0,,) RV_UX 00K/F_ ( Peak, 0. normal) 0 0U/.V/XR_ 0.U_ For ebug ard Only *U/0V/XR USP () USP- () 0U/.V/XR_ Q N00K Q N00 W# R0 00K_ WN_RF_ON# () / : dd Q,R0 XPRSS R R0V-0 WN_T_# PUS# R R R R PRST# PP# R0 0_ R0 0_ WN_T_# () VSUS_XPRSS _R PK_SM (,,) PT_SM (,,) V._XPRSS_R V._XPRSS_R WK# (,,) VSUS_XPRSS _R V_XPRSS_R USP- () USP () PI_RQ_XPRSSR# () / add R0,R0 K_PI_XPRSS_R# () for MI K_PI_XPRSS_R () PI_RXN () PI_RXP () PI_TXN () PI_TXP () 0 ON US- US PUS# Reserved Reserved SMK SMT.V.V 0 WK#.VUX PRST#.V.V KRQ# PP# RFK- RFK 0 PRn0 PRp0 hole hole PTn0 PTp0 xpress ard(00-) 00- xpress ard Q PTU T_ () P.K/F_.K/F_ *0_ *0_ *MF-0-000I-S V. 0.U/YV_ VSUS 0 0.U/YV_ 0U/.V/XR_ 0U/.V/XR_ VSUS_XPRSS _R V._XPRSS_R 0.U/YV_ V_XPRSS_R.U/.V/XR_ 0.U/YV_ VSUS V. (,,,0,) PTRST#.U/.V/XR_ V 0.U/YV_ 0.U/YV_ V 0.U/YV_ PTRST# U0 0U/.V/XR_.. UXIN.. SYSRST# SHN# RKN N 0 0FV-.VOUT.VOUT UXOUT PP# PUS#.VOUT.VOUT STY# PRST# O# 0 (.) (m) (0m) MINON PP# PUS# PRST# R R00 Short current:.vout :. ~. UXOUT : 0. ~ 0..VOUT : 0. ~. QUNT OMPUTR V_XPRSS_R VSUS_XPRSS _R V._XPRSS_R MINON (,,,,) 0K/F_ VSUS 0K/F_ WN/XPRSS R Size ocument Number Rev TW Main oard ate: Monday, ugust, 00 Sheet of
17 ... I/O ddress R-0 Index ata * 0 F F 0 0 (HFH, HF) (HFH, HF) 0 XOR-TR TST SHM: SHM(If = 0 nable share host IOS memory) OK_RST# : R0 T?: R () T0 (0) KSMI# () RIN# V / add R0.K from to RSMRST# Same as R.K_ VPU OK_INSRT# OK_PWRON OK_PWROK OK_RST# 0ms VPU _KX R (0,,) P_0 (0,,) P_ (0,,) P_ (0,,) P_ () PK_ (0,,) P_FRM# R0V-0 (0,) IRQ_SRIRQ SI# R0V-0 () R0V-0 R0V-0 R () I# () IH_SUSK Y R0.K/0PPM P_ () RSMRST# 0K/F_ 0K/F_ () TT () TK () OK_JT () OK_PWRON () MUT_UTTON# P_ () IN R R R R0 V F_SI F_S0 F_SK F_S0# (0) MX0 (0) MX (0) MX (0) MX (0) MX (0) MX (0) MX (0) MX (0) MY0 (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY (0) MY0 (0) MY (0) MY (0) MY (0) MY (0) MY () PROHOT () P_UTTON# (,) RV_ON K_ TT TK *00K_ *0_.K/F_ MUT_UTTON# HO# IN _KX 0M KX 0U/.V/XR_ 0.U_ 0.U_ 0.U_ 0.U_ 0.U_ U_ U V 0 RST# K FRM# 0 SRIRQ SMI#/PIO SI#/PIO KRST# PIO/PWURQ# F_SI F_S0 F_SK F_S0# KSIN0 KSIN KSIN KSIN KSIN KSIN KSIN KSIN WP VPU MN P-NQ MTV 0.0U_ VPU_IT_V ISNS_IN 0.0U_ SPI P KSOUT0/JNK# KSOUT/TK KSOUT/TMS KSOUT/TI KSOUT/JN0# KSOUT/TO KSOUT/RY# KSOUT KSOUT KSOUT KSOUT0 KSOUT KSOUT/PIO KSOUT/PIO KSOUT/PIO KSOUT/PIO/XOR_OUT KSOUT/PIO0 PST/PIO PSK/PIO PST/PIO PSK/PIO PST/PIO PSK/PIO T/PIO0 KOUT/PIO T/PIO T/PIO0 /PIO0 KX/KKIN KX V V V V V K/ PS/ 0 V / / PWM PIO WP 0 0 0U/.V/XR_ 0/PI0 /PI /PI /PI /PIO0 /PIO0 0/PI /PI /PI /PI _PWM0/PIO _PWM/PIO _PWM/PIO _PWM/PIO H_PWM/PIO _PWM/PIO _PWM/PIO F_PWM/PIO0 PIO0 PIO0 0 PIO S/PIO S/PIO 0 /PIO0 PP#/PIO0 KRUN#/PIO S/PIO 0 S/PIO PIO/HPIO0 PIO PIO T/PIO TK/PIO TMS/PIO TI/PIO TRST#/PIO S/PIO T/PIO TO/PIO0 RY#/PIO S/PIO KSOUT/PIO PIO0 PIO PIO PIO/TRIS# SOUT_R/PIO/R PIO/R0 SIN_R/PIO PIO SPI_I/PIO SPI_O/PIO/SHM SPI_K/PIO PIO PIO/S PIO/S VRF V_POR# VORF U_ PM_SP_S# MPWROK H_INTRRUPT T_K T_T MK MT Z_PIO0 PM_SP_S# PM_SP_S# VRON RT_SNS HWP RMRST_NTR MTV () ISNS_IN () T_PRS# () PM_SP_S# () VFN (0) H_INTRRUPT () I_ST () WN_PWN () SNS_N# (,) OK_INSRT# (,) PRSNT () ISP_ON () SP# () T# () PWR# () MINON (,,,,) NUM# () O_PWN () T_K () T_T () OK_RST# () OK_INUS# () PI_KRUN# (,) MK (,,) MT (,,) RIT_TMP_RP# () Z_PIO0 () FN-SI (0) OK_PWROK () NSWON# () TT_RST# () H_OK_N# (0) SUSON (,,) SUS_PWR_N_K () PM_SP_S# () VRON (,) RT_SNS () PS# () WIRSS_SW# () SRO# () VO_MUT () HN# () RMRST_NTR () WN_RF_ON# () T_PN# () /- (,) H_UNO_RR 0_ 00_S () 00_SK () 0.U_ R.K_ V POWR ON RST U/.V/XR_ (,) MPWROK H_UNO () Winbond WQVSSI M WQVSSI / change IOS to M. evel nvironment-related Substances Should NVR be Used.. Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as reen Partners. VPU R0 VPU R0 00K/F_ R0 0_ el R,R,R dd open-drain buffter U0, R, for H_UNO 0K/F_ F_S0# F_SI *0.0u_ R0V-0 R MPWROK PM_SYS_PWR U /S V O /HO /WP K I RV ISNS_OK () 0_ NSWON# () () HWP VPU VPU F_SK F_S0 V Y N U NSZ *S *S R0V-0 MYT WXVSSI KZP0N0 () V_RST# 0.U_ TK TT VPU (,) _PWR () PM_SYS_PWR () R_PWR () XT_INT_V_PWR. HWP R 0_ R 0K/F_ () PM_SP_S# (,) S_POO RV R00 R0 R0 R0 R R R0. U0 NSZ0PX PM_SP_S# VRON PM_SP_S# Z_PIO0 PM_SP_S# IN PM_SP_S# HWP MPWROK RSMRST# RMRST_NTR VPU R *0K/F_ 0.U_ 0.U/0V/XR_ QUNT OMPUTR ate: Monday, ugust, 00 Sheet of.k_ V.K_.K_ MK.K_ MT.K/F_ T_K.K/F_ T_T 0K/F_ 0 V RV U TSH0FU R R R NSWON# U/.V/XR_ U -0 MPWROK K/F_.K_ VOUT SHN V 0.U/0V/XR_ VR_PWROO () Q PTU VPU VPU RV 0 0U/.V/XR_ WP & FSH Size ocument Number Rev TW Main oard R R R R0V-0 R0V-0 SW00PT R0V-0 R0V-0 ST R0 K/F_ HO# R0V-0 R0V-0 R 00K/F_ K/F_ K/F_ K/F_ 0K/F_ R0 M_
Page of schematic page Rev. ate 0 0 0 0 0 0 0 0 0 0 0 0 Index lock iagram hange ist IR PROOR /(MI&HOT&PI) PROOR /(R) PROOR /(POWR) PROOR /() PH / (MI&VIO) PH / (T/P/zalia) PH / (PI/PI/K/U) PH / (PIO) PH
Page Title of schematic page Rev. Date Page Title of schematic page Rev. Date
Page Title of schematic page Rev. ate Page ist lock iagram hange ist SN /(HOST&PIE) SN /(R I/F) SN /(POWER) SN /(/Strap) PH /(MI/FI/VIEO) PH /(ST/RT/H/P) PH /(PIE/US/K/NV) PH /(GPIO/PU/STRP) PH /(POWER)
intel <MCH Processor> intel <PCH>
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UM8 UMA SYSTEM DIAGRAM
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Intel Calpella BlOCK DIAGRAM
Intel alpella lok IGRM POWER /TT ONNETOR R-SOIMM H R-SOIMM H ST-O ST-H UIO/MP L SYSTEM RESET IRUIT TT HRGER RUN POWER SW +V_S/+V_S +V_SUS/+V_SUS +V_RUN/+V_RUN/+.V_RUN ual hannel R 0.V INTEL ISRETE SYSTEM
10. Circuit Diagrams and PWB Layouts
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Surface Mount Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz Features 3V & 5V operation micro-miniature size.1"x.1" no external biasing circuit required internal DC blocking at RF input &
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65W PWM Output LED Driver. IDLV-65 series. File Name:IDLV-65-SPEC
~ A File Name:IDLV65SPEC 07050 SPECIFICATION MODEL OUTPUT OTHERS NOTE DC VOLTAGE RATED CURRENT RATED POWER DIMMING RANGE VOLTAGE TOLERANCE PWM FREQUENCY (Typ.) SETUP TIME Note. AUXILIARY DC OUTPUT Note.
65W PWM Output LED Driver. IDPV-65 series. File Name:IDPV-65-SPEC
IDPV65 series ~ A File Name:IDPV65SPEC 07060 IDPV65 series SPECIFICATION MODEL OUTPUT OTHERS NOTE DC VOLTAGE RATED CURRENT RATED POWER DIMMING RANGE VOLTAGE TOLERANCE PWM FREQUENCY (Typ.) SETUP TIME Note.
Tablet SYSTEM BLOCK DIAGRAM
VER : OM P/N escription Tablet SYSTEM LOK IGRM Memory own Max. G P M* R III /00 MHZ IM FI Ivy ridge G 0 W P,,,, MI ep US- ep onn. TOUH PNEL P MI(x) mst - H P0 ST FI MI Gyroscope P ST LG0 e-compass/ G sensor
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DIS._eDP. edp N13P-GS N13P-GL N13M-GS PEG TX/RX GPU. Display P15~P19. DMI(x4) INT_LVDS INT_CRT. Display INT_HDMI USB3.0/2.0 USB3-2/USB2-1.
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CPU Merom 478 PIN (micro FC-PGA) P3,4. FSB 667 MHz(166X4) FSB 800MHz(200X4) UNBUFFERED DDRII SODIMM DDRII 533/667 UNBUFFERED DDRII SODIMM P11
WK lock iagram.mhz VRM GR P- Mx PS PU Merom PIN (micro F-PG) P, LOK GEN ISLPR P VI P FS MHz(X) FS MHz(X) TI M P- LVS R/G/ L P RT P PIE Lanes LVS R/G/ restline GM/PM PIN (micro FG) mm x mm P- RII / RII
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LS01-15B09SS LS01-15B12SS LS01-15B15SS LS01-15B24SS LS03-15B03SR2S LS03-15B05SR2S LS03-15B09SR2S LS03-15B12SR2S LS03-15B15SR2S LS03-15B24SR2S
LS0 SS & LS0RS _ onverter. W SIP economic LS series.... W High performance & compact size series.... W ~0V wide input voltage LH series.... W 0 Low temperature & high reliability L0_LT series.... 00W LH
+3V3 Supply. +3V0 Flash + VCCPGMy +2V5 FPGA VCC + FPGA I/O +1V1 FPGA Core. Overview. abaxor engineering GmbH
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IDPV-45 series. 45W PWM Output LED Driver. File Name:IDPV-45-SPEC S&E
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Responsivity (/W) First Sensor Quad PD Data Sheet Features Description pplication Pulsed 16 nm laser detection RoHS 211/65/EU Light source positioning Laser alignment ø mm total active area Segmented in
Current Sensing Chip Resistor SMDL Series Size: 0201/0402/0603/0805/1206/1010/2010/2512/1225/3720/7520. official distributor of
Product: Current Sensing Chip Resistor SMDL Series Size: 0201/0402/0603/0805/1206/1010/2010/2512/1225/3720/7520 official distributor of Current Sensing Chip Resistor (SMDL Series) 1. Features -3 Watts
3 V, 900 MHz Si MMIC AMPLIFIER
V, 9 MHz Si MMIC AMPLIFIER UPC77T FEATURES LOW VOLTAGE - LOW CURRENT: ma at V LOW POWER CONSUMPTION: mw TYP SUPER SMALL PACKAGE TAPE AND REEL PACKAGING OPTION AVAILABLE DESCRIPTION The UPC77T is a Silicon