ZK2 SYSTEM BLOCK DIAGRAM

Transcript

1 OM MRK INT VG STUFF FOR EXT VG STUFF FOR OK SPEIL FOR EXT/INT VG MP-Stage ZKM0000: ZK M SSY(GM/UM)SSY W/O PU X'TL.MHz LOK GENERTOR IS: ISLPRSGLFT SELGO: SLGSPK0 RII ZKM000: ZK M SSY(PM/MXM)SSY W/O PU ZKM000: ZK M SSY(PM/MXM) W/O PU/E-ST SO-IMM 0 SO-IMM P P H (ST) * ZK SYSTEM LOK IGRM ual hannel R /00 MHz P Penryn ufpg N antiga P, P FS /00/0 Mhz (GM/ PM/ GL0) P, P, P, P, P, P0, P X MI interface Thermal Sensor (NS LM) PIE LVS RG P MXM (n-vidia) NM-GS VRM M Fan river (G) P P0 EXT_LVS EXT_RT EXT_VI INT_LVS INT_RT R PWR TPS THERML PROTETION.V/.V PWR ISHRGER SWITH IRUIT P P P POWER TREE P P HMI switch (PS) P RT LVS HMI US HRGER ISL OKING/VI P /V SYS PWR P ISL PU ORE PWR ISL +.0V RT0 P P P P P P est onn. US US Port x US0,, luetooth US US FingerPrint US P P P P P0 Wire ocking US0 P0 udio mplifier P,P est uffer (PIEQX0) P Sub-mplifier (MX) O (ST) udio OE (LS) P P P ST0 ST ST ST US.0 zalia M. HP ROM (Option) P SPI P RJ WIRE ONN. S IHM P,P,P,P LP E (WPLG) SPI ROM P Touch Pad P0 P X'TL.KHz PI-Express US X'TL.KHz MM P Media ardreader (RTSE) US ard Reader onnector P P PIE- PIE- THEROS Giga-LN (R) PIE-& Transformer X'TL MHz P0 P New ard US P Mini ard WLN / TV US & P US & LN SWITH OK/LN (PIL00) P P0 0ZKM0 0ZKM0 0ZKM0 0ZKM0 Speaker P S/PIF P SUWOOFER P Line in P MI Jack P Int. -MI P, P K/ OON. P0 IR P RJ P Quanta omputer Inc. PROJET : ZK Size ocument Number Rev lock iagram ate: Friday, June, 00 Sheet of

2 lock Generator +V L KP0HS-T +V_LK U0 LK V power range.0v~.v () PLK_EUG () PLK_ () PLK_IH.u_ R _ R _ R _ 0 *0p_ *.u_ PLK_MINI_R PLK R PLK_IH_R 0 *0p_.u_ *.u_ () STLKREQ# () NEW_LKREQ# 0 () LKUS_ *0p_ () LK_ard () M_IH.u_ p/0v_ p/0v_.u_ Y.MHz 0u_ G_XIN G_XOUT R /F_ STLKREQ#_R R /F_ NEW_LKREQ#_R PLK_MINI_R PLK R T PLK_PM_R PLK_IH_R PU_SEL0 R.K_ R0 _ R _ FS 0 MH_SEL PU_SEL R 0K_ R _ FS *0p/0V_ 0 V_PI V_ V_PLL V_SR V_PU V_REF XTL_IN XTL_OUT V_I/O V_PLL_I/O 0 V_SR_I/O_ V_SR_I/O_ V_SR_I/O_ V_PU_I/O PU_STOP# PI_STOP# KPWRG/P# PU_0 PU_0# PI_0/LKREQ_# PU MH PI_/LKREQ_# PU MH# 0 PI_ SR_/PU_ITP PI_ SR_#/PU_ITP# ^PI_/LLK_SEL PIF_/ITP_EN N US_MHz/FS_ FS_/TEST_MOE LLK/M LLK#/M_SS REF/FS_/TEST_SEL 0u_ +V0_LK 0.u_.u_ PM_STPPU# () PM_STPPI# () K_PWRG () LK_PU_LK () LK_PU_LK# () LK_MH_LK () LK_MH_LK# () LK_REFSSLK () LK_REFSSLK# () *.u_.u_.u_ L 00.u_ KP0HS-T +.0V Pin : It acts as a level sensitive strobe to latch the FS pins and other multiplexed inputs. (,,,0,,) PT_SM Q RHU00N0 +V +V Q RHU00N0 R 0K_ () LK_REFLK () LK_REFLK# R 0K_ GT_SM GLK_SM GT_SM SR_0/OT_ SR_ SR_0#/OT_# SR_# SR_/LKREQ_# SL SR_#/LKREQ_# S SR_ SR_# SR_ SR_# SR_/LKREQ_F# VSS_PI SR_#/LKREQ_E# VSS_ SR_ VSS_I/O SR_# VSS_PLL SR_0 VSS_SR_ SR_0# VSS_SR_ SR_/LKREQ_H# VSS_SR_ SR_#/LKREQ_G# VSS_PU VSS_REF 0 0 LK_PIE_ST () LK_PIE_ST# () LK_PIE_LN (0) LK_PIE_LN# (0) LK_PIE_NEW_ () LK_PIE_NEW_# () LK_PIE_IH () LK_PIE_IH# () LK_MXM () LK_MXM# () LK_PIE_MINI () LK_PIE_MINI# () LK_PIE_GPLL () LK_PIE_GPLL# () LK_PIE_TV () LK_PIE_TV# () (,,,0,,) PLK_SM GLK_SM SLGSP PU lock select Strap table Pin 0// : For Pin PU frequency selection () PU_SEL0 PU_SEL0 R 0_ MH_SEL0 () SEL Frequency Select Table FS FS FS Frequency Mhz 0 0 Mhz +V R0 R R 0K_ STLKREQ#_R 0K_ NEW_LKREQ#_R 0K_ PLK_MINI_R ontrol PU_0 & SR_ ontrol PU_ & SR_ R *0K_ Reserve overclocking 0 Mhz PLK_PM_R R0 0K_ () PU_SEL () PU_SEL PU_SEL PU_SEL R0 0_ R 0_ MH_SEL () MH_SEL () Mhz 00Mhz Reserved 00Mhz Pin : For Pin / and / selection 0 = LLK & OT for internal graphic controller support = M & M_SS &SR_0 for external graphic controller support PLK_IH_R R 0K_ LOK GENERTOR 0 0 Mhz Pin : For Pin / selection = PU_ITP 0 = SR_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev LOK GENERTOR ate: Wednesday, July 0, 00 Sheet of

3 () H_#[..] () H_ST#0 () H_REQ#[0..] () H_#[..] () H_ST# () H_0M# () H_FERR# () H_IGNNE# () H_STPLK# () H_INTR () H_NMI () H_SMI# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U J []# L []# L []# K []# M []# N []# J []# N [0]# P []# P []# L []# P []# P []# R []# M ST[0]# R GROUP_0 R GROUP_ K REQ[0]# H REQ[]# K REQ[]# J REQ[]# L REQ[]# Y []# U []# R []# W [0]# U []# Y []# U []# R []# T []# T []# W []# W []# Y []# U [0]# V []# W []# []# []# []# V ST[]# 0M# FERR# IGNNE# IH STPLK# LINT0 LINT SMI# M RSV[0] N RSV[0] T RSV[0] V RSV[0] RSV[0] RSV[0] RSV[0] RSV[0] F RSV[0] RESERVE XP/ITP SIGNLS ONTROL S# NR# PRI# EFER# RY# SY# R0# IERR# INIT# LOK# RESET# RS[0]# RS[]# RS[]# TRY# HIT# HITM# PM[0]# PM[]# PM[]# PM[]# PRY# PREQ# TK TI TO TMS TRST# R# THERML PROHOT# THERM THERM THERMTRIP# H LK LK[0] LK[] H E G H F E F 0 H F F G G G E 0 H_IERR# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TMS XP_TRST# SYS_RST# H_PROHOT#_ H_THERM H_THERM PM_THRMTRIP# R0 _ T T T T0 T H_S# () H_NR# () H_PRI# () H_EFER# () H_RY# () H_SY# () H_REQ# () +.0V H_INIT# () H_LOK# () H_PURST# () H_RS#0 () H_RS# () H_RS# () H_TRY# () H_HIT# () H_HITM# () onnect it to PU R# is for ITP debug port or PU interposer (like IE) to reset the system SYS_RST# () LK_PU_LK () LK_PU_LK# () +.0V R K/F_ R K/F_ Layout note: H_GTLREF: Zo= ohm L<0.", /*VP+-% () H_#[0..] () H_STN#0 () H_STP#0 () H_INV#0 () H_#[..] () H_STN# () H_STP# () H_INV# () PU_SEL0 () PU_SEL () PU_SEL H_#[0..] H_#[..] T T T T T T T H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# U E [0]# F []# E []# G []# F []# G []# E []# E []# K []# G []# J [0]# J []# H []# F []# K []# H []# J STN[0]# H STP[0]# H INV[0]# N []# K []# P []# R []# L [0]# M []# L []# M []# P []# P []# P []# T []# R []# L []# T [0]# N []# L STN[]# M STP[]# N INV[]# H_GTLREF PU_TEST GTLREF PU_TEST TEST PU_TEST TEST PU_TEST TEST F PU_TEST TEST F PU_TEST TEST PU_TEST TEST TEST SEL[0] SEL[] SEL[] Penryn T GRP 0 T GRP MIS T GRP T GRP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# STN[]# STP[]# INV[]# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# STN[]# STP[]# INV[]# OMP[0] OMP[] OMP[] OMP[] PRSTP# PSLP# PWR# PWRGOO SLP# PSI# Y V V V T U U Y W Y W W Y U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# E H_# H_# H_#0 H_# H_# H_# 0 E F H_# H_# H_# E H_# H_# H_# H_#0 H_# F H_# H_# E F 0 R OMP0 R U OMP R OMP R Y OMP R E E H_#[..] H_#[..]./F_./F_./F_./F_ H_#[..] () H_STN# () H_STP# () H_INV# () H_#[..] () Layout note: comp0,: Zo=.ohm, L<0." comp,: Zo=ohm, L<0." Layout note: PRSTP#, aisy hain (S>Power>N>PU) H_STN# () H_STP# () H_INV# () IH_PRSTP# (,,) H_PSLP# () H_PWR# () H_PWRG () H_PUSLP# () PSI# () Penryn Thermal Trip (,,,) ELY_VR_PWRGOO (,) PM_THRMTRIP# Processor hot H_PROHOT#_ PU / +.0V R _ PM_THRMTRIP# R +.0V +.0V R _ Q MMT0 H_PROHOT# () SYS_SHN# (,) No use Thermal trip PU side still PU ohm. Use Thermal trip can share PU at S side No use PROHOT PU side still PU ohm. Use PROHOT to optional receiver PU side PU ohm and through isolat.k ohm to receiver side *0_ Q FV0N PU Thermal monitor () T +V (,) THERM_LERT# +V +V () LK Q0 RHU00N0 +V (0) PUFN#_ON Q RHU00N0 R 0K_ R *0_ R *0K_ R 0K_ V_TH R0 0K_ U H_THERM SLK V S LERT# OVERT# +V R0 00_ XP XN LM RESS: H NS WINON 0.u_ 00p/0V_ H_THERM L0000 LL000 XP PU/P SYS_RST# XP_TO XP_TI XP_TMS XP_PM# XP_TK XP_TRST# R R R0 R R R R00 XP_RESET# and XP_TO reserve for XP +.0V Size ocument Number Rev ate: Wednesday, July 0, 00 Sheet of +V Quanta omputer Inc. PROJET : ZK PU Host us *K_ *./F_./F_./F_./F_./F_./F_

4 U VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] F VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] K VSS[0] K VSS[0] K VSS[0] K VSS[0] L VSS[0] L VSS[00] L VSS[0] L VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[00] P VSS[0] Penryn PU / VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y E E E E E E E E E F F F F F F F F. *0u_ 0 0u_ 0u_ *0u_ Layout Note: Place these parts reference to Intel demo board. *0u_ 0u_ 0u_ 0 0u_ *0u_ *0u_ 0 *0u_ 0 *0u_ 0u_ 0 *0u_ 0u_ + *0u_ 0u_ *0u_ 0 0u_ *0u_ *0u_ *0u_ 0u_ *0u_ 0 *0u_ + 0u_ *0u_ *0u_ 0u_ 0 *0u_ 0 0u_ 0 0u_ + 0u_ *0u_ *0u_ 0u_ 0 0u_ 0 *0u_ *0u_ + 0 *0u_ V_ORE U V[00] V[00] 0 V[00] V[00] V[00] V[00] V[00] V[00] 0 V[00] V[00] V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] 0 V[00] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[00] V[0] V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] E V[0] E V[0] E V[00] E0 V[0] F V[0] F V[0] F0 V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F0 V[00] V[0] V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[00] 0 V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] Penryn Montevina platform : Early Reference oard Schematics Feb 00. Rev.0 stuff U*, N U* stuff 0U*, N0U* V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[] VP[] VP[] VP[] VP[] VP[] V[0] V[0] VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VSENSE VSSSENSE 0 0 E E0 E E E E E E0 F F0 F F F F F F0 G V J K M J K M N N R R T T V W F E F E F E. F E V_ORE V: (Low power type) V: (Standard type) Layout Note: Inside PU center cavity in rows VP :.(Supply after V Stable).(Supply before V Stable).u/V_ *.u/v_ H_VI0 () H_VI () H_VI () H_VI () H_VI () H_VI () H_VI ().u/v_.u/v_ R R 00/F_ +.0V V_ORE VSENSE () VSSSENSE () ate: Friday, June, 00 Sheet of +.V Quanta omputer Inc. PROJET : ZK Size ocument Number Rev PU Power.u/V_.u/V_ V:0m.0u/V_ 00/F_ 0u_ + 0u_ Layout Note: Z0=.,PU/P L<"

5 Intel antiga (G)M Intel antiga (P)M +.0V R0 /F_ R0 00/F_ R./F_ H_SWING H_ROMP QI P/N JSL0T0 JSL0T0 0.*VP WIE(0):SPING(0), L<0.".u_ Layout Note: WIE(0):SPING(0), L<0." /*VP WIE(0):SPING(0), L<0." GMH (NTIG) () H_#[0..] +.0V R K/F_ R K/F_ () H_PURST# () H_PUSLP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_SWING H_ROMP H_VREF *.u_ F G F E G H H F H M M J J N J P L R N L M J N R N N P N L N0 M Y Y Y0 Y Y Y W Y 0 E E E F E E E G E E U H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_SWING H_ROMP H_PURST# H_PUSLP# H_VREF H_VREF NTIG_PM HOST H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_S# H_ST#_0 H_ST#_ H_NR# H_PRI# H_REQ# H_EFER# H_SY# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_STN#_0 H_STN#_ H_STN#_ H_STN#_ H_STP#_0 H_STP#_ H_STP#_ H_STP#_ H_REQ#_0 H_REQ#_ H_REQ#_ H_REQ#_ H_REQ#_ H_RS#_0 H_RS#_ H_RS#_ F H M J P R N M E P F G0 J E0 H J0 L L J H0 K 0 F K L0 H G F G E 0 H H J F H E H J L Y Y L0 M E L M E K F F H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_STN#0 H_STN# H_STN# H_STN# H_STP#0 H_STP# H_STP# H_STP# H_REQ#0 H_REQ# H_REQ# H_REQ# H_REQ# H_RS#0 H_RS# H_RS# H_#[..] () H_S# () H_ST#0 () H_ST# () H_NR# () H_PRI# () H_REQ# () H_EFER# () H_SY# () LK_MH_LK () LK_MH_LK# () H_PWR# () H_RY# () H_HIT# () H_HITM# () H_LOK# () H_TRY# () H_INV#[..0] () H_STN#[..0] () H_STP#[..0] () H_REQ#[0..] () H_RS#[0..] () Quanta omputer Inc. PROJET : ZK Size ocument Number Rev GMH HOST ate: Friday, June, 00 Sheet of

6 Strap table U Pin Name FG[:0] FG[:] FG FG FG FG FG FG0 FG FG FG FG[:] FG FG[:] FG FG0 SVO_TRLT P_TRLT Reserved PIE Graphics Lane Reversal PIE Loopback enable Reserved XOR Strap description FS Frequency Select Reserved MI X Select itpm Host Interface ME TLS onfidentiality LLZ Reserved FS ynamic OT Reserved MI Lane Reversal igital isplay Port (SVO/P/iHMI) oncurrent with PIE SVO Present igital isplay Present Strap pin +V +V R R R00 R R R R R R R R R R R R R R GMH (NTIG) *.0K/F_ *.0K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ *.K/F_ I@.K/F_ I@.K/F_ *.K/F_ *.K/F_ 0K_ 0K_ 0K_ onfiguration 000= FS 0MHz 00 = FS 00MHz 0 = FS MHz 0 = MI X = MI X(efault) 0 = itpm Host Interface is enabled = itpm Host Interface is disabled(efault) 0 = MT Firmware will use TLS cipher suite with no confidentiality = MT Firmware will use TLS cipher suite with confidentiality(efault) 0 = Reverse Lanes = Normal operation(efault) 0 = Enabled = isabled (efault) 0 = LLZ mode enable = disable(efault) 0 = XOR mode enable = disable(efault) 0 = ynamic OT disable = ynamic OT Enable(efault) 0 = Normal (efault) = Lanes Reversed 0 = Only igital isplay port (SVO/P/iHMI) or PIE is operational (efault) = igital isplay port (SVO/P/iHMI) and PIE are operating simultaneously via PEG port 0 = No SVO/HMI evice Present(efault) = SVO/HMI evice present 0 = igital display(hmi/p) device absent(efault) = igital display(hmi/p) device present MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ SVO_TRLT SVO_TRLLK P_T P_TRLLK LK_MH_OE# PM_EXTTS#0 PM_EXTTS# TPM isable (,,,) () PM_SYN# (,,) IH_PRSTP# () PM_EXTTS#0 () PM_EXTTS# ELY_VR_PWRGOO () PLT_RST# (,) PM_THRMTRIP# (,) PM_PRSLPVR () () () T T T T0 MH_SEL0 MH_SEL MH_SEL T T R0 R0 T T T T T0 T 00/F_ *0_ N Thermal trip pin No use Thermal trip N side can N.(N has OT) PM_PRSTP# The aisy chain topology should be routed from IHM to IMVP, then to (G)MH and PU, in that order. JTG_TK JTG_TI JTG_TO JTG_TMS MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 RST_IN#_MH THRMTRIP#_R M RSV N RSV R RSV T RSV H RSV H0 RSV H RSV H RSV K RSV T RSV RSV M RSV Y RSV0 RSV G RSV F RSV H RSV F RSV L ME_JTG_TK K ME_JTG_TI N ME_JTG_TO M ME_JTG_TMS T FG_0 R FG_ P FG_ P0 FG_ P FG_ FG_ N FG_ M FG_ E FG_ FG_ FG_0 N FG_ P FG_ T FG_ R0 FG_ M0 FG_ L FG_ H FG_ P FG_ R FG_ T FG_0 R PM_SYN# PM_PRSTP# N PM_EXT_TS#_0 P PM_EXT_TS#_ T0 PWROK T RSTIN# T0 THERMTRIP# R PRSLPVR G N_ F N_ N_ N_ H N_ G N_ E N_ H N_ F N_ G N_0 H N_ H N_ H N_ H N_ G N_ H N_ F N_ H N_ G N_ E N_0 G N_ F N_ N_ N_ F N_ NTIG_PM FG PM RSV ME JTG N R LK/ ONTROL/OMPENSTION LK MI GRPHIS VI ME MIS H S_K_0 S_K_ S_K_0 S_K_ S_K#_0 S_K#_ S_K#_0 S_K#_ S_KE_0 S_KE_ S_KE_0 S_KE_ S_S#_0 S_S#_ S_S#_0 S_S#_ S_OT_0 S_OT_ S_OT_0 S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN# H_LK H_RST# H_SI H_SO H_SYN P T V U0 R R U V0 Y Y Y V R Y F Y G H F H V R F E F F E E E E H E0 E E H0 E E E H E F H G F E H H N J H N M G E K H 0 M_ROMP M_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_POK SM_REXT LK_REFLK LK_REFLK# LK_REFSSLK LK_REFSSLK# LK_PIE_GPLL LK_PIE_GPLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVREF_R P_TRLLK P_T TSTN# R R LK_MH_OE# H_IT_LK_HMI H_RST#_HMI H_SIN_HMI H_SOUT_HMI H_SYN_HMI 0K/F_ /F_ R _ M_LK0 () M_LK () M_LK () M_LK () M_LK#0 () M_LK# () M_LK# () M_LK# () M_KE0 () M_KE () M_KE () M_KE () M_S#0 () M_S# () M_S# () M_S# () M_OT0 () M_OT () M_OT () M_OT () LK_REFLK () LK_REFLK# () LK_REFSSLK () LK_REFSSLK# () LK_PIE_GPLL () LK_PIE_GPLL# () MI_TXN[:0] () MI_TXP[:0] () MI_RXN[:0] () MI_RXP[:0] () L_LK0 () L_T0 () MPWROK (,) L_RST#0 () SVO_TRLLK () SVO_TRLT () MH_IH_SYN# () +.0V H_IT_LK_HMI () H_RST#_HMI () H_SIN_HMI () H_SOUT_HMI () H_SYN_HMI () SM_VREF=0.*V_SM SM_PWROK only for R.(R P only) SM_RMRST# only for R.(R:N).u_ +.0V If HMI not support H --> N V_H--> ifferential signal-->n Impact IHM VH and VSUSH supply.v/.v NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. R K/F_ M_ROMP M_ROMP# SM_VREF TSTN# LK_REFLK# LK_REFLK LK_REFSSLK# LK_REFSSLK SM_ROMP_VOH.u_ SM_ROMP_VOL +.0V heck list note : L_VREF=0.V R /F_ P_TRL for HMI port SVO_TRL for HMI port +VR_SUS +VR_SUS 0K/F_ 0K/F_ SM_VREF.efault use voltage divider for poor layout cause +SMR_VREF not meet spec.nd Intel circuit PU/P is K,ut heck list PU/P is 0K. INTEL FE Suggest P for Ext graphics.u_ N Thermaltrip R R R R0 R *0K_ 0./F_ 0./F_ R R R R0.0u_.0u_ Q *MMT0 K/F_ R.0K/F_ R K/F_ *E@0_ *E@0_ *E@0_ *E@0_ +VR_SUS TSTN_E# () <hecklist ver0.> If TSTN# is not used, then it must be terminated with a -Ω pull-up resistor to VP. <Pin out check issue> antiga ES 0. change all to TSTN# from TSTN Quanta omputer Inc. PROJET : ZK Size ocument Number Rev GMH MI R Friday, June, 00 ate: Sheet of

7 IV&EV is/enable setting If LVS no use,all signal can N () L_KLT_TRL () INT_LVS_LON () INT_LVS_EILK () INT_LVS_EIT () INT_LVS_IGON () INT_TXLOUT0- () INT_TXLOUT- () INT_TXLOUT- () INT_TXLLKOUT- () INT_TXLLKOUT+ () INT_TXULKOUT- () INT_TXULKOUT+ () INT_TXLOUT0+ () INT_TXLOUT+ () INT_TXLOUT+ () INT_TXUOUT0- () INT_TXUOUT- () INT_TXUOUT- () INT_TXUOUT0+ () INT_TXUOUT+ () INT_TXUOUT+ () INT_RT_LK () INT_RT_T () INT_HSYN () INT_VSYN MXM STUFFE. HSYN_G VSYN_G +V R R0 I@0K_ L_TRL_LK I@0K_ L_TRL_T R INT_TXLLKOUT- INT_TXLLKOUT+ INT_TXULKOUT- INT_TXULKOUT+ INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT0+ INT_TXLOUT+ INT_TXLOUT+ INT_TXUOUT0- INT_TXUOUT- INT_TXUOUT- INT_TXUOUT0+ INT_TXUOUT+ INT_TXUOUT+ R _ R _ R _ () INT_RT_LU () INT_RT_GRN () INT_RT_RE R R I@0._ I@0._ I@.K/F_ INT_TV_OMP INT_TV_Y/G INT_TV_/R INT_RT_LU E INT_RT_GRN G INT_RT_RE J HSYN_G RTIREF VSYN_G HSYN/VSYN serial R place close to N RTIREF pull down for IV cantiga.0k ohm/f L G M M K J M E E 0 H E G0 0 H F0 0 H G J G F K F H K H E G H J J E L U L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_PM LVS PI-EXPRESS GRPHIS TV VG PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ T T L<0.", If PIE not support still connect to +V_PEG EXP OMPX H PEG_RXN0 J PEG_RXN L PEG_RXN L0 PEG_RXN N PEG_RXN P PEG_RXN N PEG_RXN T PEG_RXN U PEG_RXN Y PEG_RXN Y PEG_RXN0 Y PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN H PEG_RXP0 J PEG_RXP L PEG_RXP L PEG_RXP N0 PEG_RXP P PEG_RXP N PEG_RXP T PEG_RXP U PEG_RXP Y PEG_RXP W PEG_RXP0 Y PEG_RXP PEG_RXP PEG_RXP PEG_RXP 0 PEG_RXP J M M M0 M R N T0 U U0 Y0 0 J L M M M R N T U U Y Y _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN0 _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN _PEG_TXN R _PEG_TXP0 _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP 0 _PEG_TXP 0 _PEG_TXP 0 _PEG_TXP _PEG_TXP 0 _PEG_TXP _PEG_TXP0 _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP _PEG_TXP +.0V./F_ PEG_RXN[:0] () an support reversal routing.if FG=, PI Express is normal operation. If FG=0, then PEG_TXP0 becomes PEG_TXP, PEG_TXP becomes PEG_TXP, PEG_TXP becomes PEG_TXP, etc. similarly for PEG_RXP[:0] and PEG_RXN[:0] PEG_RXP[:0] ().u_.u_.u_.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_.u_.u_.u_.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ *E@.u_ PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXN[:0] () PEG_TXP[:0] () IV&EV is/enable setting </>Montevina_Schematics_hecklist_Rev0_ a)for TVOUT isabled, TV_ONSEL[:0] onnect to. ut design guide Rev0. show N.What is correct. b)for RT isable, RT LK, RT T. RT_HSYN, RT_VSYNThese signals should be connected to. ut design guide Rev0. show N, Intel suggest follow esign guide. SP@ <check list> For EV@ RT R/G/ 0ohm to RTIREF 0ohm to R R R R RTIREF For IV:.0Kohm For EV:0ohm SP@.0K/F_ RT_R/G/ For IV: 0ohm For EV:0ohm SP@0_ SP@0_ SP@0_ <check list> For IV@ RT R/G/ 0ohm to RTIREF.0Kohm to RTIREF INT_RT_LU INT_RT_GRN INT_RT_RE R *E@0_ R *E@0_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev GMH VG ate: Wednesday, July 0, 00 Sheet of

8 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M M0 M M M M M M M M M M M M M M M QS M QS M QS0 M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M 0 M M M M M M M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M QS# M M QS# M 0 M M QS# M 0 M QS# M M M M QS# M M QS M QS# M M M M M M QS M M M M0 M QS M M QS M QS M M QS M M M M QS0 M QS M M M M M QS# M QS#0 M M M M M Q[:0] () M S0 () M M[:0] () M QS[:0] () M QS#[:0] () M [:0] () M RS# () M S# () M WE# () M Q[:0] () M S0 () M M[:0] () M QS[:0] () M QS#[:0] () M [:0] () M RS# () M S# () M WE# () M S () M S () M S () M S () Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Friday, June, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Friday, June, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH RII Friday, June, 00 ZK GMH (NTIG) R SYSTEM MEMORY U NTIG_PM R SYSTEM MEMORY U NTIG_PM S_Q_0 J S_Q_ J S_Q_0 U0 S_Q_ T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ 0 S_Q_ S_Q_ N S_Q_0 V S_Q_ Y S_Q_ S_Q_ 0 S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ M S_Q_0 V S_Q_ W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ J S_Q_0 S_Q_ S_Q_ U0 S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ J0 S_Q_0 T S_Q_ N S_Q_ U S_Q_ U S_Q_ T S_Q_ N0 S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_0 N S_Q_ M S_Q_ J S_Q_ J S_Q_ M S_Q_ N S_Q_ N S_S_0 S_S_ G S_S_ T S_S# 0 S_M_0 M S_M_ T S_M_ Y S_M_ U S_M_ S_M_ Y S_M_ T S_QS_0 J S_QS_ T S_QS_ S_QS_ S_QS_ W S_QS_ S_QS_ U S_QS_ M S_M_ J S_QS#_0 J S_QS#_ T S_QS#_ S_QS#_ S_QS#_ Y S_QS#_ S_QS#_ U S_QS#_ M S_M_0 S_M_ S_M_0 S_M_ G S_M_ H S_M_ H S_M_ G S_M_ H S_M_ G S_M_ S_M_ S_M_ G S_M_ F S_M_ W S_RS# 0 S_WE# Y0 S_M_ Y R SYSTEM MEMORY UE NTIG_PM R SYSTEM MEMORY UE NTIG_PM S_Q_0 K S_Q_ H S_Q_0 S_Q_ Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ P S_Q_0 E S_Q_ S_Q_ F0 S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H0 S_Q_ G S_Q_ P S_Q_0 G S_Q_ H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ J S_Q_0 S_Q_ S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ J S_Q_0 R S_Q_ N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_0 M S_Q_ M S_Q_ H S_Q_ J S_Q_ P S_Q_ U S_Q_ U S_S_0 S_S_ S_S_ S_S# G S_M_0 M S_M_ Y S_M_ 0 S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_0 L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_0 L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_0 V S_M_ S_M_0 S_M_ W S_M_ Y S_M_ H S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_ U S_RS# U S_WE# F

9 +VR_SUS Power consumption reference to Intel antiga chipset ES Volume. Section 0 GM TP 0.~W GS TP ~W PM TP W UG +.0V_XG Intel check list(rev 0.) No description for V_SM bulk P Intel R(Rev 0.) 0U* Reserve near to power 0U* near to N Intel check list(rev 0.) 0U* near to power(+v.0m). 0U* near to N Intel R(Rev 0.) 0U* near to power(+v.0m). 0U* near to N ESR=m ohm u_ u_.u_ V_SM(.V) R(00M) 000m_S0, m_s R(M) : 00m_S0 R(0M) : 0m_S0.0V Graphics core V_XG V_XG_NTF.m Voltage regulator is shared between the Graphics ore Rail, V_HPLL,V_MPLL,V_PEG_PLLV_PEG_PLL, V_SM_K, V_PLL, V_PLL, V_HPLL, V_SM, V_XF IV@ + 0u_ +.0V_XG R R +.0V_XG I@0/F_ I@0/F_ P N H G F Y W V U T R P N H G F G0 H G F Y W V U T R P W W T Y E E Y E J G E Y H0 F0 E T T M L E J H G F Y V U N M U T J H V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_0 V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_0/N V_SM_/N V_SM_/N V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_ V_XG_0 V_XG_ V_XG_ V_XG_SENSE VSS_XG_SENSE POWER V SM V GFX V GFX NTF V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_0 V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V SM LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H G F E Y W V U M K H G F E Y W V M L K J H G F E Y W V U V M0 V Y M0 V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF V_SM_LF IV@ +.0V_XG + I@0u_.V Internal connect to power.u_ +.0V R R R I@0_ +.0V_XG Place close to the GMH Intel check list(rev 0.) 0U* near to N(ESR=m ohm) Intel R(Rev 0.) 0U* near to power(+v.0s). 0U* near to N.u_ +.0V IV&EV is/enable setting esign guide(table ) For INT VG diasble.v_xg power can connect to + I@0u_.u_ I@0_ I@0_ 0.u_ I@.u_.u_ SP@ SP@u_ SP@:IV Sutff uf EVstuff 0 ohm u_ 0 u_.u_ I@0u_.u_ I@u_.u_ I@.u_ u_ Place close to the GMH I@.u_ avity apacitors + 0u_ 0 I@.u_ UF G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_ J V_0 G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_ H V_0 F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_ F V_0 G V_ J V_ H V_ F V_ T V_ NTIG_PM V ORE POWER V NTF V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ +.0V M L K J H G E Y W U M0 L0 K0 H0 G0 F0 E Y0 W0 V0 U0 L K J H G E Y W V L K L K K K K V V_NTF 0.m_EV 0.m_IV ME Engine 0.m Total Max=.m NTIG_PM. Route V_XG_SENSE and VSS_XG_SENSE differentially. V_XG_SENSE PU to +VGFX_ORE_INT with 0ohm and VSS_XG_SENSE P with 0ohm for Intel suggest GMH (NTIG) Quanta omputer Inc. PROJET : ZK Size ocument Number Rev GMH V,NTF Friday, June, 00 ate: Sheet of

10 Power consumption reference to Intel antiga chipset ES Volume. Section 0 0 0UH, 0% 0. R_max = V +.0V +.0V.V.m for V_TV_.m for V_TV_.m for V_TV_ Total.m +.V +.V.V.m for RT m for TV.0V.m for PLL_/ 0 0.uH, 0%,, R_max=0.0Ω 0 0UH, 0% 0. R_max = 0. L +.0VM_MPLL_R F 0@00 MHz, %..V R_max=0 m m +V L I@LMPGSN_ I@0u_ R no 0U heck list need min 0U~00U for V_TV_ R L L I@0uh_ R0 0_ u_ I@0_ V_TV always keep 0.U/0.0U/0U to +.V R 0_ ESR= m ESR= m.v 0m.V m F 0@00 MHz, %. R_max=0 m L I@0uh_.u_ LMPGSN_ R +V_RT_TV_ IV&EV is/enable setting SP@:INT use 0.U EXT use 0 ohm + I@0u_ + I@0u_ 0./F_.u_ I@LMPGSN_ I@.u_ SP@.u_ +.0V.0V m.0v.m 0.u_ +.0V +V_V_RT_ I@.u_ SP@.0u_ +V G I@.u_ V_PLL/ always keep to +.0V (If no use IV dynamic core power) +.V. nh, 0. nh,, R_max= m IV&EV is/enable setting SP@:INT use 0.U EXT use 0 ohm SP@.u_.u_ 0 SP@.u_.V 0.m R R0 R 0_ I@0_ SP@:INT use 0.0U SP@.0u_ EXT use 0 ohm.0u/v_ I@0_.V.m.0V R-00 m R : 0 ohm heck list :.nh +.0V IV&EV is/enable setting SP@:INT use 0.0U EXT use 0 ohm SP@.0u_ R 0_ R 0_.0V R-00 0m +.0VM SM u_ R 0_.0V.m +.0VM_PLL +.0VM_PLL +.0VM_HPLL +.0VM_MPLL +.VSUS_TXLVS +V_PEG_G.0V.u_ 0m +.0VM_PEGPLL V_PEG_PLL +.V for Teenah use(00m) R0 P0 N0 R.u_ u_ P N T R P +.0VM SM_K *.u_ u_ V_Q share to TV and RT.V m.v m I@0u_ USE same plane 0 I@000p/0V_.u_ I@0u_.V u.u_ +V_RT_TV_ +V_H +.V_TV +.V_Q +.0VM_MH_PLL +.0VM_PEGPLL F L E J J P N P N N M M M L M L M L M L F M L UH V_RT V_RT V G VSS G V_PLL V_PLL V_HPLL V_MPLL V_LVS VSS_LVS V_PEG_G V_PEG_PLL V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ V_TV V_TV V_HPLL V_PEG_PLL NTIG_PM RT PLL LVS PEG SM V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_SM_K_NTF_ V_H V_TV V_Q V_LVS_ V_LVS_ TV H LVS POWER K TV/RT XF SM K MI HV PEG VTT VTTLF VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ V_XF_ V_XF_ V_XF_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_MI_ V_MI_ V_MI_ V_MI_ VTTLF VTTLF VTTLF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 G0 F0 K V U V U U H F H G L.u_.0V.m +.0VM_XF u_ +.VSUS_V_SM_K.u_ IV&EV is/enable setting +.VSUS_TXLVS.u_ SP@:INT use 000pf EXT use 0 ohm.u_.v 0.m.0V m.0v m 0.u_.u_ /F_.u_.u_ *0u_ ESR = 0 m SP@000p/0V_ +V.u_ R.u_.0V FS-0 m.v R-00 m L uh_ +.VSUS_SMK_R.V.m L0 +.0V ESR= m ohm heck list : 0.UH R : 0 ohm 0 0.?H, 0% R max = m L.u_ + 0u_ I@u_ R 0_ 0.uh_ +.0V_S +.0V.0V Internal connect to power +.0V 00 UH, Rdc = Max rated current = 0 m +VR_SUS nh, R=0 m I@0.uh_ u_ 0u_ +VR_SUS + 0u_ External Graphics (GMH Integrated Graphics isable) VSYN_RT V_RT_ V_LVS V_TX_LVS V_LVS V_TV V_Q V G V_XG V_XG_NTF H +.0V 0 0u_ R no 0U heck list need min 0U~00U for V_Q I@.u_ SP@:INT use 0.0U SP@.0u_ EXT use 0 ohm IV&EV is/enable setting Power Net Name V_XG_# V_XG_NTF_# antiga(v).0v +.0V F MHz, %, L LMPGSN_.0V 0m V_PEG_G V_PLL V_PLL V_SM_#.V.0V.0V.0V GMH (NTIG) +.0VM_PEGPLL_R R0 0u_ ESR=0m ohm /F_.u_.u_ +VR_SUS R I@0_.V 0.m IV&EV is/enable setting +.VSUS_LVS SP@:INT use U EXT use 0 ohm SP@u_ V_HPLL V_MPLL V_SM_K_# V_PEG_PLL V_XF_# V_HPLL V_PEG_PLL.0V.0V.0V.0V.0V.0V.0V Quanta omputer Inc. PROJET : ZK Size ocument Number Rev GMH POWER Friday, June, 00 ate: Sheet of 0

11 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Friday, June, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Friday, June, 00 ZK Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : GMH VSS Friday, June, 00 ZK GMH (NTIG) VSS VSS NTF VSS S N UJ NTIG_PM VSS VSS NTF VSS S N UJ NTIG_PM VSS_ G VSS_0 W VSS_0 U VSS_0 P VSS_0 N VSS_0 H VSS_0 F VSS_0 VSS_0 R VSS_0 M VSS_0 J VSS_ G VSS_ 0 VSS_ 0 VSS_ W0 VSS_ T0 VSS_ J0 VSS_ G0 VSS_ Y0 VSS_ N0 VSS_0 K0 VSS_ F0 VSS_ 0 VSS_ 0 VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_0 R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_0 K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_0 VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G0 VSS_0 V0 VSS_ T0 VSS_ J0 VSS_ E0 VSS_ 0 VSS_ H VSS_ VSS_ G VSS_0 VSS_ M VSS_ N VSS_ VSS_ M0 VSS_ F VSS_ H VSS_ Y VSS_ L VSS_00 E VSS_0 VSS_0 Y VSS_0 U VSS_0 N VSS_0 J VSS_0 E VSS_0 VSS_0 N VSS_0 J VSS_0 G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_0 Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J0 VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_0 L0 VSS_NTF_ V0 VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_0 E N_ N_ VSS_0 R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_0 F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_0 H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_00 L VSS_ J N_ VSS UI NTIG_PM VSS UI NTIG_PM VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_0 VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_0 R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_0 VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_0 J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_0 G VSS_ VSS_ G0 VSS_ 0 VSS_ V0 VSS_ N0 VSS_ H0 VSS_ E0 VSS_ T VSS_ M VSS_0 J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_0 VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_00 M VSS_0 E VSS_0 P VSS_0 L VSS_0 J VSS_0 F VSS_0 VSS_0 H VSS_0 VSS_0 Y VSS_0 U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_0 H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_0 H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_0 G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_0 H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_0 R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_0 W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_0 J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_0

12 IHM +VRT. Ohm pull up to.v for GLN_OMPI/O is required, no matter intel LN is used or not. ST H +.V Internal pull-down resistors that are always enabled O (ST) p/0v_ p/0v_ R +V_S () Z_SIN0 () Z_SIN () ST_LE# () ST_RXN () ST_RXP () ST_TXN () ST_TXP () ST_RXN () ST_RXP () ST_TXN () ST_TXP Y.KHZ LK_KX LK_KX RT_RST# SRT_RST# SM_INTRUER# R K/F_ IH_INTVRMEN Internal VRM enabled for VccSus_0, VccSus_, E VccL_, VccLN_0 and VccL_0. F G R R T T0 R 0M_ M/F_ 0K_ IH_GPIO./F_ H_IT_LK_R H_SYN_R H_RST#_R H_SIN H_SIN H_SOUT_R U RTX RTX RTRST# F0 SRTRST# INTRUER# INTVRMEN LN00_SLP GLN_LK LN_RSTSYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX E LN_TX 0 F H_IT_LK H H_SYN E H_RST# F H_SIN0 G H_SIN H H_SIN E H_SIN G G GLN_OK#/GPIO GLN_OMPI GLN_OMPO H_SOUT STLE# J ST0RXN H ST0RXP F ST0TXN G ST0TXP H STRXN J STRXP G STTXN F STTXP IHM REV.0 RT LP LN / GLN PU IH G H_OK_EN#/GPIO E H_OK_RST#/GPIO ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRSTP# PSLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS K K L K K J J N J J E J F E G L F F H G G H J G F H J E0 F0 H J J H H_FERR#_R T T0 H_THERMTRIP_R T ST_RIS_PN STIS L<0." LRQ0/# : Internal PU R R _ R R0./F_.K_ 0K_ +V ST_RXN0 () ST_RXP0 () ST_TXN0 () ST_TXP0 () ST_RXN () ST_RXP () ST_TXN () ST_TXP () +V LK_PIE_ST# () LK_PIE_ST () L0 (,) L (,) L (,) L (,) LFRME# (,) GTE0 () H_0M# () H_PWRG () H_IGNNE# () H_INIT# () H_INTR () RIN# () H_NMI () H_SMI# () H_STPLK# () N ST H est +.0V R *_ R R *_ R _ *0_ Layout note: PRSTP#, aisy hain (S>Power>N>PU) IH_PRSTP# (,,) H_PSLP# () +.0V PM_THRMTRIP# (,) +.0V R _ Intel IHM H_FERR# () No use Thermal trip S side still PU ohm.(serial R use 0ohm) Use Thermal trip can share PU for PU and S side(nd Serial R use. ohm) PU L<" JSLQ0T0 H udio Pin Name H_OK_EN/ GPIO H_SOUT_R Weak integrated P on the H_SOUT pin. H_SYN_R R *E@_ R I@_ R _ R _ R *E@_ R I@_ R0 _ R _ Weak integrated P on the H_SYN pins South ridge Strap Pin (/) MXM_SOUT_HMI () H_SOUT_HMI () Z_SOUT_M () Z_SOUT_UIO () H_IT_LK_R.000 MHz is output from the IHM. MXM_IT_LK_HMI () H_IT_LK_HMI () IT_LK_M () IT_LK_UIO () R *E@_ MXM_SYN_HMI () MXM_RST#_HMI () R I@_ H_SYN_HMI () H_RST#_HMI () R _ Z_SYN_M () Z_RST#_M () H_RST#_R R _ Z_SYN_UIO () Z_RST#_UIO () *0p/0V_ H_SIN R *E@0_ MXM_SIN_HMI () H_SIN R I@0_ H_SIN_HMI () Strap description Sampled onfiguration PU/P Flash escriptor Security Override Strap *0p/0V_ PWROK R *E@_ R I@_ R _ R _ 0 = The Flash escriptor Security will be overridden. = The security measures defined in the Flash escriptor will be in effect *0p/0V_ *0p/0V_ *0p/0V_ This strap should only be enabled in manufacturing environments using an external pull-up resistor. RT +VPU VRT_ VRT_ 0MIL R K_ Pjt: TZ0 Ons: TZ0 T RT_N0 RT_T N Pitch:,mm; Height:.mm 0MIL RT_N0 R Q 0MIL MMT0 +VRT R u_ R K_ +VPU R.K/F_ R 0K/F_ 0K_ 0 u_ 0K_ u_ SRT_RST# RT_RST# G *SHORT_ P G *SHORT_ P STLE# PI Express Lane Reversal (Lanes -) PWROK Internal PU hange type TP H_SOUT XOR hain Entrance XOR hain Entrance /PI Express* Port onfig bit (Port -) PWROK PWROK IH_TP H_SOUT RSV escription Enter XOR hain Normal opration(efault) Set PIE port config bit () IH_TP IH_TP H_SOUT_R R R *K_ *K_ +V Quanta omputer Inc. PROJET : ZK Size ocument Number Rev IHM HOST ate: Wednesday, July 0, 00 Sheet of

13 IHM T T T T INT# INT# INT# INT# U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H J E J PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IHM REV.0 REQ0# GNT0# REQ#/GPIO0 GNT#/GPIO REQ#/GPIO GNT#/GPIO REQ#/GPIO GNT#/GPIO /E0# /E# /E# /E# IRY# PR PIRST# EVSEL# PERR# PLOK# SERR# STOP# TRY# FRME# PLTRST# PILK PME# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO F G F F E F E R E J F R H K F G REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# IRY# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# PLT_RST# PME# internal PU K~K INTE# INTF# INTG# INTH# T T T T T T T T T T T T T T T T T T T T HP ROM +VSUS R PIRST# () PLT_RST# () PLK_IH () Reserve only (un-stuff) *.K_ S_SPI_H# NEW_R TV_R WLN GLN SPI_MISO SPI_MOSI () PIE_RXN () PIE_RXP () PIE_TXN () PIE_TXP () () () () () () () () (0) (0) (0) (0) PLE NER IH WITHIN 00 MIL PLE NER PIN SOI R *_ U0 V HOL SO SI PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP GLN_RXN GLN_RXP GLN_TXN GLN_TXP R R0 R00 U N PERN MI0RXN N.u_ PIE_TXN_ PERP MI0RXP P.u_ PIE_TXP_ PETN MI0TXN P PETP MI0TXP L PERN MIRXN L.u_ PIE_TXN_ PERP MIRXP M.u_ PIE_TXP_ PETN MITXN M PETP MITXP J PERN MIRXN J PERP MIRXP K PETN MITXN K PETP MITXP G PERN MIRXN G 00.u_ PIE_TXN_ PERP MIRXP H.u_ PIE_TXP_ PETN MITXN H PETP MITXP E PERN MI_LKN E PERP MI_LKP F PETN F PETP MI_ZOMP MI_IROMP PERN/GLN_RXN.u_ GLN_TXN_S PERP/GLN_RXP USP0N 0.u_ GLN_TXP_S PETN/GLN_TXN USP0P PETP/GLN_TXP USPN *_ SPI_LK_R USPP *_ SPI_S0#_R SPI_LK USPN SPI_S# SPI_S0# USPP F SPI_S#/GPIO/LGPIO USPN *_ SPI_MOSI_R USPP SPI_MISO_R SPI_MOSI USPN E SPI_MISO USPP USO#0 USPN N USO# O0#/GPIO USPP N USO# O#/GPIO0 USPN N US USO# O#/GPIO USPP P USO# O#/GPIO USPN M USO# O#/GPIO USPP N USO# O#/GPIO USPN M USO# O#/GPIO0 USPP M USO# O#/GPIO USPN N USO# O#/GPIO USPP N USO#0 O#/GPIO USP0N P USO# O0#/GPIO USP0P P O#/GPIO USPN S_USIS USPP G USRIS G USRIS# PI-Express SPI irect Media Interface V V U U Y Y W W T T F F W W Y Y W W V V U U U U MI_IROMP_R R MI_RXN0 () MI_RXP0 () MI_TXN0 () MI_TXP0 () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () MI_RXN () MI_RXP () MI_TXN () MI_TXP () LK_PIE_IH# () LK_PIE_IH ()./F_ USP- () USP+ () USP- () USP+ () USP- () USP+ () USP0- () USP0+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- () USP+ () USP- (0) USP+ (0) USP0- (0) USP0+ (0) USP- () USP+ () +.V US+eST NEW R EXT-US M/ US Port Wireless EXT-US MINI_TV ardreader LUETOOTH Finger Printer OKING MER *.u_ R *.K_ S_SPI_WP# WP VSS SK E *WXVSSIG SPI_LK_S SPI_S0# IHM REV.0 R00./F_ L<0.",void routing next to clock/high speed signals. +V South ridge Strap Pin (/).u_ Pin Name Strap description Sampled onfiguration PU/P REQ# TRY# STOP# EVSEL# +V INT# INT# SERR# INTE# +V 0 0 RN.K_0PR RN0.K_0PR +V +V REQ# FRME# REQ# INT# INTF# INTG# PLT_RST# USO# USO# USO# USO#0 +V_S 0 RN 0K_0PR U TSH0FU R 00K_ USO# USO# USO# USO# PLTRST# (,0,,,,) +V_S H_SYN GNT# / GPIO GNT# / GPIO GNT# / GPIO SPI_MOSI PI Express Port onfig bit 0 (Port -) PI Express Port onfig bit (Port -) ESI Strap(Server Only) Top-lock Swap Override Integrated TPM Enable PWROK PWROK PWROK PWROK LPWROK 0 = efault = Setting bit 0 0 = Setting bit = efault 0 = MI for ESI-compatible = efault 0 = "top-block swap" mode = efault 0 = INT TPM disable(efault) = INT TPM enable GNT# SPI_MOSI R0 R *K_ *0K_ +V_S LOK# REQ0# +V 0 RN.K_0PR +V IRY# PERR# INT# INTH# USO# USO# USO# USO#0 RN 0K_PR +V_S GNT0# SPI_S# / GPIO / LGPIO oot IOS Selection 0 oot IOS Selection PWROK LPWROK PI_GNT#0 0 SPI_S# 0 oot Location SPI PI LP(efault) GNT0# SPI_S# R R *K_ *K_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev IHM PIE / PI / US Friday, June, 00 ate: Sheet of

14 +V_S +V R R R R R R R R R R R R R R0 R.K_.K_.K_.K_ 0K_ 0K_ 0K_ 0K_ 0K_.K_ *0K_ 0K_ 0K_.K_ 0K_ SM_LK_ME SM_T_ME PLK_SM PT_SM RI# IH_GPIO0 SYS_RST# SM_LERT# PIE_WKE# PM_TLOW# NSWON# IH_GPIO IH_GPIO LKRUN# SERIRQ PWRTN : ms of internal debounce logic on this pin and internal PU K :(/) SF issue:when imt is not implemented, IHM SMus and SMLink should be connected together to support slave mode onnect SMLINK0 to SMLK and SMLINK to SMT (dd R,R for debug use) (,,,0,,) (,,,0,,) () () () () PLK_SM PT_SM SYS_RST# PM_SYN# PM_STPPI# PM_STPPU# () LKRUN# (0,,) PIE_WKE# () SERIRQ (,) THERM_LERT# PLK_SM PT_SM R R T T PLK_SM G PT_SM IH_GPIO0 E *0_ SM_LK_ME *0_ SM_T_ME RI# SYS_RST# SM_LERT# PM_STPPI# PM_STPPU# LKRUN# PIE_WKE# E0 M THERM_LERT# J VR_PWRG_LKEN F U SMLK SMT LINKLERT#/GPIO0/LGPIO SMLINK0 SMLINK R SUS_STT#/LPP# G SYS_RESET# M PMSYN#/GPIO0 SMLERT#/GPIO STP_PI# E STP_PU# L 0 RI# LKRUN# WKE# SERIRQ THRM# VRMPWRG TP SM ST GPIO locks SYS GPIO Power MGT ST[x]GP pins if unused require.-k to 0-k pull-up to Vcc_ or.-k to 0-k pull-down to ground R0.K_ THERM_LERT# S KSMI#_IH () KSMI# G K_PWRG () S LI#_IH GPIO K_PWRG R (,) LI# H R0 0K_ E_SI# GPIO T G GPIO LPWROK R MPWROK (,) () E_SI# IH_GPIO GPIO IH_GPIO LN_PHY_PWR_TRL/GPIO SLP_M# T0 R 0K_ STLKREQ# OR_I0 ENERGY_ETET/GPIO E L VREF L_LK0 () OR_I GPIO L_LK0 F K <hecklist ver0.> R0 *0K_ MH_IH_SYN# PNEL_I GPIO L_LK T () PNEL_I F The IHM ontroller OR_I GPIO0 VREF R connect to J L_T0 () +V_S R0 0K_ KSMI#_IH SLOK/GPIO L_T0 F Link VREF circuit is T R *0_ GPIO L_T T0 hecklist connect to required only if Intel () LP_ER R0 0K_ LI#_IH STLKREQ# GPIO L_VREF0_S +V(iMT reserve) () STLKREQ# L MT is to be supported. R_WKE# STLKREQ#/GPIO L_VREF0 E L_VREF_S R *0K_ PM_STPPI# SLO/GPIO L_VREF T G STOUT0/GPIO T F L_RST#0 () R *0K_ PM_STPPU# MI_TERM_SEL STOUT/GPIO L_RST0# F H +V +V IH_GPIO GPIO L_RST# T GPIO/LGPIO +V_S MEM_LE/GPIO T IH_GPIO0 R 0K_ () PSPK M +V_S MH_IH_SYN# SPKR GPIO0/SUS_PWR_K IH_GPIO R R () MH_IH_SYN# J R0 0K_ TPM Physical IH_TP GPIO/_PRESENT R0 0K_ MH_SYN# IH_GPIO () IH_TP IH_GPIO WOL_EN/GPIO 0 R 0K_ TP Presence for T H0 *.K/F_.K/F_ R *00/F_ TP itpm. T J0 TP0 ZS efault not T J L_VREF_S L_VREF0_S TP support IMT. So this IHM REV.0 interface follow R 0K_ R_WKE# R/hecklist PU R R only R 0K_ IH_PWROK */F_ *.u_ /F_.u_ MIS GPIO ontroller Link ST0GP/GPIO H STGP/GPIO F STGP/GPIO E STGP/GPIO 0 LK H LK F SUSLK P SLP_S# SLP_S# E SLP_S# G S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# 0 G0 M R 0 OR_I PNEL_I0 IH_GPIO IH_GPIO IH_PWROK PM_TLOW# PM_LN_ENLE_R PM_RSMRST#_R R R0 T T T 0K_ 0K_ R 0_ R PNEL_I0 () *0_ M_IH () LKUS_ () SUS# () SUS# () +V PM_PRSLPVR (,) NSWON# () PM_RSMRST#_R <hecklist ver0.> If integrated LN is not used LN_RST# tie it to.n serial R from RSMRST#. If Intel LN is used with Wake On LN, tie LN_RST# to RSMRST# and N 0ohm. L_PWROK must not assert after PWROK asserts for IMT. L_PWROK to the N and S should be connected to existing PWROK inputs on the N and S on a platform with no IMT Panel I (UM only) IH PWROK Resume RST M/ I +V R I@0K_ PNEL_I0 R0 I@0K_ PNEL_I lose to L connector (N) P_I P_I0 (GPIO0) (GPIO) Resolution x 0x00 Reserved Reserved *.u_ IH_PWROK U TSH0FU +V_S R ELY_VR_PWRGOO need PU K to +V. ZS PU at power side PWROK_E 00K_ ELY_VR_PWRGOO (,,,) PWROK_E () PM_RSMRST#_R R 0K_ R0.K_ Q MMT0 R V V.K_ RSMRST# () +VSUS Z INTEL FE (0/) "dd RSMRST# isolation (important!!! See ww Santa Rosa MoW)" efault stuff for Teenah(Interposer) chipset ZS Intel FE suggestion to add for to protect RT/MOS data from corruption when system encounters an abnormal power down sequence +V R *0K_ OR_I R 0K_ oard I +V +V +V R0 *0K_ OR_I R 0K_ R *0K_ OR_I R 0K_ I I R *0K_ OR_I0 R 0K_ I I0 default South ridge Strap Pin (/) Pin Name Strap description Sampled onfiguration PU/P GPIO0 Reserved PWROK LK Enable U +V 0 *.u_ SPKR GPIO No Reboot MI Termination Voltage PWROK PWROK 0 = efault = No Reboot mode 0 = for desktop applications = for mobile applications Internal PU PSPK MI_TERM_SEL R R0 *K_ *K_ +V () VR_PWRG_K0# NSZ0 VR_PWRG_LKEN R 00K_ Quanta omputer Inc. PROJET : ZK Size ocument Number Rev IHM GPIO Friday, June, 00 ate: Sheet of

15 IHM PER INTEL SUGGESTION: HNGE TO 00OHM & UF +V +V +V_S +V_S +.V +.V +VRT H R 00_ H R 00_ 0 Ohms@ 00 MHz, 00 L LMPGSN V.V m + 0 0u_ +V +.V L.V m +.V V m V S0:m S//:m ~.v.u_g +.V_.0V, Powered by V_0 in S0.V S0:m S//:m L0 0 u_ If use S M for LN function. nd support wake up need connect to relation power. uh_.v 0m 0.u_ S_VREF u_ 0uh_ 0 0u_.u_ Power consumption reference to Intel IH Family ES Rev..u_ +VPU_IH_VREF_SUS u_ u_.v m.v m.u_ +.V_PLL_IH u_ u_ u_.v m 0.u_ 0.u_ VLN_0_INT_IH.u_ +.V_IH_GLNPLL_R 0u_.u_ E E E E E E F G H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J E F G H J E F G0 G H0 J0 G0 G J 0 E E UF VRT VREF VREF_SUS V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] VSTPLL V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] V [] V [] V [] V [0] V [] V [] V [] V [] V [] VUSPLL V [] V [] V [] V [] V [0] VLN_0[] VLN_0[] VLN_[] VLN_[] VGLNPLL VGLN_[] VGLN_[] VGLN_[] VGLN_[] VGLN_ IHM REV.0 VGP RX TX US ORE GLN POWER ORE VPSUS VPUS VP_ORE PI V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] VH VSUSH VSUS_0[] VSUS_0[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VL_0 VL_ VL_[] VL_[] E F L L L L L L M M P P T T U U V V V V V V R W Y G J 0 F0 G 0 F G G J J K J J F F E F T T T T T T U U V V W W Y Y T G G +V_H_IO_IH +.V_IH_VMIPLL.0u/V_ +.0V_IH_MI 0.u_.u_.u_ +V_VSUSH TP_VSUS_0_IH_ TP_VSUS_0_IH_ TP_VSUS IH_ VSUS INT_IH VL_0_INT_IH VL INT_IH.u_.u_.u_.0u_ 0 *u_.u_.u_ 0u_ u_ T T0 T 0.u_.u_.u_ If use S M for LN function. nd support wake up need connect to relation power..0v m L.0u/V_ *.u_.u_.v m +.0V +V +.V.0V 0m L NQ00T-00Y-N +.0V 00 MHz, 0..V S0:m S//:m uh_ 00 m, 0% +.0V.0V m.u_.v 0m +V_S.V S0:m S//:m +V +V_S I@0_ +.V_S.V /.V S0:m S//:m +V.V /.V m +.V VSUS_0 power by V_0 in S0 / VSUS_ in S/S/S VSUS_ power by V in S0 / VSUS_ in S/S/S.u_ 0.u_.u_.u_ R0 R R R0 *E@0_ *E@0_ I@0_ VL_0 power by V_0_ in S0 VL_ power by V in S0 Impact IHM VH and VSUSH supply.v/.v Support INT HMI H interface. These power only support.v.evice must to meet. NOTE: If (G)MH's H udio signals are connected to IHM for ihmi, VH and VSUSH on IHM should be only on.v. These power pins on IHM can be supplied with.v if and only if (G)MH's H is not connected to IHM. onsequently, only.v audio/modem codecs can be used on the platform. UE VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] H VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G0 VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] H VSS[00] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[00] J VSS[0] J VSS[0] J VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] IHM REV.0 VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[] VSS_NTF[] H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y G H F H H J J J J.V m.u_ +V Quanta omputer Inc. PROJET : ZK Size ocument Number Rev IH POWER Friday, June, 00 ate: Sheet of