INT_LVDS. Pineview. Graphics Interfaces CPU P4,5,6,7 CRT DMI DMI. PCI-Express(Port1~4) Tigerpoint PCI-E P8,9,10,11,12,13 PN : AJSLGXX0T14 LPC LPC

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1 ZE lock iagram 0 K0 RIII-SOIMM P MT/s R SYSTEM MEMORY Pineview PU P,,, MI Graphics Interfaces INT_LVS RT 0. "Panel Up to 0*00 or * P RT P P N0.G: JSLXEVT0 N.G: JSLXUT0 N.G: JSLXVT0 MI(x) harger P US port* G P P luetooth module P WLN P0 P0 ST 0 ST - H P US.0 (Port0~) US-0,, US- US- TTERY US- P Intel High efinition udio US- ST US RT IH MI Tigerpoint S P,,0,,, PN : JSLGXX0T LP PI-E PI-Express(Port~) PIE- PIE- PIE- PIE- US- US- G/WiMX P0 WLN/WiMX P0 LN RTL0T P ard Reader RTS0-GR P US- SIM ard P0 +VPU +VPU +V_S +V_S +VSUS +V +V P V_ORE +.VSUS +SMR_VREF +0.V_R_VTT +.V P0 +.0V +.V ischarge VGFX P P P LP udio odec Realtek LX P E NPEL P Int. SPK ONN Int. MI ONN MI Jack ombo Jack K/ on. P Touch Pad / on. P SPI Flash P harger P Quanta omputer Inc. PROJET : ZE Size ocument Number Rev lock iagram ate: Friday, March, 0 Sheet of

2 LK GEN (LK) 0 V_LK_.V +V L0 PY00T-0Y-N//00ohm_ Place close to L.U/0V_.U/0V/.U/0V_.U/0V_ V_LK_.V.U/0V_.U/0V_ 0.uF near every power pin +.V R./J_ L PY00T-0Y-N//00ohm_ <000_FE Poyueh> dd.ohm resistor for noise suppress.u/0v/ Place close to L PM_STPPI#_R PM_STPPU# LKREQ_MP#_R R R R +V 0K/J_ 0K/J_ 0K/J_ 0.uF near every power pin U LKREQ_MN#_R R0 0K/J_ V_IO can be ranging from.0v to.v. +.0V V_REF_. V_PI_. V_M_. 0 V_SR_IO_.0 V_ORE_. V_ORE_. PI_STOP# PU_STOP# PM_STPPI#_R PM_STPPU#_R R R *0/J_ *0/short_J_ / : orbettpark_schm_rev0.: If this pin is used as PI_STOP#, it is required to provide a 0-k pull-up to Vcc_. It is not recommended to connect this signal to the Tiger Point(NM0) as it may cause unexpected system behavior. PM_STPPI# [] PM_STPPU# [] To S LKREQ_LN#_R R 0K/J_ US_M R 0K/F_ FG input hardware strapping to allocate PLL assignment. LOW = oth PU and SR clock drive from PLL HIGH = PU clock drive from PLL, SR clock drive from PLL. ontains 00kΩ pull-down resistor. R0 0_ L PY00T-0Y-N//00ohm_ Place close to L.U/0V/ V_LKIO_.0V.U/0V_.U/0V_.U/0V_ V_SR_IO_.0 V_PU_IO_.0 N N N N PU_0 PU_0# PU_ 0 PU_# SR_/PU_ITP SR_/PU_ITP# LK_PU_LK [] LK_PU_LK# [] LK_MH_LK [] LK_MH_LK# [] LK_PIE_LNP [] LK_PIE_LNN [] To PU (ore LK) To PU (Host LK) To LN (LN) MHz MHz 00 MHz <EMI> 0.uF near every power pin P/0V_ G_XIN Y L=0p.MHZ P/0V_ G_XOUT [] LKUS_ [] M_IH rystal place within 00mil of K0 [0] PLK_IH [] LLK_E Follow Silegro schematic [0] PLK_EUG [,0] SMT [,0] SMK LK_SEL_FS R R R LK_SEL_FS R0 R0 R0 R K_ /J_ /J_ 0K_ /J_ /J_ /J_ G_XOUT G_XIN SMT SMK FS US_M FS ITP_EN M_SEL XTL_OUT XTL_IN S SL US_/FS US_ REF/FS 0 PIF/ITP_EN MHz/PI_/SEL_MHz SR_ 0 SR_# SR_ SR_# SR_ SR_# SR_ SR_# SR_ SR_# OT/SR OT#/SR# L_LK 0 L_LK# REFLK REFLK# PELK+ [0] PELK- [0] To Mini ard (G/Wimax) 00 MHz PELK+ [0] PELK- [0] To Mini ard (WLN) 00 MHz LK_PIE_MIP [] LK_PIE_MIN [] To PU (MI LK) 00 MHz LK_RREER [] LK_RREER# [] To ard Reader 00 MHz LK_PIE_IH [] LK_PIE_IH# [] To S (MI LK) 00 MHz REFLK [] REFLK# [] To PU (PLL LK) MHz REFSSLK [] REFSSLK# [] To PU (PLSS LK) 00 MHz US_M ITP_EN FS FS M_SEL 0 *0P/0V_ *0P/0V_ *0P/0V_ *0P/0V_ *0P/0V PI _M _L _ST _SR _PU _REF Thermal Pad SLGLVV ST ST# LKREQ_# LKREQ_# LKREQ_# KPWRG/P# LKREQ_LN#_R LKREQ_MP#_R LKREQ_MN#_R R R R0 LK_PIE_ST [] LK_PIE_ST# [] To S (ST LK) 00 MHz /F_ ontrol SR_ Register b for LKREQ_# LKREQ_LN# [] /F_ 0 = SR, =SR LKREQ_WLN# [0] /F_ ontrol SR_ Register b for LKREQ_# LKREQ_R# [] 0 = SR, =SR VR_PWRG_K0 [] ontrol SR_ Register b for LKREQ_# 0 = SR, =SR <000> dd ohm for current leakage lock Gen I +V R0.K_ [,0] PLK_SM SMK SMK [,0] +V +V R0 R0 *0K/J_ ITP_EN M_SEL = Pin / as PU_ITP 0 = Pin / as SR_ pin 0 has internal pull down resistor. 0 : follow vendor's suggestion, change from 0K to.k R0 R 0K/J_.K/J_ *0K/J_ = Pin as MHz 0= Pin as MHz FS FS Frequency 0 0 MHz 0 MHz 00MHz 0 00MHz [] [] PU_SEL PU_SEL +.0V LK_SEL_FS LK_SEL_FS [,] VR_PWRG_K0# R *0K_ no connect FS to PU, due to there is no FS PIN for PU. [,0] PT_SM need to check check how to handle it in PU LK_ESEL0 N00K +.0V R *K_ R 0K_ +V Q R 0_ R R R 0_ R *0_ *K_ *0_ VR PWRG N00K Q VR_PWRG_K0.U/0V_ <000()> hange Q,Q,Q from M0000F to M00000 (with ES protection function) VR_PWRG_K0 [] N00K Q +V R.K_ SMT SMT [,0] Quanta omputer Inc. PROJET : ZE Size ocument Number Rev LOK GENERTOR ate: Friday, March, 0 Sheet of

3 +SMR_VREF_IMM M 0 M M M M 0 M M M M M M M M M SMK SMT M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q IMM0_S0 IMM0_S +SMR_VREF_Q0 +SMR_VREF_IMM +SMR_VREF_Q0 M M [:0] [] M S0 [] M S [] M S [] M_S#0 [] M_S# [] M_LK0 [] M_LK0# [] M_LK [] M_LK# [] M_KE0 [] M_KE [] M S# [] M RS# [] M WE# [] M QS[:0] [] M QS#[:0] [] M M[:0] [] M_OT0 [] M_OT [] M Q[:0] [] SMK [,0] SMT [,0] R_RMRST# [] PM_EXTTS#0 [] +.VSUS +V +0.V_R_VTT +SMR_VREF_IMM +V +.VSUS +0.V_R_VTT +SMR_VREF_Q0 +V +SMR_VREF +.VSUS +SMR_VREF +.VSUS +SMR_VREF_IMM Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, March, 0 ZE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, March, 0 ZE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, March, 0 ZE R_ST(R) Place these aps near So-imm u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_.U/.V_.U/.V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ R *0_ R *0_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_ R0 0K_ R0 0K_ 0.u/0V_ 0.u/0V_.U/.V_.U/.V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ 0.u/.V_ 0.u/.V_ + 0 0u/V_ + 0 0u/V_ R K/F_ R K/F_.u/.V_.u/.V_ R K/F_ R K/F_ 0 0p/0V_ 0 0p/0V_ P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_RVS P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_RVS V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VTT 0 VTT 0 GN 0 GN 0 0.u/0V_ 0.u/0V_ R0 *0_ R0 *0_.U/.V_.U/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_RVS P00 R SRM SO-IMM (0P) JIM R-IMM0_H=_RVS 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q.U/.V_.U/.V_.U/.V_.U/.V_ 0.u/0V_ 0.u/0V_ R 0K_ R 0K_ 0.u/0V_ 0.u/0V_.U/.V_.U/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R *0K_ R *0K_ 0.u/0V_ 0.u/0V_

4 [] [] [] [] [] [] MI_TXP0 MI_TXN0 MI_TXP MI_TXN LK_PIE_MIN LK_PIE_MIP PU FN TRL(THM) FN_PWM_N FN_ON# [] R R PUFN# T K/F_ T T L R R W T V F F H G N N R0 R N0 N K J M L U XP_RSV_00 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_0 XP_RSV_ XP_RSV_ XP_RSV_ XP_RSV_ XP_RSV_ XP_RSV_ XP_RSV_ RSV RSV_TP RSV_TP RSV_TP RSV_TP RSV_TP RSV_TP RSV_TP RSV_TP Pineview-M.G / -test : for EMI U RSV RSV RSV RSV 0 *0p/0V_ 0K_ MI_RXP_0 MI_RXN_0 MI_RXP_ MI_RXN_ EXP_LKINN EXP_LKINP RSV_K RSV_J RSV_M RSV_L Pineview-M.G FN_SIG FN_PWM_ PUFN# PINEVIEW_M VG MIS OF PINEVIEW_M +V REV =. PL_REFLKINP PL_REFLKINN PL_REFSSLKINP PL_REFSSLKINN FN_PWM_E Q MMT0 RT_HSYN RT_VSYN RT_RE RT_GREEN RT_LUE RT_IRTN RT T RT LK _IREF PM_EXTTS#_/PRSLPVR PM_EXTTS#_0 PWROK RSTIN MI REV =. OF *0p/0V_ R 0K_ HPL_LKINN HPL_LKINP R +V R M0 M N P0 P N0 L L0 P Y0 Y 0 K J0 L W W MI_TXP_0 MI_TXN_0 MI_TXP_ MI_TXN_ EXP_ROMPO EXP_IOMPI EXP_RIS RSV_TP RSV_TP RSV_K RSV_L RSV_M RSV_N 0K_ Q MMT0 VG_HSYN_R VG_VSYN_R RT_R RT_G RT_ VG_IREF R lose pin < 00mil G G H J L0 L L N P K L M N +V EXP_OMP EXP_RIS PM_EXTTS#0 0K_ R FN_PWM_N +V Place within 0mil from PU R R0 RT_R [] RT_G [] RT_ [] RT_S [] RT_SL [] FN_SIG +V IMVP_PWRG LKLT_EN RT_R LK_MH_LK# [] LK_MH_LK [] MI_RXP0 [] MI_RXN0 [] MI_RXP [] MI_RXN [] Place within 00mil from PU pin R /F_ /F_./F_ Place within 00mil from PU pin R R0 R 0K_ /F_ *0/short_ N 0/F_ 0K_ FN R 0/F_ RT_G REFLK [] REFLK# [] REFSSLK [] REFSSLK# [] XP_TMS XP_TI H_PREQ# XP_TK XP_TRST# RT_ [] [] PM_PRSLPVR [,] PM_EXTTS#0 [] IMVP_PWRG [,,] PLTRST# [,,0,,,] +V [] [,] [] FN_SIG [] RT_HSYN [] RT_VSYN [] lose to pin within 0mil lose to pin within 00mil R 00K_ R 0/F_ N_MLK N_MT THERM_LERT# +V XP PU [] [] [] [] [] [] [] [] INT_LVS_PWM +V [] LVS_LK [] LVS_T INT_LVS_IGON L Panel acklight PLE TK/TI/TMS TERMINTION NER PU XP_PM# : Length<00mil INT_TXLLKN INT_TXLLKP INT_TXLOUTN0 INT_TXLOUTP0 INT_TXLOUTN INT_TXLOUTP INT_TXLOUTN INT_TXLOUTP FN_ON# +.0V PU Thermal monitor(thm) THERM_LERT#_R.K/F_ LIG R J N N LKLT_EN L L *.K/J_ LTL_LK L *.K/J_ LTL_TK K K H <0000()_Sighting Report Rev00_Number:> void a glitch during system power up U R R 0/F_ *0_ R R 0.u/0V_ R R TSH0FU R R /J_ /J_ /J_ /J_ /J_ *0_ R R R 0K_ R0 INT_LVS_LON [] +V R *0K_ +V LERT#:pull up at S side T T T T T XP_TI T XP_TK XP_TMS XP_TRST# H_THERM H_THERM R R T T T T0 <EMI> U +V SLK S LERT# OVERT# U U R R N N R R G E G F 0 0 G 0 E0 0.K/J_.K/J_ *0P/0V_ R U V XP XN GN I TRL(P) EM--ZL-TR SMS RESS: H Pineview-M.G LVS_LK LVS_T SMS : L0000 LV LKM LV LKP LV TM_0 LV TP_0 LV TM_ LV TP_ LV TM_ LV TP_ LV_IG LV_VG LV_VREFH LV_VREFL LKLT_EN LKLT_TL LTL_LK LTL_LK L_LK L_T LV_EN PM 0 PM PM PM PM 0#/RSV PM #/RSV PM #/RSV PM #/RSV RSV TI TO TK TMS TRST_ THRM_ THRM_ RSV_0 RSV_ *0P/0V_ *0/short_ LVS H_THERM 0 PINEVIEW_M PU H_THERM +.0V Max 00mil H_EXGREF H_THRMTRIP# IMVP_PWRG +.0V T0 H_PREQ# H_THRMTRIP# H_PWRG H_GTLREF PU_SEL0 PU_SEL PU_SEL Place within 00mil from PU pin and mil spacing 00p/0V_ REV =. IH OF 0.u/0V_ <Layout Note> Routing 0:0 mils and away from noise source with ground gard R /F_ R.K/F_ H_EXGREF +.0V PU_SEL0 PU_SEL PU_SEL +.0V egree Protection(PU) PU SMI_ 0M_ FERR_ LINT00 LINT0 IGNNE_ STPLK_ PRSTP_ PSLP_ INIT_ PRY_ PREQ_ THERMTRIP_ PROHOT_ PUPWRGOO GTLREF RSV RSV LKN LKP SEL_0 SEL_ SEL_ VI_0 VI_ VI_ VI_ VI_ VI_ VI_ RSV RSV RSV RSV RSV_TP RSV_TP EXTGREF U/.V_ E H H F0 F E F G G0 G E F E W H L E H0 J0 K H K H0 H H G0 G F E L 0 H K K R0 _ R _ IH_PRSTP# [,] H_PSLP# [] H_INIT# [] H_PROHOT# [] H_PWRG [] VI0 [] VI [] VI [] VI [] VI [] VI [] VI [] Friday, March, 0 ate: Sheet of H_SMI# [] H_0M# [] H_FERR# [] H_INTR [] H_NMI [] H_IGNNE# [] H_STPLK# [] <000()_hecklist Rev0.> PROHOT_:ohm±% pull-up to Vcc_0 (VP) at both PU side and Intel MVP PU_SEL [] PU_SEL [] Place within 00mil from PU pin R +.0V Near PU pin H_GTLREF LK_PU_LK# [] LK_PU_LK [] LK GEN no FS pin for PU_SEL0, so just pull high to fix it. +.0V SYS_SHN# [,,0] PM_THRMTRIP# [] Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Pineview MI/isplay Tigerpoint 0 R0 K/F_ : No Stuff 00 (R v.0) R K/F_ R K_ R R R Q MMT0 *0_ U/.V_ Q N00K 0/J_ 0/J_ 0/J_ *0P/0V_ <000()> hange Q from M0000F to M00000 (with ES protection function)

5 PINEVIEW_M 0 U REV =. M Q[..0] [] [] M [..0] M 0 H M J M K M K M J M H M K M J M H M K M 0 K0 M H M J M J M J0 R M_0 R M_ R M_ R M_ R M_ R M_ R M_ R M_ R M_ R M_ R M_0 R M_ R M_ R M_ R M_ R QS_0 R QS_0 R M_0 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R QS_ R QS_ R M_ F G E E M QS0 M QS#0 M M0 M Q0 M Q M Q M Q M Q M Q M Q M Q M QS M QS# M M M M[..0] [] M QS[..0] [] M QS#[..0] [] [] M WE# [] M S# [] M RS# [] M S0 [] M S [] M S M WE# M S# M RS# M S0 M S M S K J K J0 H0 K R WE R S R RS R S_0 R S_ R S_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ E G M Q M Q M Q0 M Q M Q M Q M Q M Q [] M_S#0 [] M_S# [] M_KE0 [] M_KE [] M_OT0 [] M_OT M_S#0 M_S# M_KE0 M_KE M_OT0 M_OT H K J J H0 H K0 J K H H K R S_0 R S_ R S_ R S_ R KE_0 R KE_ R KE_ R KE_ R OT_0 R OT_ R OT_ R OT_ R QS_ R QS_ R M_ R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ R QS_ R QS_ R M_ 0 E G G F0 G F F E0 K K J M QS M QS# M M M Q M Q M Q M Q M Q0 M Q M Q M Q M QS M QS# M M R PWROK [,,,] SUSON [,,] HWPG_.V +V_S U TSH0FU R.K/F_ RM_PWROK R0 0K_ [] R_RMRST# [] M_LK0 [] M_LK0# [] M_LK [] M_LK# +.VSUS R0 *0K_ M_LK0 M_LK0# M_LK M_LK# RM_PWROK G F F G K R K_0 R K_0 R K_ R K_ R K_ R K_ R K_ R K_ RSV_ RSV_ RSV_ RSV_ RSV R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R QS_ R QS_ R M_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R QS_ R QS_ R M_ H J K J F H L J G G E G F G F E E G J M Q M Q M Q M Q M Q M Q M Q0 M Q M QS M QS# M M M Q M Q M Q M Q M Q M Q M Q M Q M QS M QS# M M lose to pin +.VSUS R R 0.U/0V_ R_VREF 0./F_ SM_ROMP 0./F_ SM_ROMP# L K J RSV_TP RSV_TP R_VREF R_RP R_RPU R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ E G G E M Q0 M Q M Q M Q M Q M Q M Q M Q +.VSUS lose to R_VREF pin R K/F_ 0.0U/V_ K RSV R_ R QS_ R QS_ R M_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ E0 F F0 G G0 0 J0 J E M QS M QS# M M M Q M Q M Q0 M Q M Q M Q M Q M Q +SMR_VREF R *0_ R_VREF R QS_ R QS_ R M_ M QS M QS# M M R K/F_ <EMI> 0.u/V_ *000p/0V_ G. : It is strongly recommended that the SOIMM VREF motherboard traces, going from their VREF resistor dividers to their specified SOIMM VREF pins, be ground referenced on the motherboard where ever possible to help minimize risks of any possible noise being coupled onto VREF. If they can't be referenced to ground we recommend placing a site for a 00 capacitor near the VREF divider. These 00 capacitor sites must be connected on one end to the non ground reference plane the VREF trace is referenced to and the other end must be connected to ground. Pineview-M.G OF R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ W W W M Q M Q M Q M Q M Q0 M Q M Q M Q Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Pineview R Friday, March, 0 ate: Sheet of

6 VGFX UE VORE 0.U/.V_ U/.V_ U/.V_ T T U/.V_ T T U/.V_ T V U/.V_ V W U/.V_ W W U/.V_ W +.VSUS R *0/short_ 0.U/.V_ 00 U/.V_ K K U/.V_ K L U/.V_ L L 0 U/.V_ L lose to pin R *0/short_ V._VK_R +.VSUS K L 0 0 U/.V_ U/.V_ +.0V U0 U U U U U V u/.v_ V V.U/.V_ W0 W U/.V_ 0 lose to pin V_R and VK_R rails can be 0 *0.u/0V_ on the same source but make sure the plane shapes are split near Pineview-M *0.u/0V_ to avoid noise coupling V +.V U/.V_ U/.V_ R V._VRT +.V T0 0./00ohm_ +V u/.v_ *U/.V_ U/.V_ T +.0V J +.0V U/.V_ U/.V_ +.0V VGFX VGFX. VGFX VGFX VGFX VGFX VGFX VGFX VGFX VGFX VGFX VSM VSM VSM VSM VSM VSM VSM. VK_R VK_R GFX/MH R V_R V_R V_R V_R V_R V_R. V_R V_R V_R V_R V_R VSENSE VK_R SENSE VK_R V 0.0 V VP VP V PL V_HMPLL 0.0 EXP\RT\PLL VSFR PL 0. VRT V_GIO VRING_EST VRING_WEST VRING_WEST VRING_WEST V_LGI_VI PINEVIEW_M V REV =. V V. V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V POWER PU MI VLV VLV 0. V_MI V_MI V_MI 0.0 RSV VSFR_MIHMPLL LVS U/.V_ U/.V_ U/.V_ U/.V_ u/.v_ u/.v_ E E u/.v_ E F F F G G G H H H H J J J J K K K L L L L N N N N Y V._V R *0/short_ +.V 0 0.0U/V_ lose to pin +.0V *0.u/0V_ <000()_ES Rev0.> pin is VP, not V VP_VP R *0/short_ +.0V V._LLV R00 0.uH/00m_ +.V V0 W U/.V_ u/.v_ T VP_MI R *0/short_ +.0V T U/.V_ T U/.V_ P VP_VPLL_MI R *0_ +.0V V._MIHMPLL R *0/short_ +.V VORE R 00/F_ R 00/F_ V_SENSE [] _SENSE [] *u/.v_ VP E +.0V u/.v_ *u/.v_ OF Pineview-M.G Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Pineview Power Friday, March, 0 ate: Sheet of

7 UF PINEVIEW_M E E E E E E E F F F F F G0 G H H H H H H J J J K K K K0 K L L L L L L L0 L 0 E E0 E E E E F F REV =. RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF RSV_NTF OF GN F F F G G G G G H H H H H H J J J J K K K K K K K0 K K L L L L L L L M M N N N N N N N N N P P P P P P P P R R R T U U U U V V V V V W W W W W W W0 W W W W Y Y Y T Pineview-M.G Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Pineview GN Friday, March, 0 ate: Sheet of

8 U0 TGP 00 : exchange US port and port to fix charger port will auto wake up issue. [] MI_RXN0 [] MI_RXP0 [] MI_TXN0 [] MI_TXP0 [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP 0.U/0V_ MI_TXN0_ 0.U/0V_ MI_TXP0_ 0.U/0V_ MI_TXN_ 0.U/0V_ MI_TXP_ R R P P0 T T0 T T T T U U V V0 V V MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP H H H H J J K K K K L L M M N N USP0- [] USP0+ [] USP- [] USP+ [] USP- [] USP+ [] USP- [] USP+ [] USP- [0] USP+ [0] USP- [0] USP+ [0] USP- [] USP+ [] USP- [0] USP+ [0] SYSTEM (Right down) SYSTEM (Right up) SYSTEM (Left) SIM G T WLN LN WLN ard Reader G [] PERX- [] PERX+ [] PETX- [] PETX+ [0] PERX- [0] PERX+ [0] PETX- [0] PETX+ [] PERX- [] PERX+ [] PETX- [] PETX+ [0] PERX- [0] PERX+ [0] PETX- [0] PETX+ 0 K K 0.U/0V_ PIE_TXN_ J 0.U/0V_ PIE_TXP_ J M M 0.U/0V_ PIE_TXN_ K 0.U/0V_ PIE_TXP_ K L L 0.U/0V_ PIE_TXN_ L 0.U/0V_ PIE_TXP_ M P P *G@0.U/0V_ PIE_TXN_ N *G@0.U/0V_ PIE_TXP_ N PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PI-E US O0# O# O# O# O# O#/GPIO O#/GPIO0 O#/GPIO USRIS USRIS# LK USO#R_ R0 *0/short_ USO#R [,] USO#L_ R *0/short_ USO#L [,] USO# USO#R_ E USO# E USO# USO# USO# G G USRIS R./F_ placed within 00 mil of the chipset F LKUS_ LKUS_ [] USO#R_ USO#L_ USO# R0 R R0.K_.K_ K/F_ +V_S +.V R./F_ MI_OMP H J MI_ZOMP MI_IROMP LKUS_ [] LK_PIE_IH# [] LK_PIE_IH W W MI_LKN MI_LKP R0 *0/F_ Tiger Point *0P/0V_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Tiger Point MI/PIE/US Friday, March, 0 ate: Sheet of

9 0 U0 TGP PH_GPIO R E0 Y 0 Y0 W0 V E E U Y E E V 0 RSV0 RSV0 RSV0 RSV0 RSV0 RSV0 RSV0 RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV GPIO ST HOST ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS STLE# 0GTE 0M# PUSLP# IGNNE# INIT_V# INIT# INTR FERR# NMI RIN# SERIRQ SMI# STPLK# THERMTRIP# E E U G0 Y0 Y Y Y T KRST# V 0 STRIS# R0 ST_RXN0 [] ST_RXP0 [] ST_TXN0 [] ST_TXP0 [] LK_PIE_ST# [] LK_PIE_ST [] STLE# 0K/J_ +V G0 [] H_0M# [] H_IGNNE# [] H_INIT# [] H_INTR [] ST H R H_NMI [] KRST# [] SERIRQ [] H_SMI# [] H_STPLK# [] lose to pin within 00mil./F_ STLE# [] +.0V R /J_ <000()_hecklist Rev0.> SERIRQ:.K pull-up 0GTE:0K pull-up lose to pin SERIRQ G0 KRST# PH_GPIO H_FERR# [] +.0V R0 R0 R R.K_ 0K_ 0K/J_ *0K/J_ +V lose to pin within 00mil R0 /J_ lose to pin within " PM_THRMTRIP# [] Tiger Point NOTE:. PUSLP# is supported only on nettop platforms. Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Tiger Point Sata/Host ate: Friday, March, 0 Sheet of

10 [] PLK_IH <0000()_hecklist Rev0.> Strap#/strap#: signals have weak internal pull-ups [] E_SI# +V E_SI# IH oot IOS select PH_GPIO (INT PU) T R R PH_GPIO (INT PU) PI_EVSEL# J T PI_IRY# PI_SERR# PI_STOP# F PI_LOK# PI_TRY# 0 PI_PERR# 0 PI_FRME# T T PI_REQ# PI_REQ# PH_GPIO PH_GPIO PH_GPIO PI_INT# PI_INT# PI_INT# PI_INT# PI_INTE# PI_INTF# PI_INTG# PI_INTH# E G 0 G H0 E H F PH_WP 0K/J_ K.K/J_ M U0 PR EVSEL# PILK PIRST# IRY# PME# SERR# STOP# PLOK# TRY# PERR# FRME# GNT# GNT# REQ# REQ# PIRQ# PIRQ# PIRQ# PIRQ# PIRQE#/GPIO PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO Tiger Point oot IOS Location PI TGP GPIO/ STRP# GPIO/ STRP# GPIO GPIO STRP0# RSV0 RSV /E0# /E# /E# /E# E H L J E0 E L G H H M L PI_INT# PI_INT# PI_INTF# PI_INT# PI_IRY# PI_LOK# PI_PERR# PI_TRY# PI_EVSEL# RP PI_FRME# PI_REQ# PI_REQ# PI_STOP# PI_SERR# E_SI# PI_INT# PI_INTH# PI_INTG# PI_INTE# PH_GPIO IRQ PIRQ PIRQ PIRQ PIRQ PIRQE PIRQF PIRQG PIRQH RP RP R R R.K_ RP escription US UHI ontroller #, # ' odec; option for SMUS +V +V +V +V +V +V US UH ontroller #; ST/IE Native Mode US UHI ontroller #.K_PR.K_PR.K_PR.K/J_.K/J_ 0K_.K_PR R Internal LN; Option for SI, TO, HPET#0,, Option for SI, TO, HPET#0,, Option for SI, TO, HPET#0,, US EHI ontroller; Option for SI, TO, HPET#0,, 0 0 SPI 0 PI LP (efault) PI_GNT# Internal PU Should not be P *K_ *K_ R R PH_GPIO PH_GPIO *K_ *K_ R R00 +V SWP Override strap PH_WP (INT PU) Low = swap override enabled High = efault Quanta omputer Inc. PROJET : ZE Size ocument Number Rev TigerPoint PI(/) ate: Friday, March, 0 Sheet 0 of

11 EMI M_IH U0 TGP <000()_hecklist Rev0.> TLOW#:.K pull-up to VLWYS WKE#:0K pull-up to VccSus_ SYS_RST#:0K pull-up to VccSus_ R */J_ *0P/0V_ debug port for google require [] [] Z_ITLK_UIO Z_RESET#_UIO [] Z_SIN0 [] Z_SOUT_UIO [] Z_SYN_UIO [] M_IH [,0] [,0] R R R R.KHz,+-0PPM Y [0,] [0,] [0,] [0,] [0,] PLK_SM PT_SM LP0 LP LP LP LPFRME# /J_ /J_ Z_ITLK_R Z_RST#_R Z_SOUT_R Z_SYN_R M_IH <000()_hecklist Rev0.> If integrated LN is not used LN_RST# tie it to GN. P/0V_ P/0V_ /J_ /J_ R0 0M/J_ T RT_X RT_X RTRST# SMLERT# PLK_SM PT_SM SM_LINK_LERT# SMLINK0 SMLINK T T T T T T V Y W Y Y P U W V P Y U E T V T P W T U W V T E0 H E H F F R T M P R LRQ#/GPIO L0/FWH0 L/FWH L/FWH L/FWH LRQ0# LFRME# H_IT_LK H_RST# H_SI0 H_SIN H_SIN H_SOUT H_SYN LK EE_S EE_IN EE_OUT EE_SHLK LN_LK LNR_STSYN LN_RST# LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX RTX RTX RTRST# SMLERT#/GPIO SMLK SMT SMLLERT# SMLINK0 SMLINK SPI_MISO SPI_MOSI SPI_S# SPI_LK SPI_R RT SM SPI LP UIO LN EPROM MIS M_USY#/GPIO0 GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO GPIO GPIO PRSLPVR STP_PI# STP_PU# GPIO GPIO GPIO GPIO GPIO LKRUN# GPIO GPIO GPIO GPIO PUPWRG/GPIO THRM# VRMPWRG MH_SYN# PWRTN# RI# SUS_STT#/LPP# SUSLK SYS_RESET# PLTRST WKE# INTRUER# PWROK RSMRST# INTVRMEN SPKR SLP_S# SLP_S# SLP_S# TLOW# PRSTP# PSLP# RSV T M_USY# W PH_GPIO W PH_GPIO K E_SMI# H PH_GPIO M PH_GPIO0 PH_GPIO PH_GPIO P PH_GPIO E PH_GPIO 0 Y R PH_GPIO MI ENLE PH_GPIO 0 PH_GPIO F PH_GPIO LKRUN# U PH_GPIO MI0 MI MI V MH_SYN# E NSWON# H IH_RI# G SUSLK G SYS_RST# G PLT_RST# PIE_WKE# T SM_INTRUER# U0 TPT_PWROK E_RSMRST# IH_INTVRMEN J H0 E F PM_TLOW# F0 T0 T E_SMI# [] PM_PRSLPVR [,] PM_STPPI# [] PM_STPPU# [] T : Intel suggestion enable mode T T T LKRUN# [] T H_PWRG [] THERM_LERT# [,] VR_PWRG_K0 [] NSWON# [,] T SUSLK [] PIE_WKE# [,0] R E_RSMRST# [,] S_EEP [] SUS# [] SUS# [] T IH_PRSTP# [,] H_PSLP# [] R M/F_ K/F_ VRT PLK_SM R PT_SM R PH_GPIO0 R PM_TLOW# R THERM_LERT# R0 NSWON# R PH_GPIO R E_SMI# R SYS_RST# R SMLERT# R SM_LINK_LERT# R PIE_WKE# R SMLINK R0 SMLINK0 R0 PH_GPIO R0 IH_RI# R PH_GPIO R PH_GPIO R PH_GPIO R MH_SYN# R LKRUN# R0 M_USY# R MI ENLE R0 TPT_PWROK R E_RSMRST# R +V +V_S.K_.K_.K_.K_.K_ *0K_.K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_.K_ 0K_ 0K/J_ 0K/J_ 0K/J_ +V K/F_.K_.K_ K_ 0K_ 0K_ Tiger Point R 0K_ R *0K_ R *0K_ <000()> Stuff U and and un-stuff R0 for power sequence MI MI MI0 RT(RT) VRT +VPU H00H-0 u/0v_ R VRT_ RTRST# H00H-0 0K/F_ u/0v_ R K_ 0MIL G *SHORT_P 0MIL Platform Reset U PLT_RST# R0 +V_S +V *0.u/0V_ *TSH0FU *0/short_ R0 00K_ PLTRST# [,,0,,,] [,,] [,] [,] HWPG IMVP_PWRG EPWROK TPT Power OK U R0 +V R 0_ *0_ *0.u/0V_ *TSH0FU TPT_PWROK R R *0K_ 0K_ TPT_PWROK [] R0 *0K_ VRT_ VRT_ VRT_ Q0 MMT0 Z_SOUT (INT P) Z_SYN (INT P) escription INTVRMEN Enable internal VccSus_ VRM (default) MMT0 R0 K/F_ R K/F_ R.K/F_ 0 0 * x s 0 isable N RT SOKET R 0 Reserved 0K/F_ 0 Reserved x s( port/ lanes).level Environment-related Substances Should NEVER be Used..Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Quanta omputer Inc. PROJET : ZE Size ocument Number Rev TigerPoint GPIO Friday, March, 0 ate: Sheet of

12 Place 00 caps close to ball Place 00/00 caps close to IH 0 SS +V V_VREF u/0v_ R0 00/F_ +V TGP SS +V_S U0E m VREF F RV_VREF_SUS 0.u/0V_ R 0/F_ +V_S 0m VREF_SUS m VSTPLL u VRT m VMIPLL 0m VUSPLL F Y E Y F V._STPLL 0.u/0V_ 0.U/0V_ 0 0.0U/V_ V._VMIPLL 0.0U/V_ VRT R0.U/0V/ *0/short_ +.V L *.u/.v_ *0/short_ +.V m V_PU_IO W VP_V_0. V V V V M M0 N V._V. 0 0.U/0V_ 0.U/0V_ U/.V_ U/.V_.U/0V/ R *0/short_ +.V POWER 0. V_0_ V_0_ V_0_ V_0_ J0 K P V0 VP_V_0 U/.V_ U/.V_.U/0V/ R *0/short_ +.0V 0. V V V V V V H F0 G0 R0 T V_V R0 0 U/.V_ U/.V_ 0 U/.V_ 0.U/0V_ 0.U/0V_ *0/short_ +V 0.0 VSUS VSUS VSUS VSUS F N K F RV_VSUS R U/.V_ U/.V_ 0 0.U/0V_ *0/short_ +V_S Tiger Point.Level Environment-related Substances Should NEVER be Used..Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Quanta omputer Inc. PROJET : ZE Size ocument Number Rev TigerPoint Power Friday, March, 0 ate: Sheet of

13 UL U0F TGP E F G G H H H K K K K K0 L M M N N N N N P P P R R T T V V V V V V W W Y Y 0 0 E E0 E G E F RSV E Tiger Point.Level Environment-related Substances Should NEVER be Used..Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Quanta omputer Inc. PROJET : ZE Size ocument Number Rev TigerPoint GN Friday, March, 0 ate: Sheet of

14 + <000()> hange R from S00J0 to S0J (Follow vendor's suggestion and reduce power) +VPU R0 HLL SENSOR(HSR) 00K_ LE Panel POWER SWITH(LS) MER POWER() +V _POWER 0. PT-: L0000 ; pull-up: 0K ohm LI# Irush=. R0 *0/short POWER +V R0 0K_ 0.u/V_ MR PT- *VPORT_ LV_ R *0/short_ LV.U/0V/ 000p/0V_ *0.u/0V_ +V S LI# [] 0 *0.u/0V_ 0.u/0V_ p/0v_ 0u/0V_ LE Panel(LS) R *0/short_ V_LIGHT ISPON.U/V_ 0.U/0V_ Q N00K Q TEU RT(RT) L# Q N00K R 0K_ +V <000()> hange Q,Q from M0000F to M00000 (with ES protection function) R 00K_ 0/ Modify F INT_LVS_LON [] E_FPK# [] RTV 0 [] INT_LVS_IGON 0.u/0V_ u/0v_ N0 +V R 00K_ U IN IN ON/OFF I(P) GTU OUT GN GN LV_ [] INT_TXLOUTN0 [] INT_TXLOUTP0 R R +V reserve for IVO panel [] INT_LVS_PWM [] *0/short_ *0/short_ R 0_ ONTRST INT_TXLOUTN0_L INT_TXLOUTP0_L *.U/V_ R R *0.U/0V_ *0/short_J_ *0/J_ *00P/0V_ [] [] LVS_LK LVS_T LV +V _POWER LV LV LV _POWER USP-_ USP+_ ISPON L_VJ INT_TXLOUTN_L INT_TXLOUTP_L INT_TXLOUTN_L INT_TXLOUTP_L INT_TXLOUTN0_L INT_TXLOUTP0_L INT_TXLLKN_L INT_TXLLKP_L LVS_LK LVS_T R *0_ N [] RT_R [] RT_G [] RT_ R 0/F_ R 0/F_ R 0/F_ SM0P0TFT *0p/0V_ *0p/0V_ L L L *0p/0V_ PY00T-0Y-N PY00T-0Y-N PY00T-0Y-N 0p/0V_ 0 0p/0V_ RT_R RT_G RT_ 0p/0V_ 0 RT_ T_ RTHSYN RTVSYN LK_ T [] INT_TXLOUTN [] INT_TXLOUTP R R R *0/short_ *0/short_ *0/short_ INT_TXLOUTN_L INT_TXLOUTP_L L ONN RT ONN [] INT_TXLOUTN [] INT_TXLOUTP INT_TXLOUTN_L INT_TXLOUTP_L R *0/short_ +V R *0/short_ +V 0.u/0V_ 0.u/0V_ 0.u/V_ RTV RT_YP RT_R RT_G RT_ U V_SYN SYN_OUT SYN_OUT V_ YP SYN_IN V_VIEO SYN_IN VIEO IN 0 VIEO IN VIEO OUT GN _OUT IP_Rout=0ohm RT_VSYN RT_HSYN RT_SL RT_S LK_ T_ R _ VSYN_R R _ HSYN_R RT_VSYN [] RT_HSYN [] RT_SL RT_SL [] RT_S RT_S [] L0 LM0SN RTVSYN INT_TXLLKN_L R *0/short_ [] INT_TXLLKN L LM0SN RTHSYN INT_TXLLKP_L [] INT_TXLLKP RTV *0p/0V_ RTV R0 *0/short_ USP+_ [] USP+ USP-_ +V [] USP- 0 *p/0v_ RTVSYN R.K_ R R *p/0v_ RTHSYN R *0/short_ R.K_.K_.K_ *0p/0V_ LK_ *0p/0V_ T_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev RT/LVS ate: Friday, March, 0 Sheet of

15 TOUH P (TP) N +V_TP.K/J_ R.K/J_ R m +V_TP <EMI> +V LUETOOTH(TM) TP_ONN TP_R# TP_L# TPT_N TPLK_N +V_TP 0P/0V_ <EMI> L 0./0ohm_ L 0./0ohm_ X0T000:0./0ohm_ XT0000:0./0ohm_ 0P/0V_ TPT [] TPLK [] L /0ohm_ XT000:/0ohm_ 0.U/0V_ +V R T@O Q + 0 T@0.u/V_ T_POWER [] USP+ [] USP- T@000p/0V_ T N T_LE T@ONN [0,] T_POWERON# T@0K_ *T@000p/0V_ SW TP switch TP_L# *V/V/00P_ SW TP_R# TP switch *V/V/00P_ KEYOR (K) LE/SW (UIF) PWR utton SW N 0 0 MX MX MX MY0 MY MY MX MY MY MY MY MY MY MX MY MX MX MY0 MY MX0 MY MY MY MY MX [] MX [] MX [] MY0 [] MY [] MY [] MX [] MY [] MY [] MY [] MY [] MY [] MY [] MX [] MY [] MX [] MX [] MY0 [] MY [] MX0 [] MY [] MY [] MY [] MY [] <0000()> 00 : add P~P for EMI issue <EMI> MX MX P MX 0P_PR MY0 MY MY P MX 0P_PR MY MY MY P MY 0P_PR MY MY MX P MY 0P_PR MX MX MY0 P MY 0P_PR MX0 MY MY P MY 0P_PR MY 00 size PWR LE SUS LE FULL LE HG LE G LE WLN LE +VPU +VPU +V LE LE_MER/LUE side view LE LE_MER/LUE side view LE LE_MER/LUE 0 *.V/V/0P_ R 00/J_ R 0/J_ *.V/V/0P_ *.V/V/0P_ R 00/J_ R 0/J_ *.V/V/0P_ *G@.V/V/0P_ R *G@0/J_ R 0/J_ *.V/V/0P_ PWRLE# [] SUSLE# [] TLE0# [] TLE# [] G_MINI_LE# [0] WLN_LE# [0] power switch SW *IP-TJG--S-V-T/R W/O G: use E0R00Z00 W G: use E000Z0 NSWON# NSWON# *.V/V/0P_ NSWON# [,] K ONN H LE +V side view LE *LE_ULE R *0/J_ *.V/V/0P_ *SS Q STLE# [] <0000()_hecklist Rev.0> Need the buffer for LE driving capability since the IOL is m only. side view PWR: lue Vf:.~.V, If=0m SUS: Orange Vf=.~.0V, If=0m +V PWR indicator LE LE_LUE R 0/J_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev K/T/TP/LE/Power onnector ate: Friday, March, 0 Sheet of

16 odec(o) HPR HPL HEPHONE MI-VREFO-L Universal Jack +V OGN Place near codec +.u/.v_.u/.v_ + MI-VREFO-R MI-VREFO IN_MI-VREFO 0.U/.V_ OGN place near to codec Place next to pin + OGN *0u/.V_ 0.u/0V_ +V.U/.V_ HPL R HPR R /F_ HPL- /F_ HPR- R *K/J_ OMO MI L *0/short_ HPL_SYS L *0/short_ HPR_SYS R0 00 HP_J# *K/J_ 00P/0V_ 00P/0V_ *V/V/00P_ *V/V/00P_ *V/V/00P_ OGN OGN OGN OGN MI-VREFO N UNIVERSL JK 0000FR00GZR +V OGN Place next to pin.u/.v_ R.U/.V_ 0.u/0V_ 0.u/0V_ *0/short_ +VPV.U/.V_ 0 Place next to pin NLOG Spilt by GN 0.u/0V_ L_SPK+ L_SPK- R_SPK- OGN 0 U V PV SPK-L+ P N PVEE HP-OUT-R HP-OUT-L MI-VREFO-L LINE-R LINE-L MI-R MI-L P SPK-L- MONO-OUT P(Vista Premium Version) JREF SPK-R- MI-VREFO-R 0 MI-VREFO LO-P VREF V 0 Sense- MI-R MI_R MI_L R SENSE MI_R 0.u/0V_ OGN Place next to pin Placement near udio odec 0K/F_ R OGN 0K/F_ MI-J#.U/.V_ R.K/J_ OMO MI R R K/F_ *V/V/00P_ OGN OGN OMO MI R K/F_.U/.V_ MI_R K/J_.U/.V_ MI_L <000> dd k P by FE suggestion for discharing MI-J# Q SK0 +V R.U/.V_ 0.u/0V_ *0/short_ +VPV.U/.V_ 0.u/0V_ Place next to pin Spilt by PGN Spilt by GN +V R00 R_SPK+ EP# *0/short_ 0 0.u/0V_ +Z_V SPK-R+ PV V GPIO0/MI-T SPIFO/EP SPIFO PGN.U/.V_ GPIO/MI-LK P# ST-OUT IT-LK ST-IN V-IO SYN 0 RESET# PEEP MI-L LINE-R LINE-L Sense LX IGITL PEEP_ NLOG MI_L LINE_R LINE_L SENSE.Vrms EEP_ HP_J# MI_J# PEEP dont coupling any signals if possible / separate PEEP to igital from Realtek suggestion u/0v_ 00p/0V_ R R R.K_.K/F_ 0K/F_ R R0 K/J_ K_ PEEP [] S_EEP [] If either H device io power use +.V, all device IO power change to +.V System MI 0.U/0V/ OGN MI-VREFO-R MI-VREFO-L R R.K/F_.K/F_ Place next to pin T T0 MI_T_L MI_LK_L P# 0V : Power down lass SPK amplifer.v : Power up lass SPK amplifer Z_SIN R Z_RESET#_UIO /J_ Z_RESET#_UIO [] Z_SYN_UIO [] Z_SIN0 [] Z_SOUT_UIO [] 0.u/0V_ R.U/.V_ Place next to pin *0/short_ +Z_V -test MI_L.u/.V_ MI_R.u/.V_ 0 *P-0V_ *P-0V_ MI_L R K/F_ MI_R R K/F_ MI_J# MI_L MI_R R R *0/short_ *0/short_ *0p/0V_ MI_L MI_R MI_J# *0p/0V_ *0.u/V_ N UNIVERSL JK 0000FR00GZR Normal Open Jack *p/0v_ Z_ITLK_UIO [] OGN OGN place near codec I *VPORT_ Near N OGN Power (O) emodulation Filter L Place close to odec R *Short_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R *0_ R0 *0_ *000p/0V_ *000p/0V_ OGN /:0,R0,R short for EMI request Internal nalog MI OGN IN_MI-VREFO N INT_MI R 0K_ R 0 *V/V/00P_ *P-0V_ place near codec I K/J_ u/0v_ LINE_R u/0v_ LINE_L *P-0V_ *P-0V_ +V IGITL L 0_ NLOG +V Mute(O) OGN OGN OGN OGN OGN +V Internal Speaker P# R *0K_ *S *S *S Z_RESET#_UIO EP# MP_MUTE# [] 0mil for each signal R_SPK+ R0 *0/short_ R_SPK+_ R_SPK- R *0/short_ R_SPK-_ L_SPK- R *0/short_ L_SPK-_ L_SPK+ R *0/short_ L_SPK+_ *p/0v_ *p/0v_ *p/0v_ *p/0v_ N SPEKER-ON R 0_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev UO/MP ate: Friday, March, 0 Sheet of

17 US for ipod charge (US) +VPU GEPU: Enable: high active Need infrom E engineer modify R +VPU _EN [] US_HRGE_ON *K_ *0.u/0V_ US EN U *TSH0FU u/.v_ U GEPU IN OUT IN OUT OUT EN GN O# VUS_ USO#L [,] R 0/J_ -test: have charge I function: stuff U0,U,R,,R,R,R0,R no charge I function : stuff R,R,R,R,R type H=.mm +VPU lose to ONN VUS_ [] USP- [] USP+ USP- USP+ USP- USP+ USP- USP+ R0 R R R *0/J_ USP-_L *0/J_ USP+_L 0/J_ USP-_L 0/J_ USP+_L USP-_L USP+_L U0 *I(P)MXE EN V TM M TP P GN EP USP-_L USP+_L *0.u/0V_ USP-_L R USP+_L R USP-_L R USP+_L R *0/J_ USP-_R *0/J_ USP+_R 0/J_ USP-_R 0/J_ USP+_R USP-_R USP+_R o-lay R *0/short_ R *0/short_ 0 +.U/0V_ 00U/.V_ USP-_N USP+_N 0 *V/0V/0.P_ *V/0V/0.P_ Left N V GN - GN + GN GN GN US_ONN QI P/N & Footprint [] HRGE_I_ON System Status:. > Lo: M, autodetection charger identification active. > HI: PM, pass-through mode active, P/M connected to TP/TM. <000()> hange N,,(US ONN) from FHS0FR0 to FHS0FR. US(US) +VPU +VPU R *0K_ [] US_EN#.u/0V_ US_EN# U I(P)GEPU IN OUT IN OUT OUT EN# GN GN- O# VUS_0 USO#R [,] [] USP- [] USP+ R lose to ONN + 0u/.V_ *0/short_ USP-_N USP+_N 0.u/0V_ Right up N V GN - GN + GN GN GN US_ONN R *0/short_ *V/0V/0.p_ *V/0V/0.p_ VUS_0 lose to ONN + *00u/.V_ 0.u/0V_ Right down R0 *0/short_ N [] USP0- [] USP0+ R USP0-_N USP0+_N *0/short_ *V/0V/0.p_ *V/0V/0.p_ V GN - GN + GN GN GN US_ONN Quanta omputer Inc. PROJET : ZE Size ocument Number Rev US on oard/le/sw/hole ate: Friday, March, 0 Sheet of

18 LN (LN) +V_S +V_LN V0 R *0/short_ EV0 R *0/short_ 0.U/V_ 0.U/V_ 0.U/V_ *.U/0V/ lose To I lose To I Pin. U/0V_ 0.U/V_ 0.U/V_ 0.U/V_ 0.U/V_ lose to I R *0/short_ TRL lose To I Pin. 0.U/V_ 0 P/0V_ Y MHz-LN P/0V_ MLKX MLKX PU in LK Gen. R [] LKREQ_LN# R +V_LN TX0P TX0N TXP TXN V0 *0/short_ LKREQ_LN#_L MLKX LN_TLE# MLKX TRL GPO R K/J_.K/F_ RSET LN_LINKLE# U GN GN GN HV MIP0 MIN0 MIP MIN N V LKREQPIN RSET TRL 0 KXTL KXTL LEPIN/SPIS V GPOUTPIN EESKPIN/LE/TLK/SPISK EEIPIN/TI/SPISI/S EEOPIN/LE/SPISO EESPIN/TS/SL V LNWKEPIN 0 V ISOLTEPIN PERSTPIN RTL0T-V-G +V_LN EEI/S LE/EEO EES/SL V0 PIE_WKE# ISOLTE# +V_LN T R0 R LKREQ_LN#_L PIE_WKE# EEI/S EES/SL PIE_WKE# [,0] K/J_ K/J_ +V R R R R *0K/J_ *0K/J_ 0K/J_ 0K/J_ +V_LN Int. PU in S GN GN GN GN GN GN GN HSIP HSIN REFLK_P REFLK_N VTX HSOP HSON GNTX R *0/short_ PLTRST# [,,0,,,] 0 0 *.U/0V/ [] PETX+ [] PETX- [] LK_PIE_LNP [] LK_PIE_LNN.U/0V_.U/0V_ [] PERX+ [] PERX- EV0 PIE_RXP0_LN PIE_RXN0_LN TRNSFORMER (LN) For Rural RJ onnector (LN) TX0P TX0N TXP TXN R R R R 0/J_ 0/J_ 0/J_ 0/J_ TX0P_R TX0N_R TXP_R TXN_R U X-TXN X-TXP X-TX0N X-TX0P U LN_LINKLE# R +V_LN 0 *0.U/0V_ *0/J_ TERM N Y- Y+ N/- *ULMPT.TT *ULMPT.TT N/+ X-TXN RX-/- with ES solution:r,r,r0,r need to use ohm. without ES solution:r,r,r0,r need to use 0 ohm. TXN_R TXP_R TX0N_R TX0P_R U T- T+ T N N T R- R+ TX- TX+ 0 T N N T RX- RX+ X-TXN X-TXP TERM0 X-TX0N X-TX0P with ES solution: stuff R,U,U, without ES solution: remove R,U,U, R *0/J_ LN_TLE# 0 R +V_LN TERM X-TXP X-TX0N X-TX0P *0/J_ 0 N/- N/+ RX+/+ TX-/0- TX+/0+ GN GN W- W+ *0p/0V_ *0p/0V_ *0p/0V_ *0p/0V_ 0 0.0U/V_ The value should be 0.0uF-0.uF. NS00 LF_othhand 000P/KV_0 TERM R0 /F_ R /F_ *S00N- *0.U/0V_ RJ-ONN / change connector pin define Main:FTJFR0 White LE:pin(-),pin0(+) mber LE:pin(-),pin(+) Quanta omputer Inc. PROJET : ZE Size ocument Number Rev LN RTL0T-V-G Friday, March, 0 ate: Sheet of

19 + N 0 ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 0.0u/V_ 0.0u/V_ 0.0u/V_ 0.0u/V_ V_ST ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 R ST_TXP0 [] ST_TXN0 [] ST_RXN0 [] ST_RXP0 [] *0/short_ +V ST_RXP0 ST_TXN0 U *M-0SO ST_RXN0 H H VN VP ST_TXP0 H H +V *0.u/0V_ MIN_ST.U/0V_ *0.U/0V_.U/0V/ *00U/.V_ test: unstuff for ost down Quanta omputer Inc. PROJET : ZE Size ocument Number Rev ST-H Friday, March, 0 ate: Sheet of

20 Mini ard(mn) [,] T_POWERON# PLTRST# [] PLK_EUG [] PETX+ [] PETX- [] PERX+ [] PERX- [] PELK+ [] PELK- [] LKREQ_WLN# GN +V_Mini_V N0 R *0/J_ Reserved R *0_ Reserved R0 *0_ Reserved Reserved GN +.Vaux +.Vaux GN GN PETp0 PETn0 GN GN PERp0 PERn0 GN UIM_ UIM_ GN REFLK+ REFLK- LKREQ_WLN# GN LKREQ# Reserved Reserved WKE# +.V_Mini_V +V_Mini_V +V_Mini_V R RF_LE_ON R *0/short_ G_MINI_LE# +V.K/F_ +.V R0 GN 0 +.V +VSUS LE_WPN# WLN_LE#_R LE_WLN# WLN_LE# [] R *0/short_ R LE_WWN# GN 0 Q *G@N00K US_+ USP+ [] US_- USP- [] GN R WLN@0_ WL_SMT SM_T 0 WL_SMLK SM_LK +.V GN +.Vaux PLTRST#_ R *0/short_ PLTRST# PERST# PLTRST# [,,,,,] 0 RF_EN +.V W_ISLE# RF_EN [] GN R UIM_VPP LPFRME# [,] UIM_RESET LP [,] UIM_LK LP [,] 0 UIM_T LP [,] UIM_PWR LP0 [,] +.V GN +.V GN *0_ 0. +V_Mini_V *0/short_ 0 *0_ *0u/0V_ 0.u/0V_ 0.u/0V_ 0. +.V_Mini_V 0 *000p/0V_ *0.u/0V_ *0u/0V_ 0 0.u/0V_ 0.u/0V_ [,] SMT +V_Mini_V Q *N00E R *0/short_ +V_Mini_V Q *N00E RN *.K_PR WL_SMT 0 [,] PIE_WKE# Q0 MINI_WKE# MINI-R [,] SMK WL_SMLK +V_Mini_V *N00E R *0K_ G sku: stuff R, Q, don't stuff R W/O G sku: don't stuff R,Q, stuff R R *0/short_ Mini ard / GPS(MN) +VSUS +V_Mini_V. +.V_Mini_V R *G@0_ [] [] T [] [] PETX+ PETX- PERX+ PERX- +V_Mini_V N Reserved Reserved G_WKE_R Reserved Reserved GN +.Vaux +.Vaux GN GN PETp0 PETn0 GN GN PERp0 PERn0 GN UIM_ UIM_ +V_Mini_V +.V GN 0 +.V LE_WPN# LE_WLN# LE_WWN# GN 0 US_+ US_- GN SM_T 0 SM_LK +.V GN +.Vaux PERST# 0 W_ISLE# GN +V_Mini_V R *G@00K/F_ WLN_LE#_R G_MINI_LE# G_MINI_LE# [] USP+_R USP-_R G_SMT G_SMLK PLTRST#_ R *G@0_ PLTRST# G_EN [] +V R +.V R *G@.u/0V_ *G@0.u/0V_ *G@0.u/0V_ *G@0_ *G@0.u/0V_ *G@0.u/0V_ *G@0.u/.V_ *G@0p/0V_ 0. +.V_Mini_V +V_Mini_V *G@0_ 0 *G@000p/0V_ *G@0.u/0V_ +V_Mini_V R Q *G@0K_ *G@N00E R *G@0K_ [] [] PELK+ PELK- T T LKREQ_G# G_WKE R GN REFLK+ REFLK- GN LKREQ# Reserved Reserved WKE# GN *G@MINI-R GN UIM_VPP UIM_RST UIM_LK 0 UIM_T UIM_PWR +.V GN +.V UIM_VPP UIM_RST UIM_LK UIM_T UIM_PWR USP+_R USP-_R R R0 *G@0_ *G@0_ USP+ [] USP- [] [,] PT_SM PT_SM R *G@0_ +V_Mini_V Q G_SMT SIM [] USP+ [] USP- R *G@0_ USP+_R USP-_R UIM_LK USP-_R USP+_R Max:.m (Option) JSIM LK() GN() UIM_PWR -() V() UIM_VPP +() VPP() UIM_RST T RST() 0 UIM_T T() GN GN GN GN UIM_PWR UIM_T UIM_LK *G@p/0V_ *G@0p/0V_ *G@0p/0V_ +V ES UIM_RST UIM_VPP H H VN VP UIM_LK UIM_T H H *G@M-0SO <0000()_Qualcomm design guide> Place 0.uF near connector's V pin UIM_PWR [,] PLK_SM *G@N00E PLK_SM R *G@0_ G_SMLK R *G@0_ *G@SIM-onn UIM_RST UIM_VPP *G@p/0V_ *G@u/0V_ *G@0.u/0V_ *G@p/0V_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Mini-ard/WL/G/SIM ate: Friday, March, 0 Sheet 0 of

21 RTS0 [,,,0,,] PLTRST# [] LKREQ_R# 0 R U 0.U/0V_X.K/F_ +V_IN R *00K_ *U/.V_X RREF S_ S_0 RREF +V_IN LKREQ_R# PLTRST# EEO EES EESK for EMI issue: change R,R,R, R,R,R,R to ohm. S_# S_WP/X_ S_ R /J_ S R S_0 R /J_ S_0_R S_LK R /J_ S_LK_R S_M R /J_ S_M_R S_ R /J_ S R S_ R /J_ S R S_/X_RY S_/X_RE# S_/X_E# S_/X_WE# MS_S/X_LE MS_/X_WP# MS_0/X_ MS_/X_ MS_INS# MS_/X_ MS_LK R /J_ MS_LK_R Zdiff = 00 ohm [] PETX+ [] PETX- MS_/X_ MS_/X_ Zdiff = 00 ohm [] LK_RREER [] LK_RREER# V GN V MS_/X_0 MS_/X_WP# MS_/X_LE MS_S/X_LE V_S GN V V X_# V_ GN S_LK.U/.V_X MS_/X_ MS_/X_ MS_0/X_ Zdiff = 00 ohm PIE_RXP_R PIE_RXN_R V_X +V_IN V_X 0.u/0V_ S_ 0.U/0V/ S_/X_RY S_/X_RE# S_/X_E# S_/X_WE# S_M S_ TP X_ R *0/short_ MS_LK 0P/0V_ add for EMI. HSIP HSIN SP SP REFLKP REFLKN V SP SP0 SP 0.U/0V_X 0.U/0V_X 0 HSOP HSON GN V ard_v V_IN RTS0-GR SP 0 SP SP SP V_S GN 0 0.U/.V_X 0.U/0V_X 0 0.u/0V_.U/0V/ ard_v S_ 0 0.U/0V_X X_# V_ GN SP SP SP SP S_ S_0 S_LK S_M S_ V_IN LK_REQ# PERST# TP EEO EES TP EESK GPIO/EEI 0 MS_INS# MS_INS# S_# S_# S_WP/X_ SP X_ SP V_X N V_X S-V S--SW S-WP-SW X-V S-T S-T0 0 X_# S-LK X- S_/X_RY S-M X-R/ S_/X_RE# S-T X-RE 0 S_/X_E# S-T X-E MS_S/X_LE MM-T X-LE MS_/X_LE MM-T X-LE S_/X_WE# MM-T X-WE MS_/X_WP# MM-T X-WP S-GN MS_/X_0 S-GN X-0 MS_0/X_ S-WP-GN X- MS_/X_ S--GN X- MS_/X_ X- 0 MS_/X_ MS-V X- MS_/X_ MS-S X- X_ MS-T X- S_WP/X_ MS-T0 X- MS-T MS-INS MS-T 0 MS-SLK X-GN X-GN MS-GN X-GN MS-GN MR-0-H- /0 change connector pin define and footprint Main:FHSFR0 [] PERX+ [] PERX- +V R0 *0/short_ 00 0.U/0V_X 0 0.u/0V_ TP L *PY00T-0Y-N_ 0 0 *.U/.V_X 0 0.U/0V_X add 0 for EMI and close to chip pin S_LK_R 0 0P/0V_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev RTS ate: Friday, March, 0 Sheet of

22 E (K) I/O RESS SETTING(K) L PY00T-0Y-N//ohm_ 0mil +VPU SHM=0: Enable shared memory with host IOS +VPU R./J_ +VPU_E.U/.V_.U/0V_ 0.0 (0mils).U/0V_.U/.V_ EGN EGN Place every 0.uF close to every 0 power pin.u/0v_.u/0v_.u/0v_.u/0v_ U V V V V V V 0 V R0 *0/J_ +V +V_V_E S.U/0V_.U/.V_ EGN.0U/V_ 0m <0000()_Vendor suggest> Place 0nF-0.uF capacitors for every input. nd close to the input. SHM G_EN R 0K_ / omfirm by vendor mail : isabled ('') if using FWH device on LP. Enabled ('0') if using SPI flash for both system IOS and E firmware +VPU [,0] LPFRME# [,0] LP0 [,0] LP [,0] LP [,0] LP [] LLK_E [] [] LKRUN# G0 LLK_E LFRME L0 L L L LLK GPIO/LKRUN GPIO/G0 / / GPIO0/0 GPIO/ GPIO/ GPIO/ GPIO/0 GPI/ GPI/ IMNT_E EGN R *0/short_ 00P/0V_ TEMP_MT [] IMNT [] TLE0# TLE# R R 00K/J_ 00K/J_ <000()_E team suggest>.change R0/R0 to M or 00K ohm.change PWR/SUS LE's power from +VPU to +V_S or +VSUS can reduce pull-high resistor of SUSLE#/PWRLE# <EMI> LLK_E R */J_ *0P/0V_ [] [] [] [0] [,,,0,,] [] [] KRST# E_SI# E_FPK# MP_MUTE# [0] PLTRST# RF_EN SERIRQ E_SMI# [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MX0 MX MX MX MX MX MX MX MY0 MY MY MY MY MY MY MY MY MY MY0 MY MY MY MY MY MX0 MX MX MX MX MX MX MX MY0 MY MY MY MY MY MY MY MY MY MY0 MY MY MY MY MY KRST/GPIO ESI/GPIO GPIO/LRQ GPIO0/LPP LREST GPIO/PWUREQ SERIRQ GPIO/SMI KSIN0 KSIN KSIN KSIN KSIN KSIN KSIN KSIN LP KSOUT0/JENK KSOUT/TK KSOUT/TMS KSOUT/TI KSOUT/JEN0 K KSOUT/TO KSOUT/RY KSOUT KSOUT KSOUT/SP_VIS KSOUT0/P0_LK KSOUT/P0_T KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO/XOR_OUT GPIO0/KSOUT GPIO/KSOUT GPIO0/T GPIO0 GPIO0 GPIO0 0 GPIO0 GPIO0/IOX_OUT/RTS GPIO0 GPIO 0 GPIO0 GPIO/TS 0 GPIO GPIO/SL/TK 0 GPIO/S/TMS GPIO/TI GPIO GPO/SL GPIO0/PSLK/TO GPIO GPIO/PST/RY GPIO/S GPIO0 GPIO GPIO GPIO/SPI_SK GPO/SHM GPIO GPIO 0 GPO/IOX_LSH/TEST GPO/IOX_SLK/XORTR 0 GPIO GPIO/T GPIO0/T/IOX_IN_IO GPIO/T TIMER GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/E_PWM GPIO0/F_PWM/RI GPIO/G_PWM GPIO/H_PWM/SOUT HWPG THERM_LERT#_ S_ON HMI_IN PWROK_E_uR RSMRST#_uR R R0 R T T R R T *0/J_ *0/J_ *0/J_ *0/short_ *0/short_ S IN [] NSWON# [,] USO#R [,] USO#L [,] LI# [] HRGE_I_ON [] VRON [,] THERM_LERT# [,] SUS# [] US_HRGE_ON [] /# [] S_ON [,,0] SUS# [] EPWROK [,] E_RSMRST# [,] MINON [,,,] G_EN [0] NSWON# [,] US_EN# [] SUSON [,,,] FN_SIG [] ONTRST [] PEEP [] PWRLE# [] TLE0# [] PUFN# [] SUSLE# [] TLE# [] SM US PU(K) SPI FLSH(K) +VPU SPI_SI_uR R R _ 0K_ MLK MT N_MLK N_MT SPI_SI_uR_R SPI_SO_uR_R SPI_SK_uR_R SPI_S0#_uR R0 R R R U SO SI SK E.K/J_.K/J_ 0K_ 0K_ V HOL WP MXL0EMI-G +VPU +V HOL# Winbond WQIG KEZP0N0 EON ENF0-00HIP KEZ0Q00 MXI MXL0EMI-G KEFP0Z0 R.K_ +VPU.u/0V_ FOR PU Thermal Sensor FOR VG [] [] [] MLK [] MT N_MLK N_MT T T MLK MT N_MLK N_MT 0 0 GPIO/SL GPIO/S GPIO/SL GPIO/S GPIO/SL GPIO/S SM IR GPIO/IRRXM/SIN_R GPIO/SIN/IRRXL GPIO/IRRXM/TRST GPO/SOUT_R/TRIST T <000_FE suggestion> Stuff 00K and close to E side for improving power consumption / omfirm by vendor mail : If the Southbridge enables 'Long Wait bort' by default, the flash device should be 0MHz (or faster) [] TPLK TPLK TPT [] TPT [,0] T_POWERON# [] SUSLK R *0/short_ E_KX R *0/short_ If PEI.0 access functionality is not used, connect VTT pin to GN. GPIO/PSLK GPIO/PST 0 GPIO/PSLK GPIOPST GPIO00/KLKIN VTT PEI NPEL GN GN GN GN GN GN L PY00T-0Y-N//ohm_ F_SI/F_SIO F_SO/F_SIO0 PS/ FIU 0 F_S0 F_SK GPIO/LKOUT/IOX_IN_IO 0 0 GN VORF_uR VORF V_POR 0 VREF SPI_SI_uR SPI_SO_uR SPI_S0#_uR SPI_SK_uR E_LOK V_POR# VREF_uR R R R R T /J_ SPI_SO_uR_R /J_ SPI_SK_uR_R K/J_ +VPU *0/short_ +VPU SPI_SI_uR R 00K/J_ HWPG [,] HWPG_VGFX [,,] HWPG_.V [,,] HWPG_.0V [] HWPG_.V [] SYS_HWPG S *S *S *S *S R +V R 0K_ *0/short_ HWPG [,] EGN EGN U/.V_ INTERNL KEYOR STRIP SET (K) INTERNL KEYOR STRIP SET(K) +VPU RP 0K/J_0PR 0 MX MX MX MX MX MX MX0 MX +VPU SM US RRNGEMENT TLE SM us attery SM us PU thermal sensor 0/ UnStuff MY0 R *0K_ +VPU Quanta omputer Inc. PROJET : ZE Size ocument Number Rev WPE & FLSH Friday, March, 0 ate: Sheet of

23 EMI Hole Power Sequence onnector 0pin (PU) HOLE HOLE HOLE HOLE HOLE N *HG-P *HG-P HOLE HOLE *hg-tcbcdp *HG-P *HG-P HOLE *HG-P *HG-P HOLE *HG-P *HG-P HOLE0 *HG-TP [,] NSWON# +V_S [,] E_RSMRST# [,,,] SUSON +.VSUS [,,,] MINON +V +.V +.V [,] HWPG_VGFX [,] VRON [,] VR_PWRG_K0# [,] EPWROK [,,,0,,] PLTRST# NSWON# +V_S E_RSMRST# SUSON +.VSUS 0 MINON +V +.V +.V HWPG_VGFX 0 VRON VR_PWRG_K0# EPWROK PLTRST# 0 S_ON +V_S NSWON# +VSUS HWPG_.V +V +.0V HWPG_.0V VGFX HWPG VORE IMVP_PWRG TPT_PWROK PLTRST# S_ON [,,0] +V_S NSWON# [,] +VSUS HWPG_.V [,,] +V +.0V HWPG_.0V [,,] VGFX HWPG [,] VORE IMVP_PWRG [,,] TPT_PWROK [] PLTRST# [,,,0,,] HOLE HOLE HOLE HOLE h-cdp HOLE0 *G@h-cdp *0pin POWER SEQ ONN *HG-TP *HG-TP *HG-TP GN HWPG_.V HWPG HOLE *G@h-cdp HOLE h-tcbcdp HOLE h-tcbcdp HOLE *hg-cdox0p HOLE *O-ZE- NSWON# S_ON +V_S +V_S MINON +V +V +.0V VRON VORE VR_PWRG_K0# IMVP_PWRG E_RSMRST# +.V EPWROK NSWON# HWPG_.0V TPT_PWROK SUSON +.V H_PWRG HOLE *O-ZE- P 0 +VSUS +.VSUS 0 VGFX HWPG_VGFX 0 PLTRST# RESERVE Quanta omputer Inc. PROJET : ZE Size ocument Number Rev HMI(/) Friday, March, 0 ate: Sheet of

24 POWER_JK dcjk-dc p-v PJ V PL HI00R00R-00//0ohm_ V P SR0SP- V PQ O PR 0.0_0 PQ O 0 P 0.u/0V_ P 00p/0V_ P 0.u/0V_ P SW00PT P0 SMJ0 P 0.u/0V_ PR0 0K/F_ PR0 0K/F_ PQ PR0 *0/short_ SIP SR P0 0.u/0V_ /# [] P 00p/0V_ PR K_ PR 0K SR IMT0 SIP_ PQ MN0K- P u/0v_ +VPU PR 00K/F_ +VPU P u/0v_ MT MLK N GN GN GN GN 0 SSP SSN V VSM S 0 SL PR0 PR0 0/F_ 0/F_ P 0.u/V_ SIP SIN PR._ P u/0v_ ISL_VP P *R00V-0 P PR 0.u/0V. OOT VP ISL_UGTE UGTE ISL_PHSE PHSE PQ ON0 P 00p/0V_ P 0.u/0V_ PL.uH_XX P.u/V_ PR 0.0_0 T-V 0 PJ bat-btj-0tc0b-p-l-v att_onn [] IN PR *0/short_ +VPU PR 00K_ MT+ PR0 00_ TEMP_MT_ P 0.u/V_ P P0 p/0v_ p/0v_ PR./F_ IN PR0.K/F_ SET PR K/F_ HI00R00R-00//0ohm_ PL HI00R00R-00//0ohm_ PL T-V TEMP_MT [] P 00p/0V_ P *u/0v_ OK P 0.u/V_ IN IN VREF IOMP N VOMP PR0.K/F_ P 0.0u/V_ N IM PU ISL IMNT N ISL_LGTE LGTE 0 PGN PQ PR ON0 0/F_ SOP SOP_ SOP P 0.u/V_ SON T-V SON PR *0/short_ PR0 0/F_ N PR 00_ T-V VF GN GN ISL thermal pad tie to Pin IMNT [] PR./F_ P 00p/0V_ SOP_ T-V P0 00p/0V_ P 0u/V_0 P 0u/V_0 P 0.0u/V_ PR0 00_ PR0 00_ MLK [] PU *M-0SO H H VN VP MT +VPU P P 0.0u/V_ *0.0u/V_ MT [] TEMP_MT MLK H H dd ES diode base on E FE suggestion Quanta omputer Inc. PROJET : ZE Size ocument Number Rev HRGER (ISL) ate: Friday, March, 0 Sheet of

25 MIN MIN [,] SYS_SHN# SYS_SHN# [,,0] SUS SUS [] Ven=.V TP TP TP TP [] SYS_HWPG +VPU VL REF +VPU +VPU TP TP +VPU +VPU Volt +/- % T :. PEK :. OP : Width : 0mil + P *00u/V_X. P0.u/V_ PL0.uH_XX P 00p/0V_ PQ ON0 PR *0/short_ P 0.u/0V_ PR0 00K/F_ PR /F_ PR K/F_ PR 0K/F_ SYS_SHN# +V_PG +V_H +V_ +V_LX P 0.u/V_ 0 PR 0_ EN _ PGOO UGTE OOT PHSE _EN VREG P.u/.V_ VREG PU RTM P.u/.V_ REF SKIPSEL TONSEL UGTE OOT PHSE P u/.v_ PR *0/short_ +V_SKIP +V_TON 0 +V_H +V_ +V_LX PR *0_ PR *0_ PR /F_ PR *0/short_ P 0.u/0V_ PQ ON0 P 00p/0V_ PL.uH_XX +VPU P.u/V_ +VPU.Volt +/- % T : PEK : OP : Width : 0mil TP0 TP +VPU +V_L LGTE LGTE +V_L P 0u/.V_X. + P0 0.u/0V_ PR.K/F_ PR 0K/F_ PR *._ P *0p/0V_ PQ ON0 _EN +VPU +V_F PR 00K/F_ PR0 *Short_ VOUT F P 0.u/0V_ EN ENTRIP ENTRIP GN GN OUT F +VPU +V_F PQ ON0 PR *._ P *0p/0V_ PR.K/F_ PR 0K/F_ P 0.u/0V_ + PR PR.K/F_ 0.K/F_ P 0u/.V_X. OP: L(ripple current) =(-)*/(.u*0.m*) =. Iocp=-(./)=. Vth=.*mOhm=0mV R(Ilim)=(0mV*0)/0u ~0.K +V P 0.u/0V_ P HN P HN +V_LWP P 0.u/0V_ P 0.u/0V_ PR *0_ PR *0/short_ +V_L +V_L PR *0/short_ PR *0/short_ OP: L(ripple current) =(-.)*./(.u*0.m*) ~. Iocp=-(./)=.0 Vth=.0*mOhm=.mV R(Ilim)=(.mV*0)/0u ~.K PR _ P 0.u/0V_ +V_S +V_S +V +VPU +VPU +VPU +VPU +VPU,,0] S_ON PQ TEU PR0 M_ PR M_ PR _ PQ MN0K- PR _ PQ0 MN0K- PR M_ PQ MN0K- PR *M_ S MIN MIN S P 000p/0V_ PQ O0 +V_S T : 0.00 PEK : 0.0 Width : 0mil PQ O0 +V T :. PEK :. Width : 0mil PQ O0 +V T :. PEK : Width : 0mil PQ O0 T : 0. PEK : 0. Width : 0mil +V_S SUS PQ O0 +VSUS Quanta omputer Inc. PROJET : ZE Size ocument Number Rev SYSTEM V/V (RTM) T :. PEK :. Width : 0mil Friday, March, 0 ate: Sheet of

26 /0 : PR need to add after thermal final tune. +.0V [] H_PROHOT# [,,0] SYS_SHN# PR PR PR */F_ *0_ *0_ +V TP TP PR PR *0_ *0_ VI0 VI PR 0.K/F_ PR 0K/F_ PR *0_ VI [] VI [] VI [] VI [] VI [] VI +V P u/0v_ 0 V P u/0v_ PR 0/F_ V V ILIM 0 PR TIME.K/F_ VRHOT PGIN ST H PR._ LX P 0.u/V_ H LX P 00p/0V_ PQ OL + P.u/V_ P0 00u/V_X. R=m PL uh +VPU +VPU TP PR PR PR PR *0_ *0_ VI.0V TP *0_ *0_ VORE VI VI VI VI OP: [] VI [] VI0 0 PR *0/short_ [,] IH_PRSTP# PRSTP PR /F_ [,] PM_PRSLPVR PRSLPVR P 0.u/0V_ PR PR.K/F_ PWR PWR *.K/F_ PR0 V THRM THRM K/F_ PR0 *00K/F NT TON 0 PWRG SHN PU MXGTJ+ LKEN VP V PGN GN L SP SN F GNS P P 0.u/.V_ P 000p/0V_ 000p/0V_ PR.0K/F_ L P 00p/0V_ PQ OL PR *._ P *0p/0V_ SP PR.K/F_ SN PR.K/F_ Load-line=-.mV/ for Pine Trial-M PR *0/short_ PR 0K NT PR 0K/F_ + P 0u/V_ ESR=m + P 0u/V_ tsw =.pf x (RTON +.K ) fsw=00khz +V PR [,,] IMVP_PWRG PR0 00K/F_ K/J_ PR *0/short_ P 00p/0V_ P P F_SR GNS 000p/0V_ PR PR 000p/0V_ 0/F_ 0/F_ V_SENSE [] _SENSE [] [,] VRON [,] VR_PWRG_K0# PR 0K/F_ PR PR *0/short_ *0/short_ PR *0/short_ PR PR *0/short_ *0/short_ F_SR GNS PR PR0 *0/F_ *0/F_ VORE +V *.U/0V_ onnect to output cap GN P *0p/0V_ Quanta omputer Inc. PROJET : ZE Size ocument Number Rev Vore( IMXGTJ+) Friday, March, 0 ate: Sheet of

27 [PWM] 0mil V_R_VTT P 0u/.V_ 0_VST PR *0/short_ P 0.u/0V_ 0_H 0_LX P 0u/.V_ P 0u/.V_ 0_L P.u/V_ GN VTT VTTGN VLOIN VST RVH 0 LL RVL PGN PQ ON0 PL.uH P P 0.uF/0V_ 00p/0V_ add for EMI +.VSUS P.u/V_ +.VSUS mil 0. +SMR_VREF +.VSUS VTTSNS GN MOE VTTREF PU RT0L S_GN S VFILT PR K/F_ PR./F_ +V_S PQ ON0 PR./F_ + +.VSUS. Volt +/- % T : PEK : OP : 0 Width : 0mil +V_S P 0.0u/0V_ OMP N VQSNS VQSET 0 S S N PGOO PR 00K/F_ P P0 u/0v_ u/0v_ +V_S HWPG_.V [,,] P 000p/0V_ add for EMI P0 0u/V_ P 0u/.V_ P 000pF/0V_ add for EMI PR *0/short_ PR0 0K/F_ S_.V PR *0/short_ (For RT0 00KHZ) close to P0 SUSON [,,,] PR0 *0/short_ S_.V PR *0/short_ MINON [,,,] PR *0_ +V_S P *p/0v_ PR 0K/F_ 0_SET PR 0K/F_ Vout = (PR0/PR) X S_.V S_.V PR *0_ +.VSUS L(ripple current) =(-.)*./(.u*00k*) ~. Vtrip= (0-./)*mohm=0.V RILIM=Vtrip/0u~.0Kohm [,] MIN MIN PQ O0 S S +.VSUS REF VTT S0 ON ON ON +.V T : PEK :. Width : 0mil S S/S ON OFF ON OFF OFF OFF Quanta omputer Inc. PROJET : ZE Size ocument Number Rev R.V(TPS) Friday, March, 0 ate: Sheet of

28 +V_S PR 0_ P R00V-0 P.n/0V_ P.u/V_ [,,,] MINON PR *0/short_ PR0 M/F_ EN/EM PU G0 PR./F_ OOT PR *0/short_ P 0.u/0V_ P.u/0V_ PQ ON0 +.0V +V TON VOUT UGTE PHSE UGTE-.0V PHSE-.0V PL.uH_XX [,,] HWPG_.0V PR 0K_ P *0.u/0V_ V F PGOO O 0 VP LGTE P u/0v_ PR.K/F_ LGTE-.0V PR *._ + P 0.u/0V_ P u/0v_ GN N N PGN TP PQ ON0 P *0p/0V_ P 0u/.V_X. P *0u/.V_ P *000p/0V_.0V_F R R PR.0K/F_ PR 0K/F_ P *p/0v_ PR *0/short_ VOUT=(+R/R)*0. +.0VSUS.0 Volt +/- % T :. PEK :. OP : Width : 0mil PR *0/short_ TON=.p*RTON*Vout/(Vin-0.) Frequency=Vout/(Vin*TON) TON=.p*M*/(Vin-0.) Frequency=/(0.00)=K L(ripple current) =(-.0)*.0/(.u*k*) ~. Rth=m*(-0.)/0u RILIM=.Kohm Quanta omputer Inc. PROJET : ZE Size ocument Number Rev +.0V(G0) Friday, March, 0 ate: Sheet of

29 +.VSUS +VSUS +V [,,,] SUSON SUS_ON_G PQ TEU PR M_ PR M_ PR *_ PQ *MN0K- PR _ PQ MN0K- PR M_ SUS PQ MN0K- P0 *00p/0V_ SUS [] VGFX 0.Volt +/- % T :. PEK :. Width : 0mil VGFX PQ0 O0 +.0V P0 0u/.V_ PU G P0 0.u/0V_ +V PR 00K_ +V +V +.0V +.V +V PR M_ PR _ PR _ PR0 *_ PR _ PR0 M_ P0 0u/V_ + P0 0u/.V_ PR Rg 0/F_ PR /F_ RV F GN PG EN V +V P00 0.u/0V_ HWPG_VGFX [,] PR 0K/F_ HWPG_.0V P *0.u/0V_ [,,,] MINON PQ TEU MINON_ON_G PR M_ PQ MN0K- PQ MN0K- PQ *MN0K- PQ MN0K- MIN PQ MN0K- P *00p/0V_ MIN [,] PR Rh /F_ Vout = (+Rg/Rh)*0. P0 n/v_ P0 u/v_ +VPU PU G VPP PGOO PR 00K_ +V HWPG_.V [] [,,] HWPG_.0V PR M_ PR PQ M_ TEU VGFX PR _ PQ0 MN0K- HWPG_.0V +VSUS PR P 0u/.V_ P 0.u/0V_ *0/short_ PR 00K_ P *0.u/0V_ VEN GN GN J VO N Vout =0.(+R/R) =.V R 0.V R PR.K/F_ PR00 K/F_ P 0u/.V_ +.V +.V.Volt +/- % T : 0. PEK : 0. Width : 0mil Quanta omputer Inc. PROJET : ZE Size ocument Number Rev ischarge/.v ate: Friday, March, 0 Sheet of