ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων. Χειμερινό Εξάμηνο

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1 ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων Δυναμικές Μνήμες DRAM Χειμερινό Εξάμηνο

2 Βασικό Block Diagram Υποσυστημάτων Μνήμης Word Line Address Decoder Memory cell 2 n word lines n Address Bits RAM/ROM ονοματολογία: m Bit Lines 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words ΗΥ220 University of Crete 2

3 Κελί μνήμης με 1 transistor (DRAM) Εγγραφή Write: 1. Οδηγούμε την bit line 2. Επιλέγουμε γραμμή (row select) Ανάγνωση Read: 1. Προφορτίζουμε (precharge) την bit line σε Vdd/2 2. Επιλέγουμε γραμμή (row select) 3. Το κελί και η bit line μοιράζονται τα φορτία (charge sharing) 4. Sense στην bit line (sense amplifier) Μπορεί να ανιχνεύει πολύ μικρές αλλαγές 5. Write: επαναφέρουμε την τιμή Ανανέωση Refresh: Αρκεί ένα απλό read σε κάθε κελί bit row select ΗΥ220 University of Crete 3

4 Κλασσική Οργάνωση DRAM (τετραγωνική) r o w d e c o d e r RAM Cell Array bit (data) lines Each intersection represents a 1-T DRAM Cell Square keeps the wires short: Power and speed advantages Less RC, faster precharge and discharge is faster access time! word (row) select row address Column Selector & I/O Circuits data Column Address Row and Column Address together select 1 bit a time ΗΥ220 University of Crete 4

5 Λογική Οργάνωση DRAM (4 Mbit) 4 Mbit = 22 address bits 11 row address bits 11 col address bits A0 A10 11 Square root of bits per RAS/CAS R O W D E C O D E R 11 Row selects 1 row of 2048 bits from 2048 rows Col selects 1 bit out of 2048 bits in such a row Column Decoder Sense Amps & I/O Memory Array (2,048 x 2,048) Storage Cell Word Line ΗΥ220 - University of Crete 5

6 Λειτουργία DRAM Precharge and RAW access Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 - University of Crete 6

7 Λειτουργία DRAM Column Access Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 - University of Crete 7

8 Λειτουργία DRAM Data Transfer Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 - University of Crete 8

9 Τα σήματα της DRAM RAS_L CAS_L WE_L OE_L A 256K x 8 DRAM 8 8 D Σήματα ελέγχου (RAS_L, CAS_L, WE_L, OE_L) όλα active low Κοινό bus δεδομένων D εισόδου κα ι εξόδου (Din & Dout): WE_L ενεργοποιείται (Low), OE_L απενεργοποιείται (High) D χρησιμοποιέιται σαν είσοδος στην DRAM WE_L απενεργοποιείται (High), OE_L ενεργοποιείται (Low) D χρησιμοποιέιται σαν έξοδος από την DRAM Οι διευθύνσεις γραμμής και στήλης μοιράζονται τα ίδια pins (A) RAS_L ενεργοποιείται (low) > A αποθηκεύεται σαν row address CAS_L ενεργοποιείται (low) >A αποθηκεύεται σαν column address RAS/CAS edge sensitive ΗΥ220 University of Crete 9

10 Απλοποιημένο διάγραμμα χρονισμού DRAM Read Write Η διεύθυνση δίνεται σε 2 βήματα ΗΥ220 - University of Crete 10

11 Τυπικός χρονισμός Ανάγνωσης DRAM Κάθε προσπέλαση DRAM ξεκινάει με: Ενεργοποίηση του RAS_L 2 τρόποι ανάγνωση: early or late A RAS_L CAS_L WE_L OE_L 256K x 8 9 DRAM 8 D DRAM Read Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address Col Address Junk WE_L OE_L D High Z Junk Data Out High Z Data Out Setup Hold Read Access Time Output Enable Delay Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L ΗΥ220 University of Crete 11

12 DRAM Timing Read dtiming i for Conventional ldram Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 12

13 DRAM Timing Read dtiming i for fast page mode Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 13

14 DRAM Timing Read dtiming i for burst mode (EDO) Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 14

15 DRAM Timing Read dtiming i for synchronous DRAM Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 15

16 Τυπικός ςχρονισμός Εγγραφής DRAM Κάθε προσπέλαση DRAM ξεκινάει με: Ενεργοποίηση του RAS_L 2 τρόποι εγγραφής: early or late A RAS_L CAS_L WE_L OE_L 256K x 8 9 DRAM 8 D DRAM WR Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address Col Address Junk OE_L WE_L D Junk Data In Junk Data In Junk Setup Hold WR Access Time Early Wr Cycle: WE_L asserted before CAS_L WR Access Time Late Wr Cycle: WE_L asserted after CAS_L ΗΥ220 University of Crete 16

17 Key DRAM Timing Parameters t RAC : minimum time from RAS line falling to the valid data output. Quoted as the speed of a DRAM A fast 4Mb DRAM t RAC = 60 ns t RC : minimum time from the start of one row access to the start of the next. t RC = 110 ns for a 4Mbit DRAM with a t RAC of 60 ns t CAC : minimum time from CAS line falling to valid data output. 15 ns for a 4Mbit DRAM with a t RAC of 60 ns t PC : minimum time from the start of one column access to the start of the next. 35 ns for a 4Mbit DRAM with a t RAC of 60 ns ΗΥ220 University of Crete 17

18 SRAM (lower density, higher speed) used in CPU register file, on and off chip caches. DRAM (higher density, lower speed) used in main memory Closing the GAP: 1. Caches are growing in size. 2. Innovation targeted towards higher bandwidth hfor memory systems: SDRAM synchronous DRAM RDRAM Rambus DRAM EDORAM extended data out SRAM multibank DRAM Memory in Desktop Computer Systems: ΗΥ220 University of Crete 18

19 DRAM with Column buffer A0 A10 Pull column into fast buffer storage Access sequence of bit from there R O W D 11 Memory Array (2,048 x 2,048) E C O D E R Word Line Storage Cell Sense Amps Column Latches MUX ΗΥ220 - University of Crete 19

20 Optimized Access to Cols in Row Often want to access a sequence of bits Page mode After RAS / CAS, can access additional bits in the row by changing column address and strobing CAS Static Column mode Change column address (without repeated CAS) to get different bit Nibble mode Pulsing CAS gives next bit mod 4 Video ram Serial access ΗΥ220 University of Crete 20

21 More recent DRAM enhancements EDO extended data out (similar to fast page mode) RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns) Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) SDRAM synchronous DRAM clocked interface uses dual banks internally. Start access in one bank then next, then receive data from first then second. DDR Double data rate SDRAM Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). RDRAM Rambus DRAM Entire data blocks are access and transferred out on a high speed bus like interface (500 MB/s, 1.6 GB/s) Tricky system level design. More expensive memory chips. ΗΥ220 University of Crete 21

22 DRAM Types SDR SDRAM DIMMs These first synchronous registered DRAM DIMMs had the same bus frequency for data, address and control lines. PC66 = 66 MHz, PC100 = 100 MHz, PC133 = 133 MHz DDR SDRAM (DDR1) SDRAM DIMMs DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. PC1600 = 200 MHz data & strobe / 100 MHz clock for address and control PC2100 = 266 MHz data & strobe / 133 MHz clock for address and control DDR2 SDRAM SDRAM DIMMs DIMMs based on Double Data Rate 2 (DDR2) DRAM also have data and data strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed. PC = 400 MHz data & strobe / 200 MHz clock for address and control PC = 533 MHz data & strobe / 266 MHz clock for address and control DDR3 SDRAM SDRAM DIMMs DIMMs based on Double Data Rate 3(DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed. PC = 800 MHz data & strobe / 400 MHz clock for address and control ΗΥ220 University of Crete 22

23 DRAM Types Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 23

24 More DRAM Types Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 24

25 Οργάνωση DRAM Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 25

26 256 Mbit SDRAM Addressing ΗΥ220 University of Crete 26

27 Functional Block Diagram 8 Meg x 16 SDRAM ΗΥ220 University of Crete 27

28 DRAM Organization Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 28

29 SDRAM Details Multiple banks of cell arrays are used ACTIVE command opens a row for to reduce access time: operation Each bank is 4K rows by 512 columns by 16 bits (for our part) transfers the contents of the entire to a row buffer Read and Write operations as split into RAS (row access) followed by CAS (column access) These operations are controlled by sending commands Commands are sent using the RAS, CAS, CS, & WE pins. Address pins are time multiplexed During RAS operation, address lines select the bank and row During CAS operation, address lines select the column. Subsequent READ or WRITE commands modify the contents of the row buffer. For burst reads and writes during READ or WRITE the starting address of the block is supplied. Burst length is programmable as 1, 2, 4, 8 or a full page (entire row) with a burst terminate option. Special commands are used for initialization (burst options etc.) A burst operation takes 4 + n cycles (for n words) ΗΥ220 University of Crete 29

30 DRAM and CPU Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 30

31 Mode Register ΗΥ220 University of Crete 31

32 Command Truth Table ΗΥ220 University of Crete 32

33 Βασικές Χρονικές Παράμετροι SDRAM t RCD : ACTIVE to READ or WRITE delay CL : CAS Latency t RAS : ACTIVE to PRECHARGE time t RP : PRECHARGE Period t WR : WRITE recovery time t RC : ACTIVE to ACTIVE time ΗΥ220 University of Crete 33

34 READ burst (with auto precharge) ΗΥ220 University of Crete 34

35 WRITE burst (with auto precharge) ΗΥ220 University of Crete 35

36 DDR Read Command (with auto precharge) ΗΥ220 University of Crete 36

37 DDR Read Command (without auto precharge) ΗΥ220 University of Crete 37

38 DDR: Consecutive Read Bursts ΗΥ220 University of Crete 38

39 DDR Write Command (without auto precharge) ΗΥ220 University of Crete 39

40 DDR: Read Burst Stop Write ΗΥ220 University of Crete 40

41 Auto Refresh One autorefresh command every 70us : once every 7000 cycles at 100Mhz ΗΥ220 University of Crete 41

42 Future DRAM Source: DRAM: Architecture, Interfaces, and Systems, B. Jacob, D. Wang, ISCA 2002 ΗΥ220 University of Crete 42

43 Volatile Memory Comparison The primary difference between different memory types is the bit cell. DRAM Cell SRAM Cell addr word line word line bit line bit line data bit line Larger cell lower density, higher h Smaller cell higher density, lower cost/bit cost/bit No dissipation Needs periodic refresh, and refresh after Read non destructive read No refresh required Complex read longer access time Simple read faster access Special IC process difficult to integrate Standard IC process natural for with logic circuits integration i with ihlogic Density impacts addressing ΗΥ220 University of Crete 43

44 SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit Special fabrication process DRAM rarely merged with logic circuits. word line DRAM bit cell Needs periodic refresh h(in most bit line applications) Multiple clock cycles per Relatively slow because: read or write access High capacity leads to large cell arrays with high word and bit line Multiple reads and writes are capacitance often grouped together to Complex read/write cycle. Read amortize overhead. Referred needs precharge and write back to as bursting. ΗΥ220 University of Crete 44

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