ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2017 ΔΙΑΛΕΞΗ 5: Διαδικασία Παραγωγής Ολοκληρωμένων Κυκλωμάτων ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]

Επανάληψη - CMOS Properties l Full rail-to-rail swing Þ high noise margins Logic levels not dependent upon the relative device sizes Þ transistors can be minimum size Þ ratioless l Always a path to V dd or GND in steady state Þ low output impedance (output resistance in kw range) Þ large fan-out (albeit with degraded performance) l Extremely high input resistance (gate of MOS transistor is near perfect insulator) Þ nearly zero steady-state input current l No direct path steady-state between power and ground Þ no static power dissipation l Propagation delay function of load capacitance and resistance of transistors ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.2 Θεοχαρίδης, ΗΜΥ, 2017

1958 - Integrated circuit invented 3 September 12th 1958 Jack Kilby at Texas instrument had built a simple oscillator IC with five integrated components (resistors, capacitors, distributed capacitors and transistors) In 2000 the importance of the IC was recognized when Kilby shared the Nobel prize in physics with two others. Kilby was sited by the Nobel committee "for his part in the invention of the integrated circuit a simple oscillator IC ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.3 Θεοχαρίδης, ΗΜΥ, 2017 Lecture #1

1959 - Planar technology invented 4 l Kilby's invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity. l By late 1958 Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions. l In 1959, Robert Noyce also of Fairchild had the idea to evaporate a thin metal layer over the circuits created by Hoerni's process. l The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuits and is the process used today. Planar technology ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.4 Θεοχαρίδης, ΗΜΥ, 2017 Lecture #1

IC Fabrication Technology: History (cont.) 5 l 1960 - Epitaxial deposition developed l l Bell Labs developed the technique of Epitaxial Deposition whereby a single crystal layer of material is deposited on a crystalline substrate. Epitaxial deposition is widely used in bipolar and sub-micron CMOS fabrication. 1960 - First MOSFET fabricated l l Kahng at Bell Labs fabricates the first MOSFET. 1961 - First commercial ICs l l Fairchild and Texas Instruments both introduce commercial ICs. 1962 - Transistor-Transistor Logic invented l l 1962 - Semiconductor industry surpasses $1-billion in sales 1963 - First MOS IC l RCA produces the first PMOS IC. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.5 Θεοχαρίδης, ΗΜΥ, 2017 Lecture #1

1963 - CMOS invented 6 l Frank Wanlass at Fairchild Semiconductor originated and published the idea of complementary-mos (CMOS). l It occurred to Wanlass that a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to prove the concept with discrete devices. l l Enhancement mode NMOS transistors were not yet available and so Wanlass was used a depletion mode device biased to the off-state. Amazingly CMOS shrank standby power by six orders of magnitude over equivalent bipolar or PMOS logic gates. l On June 18, 1963 Wanlass applied for a patent. On December 5th 1967 Wanlass was issued U.S. Patent # 3,356,858 for "Low Stand-By Power Complementary Field Effect Circuitry". l CMOS forms the basis of the vast majority of all high density ICs manufactured today. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.6 Θεοχαρίδης, ΗΜΥ, 2017 Lecture #1

Silicon IC processing l Similar to photographic printing Expose the silicon wafer through a mask Process the silicon wafer Repeat sequentially to pattern all the layers l Layout: A set of masks that tell a fabricator what to pattern For each layer in your circuit Layers are metal, drain/source implants, gate, etc. You draw the layers Subject to vendor-supplied spacing rules ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.7 Θεοχαρίδης, ΗΜΥ, 2017

ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.8 Θεοχαρίδης, ΗΜΥ, 2017

The wafer l l l Czochralski process Melt silicon at 1425 C Add impurities (dopants) Spin and pull crystal Slice into wafers 0.25mm to 1.0mm thick Polish one side ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.9 Θεοχαρίδης, ΗΜΥ, 2017

The Wafer ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.11 Θεοχαρίδης, ΗΜΥ, 2017

Crystal and wafer Wand (a finished 250lb crystal) A polished wafer ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.12 Θεοχαρίδης, ΗΜΥ, 2017

Growing the Silicon Ingot From Smithsonian, 2000 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.13 Θεοχαρίδης, ΗΜΥ, 2017

Crystalline or contaminate defects will kill the operation of an IC, so it is imperative that the silicon is ultra-pure. In order to create the best possible quality of silicon, a pure layer of silicon is grown on the raw wafer via an epitaxial growth process. This is known as the epi-layer. This layer is very thin - approximately 3 percent or less of the wafer thickness. As device complexity grows, the need for epi-wafers increases. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.15 Θεοχαρίδης, ΗΜΥ, 2017

Lithography l Patterning is done by exposing photoresist with light l Requires many steps per layer l Example: Implant layer Reference: FULLMAN KINETICS ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.17 Θεοχαρίδης, ΗΜΥ, 2017

Grow Oxide Layer Reference: FULLMAN KINETICS ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.18 Θεοχαρίδης, ΗΜΥ, 2017

Add Photoresist Reference: FULLMAN KINETICS ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.19 Θεοχαρίδης, ΗΜΥ, 2017

The mask l Illuminate reticle on wafer Typically 4 reduction l Typical image is 25 25mm Limited by focus l Step-and repeat across wafer Limited by mechanical alignment 4X reticle Wafer ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.20 Θεοχαρίδης, ΗΜΥ, 2017

Mask Reference: FULLMAN KINETICS ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.21 Θεοχαρίδης, ΗΜΥ, 2017

9/03 IEEE spectrum ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.22 Θεοχαρίδης, ΗΜΥ, 2017

Photolithography 9/03 IEEE spectrum ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.23 Θεοχαρίδης, ΗΜΥ, 2017

9/03 IEEE spectrum ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.24 Θεοχαρίδης, ΗΜΥ, 2017

CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers q q One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon exception! 3 source and drain diffusions 1 tubs (aka wells, active areas) ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.25 Θεοχαρίδης, ΗΜΥ, 2017

Photolithographic Process oxidation optical mask stepper exposure photoresist removal (ashing) photoresist coating photoresist development process step spin, rinse, dry acid etch ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.26 Θεοχαρίδης, ΗΜΥ, 2017

Patterning - Photolithography 1. Oxidation 2. Photoresist (PR) coating 3. Stepper exposure 4. Photoresist development and bake 5. Acid etching Unexposed (negative PR) Exposed (positive PR) 6. Spin, rinse, and dry 7. Processing step Ion implantation Plasma etching Metal deposition 8. Photoresist removal (ashing) SiO 2 mask UV light PR ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.27 Θεοχαρίδης, ΗΜΥ, 2017

Example of Patterning of SiO2 Chemical or plasma etch Si-substrate Silicon base material Photoresist SiO 2 Si-substrate Hardened resist SiO 2 4. After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate 1&2. After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask Exposed resist Si-substrate 5. After etching Si-substrate Hardened resist SiO 2 SiO 2 3. Stepper exposure 8. Final result after removal of resist ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.28 Θεοχαρίδης, ΗΜΥ, 2017

Diffusion and Ion Implantation 1. Area to be doped is exposed (photolithography) 2. Diffusion or Ion implantation ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.29 Θεοχαρίδης, ΗΜΥ, 2017

Deposition and Etching 1. Pattern masking (photolithography) 2. Deposit material over entire wafer CVD (Si 3 N 4 ) chemical deposition (polysilicon) sputtering (Al) 3. Etch away unwanted material wet etching dry (plasma) etching ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.30 Θεοχαρίδης, ΗΜΥ, 2017

A nice step by step process at the end of the slides

Planarization: Polishing the Wafers From Smithsonian, 2000 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.32 Θεοχαρίδης, ΗΜΥ, 2017

Self-Aligned Gates 1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.33 Θεοχαρίδης, ΗΜΥ, 2017

Simplified CMOS Inverter Process cut line p well ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.34 Θεοχαρίδης, ΗΜΥ, 2017

P-Well Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.35 Θεοχαρίδης, ΗΜΥ, 2017

Active Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.36 Θεοχαρίδης, ΗΜΥ, 2017

Poly Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.37 Θεοχαρίδης, ΗΜΥ, 2017

P+ Select Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.38 Θεοχαρίδης, ΗΜΥ, 2017

N+ Select Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.39 Θεοχαρίδης, ΗΜΥ, 2017

Contact Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.40 Θεοχαρίδης, ΗΜΥ, 2017

Metal Mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.41 Θεοχαρίδης, ΗΜΥ, 2017

A Modern CMOS Process Dual-Well Trench-Isolated CMOS gate oxide field oxide Al (Cu) TiSi 2 SiO 2 tungsten n+ p well p-epi p- n well p+ SiO 2 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.42 Θεοχαρίδης, ΗΜΥ, 2017

Modern CMOS Process Walk-Through p-epi p+ Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer) p+ After plasma etch of insulating trenches using the inverse of the active area mask ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.43 Θεοχαρίδης, ΗΜΥ, 2017

CMOS Process Walk-Through, con t SiO 2 After trench filling, CMP planarization, and removal of sacrificial nitride n After n-well and V Tp adjust implants p After p-well and V Tn adjust implants ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.44 Θεοχαρίδης, ΗΜΥ, 2017

CMOS Process Walk-Through, con t poly(silicon) After polysilicon deposition and etch n+ p+ After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon. SiO 2 After deposition of SiO 2 insulator and contact hole etch ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.45 Θεοχαρίδης, ΗΜΥ, 2017

CMOS Process Walk-Through, con t Al After deposition and patterning of first Al layer. Al SiO 2 After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.46 Θεοχαρίδης, ΗΜΥ, 2017

Layout Editor: Design Frame ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.47 Θεοχαρίδης, ΗΜΥ, 2017

Layer Representation l Metals (five) and vias/contacts between the interconnect levels Note that m5 connects only to m4, m4 only to m3, etc., and m1 only to poly, ndif, and pdif Some technologies support stacked vias q Active active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc)) q Wells (nw) and other select areas (pplus, nplus, prb) ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.48 Θεοχαρίδης, ΗΜΥ, 2017

CMOS Inverter Layout Out In metal1-poly via metal1 polysilicon metal2 V DD pfet pdif metal1-diff via GND PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) ndif nfet metal2-metal1 via ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.49 Θεοχαρίδης, ΗΜΥ, 2017

Simplified Layouts l Online design rule checking (DRC) l Automatic fet generation (just overlap poly and diffusion and it creates a transistor) l Simplified via/contact generation v12, v23, v34, v45 ct, nwc, pwc 0.44 x 0.44 m1 0.3 x 0.3 ct 0.44 x 0.44 poly ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.50 Θεοχαρίδης, ΗΜΥ, 2017

Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.51 Θεοχαρίδης, ΗΜΥ, 2017

Design Rules l Interface between the circuit designer and process engineer l Guidelines for constructing process masks l Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules l Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur l A complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.52 Θεοχαρίδης, ΗΜΥ, 2017

l Why Have Design Rules? To be able to tolerate some level of fabrication errors such as 1. Mask misalignment 2. Dust 3. Process parameters (e.g., lateral diffusion) 4. Rough surfaces ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.53 Θεοχαρίδης, ΗΜΥ, 2017

Intra-Layer Design Rule Origins l Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) l Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab 0.3 micron 0.15 0.15 0.3 micron ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.54 Θεοχαρίδης, ΗΜΥ, 2017

Intra-Layer Design Rules Same Potential Different Potential Well 10 0 or 6 9 Polysilicon 2 2 Active Select 3 3 2 Contact or Via Hole 2 2 Metal1 Metal2 3 3 4 3 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.55 Θεοχαρίδης, ΗΜΥ, 2017

Inter-Layer Design Rule Origins 1. Transistor rules transistor formed by overlap of active and poly layers Transistors Catastrophic error Unrelated Poly & Diffusion Thinner diffusion, but still working ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.56 Θεοχαρίδης, ΗΜΥ, 2017

Transistor Layout ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.57 Θεοχαρίδης, ΗΜΥ, 2017

Layers! ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.58 Θεοχαρίδης, ΗΜΥ, 2017

Inter-Layer Design Rule Origins, Con t 2. Contact and via rules M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My Contact Mask Via Masks both materials 0.3 Contact: 0.44 x 0.44 mask misaligned 0.14 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.59 Θεοχαρίδης, ΗΜΥ, 2017

Vias and Contacts 2 1 Via 1 4 5 Metal to Active Contact 1 Metal to Poly Contact 3 2 2 2 ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.60 Θεοχαρίδης, ΗΜΥ, 2017

National 0.18µm process cutaway ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.61 Θεοχαρίδης, ΗΜΥ, 2017

Advanced Metallization - Copper Copper versus Aluminum ~ 40% lower resistivity ~ 10 less electromigration ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.62 Θεοχαρίδης, ΗΜΥ, 2017

An AMD 50nm transistor ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.63 Θεοχαρίδης, ΗΜΥ, 2017

Defects kill yield and drive up manufacturing cost, so defect inspection is vital in the Fab. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.74 Θεοχαρίδης, ΗΜΥ, 2017

Wafer probe or test is the first time that chips are tested to see if they function as they were designed to do. ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.76 Θεοχαρίδης, ΗΜΥ, 2017

Redundancy Repair is a process step almost exclusively used for memory chips ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.77 Θεοχαρίδης, ΗΜΥ, 2017

each pad on the die is connected to a corresponding pin on the package frame via a thin gold or aluminum wire (approx. 0.001" diameter). ΗΜΥ307 Δ5 Διαδικασία Παραγωγής.78 Θεοχαρίδης, ΗΜΥ, 2017