/MM M/M Pro/x RJ ONN RJ ONN LIN OUT MI IN INTRNL MI VIT lock iagram lock enerator ILPR RII /00 lot 0 RII /00 Realtek RT lot Realtek RTL0-R 0/00 MOM MOM X0-Z H UIO O X0-Z RII /00 hannel R II /00 hannel U.0 PI H UIO MIx Intel PU Penryn V antiga-pm F 00/0MHz TL+ PU I/F R I/F INTRT RHPI LV, RT I/F INTL IH-M U.0/. ports THRNT (0/00/000Mb) High efinition udio T ports PI ports PI. LP I/F PI/PI RI PI+U.0,,,,,,0,,,,0, Project code :.I0.00 P P/N : 0 Revision : PI x -LINK PI U.0 U x T LP us XM RII nvii NM-,,, K WINON WPL R RT LV(ual hannel) HMI 0 V / INPUT OUTPUT +VLW WM H O YTM / PL INPUT +.V RT 00X00@ L WX+ LUTOOTH V_OR_0 OUTPUT +.V HMI YTM / INPUT OUTPUT +.V +.V YTM / TP INPUT OUTPUT TOUT +VLW +VLW +VL YTM / TP INPUT TOUT OUTPUT +0.V +.V YTM / INPUT +VLW MXIM HRR MX INPUT OUTPUT T+ TOUT V.0 PU / IL0RZ INPUT TOUT P LYR L: L: L: L: L: L: ignal N V 00m OUTPUT 0.~.V ignal ignal +_OR ignal OUTPUT +.0V 0, H PKR OP MP MT Mini-ard 0.a/b/g/n Flash ROM M Touch P Int. K Thermal & Fan MT <ore esign> L: N L: ignal Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock iagram ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
ignal H_OUT PIO0 NT#/ PIO IHM Functional trap efinitions IH Rev.. page Usage/When ampled omment XOR hain ntrance/ llows entrance to XOR hain testing when TP PI Port onfig bit, pulled low. When TP not pulled low at rising edge Rising dge of PWROK. of PWROK, sets bit of RP.P (ofig Registers: offset h). This signal has weak internal pull-down. = ynamic OT nabled (efault) TL# PKR TP PIO/ H_OK Reserved. PI xpress Lane Reversal. Rising dge of PWROK. No Reboot. Rising dge of PWROK. XOR hain ntrance. Rising dge of PWROK. Flash escriptor ecurity Override This signal has a weak internal pull-up. ets bit of PR.P (onfig Registers: Offset h). ignal has weak internal pull-up. ets bit of MP.LR (evice : Function 0:Offset ). If sampled high, the system is strapped to the "No Reboot" mode (IH will disable the TO Timer system reboot feature). The status is readable via the NO ROOT bit. This signal should not be pull low unless using XOR hain testing. ampled low: the Flash escriptor ecurity will be The pull-up or pull-down active when configured for native LN_OK# functionality and determined by LN controller. others = Reserved F[:] Reserved F F[:] F[:] F MI x elect 0 = MI x = MI x (efault) F itpm Host Interface 0 = The itpm Host Interface is enabled (Note ) = The itpm Host Interface is disabled (default) F Intel Management engine crypto strap 0 = Transport Layer ecurity (TL) cipher F MI Lane Reversal 0 = Normal operation (efault): Lane Numbered in Order = Reverse Lanes MI x mode [MH->IH]: (->0, ->, -> and 0->) MI x mode [MH->IH]: (->0, ->) _N# trap. Rising dge of in effect. This should only be enabled in U[:0][P,N] PULL-OWN K PWROK. overridden. If high, the security measures will be manufacturing environments using an external pull-up resister. IH Integrated pull-up and pull-down Resistors PIO Mus antiga chipset and IHM I/O controller Hub strapping configuration IH Rev.. Montevina Platform esign guide 0. page INL Resistor Type/Value Pin Name trap escription onfiguration L_LK[:0] PULL-UP 0K F[:0] F Frequency elect 000 = F0 0 = F L_T[:0] PULL-UP 0K 00 = F00 L_RT0# PULL-UP 0K H_YN PI config bit0, This signal has a weak internal pull-down. Rising dge of PWROK. ets bit0 of PR.P (onfig Registers: Offset PRLPVR/PIO PULL-OWN 0K h). NRY_TT PULL-UP 0K NT#/ PI config bit, H_IT_LK PULL-OWN 0K PIO Rising dge of PWROK. H_OK_N#/PIO PULL-UP 0K NT#/ PIO NT0#: PI_#/ PIO PI_MOI PIO I trap (erver Only) Rising dge of PWROK. Top-lock wap override. Rising dge of PWROK. oot IO estination election 0:. Rising dge of PWROK. This signal should not be pulled high. I compatible mode is for server platforms only. This signal should not be pulled low for desktop and mobile. ampled low: Top-lock wap mode (inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down. ontrollable via oot IO estination bit (onfig Registers: Offset 0h:bit :0). NT0# is M, 0-PI, 0-PI, -LP Integrated TPM nable, ample low: the Integrated TPM will be disable. Rising dge of LPWROK. ample high: the MH TPM enable strap is sampled low and the TPM isable bit is clear, the Integrated TPM will be enable. MI Termination Voltage. Rising dge of LPWROK. PI Routing The signal is required to be low for desktop applications and required to be high for mobile applications. U Table page page H_RT# H_IN[:0] H_OUT H_YN LN_OK# NT[:0]#/PIO[,,] PIO0 L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PM# PWRTN# TL# PI_#/PIO/LPIO PI_MOI PI_MIO PKR TH_[:0] TP[] PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K U Thermal Pair evice LN LN 0 U K LN WLN Miniard FR xternal U TTRY FR xternal U FR MINI <ore esign> WLN LUTOOTH IHM Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, R_RR Taipei Hsien, Taiwan, R.O.. FR 0 MR FR Table of ontent lock enerator F0 suite with no confidentiality = TL cipher suite with confidentiality(efault) F PI raphics Lane 0 = Reserved Lanes, ->0, -> ect.. = Normal operation (efault): Lane Numbered in Order F0 PI Loopback enable 0 = nable (Note ) = isable (efault) F[:] XOR/LL 00 = Reserve 0 = XOR mode nabled 0 = LLZ mode nable (Note ) = isabled (efault) F F ynamic OT 0 = ynamic OT isabled igital isplay Port 0 = Only igital isplay Port or PI is (VO/P/iHMI) operational (efault) oncurrent with PIe = igital display Port and PIe are operating simulataneously via the P port VO VO Present 0 = No VO ard Present (efault) _TRLT = VO ard Present L T Local Flat Panel (LFP) 0 = LFP isabled (efault) Present = LFP ard Present; PI disabled NOT:. ll strap signals are sampled with respect to the leading edge of the ()MH Power OK (PWROK) signal.. itpm can be disabled by a 'oft-trap' option in the Flash-decriptor section of the Firmware. This 'oft-trap' is activated only after enabling itpm via F. Only one of the F0/F/F straps can be enabled at any time. ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
H_#[..] H_#[..] H_T#0 H_RQ#[..0] H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# TT TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP TP0 TP0 TP0 TP TP0 TP TP0 TP TP0 TP0 TP0 TP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# RV_PU_ J # L # L # K # M # N # J # N 0# P # P # L # P # P # R # M T0# K RQ0# H RQ# K RQ# J RQ# L RQ# H_# Y H_# # U H_# # R H_#0 # W H_# 0# U H_# # Y H_# # U H_# # R H_# # T H_# # T H_# # W H_# # W H_# # Y H_#0 # U H_# 0# V H_# # W H_# # H_# # H_# # # V T# 0M# FRR# INN# TPLK# LINT0 LINT MI# RV_PU_ M RV_PU_ RV#M N RV_PU_ RV#N T RV_PU_ RV#T V RV_PU_ RV#V RV_PU_ RV# RV_PU_ RV# RV_PU_ RV# RV_PU_ RV# RV_PU_0 RV# F RV#F U OF KY_N RRV R ROUP 0 R ROUP IH -KT-PU XP_RT#_R XP_TI XP/ITP INL ONTROL.00.00 R # H NR# PRI# FR# H R# F Y# R KRJ--P H_R#0 H_R# H_R# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# XP_RT#_R PM_THRMTRIP# should connect to IH and MH without T-ing ( No stub) RF-L-P H_# H_NR# H_PRI# H_FR# H_R# H_Y# R0# F H_RQ#0 RJ--P PU_IRR# R IRR# 0 +.0V INIT# H_INIT# LOK# H RT# R0# F R# F R# TR# HIT# HITM# PM0# PM# PM# PM# PR# PRQ# TK TI TO TM TRT# R# 0 THRML PROHOT# THRM THRM THRMTRIP# HLK LK0 LK H_LOK# H_TR# H_HIT# H_HITM# +V +.0V H_R#[..0] PM_THRMTRIP-#, LK_PU_LK LK_PU_LK# Reserve for ITP, when install ITP connector, install R. +.0V H_PURT# H_THRM, H_THRM routing together, Trace width / pacing = 0 / 0 mil R R-P R RF--P onnect to V ore PU_PROHOT#_R +.0V / Houston H_THRM H_THRM +.0V ITP onnector Reserve for ITP 0 R ITP UVKX-P 0 0 +.0V +.0V ITP_V R XP_RT#_R 0RJ--P XP_RT# XP_PM#0 XP_RT# XP_PM# R 0RJ--P XP_PM# MH_LKL, 0 R 0RJ--P XP_PM# MH_LKL, 0 R 0RJ--P XP_PM# MH_LKL0, H_PURT# H_RT#_R XP_PM# R KRJ--P XP_TK LK_PU_XP# 0 XP_TO_R XP_TO LK_PU_XP R0 0RJ--P XP_TK XP_TM XP_TRT# 0 XP_TI 0RJ--P MLX-ONN--P XP_TM R RF-L-P XP_TO R RF-L-P XP_PM# R RF-L-P XP_TRT# R RF-L-P <ore esign> (Place R0 with in 00ps (~") to PU Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. XP_TK R RF-L-P PU ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
H_INV#[..0] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_TN#[..0] H_TP#[..0] H_#[..0] H_#[..0] PU_L0 PU_L PU_L H_TN#0 H_TP#0 H_INV#0 Layout notes Z= Ohm 0." MX for TLRF H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U OF 0# F # # # F # # # # K # # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# H_# N H_# # K H_# # P H_# # R H_#0 # L H_# 0# M H_# # L H_# # M H_# # P H_# # P H_# # P H_# # T H_# # R H_# # L +.0V H_#0 # T H_# 0# N # H_TN# L TN# H_TP# M KRF--P TP# H_INV# N R INV# PU_TLRF0 TT TLRF TT TT R PU_TT TT 0 KRF--P KP0VKX-P TT F PU_TT TT F TT TT L0 L L # # # # # # # # 0# # # # # # # # TN# TP# INV# # # 0# # # # # # # # # # 0# # # # TN# TP# INV# OMP0 MI OMP OMP OMP PRTP# PLP# PWR# PWROO LP# PI# T RP0 T RP T RP T RP Y V V V T U U Y W Y W W Y U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# H_# H_# H_#0 H_# H_# H_# 0 H_# H_# F H_# H_# H_# H_# H_#0 H_# F H_# H_# H_TN# F H_TP# 0 H_INV# R U OMP0 OMP R0 R RF-L-P RF-L-P OMP R RF-L-P Y OMP R RF-L-P H_PRTP#,, H_PLP# H_PWR# H_PWR H_PULP# PI# onnect to V ore TT R KRJ--P TT R KRJ--P R KRJ--P R0 KRJ--P -KT-PU Layout Note: omp0, connect with Zo=. ohm, make trace length shorter than 0.". omp, connect with Zo= ohm, make trace length shorter than 0.". Route the TT and TT signals through a ground referenced Zo = -ohm trace that ends in a via that is near a N via and is accessible through an oscilloscope connection. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
+_OR U OF 0 0 0 0 0 0 0 0 F F F0 F F F F F F0 0 0 0 0 Please these inside socket cavity on L(North side econdary) 0 0 0 0 F F0 F F F F F F0 P P V P J P K P M P J P K P M P N P N P R P R P T P T P V P W VI0 VI F VI VI F VI VI F VI N N -KT-PU F +_OR H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI 00RF-L-P-U 00RF-L-P-U H_VI[..0] +_OR R +_OR Please these inside socket cavity on L(outh side econdary) +_OR +_OR +.0V 0 layout note: "V 0" as short as possible R 0UVKX-P UVMX-P UVMX-P +.V 0 0 0 UVMX-P UVMX-P 0 UVMX-P Please these inside socket cavity on L(North side Primary) 0 UVMX-P UVMX-P T T0UVM-LP 0 _N _N UVMX-P 0 UVMX-P UVMX-P R 0 UVMX-P UVMX-P 0 UVMX-P UVMX-P +.V 0R00-P 0 PV 0UVMX-P UVMX-P onnect to V ore Layout Note: UVMX-P 0 UVMX-P UVMX-P 0 UVMX-P N and N lines should be of equal length. Layout Note: Provide a test point (with no stub) to connect a differential probe between N and N at the location where the two.ohm resistors terminate the ohm transmission line. +_OR Please these inside socket cavity on L(North side econdary) +_OR +.0V +_OR Please these inside socket cavity on L(outh side Primary) Layout Note: Place as close as possible to the PU pin. Please these outside socket cavity on L(North side econdary) 0 0 Please these outside socket cavity on L(outh side econdary) UVMX-P UVMX-P UVMX-P 0 U0VKX-P UVMX-P UVMX-P UVMX-P U0VKX-P UVMX-P UVMX-P 0 UVMX-P U0VKX-P UVMX-P UVMX-P UVMX-P U0VKX-P UVMX-P 0 U0VKX-P 0 U0VKX-P U F F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P OF -KT-PU P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F PU_N PU_N PU_N PU_N Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. PU ( of ) ize ocument Number Rev VIT TP NTF PIN TP TP TP ate: Monday, May 0, 00 heet of
H_WIN routing Trace width and pacing use 0 / 0 mil H_WIN Resistors and apacitors close MH 00 mil ( MX ) H_ROMP routing Trace width and pacing use 0 / 0 mil H_WIN U0VKX-P H_ROMP R RF-L-P Place them near to the chip ( < 0.") +.0V R RF--P +.0V R0 00RF-L-P-U R KRF--P H_#[..0] H_VRF H_VRF H_#[..0] H_PURT# H_PULP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP U F H_#_0 H_#_ F H_#_ H_#_ H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ F H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_WIN H_ROMP H_PURT# H_PULP# H_VRF H_VRF HOT OF 0 H_#_ H_#_ H_#_ F H_#_ H H_#_ H_#_ M H_#_ J H_#_0 P H_#_ R H_#_ N H_#_ M H_#_ H_#_ P H_#_ F H_#_ 0 H_#_ H_#_ J H_#_0 0 H_#_ H H_#_ J0 H_#_ L H_#_ H_#_ H_#_ L H_#_ H_#_ J H_#_ H0 H_#_0 H_#_ K H_#_ 0 H_#_ F H_#_ K H_#_ L0 H_# H H_T#_0 H_T#_ H_NR# H_PRI# F H_RQ# H_FR# H_Y# 0 HPLL_LK H HPLL_LK# H H_PWR# J H_R# F H_HIT# H H_HITM# H_LOK# H H_TR# H_INV#_0 J H_INV#_ L H_INV#_ Y H_INV#_ Y H_TN#_0 L0 H_TN#_ M H_TN#_ H_TN#_ H_TP#_0 L H_TP#_ M H_TP#_ H_TP#_ H_RQ#_0 H_RQ#_ K H_RQ#_ F H_RQ#_ H_RQ#_ H_R#_0 H_R#_ F H_R#_ H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] R KRF--P UVZY-P NTI-M-P-U-NF <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
+V R 0 R R KRF-P KRF-P KRF-P F F F F0 F F F F F F F F F0 +.V M_ROMPP M_ROMPN PM_XTT#0 PM_XTT# PM_YN#,, H_PRTP# PM_XTT#0 PM_XTT#, PM_PWROK,,,,0, PLT_RT# MI Lane Reversal MH_F_ Low = Normal (default) antiga =.K High = Lanes Reversed PI xpress raphics Lane MH_F_ Low = Normal (default), PM_THRMTRIP-#, PM_PRLPVR onnect to V ore RN RN0KJ--P,,, +V F setting MH_LKL0 MH_LKL MH_LKL PM_XTT#0 PM_XTT# PWROK_R RTIN# F F F F F F0 F F F F F F F0 M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL M_RXT MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVRF H_LK H_RT# H_I H_O H_YN M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# TTN# M_LK_R0 M_LK_R M_LK_R M_LK_R M_K0 M_K M_K M_K M_0# M_# M_# M_# M_OT0 M_OT M_OT M_OT Use R need enable MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP R_VRF_ LK_MH_PLL LK_MH_PLL# 0 IH_VO_LK TP IH_VO_T TP L_LK0 L_T0 M_PWROK L_RT#0 MH_LK_RQ# MH_IH_YN# +.V +.0V P/VO for HMI used TP TP TP TP TP R0 KRF--P L_VRF ~= 0.V 0 +.V M_ROMP_VOH UVMX--P M_ROMP_VOL 0 UVMX--P T P_MP T H J L L0 N P N T U Y Y Y H J L L N0 P N T U Y W Y 0 J M M M0 M R N T0 U U0 Y0 0 J L M M M R N T U U Y Y +_P 0 0 0 0 0 00 0 Place the Ohm resistor within 00 mils (. mm) of the ()MH. P_RXN0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN P_RXN0 P_RXN P_RXN P_RXN P_RXN P_RXN P_RXP0 P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP P_RXP0 P_RXP P_RXP P_RXP P_RXP P_RXP U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP High = Lanes Reversed antiga =.K +V Please lose MH +.0V TTN#_K TTN#_K 0 R R R R R R R R R R KRF-P K0RF-P K0RF-P KRF-P KRF-P K0RF-P KRF-P KRF-P KRF-P KRF-P R 0RF-L-P R 0RF-L-P R 0R00-P R0 00RJ--P 00P0VJN-P M N R T H H0 H H K L K N M T M Y F H F T R P P0 P N M N P T R0 M0 L H P R T R N P T0 T T0 R F H H F H H H H H F H F F U RRV#M RRV#N RRV#R RRV#T RRV#H RRV#H0 RRV#H RRV#H RRV#K RRV#L RRV#K RRV#N RRV#M RRV#T RRV# RRV# RRV#M RRV#Y RRV# RRV#F RRV#H RRV#F F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_YN# PM_PRTP# PM_XT_T#_0 PM_XT_T#_ PWROK RTIN# THRMTRIP# PRLPVR N# N#F N# N# N#H N# N# N#H N#F N# N#H N#H N#H N#H N# N#H N#F N#H N# N# N# N#F N# N# N#F N# NTI-M-P-U-NF RV F PM N R LK/ ONTROL/OMPNTION LK MI RPHI VI M MI H OF 0 _K_0 _K K_0 _K K#_0 _K# K#_0 _K# K_0 _K K_0 _K #_0 _# #_0 _# OT_0 _OT OT_0 _OT_ M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF M_PWROK M_RXT M_RMRT# PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FX_VI_0 FX_VI_ FX_VI_ FX_VI_ FX_VI_ FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF P_TRLLK P_TRLT VO_TRLLK VO_TRLT LKRQ# IH_YN# TTN# H_LK H_RT# H_I H_O H_YN P T V U0 R R U V0 Y Y Y V R Y F Y H F H V R F F F H 0 H0 H F H F H H N J H N M K H 0 R RF--P U0VKX-P R KRF--P R KRF--P R RF--P R KRF--P R K0RF--P R KRF--P 0UVKX-P 0 0UVKX-P L M M K J M 0 H 0 0 H F0 0 H J F K F H K H J H J J L U L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N LV_I LV_V LV_VRFH LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ TV_ TV_ TV_ TV_RTN TV_ONL_0 TV_ONL_ RT_LU RT_RN RT_R RT_IRTN RT LK RT T RT_HYN RT_TVO_IRF RT_VYN NTI-M-P-U-NF LV PI-XPR RPHI TV V OF 0 P_OMPI P_OMPO P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_TX#_0 P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_0 P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX#_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ R0 RF-P TXN0 TXN TXN TXN TXN TXN TXN TXN TXN TXN TXN0 TXN TXN TXN TXN TXN TXP0 TXP TXP TXP TXP TXP TXP TXP TXP TXP TXP0 TXP TXP TXP TXP TXP R 0KRJ--P R0 RJ--P TTN# Q MMT0WT-P Please lose to U Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev VIT Monday, May 0, 00 ate: heet of
M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U J _Q_0 J _Q_ N _Q_ M _Q_ J _Q_ J0 _Q_ M _Q_ M _Q_ N _Q_ N _Q_ U0 _Q_0 T _Q_ N _Q_ N _Q_ U _Q_ U _Q_ V _Q_ Y _Q_ 0 _Q Q_ V _Q_0 Y _Q Q_ 0 _Q_ Y _Q Q_ V _Q_ T _Q_ Y _Q Q_ V _Q_0 W _Q Q_ U _Q Q Q_ U _Q_ V _Q Q Q Q_0 _Q_ U0 _Q_ V _Q Q Q_ Y _Q Q_ V _Q_ V _Q_ T _Q_0 N _Q_ U _Q_ U _Q_ T _Q_ N0 _Q_ M _Q_ M _Q_ J _Q_ J _Q_ N _Q_0 M _Q_ J _Q_ J _Q_ R YTM MMORY NTI-M-P-U-NF OF 0 0 T _R# 0 _# 0 _W# Y0 M #0 M # M # M R# M # M W# M M[..0] M M[..0] M M0 _M_0 M M M _M_ T M M _M_ Y M M _M_ U M M _M_ M M _M_ Y M M _M_ T M M _M_ J M Q[..0] M Q[..0] M Q0 _Q_0 J M Q _Q_ T M Q _Q_ M Q _Q_ M Q _Q_ W M Q _Q_ M Q _Q_ U M Q M Q#[..0] _Q_ M M Q#[..0] M Q#0 _Q#_0 J M Q# _Q#_ T M Q# _Q#_ M Q# _Q#_ M Q# _Q#_ Y M Q# _Q#_ M Q# _Q#_ U M Q# _Q#_ M M [..0] M [..0] M 0 _M_0 M M_ M M_ M M_ H M M_ M M_ M M_ M M_ M M_ F M M_ W M 0 _M_0 M M_ M M_ H M M_ H M M_ Y M Q[..0] M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U K _Q_0 H _Q_ P _Q_ P _Q_ J _Q_ J _Q_ M _Q_ P _Q_ U _Q_ U _Q Q_0 Y _Q_ T _Q_ R _Q Q Q Q Q Q_ F _Q Q_0 _Q_ F0 _Q_ F _Q Q_ F _Q_ H _Q Q_ H0 _Q Q Q_0 H _Q_ H _Q Q_ H _Q Q_ H _Q_ F _Q_ F _Q Q Q_0 _Q_ Y _Q_ Y _Q_ F _Q_ F _Q Q Q_ V _Q_ U _Q_ R _Q_0 N _Q_ Y _Q_ V _Q_ P _Q_ R _Q_ L _Q_ L _Q_ J _Q_ H _Q_ M _Q_0 M _Q_ H _Q_ J _Q_ R YTM MMORY NTI-M-P-U-NF OF 0 0 _R# U _# _W# F _M_0 M _M_ Y _M_ 0 _M_ F _M M M_ P _M_ K _Q_0 L _Q_ V _Q Q Q_ H _Q Q_ U _Q_ N _Q#_0 L _Q#_ V _Q#_ H _Q#_ H _Q# Q# Q#_ T _Q#_ N _M_0 V _M M M_ U _M_ W _M M_ U _M_ W _M_ T _M M_0 _M_ W _M_ Y _M_ H _M_ U M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[..0] M Q[..0] M Q#[..0] M [..0] M R# M # M W# M #0 M # M # M M[..0] M Q[..0] M Q#[..0] M [..0] Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
+.V U OF 0 TP TP P _M N _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M N _M H _M _M F _M 0 _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M _M/N _M/N _M/N _M/N W _M/N W _M/N T _M/N Y _X _X _X _X _X _X _X Y _X _X _X _X _X J _X _X _X _X _X Y _X H0 _X F0 _X 0 _X 0 _X 0 _X 0 _X T _X T _X M _X L _X _X J _X H _X _X F _X _X _X Y _X V _X U _X N _X M _X U _X T _X _X_N J _X_N _X_N H _X_N POWR M FX NTI-M-P-U-NF FX NTF M LF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF W V W V W V W V W V M +.0V L K W V U M0 K0 W0 U0 M L K J H F Y W V U M K H F Y W V M L K J H F Y W V U V M_LF_MH M_LF_MH M0M_LF_MH V M_LF_MH Y M_LF_MH M0M_LF_MH M_LF_MH U0VKX-P +.0V 0 0 T UVZY-P U0VKX-P UVKX-P UVZY-P 0U0VZY-P Place on the dge oupling P Place P where LV and R taps FOR M 0 U0VKX-P T UVZY-P U0VKX-P UVKX-P U0VKX-P T0UVM-LP U0VKX-P T0UVM-LP UVMX-P UVKX-P UVMX-P U0VKX-P U0VZY-P UVZY-P +.V Place on the dge UVZY-P UVZY-P FOR OR 0 UVMX-P oupling P 0 mils from the dge 0U0VZY-P U0VKX-P U0VKX-P 0 UVZY-P oupling P UVZY-P 0 UVZY-P R _MH_ 0R00-P Y V U M K J F Y W V U H F J H F J H F T UF OR NTI-M-P-U-NF POWR NTF OF 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF +.0V M L K J H Y W U M0 L0 K0 H0 0 F0 0 0 0 0 Y0 W0 V0 U0 L K J H Y W V L K L K K K K Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev VIT Monday, May 0, 00 ate: heet of
UH OF 0 m +.0V +.0V +.0V_PLL 0 PV R 0R00-P FM0KF--P L FM0KF--P L0 0ohm 00MHz +.0V L0 LMN-P 0ohm 00MHz 0 0ohm 00MHz 0U0VZY-P UVKX-P 0UVMX-P M HPLL M MPLL +.V R 0RJ--P VRUN_TV 0 0UVKX-P UVZY-P 0V_RUN_PPLL UVZY-P UVZY-P 0 UVZY-P +.V R 0 PV 0R00-P +.0V R 0R00-P 0 PV +.0V R0 0R00-P 0 PV UVMX-P 0V_M UVMX-P +.0V R 0R00-P 0 PV UVMX-P 0UVKX-P 0V_M_K VRUN_TV UVMX--P _P_ UVZY-P 0V_RUN_PPLL UVZY-P U0VZY-P 0V_RUN_HPLL UVZY-P U0VKX-P M HPLL M MPLL _RT RT F L J J _PLL _PLL _HPLL _MPLL _LV _P P_PLL R0 _M P0 _M N0 _M R _M P _M N _M T _M R _M P _M P _M_K N _M_K P _M_K N _M_K N _M_K M _M_K_NTF M _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF _TV TV_ M L F _LV _H _TV _Q _HPLL 0V_RUN_PPLL _P_PLL M _LV L _LV RT PLL LV P M TV H LV NTI-M-P-U-NF POWR K TV/RT M K MI XF HV P _XF _XF _XF _M_K _M_K _M_K _M_K _TX_LV LF _HV _HV _HV _P _P _P _P _P _MI _MI _MI _MI LF LF LF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 0 F0 K V U V U U H F H L 0m LF LF LF +.0V +V +V_HV R T--F-P +.0V_+V 0RJ--P R 0 PV 0R00-P 0 0m +V_HV 0 0V MI UVKX-P UVKX-P 0 +.0V R 0V XF 0R00-P 0 PV 0UVMX-P UVKX-P U0VZY-P V_M_K m UVKX-P U0VZY-P m UVKX-P UVZY-P 0 UVKX-P UVMX-P UVZY-P 00 PV +_P UVKX-P 00m R UVMX-P UVZY-P T T0UVM-LP 0U0VZY-P RF-P +_P R 0R00-P 0 PV +.V R 0R00-P 0 PV R 0R00-P 0 PV UVMX-P +.0V UVZY-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. antiga ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet 0 of
UI U R L W N J F Y T N L Y V R M V R P H F F H Y U T M F V U M J Y T N J N L U M H Y U T M 0 0 V0 N0 H0 0 T M J N L H U H Y U T J F F W T N J H K U NTI-M-P-U-NF OF 0 M P L J F H Y U T F M J F W V R L H P L H N K F N T N K H F V T R J Y P K H F F H F H V R J Y N L J F Y T J H F R L K J F H Y J Modification J to reserved Pin R 0R00-P 0 PV UJ L W U P N H F R M J 0 0 W0 T0 J0 0 Y0 N0 K0 F0 0 0 W T R M H U N N K W N J N L F V T M J Y N H Y N 0 V0 T0 J0 0 0 M0 F N M H V T NTF N NTI-M-P-U-NF 0 OF 0 H Y L Y U N J N J V T M M H Y L J H F V L R P F W U R P J H F Y M K M P H U U U U _NTF F _NTF _NTF V _NTF J0 _NTF M _NTF F _NTF _NTF U _NTF U _NTF L0 _NTF V0 _NTF _NTF L _NTF J _NTF _NTF U _ H _ H _ N# N# N# N# N# N# N# N# N# N# N# N# N# N#F F N# N# N# MH_N MH_N MH_N MH_N TP TP TP0 TP NTF PIN antiga ( of ) Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
M M_LK_R0 M_LK_R#0 Layout Note: Place near M +.V Layout Note: Place one cap close to every pullup resistors terminated to +0.V +0.V M M # M #0 M 0 M_OT0 M_0# M M M # M W# U0VZY-P UVZY-P UVZY-P U0VZY-P 0 UVZY-P U0VZY-P RN RNJ--P RN RNJ--P RN RNJ--P RN RNJ--P RN RNJ--P +0.V U0VZY-P 0 UVZY-P UVZY-P RN U0VZY-P M Q#[..0] 0 RN RN RN RN0 UVZY-P M Q[..0] M M[..0] M Q[..0] M [..0] UVZY-P UVZY-P RNJ--P M_K0 RNJ--P M M RNJ--P M M RNJ--P M M UVZY-P RNJ--P M M UVZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P UVZY-P UVZY-P T T0UVM-LP UVZY-P Layout Note: Place these resistors closely M,all trace length Max=." R_VRF_ M # M #0 M # M_OT0 M_OT R_VRF_ M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT0 M_OT U0VZY-P 0 0 00 0 0 0 0 0 0 0 0 0 0 0/P / 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q /Q0 /Q /Q /Q /Q /Q /Q /Q Q0 Q Q Q Q Q Q Q OT0 OT VRF /R 0 /W 0 / /0 0 / K0 K 0 K0 0 /K0 K /K M0 0 M M M M 0 M M 0 M L VP 0 00 N#0 0 N# N# N#0 0 N#/TT V V V V V V V 0 V 0 V V V V 0 0 0 0 M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK RN RN0KJ--P-U +.V M R# M W# M # M_0# M_# M_K0 M_K M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# UMMY- UMMY- IH_MT,,, IH_MLK,,, UVZY-P PM_XTT#0 put near connector +V M_OT M_# RNJ--P M # M R# 0 0 UMMY- UMMY- UVKX-P RN RNJ--P RN 0 N N 0 R-00P--P-U M_K M RN RNJ--P RN RNJ--P M M 0 UVZY-P <ore esign> M use.00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom VIT Monday, May 0, 00 ate: heet of
M_LK_R M_LK_R# M Q#[..0] M Q[..0] 0 UMMY- 00 UMMY- Layout Note: Place near M +.V +0.V M # M W# M M_K M M M 0 M # M M M_# M_OT M_K U0VZY-P +0.V M M[..0] M Q[..0] M [..0] Layout Note: Place one cap close to every pullup resistors terminated to +0.V UVZY-P RN RN RN RN RN RN RN UVZY-P U0VZY-P UVZY-P 0 U0VZY-P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P UVZY-P U0VZY-P 00 UVZY-P 0 RN RN RN RN RN RN RN0 U0VZY-P UVZY-P RNJ--P 0 UVZY-P UVZY-P M R# M RNJ--P M M RNJ--P M M RNJ--P M M RNJ--P M 0 M #0 RNJ--P M_# M_OT UVZY-P RNJ--P M # M UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P T T0UVM-LP UVZY-P UVZY-P Layout Note: Place these resistors closely M,all trace length Max=." R_VRF_ M # M #0 M # M_OT M_OT R_VRF_ UVZY-P 0 M 0 0 M 0 M 00 M M M M M M M M 0 0 M 0 M M M M # M #0 0 M # 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q 0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q 0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 M Q M Q M Q M Q M Q M Q M Q0 0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q 0 M Q M Q M Q M Q M_OT M_OT U0VZY-P 0 M 0 /R 0 /W 0 / /0 0 / K0 K 0 0/P K0 0 /K0 K /K / M0 0 M 0 M M M 0 Q0 M Q M 0 Q M Q Q Q L Q Q VP Q Q 0 Q0 00 Q Q N#0 0 Q N# Q N# Q N#0 0 Q N#/TT Q Q Q V Q0 V Q V Q V Q V Q V Q V 0 Q V 0 Q V Q V Q V Q0 V Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q 0 Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q Q Q /Q0 /Q /Q /Q /Q /Q /Q 0 /Q Q0 Q Q Q Q Q Q Q OT0 OT 0 VRF N N 0 R-00P--P-U M use.00. M_LK_R M_LK_R# M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK UVZY-P +V RN 0 PV +V 0 UVKX-P RN0KJ--P-U PM_XTT# 0 +.V 0 M R# M W# M # M_# M_# M_K M_K M_LK_R M_LK_R# M_LK_R M_LK_R# IH_MT,,, IH_MLK,,, UVZY-P <ore esign> put near connector UMMY- UMMY- Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom VIT Monday, May 0, 00 ate: heet of
+V_RT +V RT I/F & ONNTOR F +V_RT 0 0 +V FU-V-P 00 UVZY-P +V_RT H0H-0PT--P _LK 0 LU 0 RN UVZY-P RNKJ--P RT 0 _T R R V-P V-P RN _T LU JV_H +V_RT JV_V 0 +V _LK JV_H RN 0 YN-ONN-P P0VJN-P P0VJN-P P0VJN-P P0VJN-P V--F-P JV_V 00 V-P UVZY-P Layout Note: * Must be a ground return path between this ground and the ground on the V connector. Pi-filter & 0 Ohm pull-down resistors should be as close as to RT ONN. R will hit Ohm first, pi-filter, then RT ONN. +V_RT M_HYN M_VYN 0 U O# N Y HTW--P U O# N Y HTW--P HYN_ VYN_ UVZY-P RN RNJ--P-U JV_H JV_V M_R M_RN M_LU M_R M_RN M_LU RT Termination/MI Filter R0 0RJ-L-P-U R R 0RJ-L-P-U 0RJ-L-P-U P0VJN-P 0 P0VJN-P L LM0N-P L LM0N-P L LM0N-P P0VJN-P 00 Place lose onnector P0-P 0 P0-P P0-P R RN LU 0 <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT onnector ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
White L: Lite-On.00.0 verlight..f0 00 PV L / INVRTR INTRF / MR 0 I TOUT +V R 0RJ--P 0, LI_LO# P_L_PWR LI_LO# L K L-W--P 0 R 00RJ--P UVZY-P P_L#,0 OVR_W 0 KP0VKX-P +LV +V UVZY-P 0U0VZY-P 0 UVZY-P UVZY-P 0 0 0 +V_MR 0 UVZY-P IZ_T +V _LON _LK _T R 00KRJ--P RIHTN_ONN OVR_W U_0+ U_0-0 0 LV 0 0 R TXOUT_L+ TXOUT_L- TXOUT_L+ TXOUT_L- TXOUT_L0+ TXOUT_L0- TXLK_L+ TXLK_L- TXOUT_L+ TXOUT_L- TXOUT_L+ TXOUT_L- TXOUT_L0+ TXOUT_L0- TXLK_L+ TXLK_L- 00KRJ--P +V IZ_T0 0 UVZY-P.".0".".0" 0 IZ_T0 (PIN) 0 0 IZ_T (PIN) 0 0 0 00 PV +V -ONN--P-U hange to 0.F.0 T_L# Q R PTU--P R T L_ T_L#_ R 00KRJ--P U N00W-P 0 T L T_L 0 0 +V_MR U_0+ U_0- N R TP TP--P TP TP--P TP TP--P TP TP--P 0 RIHTN_ONN R0 0 PV 0R00-P R 0RJ--P R 00KRJ--P RIHTN 0 L_KLTTL +V 0R-0-U-P Q O0-P +V_MR L_V_N U0_N0 U0_P0 +LV R 0R00-P R 0R00-P 0 PV Layout 0 mil +V R 00KRJ--P UVZY-P U0VZY-P U IN# OUT N N U_0- U_0+ N IN# IN# IN# IN# RU-P 0 M_PWR# UVZY-P 00 PV R 00KRJ--P M_PWR# M_PWR_# R 0KRJ--P +LV L_V_N R 00RJ--P U +VLW N00W-F-P UVZY-P KP0VKX-P R 0KRJ--P U0VKX-P R 00KRJ--P +V VW--P _LON 0 000P0VJN-P RIHTN_ONN 000P0VJN-P +V VW--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. L/Inverter onnector/m/l ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
+V L K00T-0Y-N-P +V_K0 0 I +V +V_K0 R 0KRJ--P R 0KRJ--P MH_LK_RQ# ITP_N R 0KRJ--P R 0KRJ--P R 0KRJ--P R-_N/PI- +V_K0 00 0U0VZY-P 0 UVZY-P PI_TM LK_T_O# MH_LK_RQ# PLK_FWH 0 LK_IH LK_PI_K PLK_IH ITP_N Output 0 R PU_ITP PU_L PU_L PU_L0 +V_K0 R-_N/PI- PIN, 0 PI_TOP#/PU_TOP# R esign Note:. ll of Input pin didn't have internal pull up resistor.. lock Request (R) function are enable by registers.. Y integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic. R 0KRJ--P R 0KRJ--P UVZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P P0VN-P 0 P0VN-P LK_IH LK_ LK_XTL_IN TP_PI# TP_PU#,,, IH_MLK,,, IH_MT K_PWR P0VJN-P 0 PV LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_XP LK_PU_XP# LK_PI_LN LK_PI_LN# LK_PI_MINI_ LK_PI_MINI_# RT R R PI0/R#_ RF-L-P 0 LK_MH_PLL R RJ--P PI_TM PI/R#_ RT LK_MH_PLL# R 0R00-P R-_N/PI- PI/TM R R 0R00-P R RJ--P _L PI LK_PI_IH R ITP_N PI/_LT RT/R#_ RJ--P LK_PI_IH# R 0R00-P PI_F/ITP_N R/R#_ R 0R00-P 0 PV LK_PI_T RT/TT LK_PI_T# R F R/T R 0R00-P R 0R00-P F FL/TT_MO RF0/FL/TT_L MH_RFLK MHZ_NON/RT/ MH_RFLK# RJ--P N# MHZ_/R/ R RJ--P R RJ--P LK_MH_RFLK RT0/OTT_ 0 LK_MH_RFLK# R0 0R00-P R0/OT_ R 0R00-P P0VN-P R 0RJ--P R0 0RJ--P R 0RJ--P P0VN-P LK_L LK_L LK_L0 LK_XTL_IN LK_XTL_OUT R RJ--P F R RJ--P I.0.0 Realtek.00.00 +.0V +.0V +.0V R R0 0RJ--P 0RJ--P R R0 KRJ--P KRJ--P 0 PV X LK_XTL_OUT X-M-0P P0VJN-P U R KRJ--P X X LK T N NPI NRF +V_K0 VRF V VPI VR VPU VPLL U_MHZ/FL PI_TOP# PU_TOP# K_PWR/P# ILPRKLFT-P R RJ--P F_ F_ F_ PU 0 00M 0 0 M 0 M 0 0 00M 0 0 0 M R 0KRJ--P R0 0RJ--P R KRJ--P R KRJ--P R0 KRJ--P R KRJ--P N NR NR NR NPU N 0 +V_K0_IO V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO F F F N MH_LKL, MH_LKL, MH_LKL0, +V_K0 +V PUT0 PU0 0 PUT_F PU_F PUT_ITP/RT PU_ITP/R RT/R#_F R/R#_ 0 RT R RT0 R0 RT/R#_H 0 R/R#_ R0 0KRJ--P _L R 0KRJ--P L K00T-0Y-N-P 0 I <ore esign> 0 0U0VZY-P UVZY-P UVZY-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R0 0R00-P 0 PV 0 PV +V_K0_IO LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_XP LK_PU_XP# LK_PI_LN LK_PI_LN# LK_PI_MINI LK_PI_MINI# LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# LK_PI_T LK_PI_T# MHZ_NON MHZ_ RFLK RFLK# _L PIN 0 PIN PIN PIN 0 OTT OT RT/LT_00 RT/LT_00 RT0 R0 M_N M_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock enerator ILPR ize ocument Number Rev VIT 0 00 I ate: Monday, May 0, 00 heet of UVZY-P 0 UVZY-P 0 UVZY-P 0U0VZY-P
+V RN RNKJ--P RN RNKJ--P RN RNKJ--P RN RNKJ--P RN PI_TR# PI_FRM# INT_PIRQ# PI_RQ# PI_PLOK# PI_IR# PI_RR# INT_PIRQ# PI_PRR# PI_RQ0# INT_PIRQ# INT_PIRQH# PI_RQ# PI_RQ# PI_TOP# PI_VL# INT_PIRQ# INT_PIRQ# INT_PIRQF# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# U 0 0 0 F F F0 0 F 0 F F H H 0 H J PIRQ# PIRQ# J PIRQ# PIRQ# PI RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IR# PR PIRT# VL# PRR# PLOK# RR# TOP# TR# FRM# PLTRT# PILK PM# Interrupt I/F IHM-P-NF OF PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F F F F R J F R H K F PI_RQ0# PI_NT0# PI_RQ# PI_RQ# PI_RQ# PI_NT# PI_IR# PI_VL# PI_PRR# PI_PLOK# PI_RR# PI_TOP# PI_TR# PI_FRM# PI_PLTRT# IH_PM# INT_PIRQ# INT_PIRQF# INT_PIRQ# INT_PIRQH# TP PLK_IH RNKJ--P 0 PI_# PI_NT0# R R0 PI_NT# R KRJ--P KRJ--P KRJ--P U LP +VLW OOT IO trap PI_NT#0 PI_# OOT IO Location 0 PI 0 swap override strap PI_NT# PI LP(efault) low = swap override enable high = default PI_PLTRT# U PLT_RT# Y N LV0W--P R 0RJ--P PLT_RT#,,,,0, <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
IH_RTX +RT R 0MRJ-L-P IH_RTX +RT MRJ--P P0VJN--P X X-KHZ-P 0 I H_RT#_V H_ITLK_V H_YN_V H_OUT_V H_RT#_O H_ITLK_O H_YN_O H_OUT_O P0VJN--P +RT RN0 RN R 0KRJ-L-P RNJ--P RNJ--P U0VKX-P R 0KRJ-L-P Z_RT#_R Z_IT_LK Z_YN_R Z_TOUT_R H O U0VKX-P H_IN0 H_IN P-OPN T_RXN T_RXP T_TXN T_TXP Z_IT_LK Z_YN_R Z_TOUT_R T_L# T_RXN0 T_RXP0 T_TXN0 T_TXP0 +.V T_L# IH_INTVRMN R 0KRF-L-P R0 LN_OMP place within 00 mil of IHM IH_RTX IH_RTX LN_OMP R RF-L-P Z_RT#_R M_INTRUR# IH_INTVRMN RTX RTX IH_RTRT# RTRT# new signal Pin RTRT# RTRT# F0 M_INTRUR# RTRT# INTRUR# INTVRMN LN00_LP LN_LK LN_RTYN F LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX 0 F H_IT_LK H H_YN H_RT# F H_IN0 H_IN H H_IN H_IN U LN_OK#/PIO LN_OMPI LN_OMPO H_OUT H_OK_N#/PIO H_OK_RT#/PIO TL# J T0RXN H 0U0VKX-P T_TXN0_ T0RXP F 0U0VKX-P T_TXP0_ T0TXN T0TXP H TRXN J 0U0VKX-P T_TXN_ TRXP 0U0VKX-P T_TXP_ TTXN F TTXP IHM-P-NF OF RT LP LN / LN PU IH T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# PI TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI LP_[0..] LP_[0..],0 K K L K LP_0 LP_ LP_ LP_ K LP_FRM#,0 +V J R J PIO TP TP0 0KRJ--P +.0V N K0T 0 J H_0M# J H_PRTP# R H_PRTP#,, H_PLP# RJ--P J H_FRR#_R R RJ--P H_FRR# H_PWR +V F H_INN# R H_INIT# 0KRJ--P H_INTR L KRIN# 0 F H_NMI +.0V F H_MI# R H H_TPLK# RJ--P H_THRMTRIP_R R PM_THRMTRIP-#, RF-L-P Placed Within " from IH H J F H J 0 F0 H LK_PI_T# J LK_PI_T J TRI H RF-L-P R0 Place within 00 mils of IH ball +VL +RT U W=0mils R RT_PWR_L 0R00-P W=0mils 0 PV RT_PWR HFPT-P U0VZY-P W=0mils TT. R W=0mils KRJ--P RT MP-ON--P 0.00.0 integrated Vccus_0,Vccus_,VccL_ INTVRMN High=nable Low=isable integrated VccLan_0VccL_0 LN00_LP High=nable Low=isable <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev VIT 0 I ate: Monday, May 0, 00 heet of
LN WLN PI_RXN PI_RXP PI_TXN PI_TXP PI_RXN PI_RXP PI_TXN PI_TXP PI_# PI_RXN PI_RXP U0VKX-P U0VKX-P PI_RXN PI_RXP U0VKX-P 0 U0VKX-P TP0 TP0 TP0 TP TP0 TP TP0 TP 0 I R RF-L-P U N PRN N TXN_ PRP P TXP_ PTN P PTP L PRN L TXN_ PRP M TXP_ PTN M PTP J PRN J PRP K PTN K PTP PRN PRP H PTN H PTP +V OF PI-xpress +VLW MI0RXN V MI0RXP V MI0TXN U MI0TXP U irect Media Interface MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP PRN MI_LKN T PRP MI_LKP T F PTN F PTP MI_ZOMP F MI_IROMP F PRN/LN_RXN PRP/LN_RXP UP0N PTN/LN_TXN UP0P PTP/LN_TXP UPN PI_LK UPP PI_#0 PI_LK UPN PI_# PI_0# UPP F PI_#/PIO/LPIO UPN PI_MOI UPP PI_MOO PI_MOI UPN PI_MIO UPP U_O#0 UPN N U_O# O0#/PIO UPP N U_O# O#/PIO0 UPN N U_O# O#/PIO U W UPP W P U_O# O#/PIO UPN Y M U_O# O#/PIO UPP Y N U_O# O#/PIO UPN W M U_O# O#/PIO0 UPP W M U_O# O#/PIO UPN V N U_O# O#/PIO UPP V N U_O#0 O#/PIO UP0N U P U_O# O0#/PIO UP0P U P O#/PIO UPN U U_RI_PN UPP U URI URI# IHM-P-NF PI RN TP_PI# TP_PU# +VLW RN0KJ--P 0 PM_LKRUN# R 0KRJ--P +V PI_WK# LK_T_O# MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_IROMP_R U0_N0 U0_P0 U0_N U0_P U0_N U0_P PIO IRQ IH_M_LK IH_M_T +.V IH_TP R 0RJ--P +V +V +VLW,,0 PI_WK# 0 IRQ, THRM_I# 0 _I# 0 _WI# _PWR_L U0_N U0_P WLN U0_N U0_P luetooth U0_N U0_P ard Reader U0_N0 U0_P0 RN RN0KJ--P XP_RT# +V PM_YN# PIO Reserved for future R TP_PI# KRJ--P TP_PU# 0 I TP U M 0KRJ--P KRJ--P R0 _PKR MH_IH_YN# xternal U xternal U RN R0 RF-L-P R RN0KJ--P 0 LK_N# R 0KRJ--P PIO IH_M_LK IH_M_T LINKLRT# M LK M T TP TP TP TP TP 0 0 IH_RI# XP_RT# TP M_LRT# TP0 TP_PI# TP_PU# PI_WK# IRQ VRMPWR 0 _I# TP0 TP PIO PIO PIO PIO PIO TP TP TP PIO IH_TP Q +VLW OF U MLK MT LINKLRT#/PIO0/LPIO MLINK0 MLINK F R U_TT#/LPP# Y_RT# M PMYN#/PIO0 MLRT#/PIO TP_PI# TP_PU# L LKRUN# 0 WK# M RIRQ J THRM# 0 RI# VRMPWR T TH/PIO H TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO NRY_TT/PIO TH0/PIO K PIO F PIO0 J LOK/PIO PIO PIO L TLKRQ#/PIO LO/PIO TOUT0/PIO F TOUT/PIO H PIO PIO/LPIO M PKR J MH_YN# TP H0 PWM0 J0 PWM J PWM.. IHM-P-NF.. N00--P +V R KRJ--P RN RNKJ--P +V R 0KRJ--P Pair 0 VRMPWR U U xternal U 0 M T PIO locks Y PIO Power MT MI PIO ontroller Link evice FR xternal U FR FR WLN LUTOOTH R RR FR MR FR T0P/PIO TP/PIO TP/PIO TP/PIO LK LK ULK LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VRF0 L_VRF L_RT0# L_RT# PIO/MM_L PIO0/U_PWR_K PIO/_PRNT PIO/WOL_N H F 0 H F P 0 0 M R IH_ULK T0P TP TP TP PM_LP_#,,0,,,0,, PM_LP_# 0,,, PM_LP_# TP R 0KRJ--P PIO TP PM_PWROK R PM_PWROK, M_PWROK 0RJ--P PM_PRLPVR, R PM_TLOW#_R 00KRJ--P 0 LN_RT# R R F F F 0 M_PWROK PM_LP_M# PIO PIO0 LK_IH LK_IH L_LK0 L_T0 L_VRF0_IH L_VRF_IH L_RT#0 0 IH_ULK TP TP TP T0P PWRTN#_ 0 0 PV R 0R00-P U_O# RP 0 +VLW U_O# PM_TLOW#_R IH_RI# M_LRT# XP_RT# U_O#0 +VLW U_O# 0 <ore esign> 0 I U_O# U_O# U_O# U_O# +VLW +VLW +VLW U_O#0 U_O# U_O# U_O# +V RMRT#_ K_PWR LL_PWR,,,0, M_PWROK R 0RJ--P TP TP0 TP RP U0VKX-P 0 RN0KJ-L-P +V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of R KRF-P RN0KJ-L-P RN R KRF-P R RF--P RN0KJ--P U0VKX-P R RF--P
m +.V VRF_0 Layout Note: Place near IH m VRF_ m R 0R00-P 0 PV +.V_PI 0 PV +V R0 m in 0;0m in // _LN_ 0R00-P +.V R0 0RJ--P 0 +.V +V +VLW +V +VLW m *Within a given well, VRF needs to be up before the corresponding.v rail UVZY-P HH-0PT UVZY-P I U0VKX-P 0 U0VKX-P R 0RJ--P 0 HH-0PT U0VZY-P R0 0RJ--P I I 0m +RT +.V R0 0R00-P +.V R0 0R00-P m 0 PV 0 PV 0 PV +.V R 0R00-P U0VKX-P UVKX-P U0VKX-P UVZY-P UVZY-P 0U0VZY-P +.V +.V_PLL L IN-UH--P 0 R 0RJ--P U0VKX-P T UPLL=0m U0VKX-P T0UVM-LP UVZY-P u in _T_U m VRF_0 VRF_ T+U=. 0U0VZY-P U0VZY-P 0U0VZY-P UVZY-P UVZY-P U0VZY-P 0 U0VZY-P V_U_0 LN0 U0VKX-P _LN_PLL 0UVMX-P +V R 0RJ--P UVZY-P U0VZY-P LN_ V_LN_0 0 UF RT VRF VRF_U F H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J TPLL F H J F 0 H0 J0 0 J UPLL 0 LN_0 LN_0 LN_ LN_ LNPLL LN_ LN_ LN_ LN_ LN_ IHM-P-NF OF P RX TX U OR LN POWR OR PU PU P_OR PI _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 MIPLL MI MI V_PU_IO V_PU_IO H UH U_0 U_0 U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ L_0 L_ L_ L_ F L L L L L L M M P P T T U U V V V V V V U_0[] U_0[] U_[] F U_[] U_0[] U_[] _L_ m UVZY-P V_MIPLL_IH_0 R +V 0R00-P 0 PV. Layout Note:Place near IHM 0 _UH _U_U 0U0VZY-P 0 m V_MIPLL_IH_0 IN-UH--P L0 0 0UVKX-P 0U0VZY-P m 0 PV m 0 0 PV 0UVKX-P +.V +.0V R 0 +VLW 0R00-P 0 +VLW +VLW 0m 0 PV 0 PV R +.0V MI R W 0R00-P Y 0 PV m _V_PU_IO R +V J UVZY-P 0 0R00-P 0 PV 0 U0VZY-P UVZY-P 00 PV +V _=m F0 V_POR_IH_0 R 0R00-P 0 +V R0 0 PV R /_PI_P_OR_0 F 0R00-P _H 0R00-P 0 PV J 0 PV J K m J J F F T T T T T T U U V V W W Y Y T UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P TP TP0 TP UVZY-P 0 UVZY-P U0VKX-P _U_ 0 U0VKX-P U0VKX-P UVZY-P U0VKX-P UVZY-P UVMX-P R 0R00-P UVZY-P U0VKX-P U0VKX-P R 0R00-P UVZY-P U0VKX-P UVZY-P R 0R00-P UVZY-P UVZY-P UVZY-P +V 0 +.0V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH (/) ize ocument Number Rev VIT R 0R00-P 0 PV UVMX-P ate: Monday, May 0, 00 heet 0 of
OF U 0 0 F F F F H F F F F F 0 H H H H H H H H H H J J J J 0 F F F H H H H IHM-P-NF H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y H F IH_N IH_N H H J IH_N J J J IH_N TP TP TP TP NTF PIN,,, IH_MT IH_M_LK RN RNKJ--P +V IH_M_LK U N00W-P MU +V IH_M_T IH_M_T IH_MLK,,, Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH-M ( of ) ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of
U PORT +V 00 mil +V U0_P0 U0_N0 U0_N U0_P +V_U +V_U LUTOOTH 0 F FU-V-P F FU-V-P 0 U 0 I 0 I I/O N I/O T TY-ON--P +VUX_T 00 mil T0 T00U0VM-P UVZY-P 000P0VJN-P IP0Z-P 00 mil UVZY-P I/O VP I/O 0 PV 0 PV 0 00 PV UVZY-P UVZY-P UVZY-P R 0R00-P +V UVZY-P R 0R00-P 0 0 U0- U- U+ N N U0VKX-P U0_P U0_N T_L WL_PRIORITY T_PRIORITY T_T# 0 U0_N0 U0_P0 +V_U TP TP--P +V_U U0_N U0_P TP TP TP TP--P TP--P TP--P U0_N TP TP--P U0_P N +V TP TP TP TP--P TP--P TP--P NUMLK_L_PWM TP TP--P TP TP--P TP TP--P 0 0 U +VUX_T N U+ U+ U- U- T_L WL_PRIORITY T_PRIORITY T_T# NUMLK_L# I/O N I/O IP0Z-P 0 I/O VP I/O 0 I T_N# R 0R00-P 0 PV R 0R00-P 0 PV NUMLK_L# U0_N U0_P 00 PV TP TP--P TP TP--P TP TP--P TP TP--P TP TP--P TP TP--P TP TP--P TP TP--P +V U0+ U0_N U0_P U0_N U0_P R +V +V_U +V 0RJ--P 0 U0VZY-P K +V_U 0 NUMLK_L_PWM R T_N#_ PT-P U0VKX-P 0 T_N#_ 0 I 0 MX 0m R 00KRJ--P 0KRJ--P U 0 KT-U--P-U U MLX-ON0--P-U Q O0-P +V 00 PV T_TXP0 T_TXN0 T_RXN0 T_RXP0 T_TXP T_TXN T_RXP T_RXN 0U0VKX-P 0U0VKX-P UVZY-P +VUX_T 0 UVKX-P U0VKX-P 00 PV UVZY-P 0 0 UVZY-P UVZY-P T H onnector 0U0VKX-P T_RXN0_ T_RXP0_ 0U0VKX-P UVZY-P T 0U0VZY-P +V T_RXP_ T_RXN_ <ore esign> 0U0VZY-P O onnector P +V P +V + - + - NP NP NP NP O P P M P N N N N P N P N N KT-TP+P--P NP 0 0 NP 00 O_P O_M 0 I Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. H/ROM/U/T TP TP0 ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of H KT-TP-0-P R 0KRJ--P
V 0 V R 0 mils +V_LN V V 0R00-P 0 0 0U0VZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P TRL 00 PV 00 PV 0 mils UVZY-P R0 0R00-P 0 PV UVZY-P R0 00 PV V 00 PV V V UVZY-P V LN_PY R0 00KRJ--P LN_PY 000P0VJN-P Q 0 R should be.k % ohm for 0, R should be K % for 0. 0R-0-U-P UVZY-P UVZY-P P0VJN--P P0VJN--P 00 PV U0VZY-P X XTL-MHZ-P 0 UVZY-P UVZY-P PROM L OPTION U '0' (FIN IN P) => L0 : T (Yellow) => L : LINK (reen) (OTH 0/00 N I HIP) LN_M# 0 UVZY-P 0 0 LN_PWR_ON,,0,,,0,, YLLOW_L# RN_L# LN_M# 0 00 PV 0 UVZY-P 0 I R00 0R00-P 0 PV +VLW.... PM_LP_# V R MRJ--P UVZY-P N00--P LN_PY R 0RJ--P Q -F-P O-P Q 0 I +V_LN 0 0 mils R KRF-P 0_RT TRL LN_X LN_X V V V 0 I V U MIP0 MIN0 MIP MIN MI0_LN R RF-P 0UVKX-P R0 RF-P MI_LN R RF-P 0UVKX-P R RF-P <ore esign> MIP0 MIN0 MIP MIN 0 use this circuit, 0 dummy this circuit,,0 PI_WK#,,,,0, PLT_RT# PI_TXP PI_TXN LK_PI_LN LK_PI_LN# PI_RXP PI_RXN V V MIP0 MIN0 V MIP MIN V V V.00.0 0 I PI_WK# PLT_RT# PI_TXP PI_TXN LK_PI_LN LK_PI_LN# PI_RXP 0 U0VKX-P PI_RXN U0VKX-P N RT VTRL V MIP0 MIN0 N# MIP MIN N# N# 0 N#0 N# N# N# N# V V RTL0L-V-R-P VTRL N# 0 KXTL KXTL N# V L0 L L L V N# MPIN0 MPIN LNWK# PRT# V N# HIP HIN N RFLK_P RFLK_M V HOP HON N N# 0 0 V V V PI_HOP PI_HON PO PI 0 V K I/UX V O V TT TT TT 0 TT N# V IOLT# TT TT0 LKRQ# 0 LN_K LN_I V LN_O LN_ V V IOLT# +V R KRJ--P R0 R KRJ--P KRF-P 00 PV 0 PV R KR-P R 0KRJ--P LN_ LN_K LN_I LN_O M_IOLT# 0 For U K I O OR N TN-H--P V Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTL0 VIT ize ocument Number Rev ate: Monday, May 0, 00 heet of UVZY-P
+V UVZY-P *Layout* mil FN_ 0U0VZY-P MM-F-P R 0KRJ--P 00 I FN +V FN_F FN_ *Layout* mil U0VZY-P UVZY-P _RT# KP0VKX-P _RT# -ON--P-U +V R 00RF-L-P-U UVKX-P etting T as egree V_R =(((egree-)*0.0)+0.)* *Layout* 0 mil R KRF-P, THRM_I# R 00KRF-L-P V_R +V R0 0KRJ--P M_ M_ 0 V 0 0 LRT# L U.0.0 FN RT# F LK XP THRM# XP THRM_T XP N# FU-P N N 0 N N N _ULK _LRT# R 00KRJ--P _XP _XN 0 P-LO 00P0VKX-P FN_F FN_ N 00P0VKX-P Q H0PT-P TP TP--P TP TP--P TP0 TP--P N for ystem N for PU THRM +V XP:0 egree XP:H/W etting XP: egree Place near chip as close as possible 00P0VKX-P THRM H_THRM N for PU H_THRM R 0KRJ--P Q 0 _RT#... N00--P _LRT# _LRT# +V +V RN0 RNKJ--P +VLW M_ 0 U K_ 0 U 0 K_L M_,,0,,,0,, PM_LP_# IH_ULK N Y HT0KR-P _ULK N00W-F-P R 0RJ--P R 0RJ--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Thermal/Fan ontrollor ize ocument Number Rev ustom VIT ate: Monday, May 0, 00 heet of
LK_ R RJ--P R0 resistor need close pin. 00 I I U0VZY-P +V +V U0VZY-P UVZY-P R R R vendor suggest ues.pf, or use MHz directly by lock gne. R UVZY-P U0VKX-P VR +V_ +V_ UVZY-P 0 R UVZY-P 0RJ--P 0RJ--P +V_R _VIN R 00 I P0VJN--P R 0KRF-P P0VJN--P U0_N U0_P +V_ VR 0 U R R R R UVZY-P 0RJ--P R V_PLL V_PLL R RRF R KRF-P RRF V R U0VKX-P UVZY-P R R R RJ--P M P V_OUT V_IN R_V VR V_OUT N M_XI X XTL-MHZ-P M_XO XTLO F_# XTLI PIO0 _PLL F_0 MO_L MO_L F_ RT# RT# F_ X_L X_L/F_ F_/M_# X_# X_#/F_ F_/X_# X_L X_L/F_ F_0/M_WPM#/_WP _T/X_R# 0 _T/X_R#/F T/X_W# X_R/# _T/X_WP# _M _T/X_0/F LK/X_/M_LK/F_ V N _T/X_/M_/F_ F_0# M_IN#/F_IOR# _T/X_/M_/F_IOWR# _T0/X_/M_0/F_RT# _T/X_/M_/F_IOR F_0/_# _T/X_W#/F_ F_MK# X_R/F_ F_/X T/X_WP#/F_ F_MRQ X_/M_/F_ 0 00 I +V _M _T/X_0 _LK/X_/M_LK R _T/X_/M_ M_IN# _T/X_/M T0/X_/M_0 _T/X_/M R X_/M_ Reserve for used. R _VIN R 0RJ--P R +V_ R 0RJ--P R +V_ R0 0RJ--P 00 I 0 PV 0 I R _LK/X_/M_LK_L R 0R00-P R _LK/X_/M_LK_R R 0R00-P +V_ RT# UVZY-P 0 I 0 I +V_ R R 00KRJ--P R R 0R00-P R 0 PV R KRF--P U0VKX-P MO_L 0 I +V_ High is use MHz, N is use R rystal. RYTL_L R0 0RJ--P VU_L# X_# 0 _WP _# X_ RT-R-P.0.0 00 I R 0RJ--P _T/X_/M R _T X_ R R 0R00-P 0 PV P0VJN-P R 0KRJ--P 00 I +V R R 0RJ--P VU_L_L L K L-Y--P R VU_L R 0RJ--P R Q R R PTU--P +V VU_L# IN R-RR (/ IO/MM/MM.0/M/M PRO/X) +V_R R U0VZY-P +V_R UVZY-P R 0 I _T/X_/M R _M _LK/X_/M_LK_L _T0/X_/M_0 _T _T/X_R# _T/X_W# _# _WP _ M_ M M _LK _T0 _T _T _T TT _WP_PROTT L R/# R# # L W# WP# 0 _O _O 0 X_# X_L X_R/# _T/X_R# X_# X_L _T/X_W# _T/X_WP# _T/X_0 _LK/X_/M_LK _T/X_/M T/X_/M R X_ X_/M T0/X_/M_0 _T/X_/M # 0 I _WP X_/M T0/X_/M_0 M_IN# _LK/X_/M_LK_R _T/X_/M_ TP _T/X_/M_ R IO TP 0 NP NP NP NP NP NP _WP _WP M_ M_IO M_IN M_LK M_RRV#M_ M_RRV#M I/O NP NP NP NP NP NP _P _P _P _P M _ N N 0 N 0 N 0 N N N N _T0/X_/M_0 _T <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. TI-ON-P-U 0.I000.00 U ard Reader ontroller - RT ize ocument Number Rev Warrior Monday, May 0, 00 ate: heet of
HMI onnector Mini ard onnector(0.a/b/g) +.V +V_MINI 0 _RX 0 _TX 0 WIFI_RF_N 0 PI_RXN PLT_RT# PLT_RT#,,,,0, PI_RXP +V +V 0 PI_TXN 0 IH_MLK IH_MLK,,, PI_TXP IH_MT,,, R IH_MT R 00KRJ--P U0_N 0KRJ--P +V_MINI U0_P 0 0 U0 TP TP0 WLN_L# HMI_HP HMI_HP +V +V_MINI TP TP0 +VL 0 HP 00 PV R NP N00W-P 0R00-P KT-MINIP--P-U HP L HP_ LMN-P R0 0KRJ--P R 00KRJ--P R0 00KRJ--P HMI_HP HMI 00 PV,,0 PI_WK# WL_PRIORITY T_PRIORITY 00 0 PV R 0RJ--P R 0RJ--P R 0RJ--P LK_PI_MINI# LK_PI_MINI +VL TP0 TP0 0 WL_PRI T_PRI MINI +V_MINI NP 0.00. +.V +V_MINI +V_MINI 0 0 0 0 UVZY-P UVZY-P UVZY-P 0 +V UVZY-P HMI_TX HMI_TX 0U0VZY-P 0U0VZY-P 0 HMI_TX# HMI_TX# T--P HMI_TX HMI_TX 00 PV HMI_TX# HMI_TX# HMI_TX0 HMI_TX0 HMI_TX0# HMI_TX0# HMI_TX HMI_TX 0 RN RNKJ--P HMI_TX# HMI_TX# HMI_L HMI_ HMI_L +V_HMI HP HMI_ 00 PV 0 PV Q KT-HMIP-P-U <ore esign> RUN_PWR_TLR +V_HMI... +V N00--P.0.0 0 PV 00 PV R0 ize ocument Number Rev 0RJ--P VIT ate: Monday, May 0, 00 heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. MINI R/HMI ONN.
00 PV V R 0RJ--P 0 need connect to.v, 0 don't need. 0/00M Lan Transformer LN onnector XF MIP0 MIP0 RJ- XRF_R XFR_RX 00 I MIN0 MIN0 RJ- RJ-P--P MIP MIP 0 RJ- KP0VKX-P XRF_R XFR_MT 0 MIN MIN RJ- RN_L# R00 +V_LN 0RJ--P 0 0 RJ- 0 RJ- XFORM-P--P 0U00VKX-P 0U00VKX-P RJ- RJ- UVZY-P UVZY-P UVZY-P UVZY-P 0 XFR_MT_ XFR_RX_ RJ- RJ- RN RNJ--P LN_TRMINL 00PKVKX-P 0 +V_LN YLLOW_L#.route on bottom as differential pairs..tx+/tx- are pairs. Rx+/Rx- are pairs..no vias, No 0 degree bends..pairs must be equal lengths..mil trace width,mil separation..mil between pairs and any other trace..must not cross ground moat,except RJ- moat. R0 reen : Link up linking : TX/RX activity 00 I RJ- RJ- 0RJ--P KP0VKX-P 0 PIN : RN PIN : ORN PIN : YLLOW Remark: dd trace width to 0mils for RJ pin, and pin,. RJ 0 olden Finger for ebug oard +V_LP +V_LP +V P-OPN-PWR P-OPN-PWR PLT_RT#_ PLT_RT#_ LP_FRM#_ LP_FRM#_ LP_N LP_N PLK_FWH_ PLK_FWH_ LP_ LP LP_FRM# LP_FRM#_,0 LP_FRM# () P-OPN-PWR P-OPN-PWR () LP LP LP 0 LP LP 0 0 0 LP LP_ LP PLT_RT# PLT_RT#_ LP_0_ LP_0_,,,,0, PLT_RT# () XT_FWH#_ XT_FWH#_ P-OPN-PWR () P-OPN-PWR +V_LP +V_LP LP_ LP PLK_FWH PLK_FWH PLK_FWH_ FOX-F0 P-OPN-PWR P-OPN-PWR... TOP VIW... OTTOM VIW oot evice must have I[:0] = 0000 Has internal pull-down resistors ll may be left floated FPT lec. P- U ZZ.F00.XXX Please put near board edge. LP_[0..],0 LP_0 <ore esign> P-OPN-PWR 0 P-OPN-PWR +V_LP LP_0_ LP_N +V P-OPN-PWR +V_LP XT_FWH#_ Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. LN ONN/ebug ize ocument Number Rev VIT ate: Monday, May 0, 00 heet of