Schematics Page Index (Title / Revision / Change Date)

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1 Page of chematics Page chematics Page Index lock iagram LOK N (K0) MROM(HOT U) / MROM(HOT U) / MROM(Power/nd) / restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) / restline (POWR,V) / restline (V OR) / restline (V) / RII(O-IMM_0) / RII(O-IMM_) / RII(Termination) / V(PI-) V(TRP) V(R) V(MULTIU) V(LV/V ) VRM(R)# / VRM(R)# / V(POWR) / V(POWR) / V(POWR) / VRM(YP) / VRM(YP) / TVIN and OUT/emi-PnP# RT LV HMI MINI PI (TV) IH-M( PI/U ) / IH-M(LP,I,T)/ IH-M( PIO) / IH-M( POWR) / IH-M( N) / LN (0 MRVLL) K (0) chematics Page Index ( / Revision / hange ate) Rev. ate.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00//.0 00// Page of chematics Page Flash ROM/XU T H RI PT -ROM PI (PI U) PI ( ILINK) PI (M-T/UO/M/) PI ( PMI) luetooth Mini-PI ard XPR U.0 IR Reciver FN / HW THRML PROTTION aughter oard onn. M/OI Logo L UIO(O & POWR) UIO( MP & HP & PK) UIO (MUT & INTMI) UIO (econd odec) udio OR conn Power esign iagram IN&harger Y Power (_V/V) Y Power(_V/_0V) R Power(_V/0_V) PU_Vcore ---MX Others power plan OVP protection V POWR(_V/ _V) Inverter oost ircuit HOL & O HITORY(VT) econd ource 0 econd ource 0 Power On equerce lock iagram Power On equerce Timing Rev ate 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// 00// P. Leader heck by esign by Project ode & chematics ubject: M0 PVT Main oard P P/N: P P HON HI PRIION IN. O., LT. FOXONN P - R& ivision Index Page ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

2 M0(eagle anta Rosa )lock iagram Red texts: New modified -OUT P LV WX P V -type-p P 0 HMI (HP) P udio aughter oard U.0 ONN udio board -OUT/LV/V/HMI PIF udio board xt. Mic In Jack udio board H PHON JK udio board Int. peaker.0 Walt x P PIF NP P0KI-TRL P PROM HMI KY L O P 0 XK O P FX nvii H NP-(HMI) M NM-T(HMI) L NM-T(HMI) R.V RM P ~ PIF for HMI ZLI ZLI PI X PU Merom Processor Micro-F- (ocket -pin Micro FP) P ~ North ridge restline F-pin P ~ F 00 MHZ lock en. K0 I,ILPRYLFT P X,TL.MHZ M/M/M/M O-IMM 0 MHZ R(II) 00 pin P O-IMM MHZ R(II) 00 pin P M0 OM configuration N_ NV_ unstuff NP- NM-T NP- NM-T NM-T NM-T for L Model NX Hynix VRM NX Infineon VRM NX Infineon & amsung VRM NX Hynix & Infineon VRM NX Mxbit VRM NVP_ NVM_ NVMM_ NVML_ NVH_ NVI_ NVI_ NVH_ NV_ Int. Microphone P RJ PMI onn. P M UO P P i.link P RJ P M. Modem pin P TI PIZHK ardus ardreader i.link P ~ Transformer Netswap, N0P, Mini stereo P - P -IN P F/PL P JP igital only FN MHZ,.V PI U thernet -LN 0 MRVLL 0/00/000 P Mini PI (TV) PWM ZLI U.0 P P Lid witch & L LI PI _pin KU(H):nhanced KU(M)(L):ase P ~ Touchpad ontroller Link0 X/X MI (irect Media Interface) outh ridge IHM / IHM- LQFP- P 0 P/ LP N K0F I Flash IO M P P P I T 00 PT O P M hannel M hannel TT ONN. P U.0 PI U.0 PI U.0 U.0 T b/s T H -RI0 P Thermal ensor FM (PU/MH) uop- P T H -RI P U.0 U.0 U.0 Thermal ensor FM (V/IMM) uop P 0 U.0 ONN.X P xpress ard P 0 Mini-ard PI P M(.M) P 0 luetooth P Oide P 0 IR Reciver P NX Mxbit VRM NV_ *JP igital TV Tuner KU unstuff Mini PI ONN,T ONN, IR ONN,Felia ONN unstuff for L Model JTVN_ LN_ HON HI PRIION IN. O., LT. FOXONN P - R& ivision lock iagram ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

3 / backup for MI request close to R _VRUN H0KF-T0 R 0_J 00 L 0R-00MHZ_00 N_0.U_0V_K 00_XR K_IO_VOUT R H0KF-T0 N_0_J L0 0R-00MHZ_00 00 R0 N J 00 Q H0KF-T0 L 0R-00MHZ_00 N_ 00 N_00P_0V_K_N VP0 VP0 VP0 VP0 V_LK_F V_LK_ V_LK_ V_LK_ V_LK_ V_LK_ PU_L0 PU_L PU_L V_LK_ V_LK_ V_LK_ VRUN R_PI_F_ITP_N U VRUN R_PI_TM Y VP0 ITTI_L VP0 V_IO.MHZ_0P_0PPM VP0 VPU_IO 0 R N_0K_J VP0 VPLL_IO VR_IO PM_TPPI# 0 VR_IO PI_TOP# TP_PU# P_0V_J_N P_0V_J_N VR_IO PU_TOP# TP 00// Roger request R0 0K_J 00 R_LK_MH_LK MIL R_PI_M_L PUT_F LK_MH_LK VRUN Length as short R_LK_MH_LK# RP PU_F 0 LK_MH_LK# 00_PR R0 N_0K_J 00 as possible. R0 0_J 00 U_XTLIN 0 R_LK_PU_LK LK_PU_LK R R_LK_PU_LK# LK_._F 00 X PUT0 RP LK_PU_LK# U_XTLOUT PU0 00_PR R R_R_PUITP LK_U._F 00 X RT/PUT_ITP R_R#_PU#ITP TP MIL PU_L0 R.K_J 00 R_FL_UM R/PU_ITP 0 TP MIL PU_L R 0_J 00 R_FL_TT_MO FL/U_MHZ R_RT_R#_F FL/TT_MO RT/R#_F VRUN TP MIL TP MIL K_IO_VOUT R_LK_MH_PLL R_PI0_R#_ LK_MH_PLL _F 00 N RT 0 R_LK_MH_PLL# RP R0 LK_MH_PLL# R R_PI_F_ITP_N LK_IHPI _F 00 R 00_PR PI_F/ITP_N R_R_R#_ R/R#_ VRUN R _F 00 R_PI R_R PLK_ PI RT LK_PI_LN R_R# RP0 R_PI_R#_ LK_PI_LN# _F 00 R0 0 LK_KPI._F 00 R 0 00_PR R0 R_PI_TM R_R_R#_ R0 TP000 MIL PLK_JI._F 00 PI/TM R/R#_ R_LK_PI_MINI LK_PI_MINI R 00_J R_PLK_MINI L0 R_PI_M_L RT R_LK_PI_MINI# RP LK_PI_MINI# PLK_MINI 00 MMZ00T PI/_elect R 00_PR VRUN 0R-00MHZ_00 R_PI_R#_ PI/R#_,,,0 M_LK_U R_R_R# F 00 LK,,,0 M_T_U R_LK_PI_XP# R T R0 LK_PI_XPR# 0 R_LK_PI_XP RP LK_PI_XPR 0 R_LK_PI_IH# RT0 00_PR LK_PI_IH# RP R_LK_PI_IH R/R#_ R_RT_R#_H LK_PI_IH VRUN 00_PR RT/R#_ RT/R#_H R_RT_M_NON R_LK_PI_T R_RT_R#_H 0 R_RT_M_NON LK_PI_T _F 00 R_R_M_ RT//MHZ_nonss RT/TT R_LK_PI_T# RP 0 R_R_M_ R R//MHZ_ R/T LK_PI_T# 00_PR R_PI0_R#_ N PI0/R#_ N NR OT_OR_R0 LK_PI_P M0 M0 NR RT0/OTT_ OT#_OR_R0# RP LK_PI_P# LK_ NR R0/OT_ N N 00_PR N_0P_0V N 00 N LK_U N N NPU LK_N N_0P_0V N 00 NPI K_PWR/P# ebug card/(k) ebug card R_LK_IH LK_KPI NRF FL/RF0/TT_L LK_IH N_0P_0V N 00 PI0 PI0 ILPRYLFT R _F 00 onnect this pin via a 0 K PLK_ TV tuner (K) M bus ddress : series resistor to the F N_0P_0V N 00 PU_L pin on the processor IH IH 000 (IH) R0 0K_J 00 For clock generator This dumping resistor and F should be placed close to U, update for MOR requirement on/. MHz Port PI0 (pin) PI (pin) PI (pin) PI (pin) PI (pin) PI-F (pin) 00 MHz Port R0 (pin,) R (pin,) R (pin,) R (pin,) R (pin,) R(pin0,) R(pin,) R(pin,) R(pin0,) R0(pin,) R(pin,) If LP0, populate R,R0,,Q and depopulate R. Ig LP0, populate R and depopulate R,R0,,Q. M0 setting configuration FX PI_P (R0 /R only either one) PI T PI IH PI MINI PI -LN N N MH PLL PI XPR R#(MH)/R#H(XPR) H0KF-T0 L 0R-00MHZ_00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0 0U_.V_M 00_XR /W etting this pin type (b0=0) for use R0 /W etting LKRQ for this pin R# (b=;b=) (b=;b=0,b=0) for use R (b=0) for use R R# (b=,b=) R# (not control) (b=,b=0,b=0) for use R(not control R#/F) R#F (not control) R# (b=) R#H (b=) (b=0,b=0 for use LKRQ,H) VRUN H0KF-T0 L 0R-00MHZ_00 R _F 00 V_LK_ 0.0U_V_K_ U_V_K_ R _F 00 V_LK_ 0.0U_V_K_ U_V_K_ R _F 00 V_LK_F 0.0U_V_K_ 00 U_V_K_ 00 VPU VR VRF VPI V VPLL R _F 00 R _F 00 R _F 00 0U_.V_M 00_XR 0.0U_V_K_ U_V_K_ U_V_K_ 00 U_V_K_ 00 U_V_K_ 00 U_V_K_ 00 F Frequency Table: FL FL FL PU R[:0] PI F / / / / / (Reserced) R N_0K_J00 R0 N_0K_J 00 R0 0K_J 00 close to terminal side (For MI) pin setting 0=R,=ITP for pin, pin setting 0= Overclocking of PU and R llowed = Overclocking of PU and R NOT allowed pin setting 0= L_T 00MHz differential clock. for pin, = MHz non-spread clock, R0 0K_J 00 R0 0K_J 00 R 0K_J 00 R 0K_J 00 PLK_MINI N_0P_0V N 0 00 LK_IHPI N_0P_0V N 00 LK_IH N_0P_0V N 00 PLK_JI N_0P_0V N 00 onnect this pin via a. K series resistor to the F pin on the processor, _0VRUN R 0_J 00 N_K_J 00 heck List.0 R MH_L0 *.F[:0] do not have internal pullups or pull downs. Please refer to the latest restline volume for R configuration options N_K_J 00 _0VRUN *. k pull-up or pull-down or direct connect from processor. R0 0_J 00 N_K_J 00 M0 R MH_L only MH_L[0..]pull down K R N_K_J 00 _0VRUN R 0_J 00 N_K_J 00 HON HI PRIION IN. O., LT. R MH_L FOXONN P - R& ivision R N_K_J 00 LOK N(K0) TLKRQ# MINI_R_T# MH_LK_RQ# XPR_T# 0 ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

4 H_#[..] H_T#0 H_RQ#[..0] Layout note: no stub on H_TPLK TP. H_TPLK# to be routed in daisy chain fashion from IH to LP slot and then to PU. H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# dd H_#[..] TP TP TP0 TP TP TP TP TP TP0 TP MIL MIL MIL MIL MIL MIL MIL MIL MIL MIL H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 U J []# # L []# NR# L []# PRI# K []# M []# FR# N []# RY# J []# Y# N [0]# P []# R0# P []# L []# IRR# P []# INIT# P []# R []# LOK# M T[0]# RT# K RQ[0]# R[0]# H RQ[]# R[]# K RQ[]# R[]# J RQ[]# TRY# L RQ[]# HIT# Y []# HITM# U []# R []# PM[0]# W [0]# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PRQ# T []# TK T []# TI W []# TO W []# TM Y []# TRT# U [0]# R# V []# W []# []# THRML []# []# PROHOT# V T[]# THRM THRM 0M# FRR# THRMTRIP# INN# R ROUP 0 R ROUP TPLK# LINT0 LINT MI# M RV[0] N RV[0] T RV[0] V RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] F RV[0] IH RRV XP/ITP INL ONTROL H LK LK[0] LK[] H H F F 0 H TP F F 0 H_IRR# H_R#0 H_R# H_R# TP MIL MIL XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# 00 PROHOT# H_THRM H_THRM PM_THRMTRIP# 00// Roger request H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_RQ#0 H_INIT# H_LOK# H_PURT# H_R#[..0] H_TRY# H_HIT# H_HITM# MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP PM_THRMTRIP# LK_PU_LK LK_PU_LK# _0VRUN lose to PU side PM_THRMTRIP# IHM's PIO: VIL---> -0.V ~ 0.V VIH--->.0V ~.0.V MROM's PROHOT#: VIL---> -0.V ~ 0.*VP VIH---> 0.*VP ~ VP0. R _J 00 _0VRUN R _J 00 PM_THRMTRIP# should connect to IH-M and MH without T-ing (No stub) VRUN _0VRUN eagle=0r(%) R.0=.R(%) heck.0=0r(%) 00 0_J R M0 VT=0R(%) XP_TI eagle=r(%) R.0=.R(%) 00 _ R heck.0=r(%) XP_TM M0 VT=R(0.%) 00 N_._F R0 XP_PM# 00 _F R XP_TK 00 _F R XP_TRT# ebug port not used. resistors close to PU. W/:0/0 (microstrip) eagle=--- R.0=.R(%) heck.0=--- M0 VT=N_.(%) eagle=r(%) R.0=.R(%) heck.0=r(%) M0 VT=R(%) eagle=0r(%) R.0=R(%) heck.0=00~0r(%) M0 VT=R(%) OVT_# Q VRUN R R.K_J TU _0VRUN _J 00 Q0 N00 ase on R change net name PU OKT_P FOX_PZ-M-0 PROHOT# V N_-0LM-XT_. N 0 N_0P_0V_K_ 00 V V U R OUT N_0_J 00,,,,0,,,,,0 PLT_RT# V Q R K_J 00 N00 TP TP MIL MIL,0, OVT_# 00P_0V_K_ 00 RT# 0,0 H_THRM H_THRM R_OVT_# R 00 0_J When using Reset I solution, & R need to change to N condition 0.U_V_M_ 00 R.K_J 00 0.U_V_M_ 00 U V L - LRT# THRM# N -Pf null M bus ddress : 000 = For FM Place Thermal-ensor near PU & MH. / change part from FM ( -FM-0000) to -Pf (-P-0000) R.K_J 00 R.K_J 00 R0.K_J 00 M_THRM_LK 0,0 M_THRM_T 0,0 PM_THRM# 0 _0VRUN R.K_J Q 00 MMT0 HON HI PRIION IN. O., LT. FOXONN P - R& ivision Merom(HOT U)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) PM_THRMTRIP# ate: Thursday, May 0, 00 heet of

5 H_#[..0] H_TN#0 H_TP#0 H_INV#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U [0]# F []# []# []# F []# []# []# []# K []# []# J [0]# J []# H []# F []# K []# H []# J TN[0]# H TP[0]# H INV[0]# T RP 0 T RP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# TN[]# TP[]# INV[]# Y V V V T U U Y W Y W W Y U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# Place close to PU /0 change from 00 to 00 _0VRUN mil(microstrip) R K_F 00 R K_F 00 N_0.U_V_M_ 00 0 Layout Note: Zo= ohm, 0." max for TLRF. H_TN# H_TP# H_INV# Max Length 0. inch TP0 MIL 00_XR TP N_0.U_0V_K TP PU_L0 PU_L PU_L R N_K_J 00 R N_K_J 00 MIL MIL H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TLRF PU_TT PU_TT PU_TT PU_TT PU_TT PU_TT N []# K []# P []# R []# L [0]# M []# L []# M []# P []# P []# P []# T []# R []# L []# T [0]# N []# L TN[]# M TP[]# N INV[]# TLRF TT MI TT TT F TT F TT TT T RP T RP []# []# [0]# []# []# []# []# 0 []# []# F []# []# []# [0]# []# []# F []# TN[]# TP[]# F INV[]# 0 OMP[0] R OMP[] U OMP[] OMP[] Y PRTP# PLP# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP R0._F 00 R._F 00 R._F 00 R._F 00 H_PRTP#,, H_PLP# PWR# L[0] PWROO L[] LP# H_PULP# L[] PI# PI# PU OKT_P FOX_PZ-M-0 Layout Note: omp0, connect with Zo=. ohm, make trace length shorter then 0.". omp, connect with Zo= ohm, make trace length shorter then 0.". H_TN# H_TP# H_INV# Layout: onnect test point with no stub TP 0MIL H_PWR# H_PWR TP MIL 00// Roger request HON HI PRIION IN. O., LT. FOXONN P - R& ivision Merom(HOT U)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

6 U_.V_M_ 00 U_.V_M_ 00 0 U_.V_M_ U_.V_M_ ackup 0uF capacitors for uf shortage. VHOR VHOR U_.V_M_ 00 VHOR VHOR U_.V_M_ U_.V_M_ U_.V_M_ VHOR 0 U_.V_M_ U_.V_M_ N_0U_.V_M N_0U_.V_M 00_XR 00_XR N_0U_.V_M 00_XR N_0U_.V_M 00_XR U_.V_M_ 00 U_.V_M_ U_.V_M_ U_.V_M_ U_.V_M_ U_.V_M_ U_.V_M_ N_0U_.V_M 00_XR N_0U_.V_M 00_XR U_.V_M_ 00 N_0U_.V_M 00_XR N_0U_.V_M 00_XR 0 N_0U_.V_M N_0U_.V_M N_0U_.V_M N_0U_.V_M 00_XR 00_XR 00_XR 00_XR U_.V_M_ 00 U_.V_M_ 00 VHOR VHOR U V[00] V[0] V[00] V[0] 0 V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] 0 V[00] V[0] V[00] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] 0 V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] 0 V[0] VP[0] V[0] VP[0] V[0] VP[0] V[0] VP[0] V[0] VP[0] V[00] VP[0] 0 V[0] VP[0] F V[0] VP[0] F V[0] VP[0] F0 V[0] VP[0] F V[0] VP[] F V[0] VP[] F V[0] VP[] F V[0] VP[] F V[0] VP[] F0 V[00] VP[] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] V[0] VI[] V[0] VI[] V[0] VI[] 0 V[0] VI[] V[00] VI[] 0 V[0] VI[] 0 V[0] V[0] V[0] VN V[0] V[0] V[0] VN PU OKT_P FOX_PZ-M-0 VHOR F F0 F F F F F F0 V J K M J K M N N R R T T V W F F F F VHOR H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI VN VN PU_V---->0m PU_VP----->. PU_V------> eagle=0u R.0=NO heck.0=no M0 VT=NO ame Length Layout Note: Route VN traces at. Ohms with 0 mil spacing. Place PU and P within inch of cpu. width= mil spacing= mil R 0_J 00 R0 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 _0VRUN VI0 VI VI VI VI VI VI (esign check.0) 00.. No tuff. ± % pull-down to N near Intel MVP controller for testing purposes. N_0U_.V_M 0.U_V_M_ 0.U_V_M_ 00_XR U_V_M_ 00 R _VRUN PU 0_J 00 0U_.V_M 0.0U_V_M_ 00_XR 00 VHOR _VRUN R 00_F 00 R 00_F 00 0.U_V_M_ 00 0 mil LYOUT NOT: Place 0.0uF near PIN VN VN 00 mil 0.U_V_M_ 00 0.U_V_M_ 00 _0VRUN FX0R 0U_V_T P P move from page fix P location,but change P val from N_U to 0U M0 check U V[00] V[00] V[00] V[00] V[00] V[00] V[00] F V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[00] F V[0] F V[0] V[0] V[0] V[0] V[0] H V[0] H V[0] H V[0] H V[00] J V[0] J V[0] J V[0] J V[0] K V[0] K V[0] K V[0] K V[0] L V[0] L V[00] L V[0] L V[0] M V[0] M V[0] M V[0] M V[0] N V[0] N V[0] N V[0] N V[00] P V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] PU OKT_P FOX_PZ-M-0 P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F 0 N_0.U_V_M_ 00 N_0.U_V_M_ 00 N_0.U_V_M_ P_0V_K_ P_0V_K_ P_0V_K_ 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision Merom(POWR/N) ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

7 _0VRUN _0VRUN R0 00_F 00 R0._F 00 R0._F 00 _0VRUN R0 _F 00 R0._F 00 W/ = 0/0mil H_WIN 0.U_V_M_ 00 W/ = 0/0mil H_ROMP H_OMP H_OMP# ifferent with PM H_#[..0] H_PURT# H_PULP# _0VRUN R0 K_F 00 H_#[..0] ifferent with PM TP Place ap. near MH within 00 mils. MIL H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_OMP H_OMP# H_VRF U H_#0 H_# H_# M H_# H H_# H H_# H_# F H_# N H_# H H_# M0 H_#0 N H_# N H_# H H_# P H_# K H_# M H_# W0 H_# Y H_# V H_# M H_#0 J H_# N H_# N H_# W H_# W H_# N H_# Y H_# Y H_# P H_# W H_#0 N H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# Y H_# H_# H_# H_# H_# J H_# H H_# J H_#0 H_# H_# H H_# J H_# H H_# J H_# H_# J H_# J H_# H_#0 J H_# H H_# H H_# H_WIN H_ROMP W H_OMP W H_OMP# H_PURT# H_PULP# H_VRF H_VRF HOT restline MH-QN_ 0 mil -RTL-0 H_# J H_# H_# H_# M H_# H_# F H_# L H_#0 H_# H_# K H_# H_# L H_# J H_# H_# K H_# P H_# R H_#0 H_# H0 H_# L H_# H_# M H_# N H_# J H_# H_# H_# H_#0 H_# H_# H_# H_# H_# N H_# H_T#0 H H_T# 0 H_NR# H_PRI# H_RQ# F H_FR# H_Y# 0 HPLL_LK M HPLL_LK# M H_PWR# H H_RY# K H_HIT# H_HITM# H_LOK# 0 H_TRY# H_INV#0 K H_INV# L H_INV# H_INV# H_TN#0 M H_TN# K H_TN# H_TN# H H_TP#0 L H_TP# K H_TP# H_TP# J0 H_RQ#0 M H_RQ# H_RQ# H_RQ# H H_RQ# H_R#0 H_R# H_R# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# dd H_#[..] H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_#[..] H_HIT# H_HITM# H_LOK# H_TRY# H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] ifferent with PM R00 K_F 00 0.U_0V_K 00_XR R0 0_J 00 H_VRF HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (HOT)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

8 U R YTM MM LV F[:0] 00 = F 00 MHz 0 = F MHz PM_MUY#,, H_PRTP# PM_XTT#0 PM_XTT#,0 IMVP_PWR,,,,0,,,,,0 PLT_RT# PM_THRMTRIP#, PRLPVR VRUN MH_F_ (PI raphics Lane) 0,0 R_LRT# R 0_J Form (U)thermal sanser & () 00 TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP00 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL, M, M TP0 MIL TP0 MIL TP0 MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL Low = Reverse Lane High = Normal operation M0 /R M0 /R For layout convenience MH_L0 MH_L MH_L TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL PM_XTT# PM_XTT#0 PM_XTT#0 MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_0 MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_ MH_F_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ Wait to confirm with Page / R esign check.0 R onnect to PM_XT_T#0/ pins of MH, pull up with 0K to Vcc_ R0 R0 0K_J 00 0K_J 00 TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL R0 00_J 00 TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_0 MH_RV_ M M MH_RV_ MH_RV_ MH_RV_ M_O_RXIN- M_O_RXIN MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ PLTRT#_R PM_THRMTRIP# MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N MH_N0 MH_N MH_N MH_N MH_N MH_N MH_N P RV P RV R RV N RV R RV R RV M RV N RV J RV R RV0 M RV L RV M RV 0 RV H0 RV0 RV J0 RV K RV F RV H0 RV K RV J RV F RV RV RV0 RV J _M _M H RV W0 RV K0 RV LV_T# LV_T RV RV0 RV RV RV RV RV P F0 N F N F F F F F N F F J0 F 0 F R F0 L F J F F 0 F K F M0 F M F L F N F L F0 F[:] internal pull-up F[0:] internal pull-down PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# N0 THRMTRIP# PRLPVR J N K N K0 N L0 N L N L N L N K N J N N0 N N 0 N 0 N N K N restline MH-QN_ RV R MUXIN LK F MI RPHI VI PM M N MI M_K0 M_K M_K M_K M_K#0 M_K# M_K# M_K# M_K0 M_K M_K M_K M_#0 M_# M_# M_# M_OT0 M_OT M_OT M_OT M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF0 M_VRF PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF VO_TRL_LK VO_TRL_T LKRQ# IH_YN# TT TT V V W0 W W Y 0 K H J J L K K L R W H H K K N J N N M J N N J J M0 M J J M M M K0 T N M0 H K 0 R M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL MR_VRF RFLK RFLK# RFLK RFLK# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FT_VI_0 FT_VI_ FT_VI_ FT_VI_ FT_VR_N MH_LVRF VO_TRLLK VO_TRLT MH_LK_RQ# LK_MH_PLL LK_MH_PLL# MH_TT_ MH_TT_ R0 0_F 00 R0 0_F 00 MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] MIL TP MIL TP MIL TP MIL TP MIL TP R0 0K_J 00 M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_K0, M_K, M_K, M_K, M_#0, M_#, M_#, M_#, L_LK0 L_T0 MPWROK L_RT#0 M_OT0, M_OT, M_OT, M_OT, _VU R0 NV_0_J 00 R00 NV_0_J 00 MH_LK_RQ# MH_IH_YN# MH_LK_RQ# MIL TP R0 0_J 00 _VU R0 waiting change 0.% K_F 00 R0 waiting change 0.% K_F 00 RIMM_VRF _VRUN MR_VRF RFLK RFLK# RFLK RFLK# M_ROMP_VOH M_ROMP_VOL Note:If the voltage regulator for the system memory interface already supplies a VRF output and meets the voltage tolerance and current requirements for these pins, then a voltage divider would not be needed. xternal raphics (MH RT/TVOUT isable) R0.0K_F 00 R0 0_J 00 0.U_V_M_ 00 0.U_0V_K 00_XR R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J U_V_K_ U_V_K_ 00 0.U_V_M_ 00 R0 K_F 00 R0 _F 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (MI)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) U_0V_Y 00_YV.U_0V_Y 00_YV ate: Thursday, May 0, 00 heet of

9 VRUN TYP is open drawn(output) heck list.k to.v M0.KK to.v R.KK to.v R N_.K_J 00 0/ hange N to stuff TP MIL TP MIL heck List=.K R=.K M0=.K R TP MIL N_.K_F 00 TP MIL VRUN R N_.K_J 00 L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N L_I L_V R0 N_0_J 00 R0 N_0_J 00 0/ F suggest N to N M_ M_ M_ TV_ONL0 TV_ONL M_LU M_RN M_R M_LK M_T M_HYN_R RT_IRF M_VYN_R TV_ONL0 TV_ONL U J0 L_KLT_TRL H L_KLT_N L_TRL_LK 0 L_TRL_T L LK L T K0 L_V_N L LV_I L LV_V N LV_VRFH N0 LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#0 LV_T# F LV_T# 0 LV_T0 0 LV_T F LV_T LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T TV_ TV_ K TV_ F TV_RTN J TV_RTN L TV_RTN M TV_ONL0 P TV_ONL H RT_LU RT_LU# K RT_RN J RT_RN# F RT_R RT_R# K RT LK RT T F RT_HYN RT_TVO_IRF RT_VYN LV PI-XPR RPHI TV V P_OMPI P_OMPO P_RX#0 P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX#0 P_RX# P_RX# P_RX# P_RX# P_RX# P_RX0 P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX0 P_RX P_RX P_RX P_RX P_RX P_TX#0 P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX#0 P_TX# P_TX# P_TX# P_TX# P_TX# P_TX0 P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX0 P_TX P_TX P_TX P_TX P_TX N P_OMP M J P_RXN0 L P_RXN N P_RXN T P_RXN T0 P_RXN U0 P_RXN Y P_RXN Y0 P_RXN P_RXN W P_RXN P_RXN0 0 P_RXN P_RXN H P_RXN P_RXN P_RXN J0 P_RXP0 L0 P_RXP M P_RXP U P_RXP T P_RXP T P_RXP W P_RXP W P_RXP 0 P_RXP Y P_RXP P_RXP0 P_RXP H P_RXP P_RXP H P_RXP P_RXP N U P_TXN0 P_TXN U P_TXN N P_TXN R0 P_TXN T P_TXN Y P_TXN W P_TXN W P_TXN P_TXN P_TXN0 P_TXN P_TXN H H P_TXN P_TXN P_TXN M P_TXP0 T P_TXP T P_TXP N0 R U W P_TXP P_TXP P_TXP P_TXP Y P_TXP Y P_TXP P_TXP P_TXP0 0 P_TXP P_TXP P_TXP 0 P_TXP H P_TXP R._F 00 P_RXN[..0] P_RXP[..0] V_P (source)_0vrun 00 NV_0.U_V_M_ P_TXN0 00 P_RXN_0 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN0 00 P_RXN_0 NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ P_RXN_[..0] P_RXP_[..0] restline MH-QN_ xternal raphics (MH RT/TVOUT isable) R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 M_LU M_RN M_R RT_IRF M_ M_ M_ R0 NV_0_J 00 R0 NV_0_J 00 R00 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R00 NV_0_J 00 R0 NV_0_J 00 M_HYN_R M_VYN_R M_LK M_T L LK L T TV_ONL0 TV_ONL L_TRL_LK ase on below document: Mobile Merom Processor and restline hipset - anta Rosa Platform esign uide-,.0.pvd.pdf (May 00/ Rev.0)page Table. xternal raphics (MH Integrated raphics isable) onnect these signals to N R0 NV_0_J 00 L_TRL_T HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline(rphi)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

10 M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U R _Q0 W _Q _Q Y _Q R _Q R _Q T _Q W _Q _Q F _Q _Q0 J _Q _Q 0 _Q H _Q _Q W _Q _Q _Q 0 _Q F _Q0 H _Q 0 _Q F0 _Q R0 _Q W0 _Q T _Q W _Q W _Q Y _Q V _Q0 T _Q V _Q T _Q W _Q V _Q U _Q T _Q _Q _Q 0 _Q0 0 _Q _Q Y _Q 0 _Q W _Q _Q _Q _Q Y _Q T _Q0 T _Q Y _Q _Q R _Q R _Q R _Q N _Q M _Q N0 _Q T _Q0 N _Q M _Q N _Q R YTM MMORY restline MH-QN 0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M _M _M _M _M _M _M _M _M0 _M _M _M _R# _RVN# _W# K F L T W W Y N T H P T H P J 0 K H L K J J L 0 J Y0 M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M RVN# M 0, M, M, M #, M M[..0] M Q[..0] M Q#[..0] M [..0], restline add page M R#, MIL TP M W#, M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U P _Q0 R _Q W0 _Q W _Q N _Q N0 _Q V0 _Q V _Q 0 _Q 0 _Q _Q0 0 _Q _Q Y _Q F0 _Q F _Q J0 _Q J _Q J _Q L _Q K _Q0 K _Q K _Q K _Q J _Q L _Q J _Q J _Q K _Q J0 _Q L _Q0 K _Q K _Q _Q K _Q _Q _Q _Q _Q _Q J0 _Q0 L _Q K _Q L _Q K _Q K0 _Q J _Q J _Q F _Q H _Q _Q0 _Q K _Q _Q _Q J _Q _Q _Q R _Q T _Q Y _Q0 Y _Q U _Q T _Q R YTM MMORY restline MH-QN 0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M _M _M _M _M _M _M _M _M0 _M _M _M _R# _RVN# _W# Y R0 K L H J F W M M0 M M M M M M M M M M M M M M T0 M Q0 0 M Q K M Q K M Q J M Q L M Q M Q V M Q U0 0 L K M Q#0 M Q# M Q# M Q# K M Q# K M Q# F M Q# V M Q# W F Y V Y M 0 M M M M M M M M M M 0 M M M RVN# M 0, M, M, M #, M M[..0] M Q[..0] M Q#[..0] M [..0], restline add page M R#, MIL TP0 M W#, HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline(rii)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet 0 of

11 _VRUN V.M_MH_PLL _VRUN _VRUN R0 0_J 00 L 0R-00MHZ_00 H0KF-T0 00 U_.V_M_ V._PPLL_R 00_XR 0U_.V_M L 0R-00MHZ_00 H0KF-T0 R _F 0 0.0U_V_M 0U_0V_M 0.U_V_M_ 00_XR 00_XR 00 R00 _F 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J 00 R0 NV_0_J U_.V_M_ LLMPN 0R-00MHZ_00 V.RUN HPLL V.RUN MPLL NFMR L_FILTR V._TV VRUN_YN VRUN RT V.RUN V.RUN PLL V.RUN PLL V._TXLV V._LV V._Q V._RT V._TV V._TV V._TV m V._PPLL 0m 0m 00_XR 0.U_0V_K / backup for MI request close to P 0 00_XR 0.U_0V_K 0.U_V_M_ 00 N_0.U_0V_K 00_XR VRUN V._PPLL _VRUN _VRUN 00 U_.V_M_ FX0J0R P 00U_.V_ V.M_MH_PLL 0.U_0V_K 00_XR 00 0 U_.V_Y_Y 00 U_.V_M_ VRUN_YN VRUN RT V.RUN V.RUN PLL V.RUN PLL V.RUN HPLL V.RUN MPLL 00 U_.V_Y_Y V._TXLV 0.U_0V_K 00_XR 00 U_.V_M_ V._PPLL 0.U_0V_K 0 00_XR 0.U_0V_K 00_XR 00 U_.V_Y_Y V._TV V._TV V._TV V._RT V._TV V._Q 0m 00m V._LV 00_XR.U_.V_K J V_YN V_RT_ V_RT_ 0 H L M K0 K U UH M V_RT L V_TV N V_Q N V_HPLL U V_P_PLL J V_LV H V_LV VRUN V V V_PLL V_PLL V_HPLL V_MPLL V_LV V_LV V_P_ V_P_ V_P_PLL W V_M V V_M U V_M U V_M U V_M T V_M T V_M T V_M T V_M0 T V_M R V_M_NTF R V_M_NTF V_M_K V_M_K V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_TV 0VRUN RT PLL K M P LV POWR TV TV/RT LV restline MH-QN_ 00V-0-LF 0 R0 0_J 00 X M K MI R0 0_J 00 V._HV VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT V_X V_X V_X V_X V_X V_X V_X_NTF XF P VTT V_XF V_XF V_XF V_MI V_M_K V_M_K V_M_K V_M_K V_TX_LV HV V_HV V_HV V_P V_P V_P V_P V_P V_RXR_MI V_RXR_MI VTTLF VTTLF VTTLF VTTLF U U U U U U U U U U T T T0 T T T T T T R R R T U U T T T0 R J0 K K J J 0 0 W0 W V V0 H0 H V._HV VTTLF_P F VTTLF_P H VTTLF_P 00 0.U_.V_Y_Y 0m 0.U_.V_K 00_XR 00m 0 U_.V_Y_Y 00 0.U_0V_K 00_XR 00 0.U_.V_Y_Y 0m 00m 00m V._TXLV 00m 0m 00 0.U_.V_Y_Y 0U_.V_M 00_XR 0.U_.V_K 00_XR U_0V_Y 0_YV 00_XR 0.U_0V_K _VRUN U_.V_Y_Y 00 V_P 0.U_0V_Y_Y 00 _VRUN 00_XR 0.U_0V_K 0.U_0V_K 00_XR P 0U_.V_M 0U_.V_ 00_XR TP0MI 0 0.U_.V_Y_Y 00 _VRUN _0VRUN V._M_K _VU L UH_00 FI0F-R0K R0 _F U_.V_M_ 00_XR 0.U_0V_K L 0.0UH_00 WF0-0NM-L0 V_MI L0.0UH_00 WF0-0NM-L0 P 0U_.V_M 0U_.V_ 00_XR TP0MI P 0U_V_ FL0Y 0U_.V_M 00_XR V_MI V_P R00 00 N_0_J To connect the P & MI to same rail (V_P) tuff R and Remove, P, L _0VRUN _0VRUN / backup for MI request close to L HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline(powr,v)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) N_0.U_0V_K 00_XR ate: Thursday, May 0, 00 heet of

12 _0VRUN. U V_X R0 0_J 00. Note: ll VM pins shorted internally. V_X _VU T V T V H V V V K V J V J V H V H V0 H V F V R0 V U V_M U V_M U V_M V V_M W V_M W V_M Y V_M V_M V_M V_M0 V_M V_M V_M V_M V_M V_M V_M V_M V_M F V_M0 F V_M V_M V_M V_M H V_M H V_M H V_M J V_M J V_M J V_M0 K V_M K V_M K V_M K V_M L V_M U0 V_M V OR R0 V_X T V_X W V_X W V_X Y V_X 0 V_X V_X V_X V_X V_X0 V_X V_X 0 V_X V_X V_X V_X V_X V_X V_X 0 V_X0 V_X V_X V_X F V_X F V_X V_X H0 V_X H V_X H V_X H V_X0 H V_X V_X J0 V_X N V_X POWR V M V FX restline MH-QN_ V FX NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V M LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF T T T T T T T U U U U U0 U U U V V V V0 V V V Y Y Y Y Y0 Y Y Y Y Y Y F F H H H H J J J K K L L L L0 L L M M M M0 M M P P P P P0 P P P R0 R R R R V V V Y W W T 0.U_0V_K 00_XR R0 0_J 00 _VU Place where LV and R taps. 0.U_0V_K 00_XR 0.U_0V_Y_Y 00 0.U_0V_Y_Y _0VRUN 0.U_0V_K 00_XR 0.U_.V_Y_Y 0 00 U_.V_M_ mils from the dge. U_.V_M_ 00 P N_0U_V_T FX0R U_.V_M_ 0 00 P 0U_.V_ RTP0M U_.V_M_ 00 Place on the dge. 0.U_0V_Y_Y 00 U_.V_M_ 00 Place on the dge. U_.V_M_ 00 _0VRUN 0.U_0V_Y_Y 00 avity apacitors 0 0.U_0V_Y_Y 00 0.U_0V_Y_Y 00 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR avity apacitors N_0.U_V_Y_Y 00 0.U_0V_K 00_XR UF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF F V_NTF F V_NTF0 H V_NTF H V_NTF H V_NTF H V_NTF J V_NTF J V_NTF K V_NTF K V_NTF K V_NTF K V_NTF0 V_NTF J V_NTF M V_NTF L V_NTF L V_NTF V_NTF V_NTF V_NTF P V_NTF P V_NTF0 R V_NTF R V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF T0 V_NTF T V_NTF T V_NTF0 U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF V V_NTF V V_NTF V V_NTF V V_NTF0 V NTF L V_XM_NTF L V_XM_NTF L V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF P V_XM_NTF0 P V_XM_NTF P V_XM_NTF P V_XM_NTF L V_XM_NTF L V_XM_NTF L V_XM_NTF R V_XM_NTF R V_XM_NTF R V_XM_NTF V NTF POWR V XM NTF V V XM V_NTF T V_NTF T V_NTF U V_NTF U V_NTF V V_NTF V V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF F V_NTF F V_NTF K V_NTF M V_NTF M V_NTF P V_NTF P V_NTF R V_NTF0 R V_NTF R V_ V_ V_ V_ L V_ L V 0VRUN V_XM T V_XM T V_XM K V_XM K V_XM K V_XM J V_XM J. restline MH-QN_ HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline(v OR)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

13 UI V V V V V V V 0 V V V0 V V 0 V V V V V V V V0 V V V V V V V 0 V V 0 V0 V V F0 V F V F V F V V V V V0 0 V H V H0 V H V H V H V J V J V J V J V0 J V J V J V J V J V K0 V K V K V K V K V0 K V L V M V M V M V M V M V M V N V N V0 N V N V N V N V P V P V P0 V R V R V R V0 R V R V R V T0 V T V T V T V U V U V U V0 U V U V U V U V V V V V W V W V W V V restline MH-QN_ V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V W W W W W Y0 Y Y Y Y Y Y Y F F F H H0 H H H J J J J J J K K K K K K0 K K K L L L L L L UJ V 0 V00 V0 V0 V0 V0 V0 V0 V0 V0 0 V0 V0 V V V V F V F V F V F0 V F0 V V0 V V V V V V V V V V0 V H V H V H V H V J V J V J V J V J V0 J V J V J V K V K V K V L V L V L0 V0 L V L V L V L V L V M V M V M V M V M V0 M0 V M V N V N V N V N V N V N V N V N V0 N V N V P V P V P V P V P0 V R V T V T V0 T V U V U V U0 V V V V V V restline MH-QN_ V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V W W W W W W Y Y Y Y Y Y Y0 Y P T T T R F F T V H0 HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (V)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

14 0.U_V_M_ µf and. µf placed close to VRF pins R_VRF.U_0V_Y_Y 00 R_VRF M Q0 M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q0 M Q _VU _VU.V per IMM=.0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M Q V V0 M Q0 M Q Q Q0 M Q Q Q R M Q# V V R_XTT#0 M Q Q# N 0 PM_XTT#0 M M 0_J 00 Q M M Q V V M Q M Q Q Q M Q Q Q M Q V V 0 M Q M Q Q Q M Q Q Q M M V V M Q# M Q# M Q N Q 0 M Q V V0 M Q0 M Q Q Q0 M Q Q Q V V, M_K0 K0 K 0 M_K, V V R0 N R_M 0, M M, 0_J 00 M V V M M 0 M M M M V V M M M M 00 0 M M 0 V0 V 0 0 0/P 0 M 0, 0, M R# 0 M R# 0, 0, M W# 0 W# 0# 0 M_#0, V V 0, M # # OT0 M_OT0, M, M_# # V V, M_OT OT N 0 M Q V V M Q M Q Q Q M Q Q Q M Q# V V M M M Q Q# M 0 Q V M Q M Q V Q M Q M Q Q Q Q V M Q M Q0 V Q 0 M Q M Q Q0 Q Q V M Q# M M V Q# M Q M Q M Q V V 0 M Q M Q Q Q M Q Q Q M Q V0 V M Q M Q Q Q M Q Q Q 0 V V NTT K M_LK_R M_LK_R# M Q# V0 K# M Q Q# V M M Q M 0 M Q0 V V M Q M Q Q0 Q M Q Q Q M Q V V M Q0 M Q Q Q0 0 M Q Q Q M M V V M Q# M Q# M Q M Q V Q M Q Q V 0 M Q Q Q M Q V Q R,,,0 M_T_U V 0_IM0,,,0 M_LK_U 0K_J 00 L 0 VRUN _IM0 V(P) 00 R R O-IMM_00P 0K_J 00 0 FOX_0_NR_F Mus ddress: 0(W)/(R).U_0V_Y_Y 0.U_V_M_ IMM_0 Place IMM_0 near MH VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 0 0 MFIX MFIX NPTH NPTH 0 0 N V Q Q V M0 0 V Q Q V Q 0 Q V M V K0 0 K0# V Q Q V 0 P00 R RM O-IMM (00P) M_LK_R0 M_LK_R#0 M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0, RIMM_VRF R 0_J R_VRF 00 R_VRF (0 mil) 0.U_V_M_ 00 Place these aps near o-imm0. _VU.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y _VU Place these aps near o-imm U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)O-IMM_0 ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

15 0.U_V_M_ 00 R_VRF 0.U_V_M_ 00.U_0V_Y_Y µf and. µf placed close to VRF pins M Q0 M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q0 M Q _VU N VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 0 0 MFIX MFIX V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V _VU.V per IMM=.0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M_LK_R M_LK_R# 0/ wap strob,strob M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0,, 0, M 0, M 0 0, M W# 0, M #, M_#, M_K M_OT,,,0 M_T_U,,,0 M_LK_U VRUN / N 0 N_.U_0V_Y_Y 00 M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M M M M M M M 0 M Q M Q M Q# M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M M M Q M Q 0.U_V_M_ V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V K0 V N _ V V V0 0/P 0 W# V # # V OT V Q Q V Q# Q V Q Q V Q0 Q V M V Q Q V0 Q Q V NTT V0 Q# Q V Q0 Q V Q Q V M V Q Q V L V(P) IMM_ NPTH NPTH 0 0 V0 Q0 Q V N 0 M V Q Q V 0 Q Q V Q# Q 0 V0 Q0 Q V K 0 V V 0 V V 0 0 R# 0 0# 0 V OT0 V N 0 V Q Q V M 0 V Q Q V Q 0 Q V Q# Q V 0 Q Q V Q Q 0 V K K# V M 0 V Q Q V Q0 0 Q V Q# Q V 0 Q Q V 0 00 P00 R RM O-IMM (00P) M Q0 M Q R_XTT# M M M Q M Q M Q M Q M Q# M Q M Q0 M Q R_M M M M M M M 0 M M Q M Q M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q# M Q M Q M Q 0_IM _IM R 0-IMM_00P FOX_0_N_F R 0_J 00 hange net name from PM_XTT#_L to R_XTT# M_K, R0 0_J 00 M 0, M R# 0, M_#, M_OT, M_LK_R M_LK_R# 0/ wap strob,strob R 0K_J R 0K_J VRUN Mus ddress: (W)/(R) IMM_ is placed farther from the MH than IMM_0 PM_XTT# M, Place these aps near o-imm..u_0v_y_y.u_0v_y_y Place these aps near o-imm. _VU 0.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y _VU 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)O-IMM_ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

16 0_VU, M R 00 _J, M R 00 _J 0, M R# 0, M RP 00_PR M M RP 00_PR M M RP 00_PR M M RP 00_PR 0_VU 0, M 0 M 0 RP 00_PR 0, M W# 0, M # RP 00_PR M M RP 00_PR 0, M [0..] M M RP 00_PR 0_VU 0, M [0..], M_OT M 0 M M RP0 00_PR RP 00_PR 0_VU M M RP 00_PR 0_VU 0 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y Layout note: Place cap close to every R-pack terminated to 0_VU 0, M R# 0, M M M RP 00_PR RP 00_PR 0_VU, M_OT0 M RP 00_PR 0_VU 0, M M RP 00_PR U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y M M M M RP 00_PR RP 00_PR Layout note: Place cap close to every R-pack terminated to 0_VU 0, M 0 M 0 RP 00_PR 0_VU 0, M W# 0, M # RP0 00_PR M 0 M RP 00_PR, M_K0 R 00 _J 0_VU 0_VU 0_VU R 00, M_#0 _J R 00, M_OT _J, M_K R 00 _J, M_# R 00 _J, M_OT R 00 _J,, M_K M_K R R _J _J,, M_# M_# R R _J _J 0, M M R R _J _J HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)Termination ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

17 VRUN R0 N_0_J 00 R0 VRUN,,,,0,,,,,0 TXP[0..] TXN[0..] P_RXP_[0..] P_RXN_[0..] PLT_RT# NV_0K_J 00 TXP0 TXP TXP TXP TXP TXP TXP TXP TXP TXP TXP0 TXP TXP TXP TXP TXP TXN0 TXN TXN TXN TXN TXN TXN TXN TXN TXN TXN0 TXN TXN TXN TXN TXN P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ U NV_H0W LK_PI_P LK_PI_P# 00MHz R0 NV J 00 LK_PI_P LK_PI_P# TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN H U PX_RT# H PX_RFLK J PX_RFLK# J PX_TX0 K PX_TX0# H PX_TX PX_TX# PX_TX H PX_TX# PX_TX H PX_TX# K PX_TX J PX_TX# J PX_TX H PX_TX# 0 PX_TX H0 PX_TX# PX_TX H PX_TX# K PX_TX J PX_TX# J PX_TX H PX_TX# PX_TX0 H PX_TX0# K PX_TX J PX_TX# J PX_TX H PX_TX# H PX_TX PX_TX# K PX_TX J PX_TX# J PX_TX H PX_TX# P_RXP_0 K P_RXN_0 PX_RX0 K P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K0 P_RXP_ PX_RX# L0 P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_0 PX_RX# L P_RXN_0 PX_RX0 L P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L PX_RX# NV_NP- PI XPR MULTI-U I/O INTRF MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ P N N N M M P N N M L L R R P P R P L L L F Y Y Y MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ MIO0 MIO MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO R NV_K_F 00 MIO_HYN MIO_TL VRUN R NV_0K_J 00 TP MIL TP MIL TP MIL TP MIL TP00MIL TP00MIL TP MIL TP00MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL [MIO_HYN : LOT_LOK_F] 0 PU and MH share a common reference clock PU and MH do not share a common reference clock HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (PI XPR) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

18 P_RXN[0..] TXN[0..] VRUN P_RXP[0..] P_RXP0 P_RXP TXP0 NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP[0..] P_RXN0 TXN0 NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 NX trap for R-ball 000 MxInfineon 000 MxHynix 00 Mxamsung 00 MxInfineon 00 MxHynix 0 Mxamsung RM_F0 RM_F RM_F RM_F MIO0 R0 NVH_K_J 00 MIO R0 NVI_K_J 00 MIO R0 NV_K_J 00 MIO R0 NV_K_J 00 R0 NVI_K_J 00 R0 NVH_K_J 00 R0 NV_K_J 00 R0 N_K_J 00 P_RXP P_RXP TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 U_VNOR 0 (U YTM IO) (U XTRNL ROM) UVNOR MIO R NV_K_J 00 MIO P_RXP P_RXP TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 MIO0 is used to set the PI xpress PLL termination enable. FULT "0" PX_PLL_N_TRM MIO0 R NV_K_J 00 MIO0 P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN 00 NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP0 TXP0 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP 0 NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN0 0 NV_0.U_V_M_ TXN0 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN 0 NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ 00 NX IO_PF[:0] 000 NM-T evice I setting mismatch between VIO and H/W traps hange R value from N_ to NVMH_ hange R value from NV_ to NVP_ NX PI_VI[:0] NP- X0 "X" NM-T X00 "X" IO_PF0 IO_PF IO_PF IO_PF PI_VI 0 PI_VI PI_VI PI_VI PI_VI MIO R N_K_J 00 MIO R NV_K_J 00 MIO R NV_K_J 00 MIO_HYN R NV_K_J 00 MIO R NVM_K_J 00 MIO R N_K_J 00 MIO R N_K_J 00 MIO R NV_K_J 00 MIO_TL R N_K_J 00 R NV_K_J 00 R N_K_J 00 R0 N_K_J 00 R N_K_J 00 R NVP_K_J 00 R NV_K_J 00 R NV_K_J 00 R N_K_J 00 R N_K_J 00 MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO_TL MIO_HYN MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO_TL MIO_HYN RYTL(NX) 0 (M Hz) (Reserved) RYTL MIO R NV_K_J 00 MIO HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (PI-XPR/TRP) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

19 F_[0..] F_[0..] F[0:] FQM[..0] F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F FQM0 FQM FQM FQM FQM FQM FQM FQM U N F0 M F N F L F K F K F J F J F P0 F N F N0 F0 N F L F L0 F J0 F L F H0 F K0 F H F F0 F H F0 F 0 F 0 F H F H F F J F F F F F0 F F F F F F F 0 F Y F 0 F M0 F0 F0 F J F J0 F J F K F M F L0 F F 0 F F0 0 F F F F F F F F H F F F0 F F F F M FQM0 M0 FQM 0 FQM F FQM FQM K0 FQM 0 FQM 0 FQM R(-ROUP) F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_LK0 F_LK0# F_LK F_LK# FQ_WP0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_RN0 FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN P U P U0 Y W W T V T T U W W0 T V V0 U R V T0 W R R0 P U Y F_ F_R# F_ F_ F_ F_ F_ F_ F_0# F_ F_# F_W# F_0 F_ F_ F_RT F_ F_0 F_K F_0 F_ F_ F_ F_ F_ F_ F_ F_LK0 F_LK0# F_LK F_LK# FWQ0 FWQ FWQ FWQ FWQ FWQ FWQ FWQ M FRQ0 K FRQ FRQ FRQ FRQ L FRQ F FRQ H FRQ U F[0:] F0 F_ F F0 F_M0 F_R# F F F_M F_[..] F_ F_[..] F F F_M F_ F F F_M F_ F_R# F_R# F F F_M 0 F_R# F_ F_ F_R# F_ F F F_M F_ F_ F_ F_ F_ F F F_M F_ F_ F_0# F_ F_0# F F F_M F_0# F_0# F_0# F F F F_M F0 F_ F0 F F_M F_# F_# F F0 F_M0 F_# F_W# F_W# F F F_M F_W# F_0 F_0 F F F_M F F_0 F F F_ F F F_M F F F_ F F F_M F_RT F_RT F F F F_M F_RT F F F0 F F_ F F0 F_M F_0 F_K F F F_M F_K F F F_M F_K F F 0 F_0 F F F_M F 0 F_ F F F_M0 F_ F F F_M 0 F_ F F F_M F_ F F F_M F_ F0 F F_M F_ F F0 F_M F TP MIL F F F_ F F F_M 0 TP MIL TP MIL F F F_ F F F_M 0 TP MIL NX: dditional memory address bit F F 0 to support dual rank bank memory configurations F F F F F_LK0 F_LK0 F_LK0 F F F_LK0 F_LK0# F_LK0# F_LK0# F0 F F_LK0# F F_LK F_LK F_LK F F0 F_LK F F_LK# F_LK# F_LK# F F F_LK# F F F F F F F F F FWQ0 FWQ[..0] FWQ[..0] F F FQ_WP0 F FWQ F F FQ_WP 0 FWQ F F FQ_WP FWQ F0 F FQ_WP FWQ F F0 FQ_WP FWQ F F FQ_WP FWQ F F FQ_WP FWQ F F FQ_WP F0 F F F F F F F F FRQ0 FRQ[..0] FRQ[..0] F F FQ_RN0 FRQ F0 F FQ_RN FRQ F F0 FQ_RN FRQ F F FQ_RN FRQ F F FQ_RN FRQ F FQ_RN FRQ FQM[..0] FQM0 FQ_RN FRQ FQM FQM0 FQ_RN F FQM FQM F FQM FQM FQM FQM FQM FQM F FQM FQM FQM FQM 0 FQM Y0 F_ NX: dditional memory address bit to support dual rank bank memory configurations P R Y L K L F H0 R(-ROUP) NV_NP- NV_NP- HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (R) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

20 M bus ddress : 0000() For FM VRUN Use PU internal thermal sensor hange R,R form N to mount,0 M_THRM_LK,0 M_THRM_T NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 M_THRM_LK M_THRM_T HMI RT R NV_0_J 00 R NV_0_J 00 HP ackup NV_I_L NV_I_ 0 NV_I_L 0 NV_I_ MIL TP0 MIL TP0 MIL TP0 MIL TP NV_I_L NV_I_ HP_L HP_ NV_I_L NV_I_ NV_I_L NV_I_ NV_I_L NV_I_ ROM_# ROM_O TP_ROM_I ROM_LK UF I_L I_ IH_L H IH_ I_L I_ H I_L J I_ K I_L J I_ W ROM# ROM_O ROM_I ROM_LK I ROM NRL INL THRMN THRMP UFRT# TRO WPRY_ MMTRPL0 MMTRPL MMTRPL MMTRPL J K F T M NV_THRMN NV_THRMP UFRT# TRO WPRY TP00MIL TP MIL TP MIL MMTRPL TP MIL TP_MMTRPL TP MIL H MMTRPL TP MIL H MMTRPL0 TP MIL 00 NV_00P_0V_K_ VRUN R.K_J 00 U THRM# N - LRT# V L Pf 0.U_V_M_ 00 R N_0_J 00 R N_0_J 00 OVT_FX# NV_PIO R_LRT# M_THRM_T M_THRM_LK / change part from FM(VRIION:0.P) ( -FM-000) to Pf (-P0-0000) To PU From R_LRT#,0 VRUN R N_0K_J 00 ackup PIO for PU thermal trigger signal hange R from mount to N for using internal thermal sensor NV_I_L R0 NV_.K_J 00 NV_I_ R0 NV_.K_J 00 NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 NV_I_L R NV_.K_J 00 NV_I_ R NV_.K_J 00 VRUN NV_JT_TI R NV_0K_J 00 NV_JT_TM R NV_0K_J 00 NV_JT_TRT# R NV_0K_J 00 NV_JT_TK R NV_0K_J 00 HP_L HP_ R NV_0K_J 00 VRUN MIL TP MIL TP MIL TP0 MIL TP0 MIL TP0 MIL TP0 R0 NV_0K_J 00 U L V N N N N N HP ROM IFP_VPRO IFP_VPRO PX_TTLK_OUT PX_TTLK_OUT# TTMO R0 NV_0K_J 00 MIL TP0 NV_PROM_OI-_ K T00-U NV_JT_TK J JT_TK NV_JT_TM K JT_TM NV_JT_TI K JT_TI NV_JT_TO L JT_TO NV_JT_TRT# L JT_TRT_N NV_0.U_V_M_ 00 M K M M F H _0 XTLOUTUFF XTLIN NV_XTLOUT NV_PIO0 R0 NV_0_J 00 NV_HMI_T_, NV_PIO R0 NV_00K_J 00 NV_RJ NV_RJ NV_LV_N# NV_LV_N# NV_INV_N NV_INV_N V_PIO V_PIO 0 NV_PIO R 00 N_0_J TP0 MIL NV_PIO TP MIL NV_PIO R N_0_J 00 RT#,0 OVT_FX# OVT_FX# 0 NV_PWR_MIZR NV_PWR_MIZR,, NV_RT_TL R0 N_0_J 00 HMI_ NV_PIO TP MIL NV_PIO TP MIL NV_PIO TP MIL NVII F suggestion: hange PU thermal alert signal input from PIO to PIO. elete TP and pull-up PIO (R.K to VRUN) XTLIN R0 0_J 00 R_R_M_ XTLOUTUFF NV_XTLIN R0 0_J 00 R_RT_M_NON Y N_MHZ_0P_0PPM ITTI_L //0 PVT hange / F suggest If use internal spread function, U0 and related components can be N. 0/ hange R,R0 from N_ to NV_ for use internal spread spectrum. IFP_VPRO IFP_VPRO PX_TTLK_OUT PX_TTLK_OUT# F_U F_U TTMO NV_NP- R N_0K_J 00 R N_0K_J 00 TT INL RYTL PIO PIO0 K PIO H PIO K PIO PIO PIO J PIO PIO K PIO PIO PIO0 H PIO F PIO PIO U PIO U XTLIN T XTLOUTUFF T XTLIN U XTLOUT R N_0K_J 00 R U R0 N_0K_J 00 N_P_0V_J_N 00 N J 00 N_P_0V_J_N R N J R N_0K_J 00 N_U_0V_Y_Y 00 XTLOUTUFF_R _0 VMOUT N_000P_0V_M_ 00 U0 X/ILK X N V 0 P# LK RFLK N_MK-0 R place near PU R place near spectrum chip RFLK PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO0 PIO I/O VRUN Tis chip can use MK or P I/O I I O O O O O I O Internal pull low Yes Yes Yes No Yes Yes No No No No TP MIL PIO TL HMI Hot Plug etect 0(HP0) ctive High VI Hot Plug etect (HP) ctive High L L rightness(l0_l_pwm) ctive High Panel Power(L0_V) ctive Low L acklight enable(l0_l_n) ctive High PU Power owngrade for NV_V ctive Low Thermal lert Output (> egree) ctive Low ystem Power Limit lert Input ctive Low Memory Vref switch(mm_vrf) ctive High HMI Function ackup NV_RJ 00 NV_0K_J R NV_INV_N 00 NV_0K_J R PR PTRUM TTIN FOR MK 0 PR IRTION 0 OWN M OWN OWN 00// Update pread Percentage(%) = connect to N M= unconnected = connect directly to V NV_PIO 00 NV_.K_J R OVT_FX# 00 NV_.K_J R VRUN hange R from N to mount for using internal thermal sensor PR PTRUM TTIN FOR P R PR pread PIN IRTION Percentage(%) 0 OWN -. OWN -. nvidia support own -.% HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (POWR) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet 0 of

21 NV_R R NV_0_F 00 NV_RN R NV_0_F 00 NV_LU R NV_0_F 00 NV RT R0 NV F 00 H U _RT _RT R NV RT R NV F 00 UH N N N N N N 0 N N N N0 N N N N N N N F N F N F N0 F N F N 0 N N N N N N N N0 N H N J0 N J N J N J N J0 N J N J N J N0 J N J N K N K N K N L N L N L N L N L N0 L N L N L N M N M N M N M0 N M N M N M N0 N N N N N N N 0 N N N0 N N 0 N N N N 0 N N N N0 NV_NP- N N N N N N N N N N N0 N N N N N N N N N N00 N0 N0 N0 N0 N0 N0 N0 N0 N0 N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N F F F F F F F F H H J J J J K0 K K K L L M M M M N N N N P P P P R R R R R R R0 R T T T T T U U U U U V V V V V V V0 V W W W W Y Y Y Y L0 M0 LO TO PU N_N -R -RN -LU -HYN -VYN 0 NV_R 0 NV_RN 0 NV_LU 0 NV_HYN 0 NV_VYN V-RT R HYN VYN V-LK V-T NV_O_RXIN- NV_O_RXIN N_N NV_O_LKIN- NV_O_LKIN NV_O_RXIN0- NV_O_RXIN0 NV_O_RXIN- NV_O_RXIN NV_O_RXIN- NV_O_RXIN NV_VN_LKIN- NV_VN_LKIN NV_VN_RXIN- NV_VN_RXIN NV_VN_RXIN0- NV_VN_RXIN0 NV_VN_RXIN- NV_VN_RXIN I L MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP00 NV_R H _R NV_RN J _RN NV_LU H _LU 0m NV_HYN _IUMP F0 NV_VYN _HYN K0 _VYN F _RT NV_R F _R NV_RN _RN NV_LU 0m _LU _IUMP NV_HYN NV_VYN _HYN _VYN -R -RN -LU IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT -VIO Y J IFP_TX# K IFP_TX J IFP_TX0# H IFP_TX0 H IFP_TX# H IFP_TX K IFP_TX# J IFP_TX H IFP_TX# J IFP_TX L IFP_TX# K IFP_TX M IFP_TX# M IFP_TX L IFP_TX# M IFP_TX K IFP_TX# K IFP_TX L IFP_TX# K IFP_TX L IFP_RT NV_NP- VIO LV OMPOIT -ONNTOR PR Y OMPOITP LIN LIN LIN _R _RN _LU _IUMP _YN IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX TM IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT I L R T T V U NV_R NV_RN NV_LU 00m NV YN NV_HMI_TX- NV_HMI_TX NV_TM_- NV_TM_ NV_TM_0- NV_TM_0 NV_TM_- NV_TM_ TM LK MHz VI_TM_- VI_TM_ VI_TM_LKIN- VI_TM_LKIN VI_TM_- VI_TM_ VI_TM_- VI_TM_ NV_O_LKIN- NV_O_LKIN NV_O_RXIN0- NV_O_RXIN0 NV_O_RXIN- NV_O_RXIN NV_VN_RXIN- NV_VN_RXIN NV_VN_LKIN- NV_VN_LKIN NV_VN_RXIN- NV_VN_RXIN NV_VN_RXIN0- NV_VN_RXIN0 IFP_RT -R -RN -LU -HYN -VYN VI-I R HYN VYN VI-LK VI-T NV_R NV_RN TP MIL NV_HMI_TX- NV_HMI_TX NV_TM_0- NV_TM_0 NV_TM_- NV_TM_ NV_TM_- NV_TM_ I L NV_R NX: dd composite sync for RT support M M F F H H J K L L J J H TP00MIL TP00MIL TP0MIL TP0MIL TP0MIL TP0MIL TP0MIL TP0MIL TP0 MIL LO TO PU R NV_0_F 00 NV_RN R NV_0_F 00 NV_LU R NV_0_F 00 0/ dd test point for TM channel cause by VI on docking been cacelled HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (POWR) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

22 _VRUN _VRUN F[0:] FQM[..0] FRQ[..0] FWQ[..0] _VRUN F0 F F F F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F0 U_ZQ R NV_0_F 00 V V F V F V M V M V V V V V K V K V T Q T Q0 R Q R Q M Q N Q L Q M Q T0 Q T Q R0 Q R Q0 M0 Q N Q L0 Q M Q 0 Q F Q F0 Q Q 0 Q Q0 0 Q Q Q F Q F Q Q Q Q Q Q0 ZQ V V R R R R N N N N J J V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 U VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T _VRUN U_RFU RFU J TP MIL F_ F_0 F_ 0 F_0 F_ RFU J F_ L F_0 0 K F_ M F_ /P K F_ L F_ K0 F_ H F_ K F_ M F_ K F_ H F_0 0 K FQM M N FQM0 M N0 FQM M 0 FQM M0 FRQ RQ P FRQ0 RQ P0 FRQ RQ 0 FRQ RQ0 F_R# R# H F_# F_R# # F F_W# F_# W# H F_0# F_W# # F F_LK0 F_0# K J F_LK0# F_LK0 K# J0 F_K F_LK0# K H F_K VRM_VRF_ VRF0 H R FWQ WQ P FWQ0 WQ P NV_0K_J FWQ WQ 00 FWQ WQ0 MF 00 RFM F_ RFM H0 N V R NVP_0_J F_RT RT V F_RT R VRM_VRF_ VRF H M stuff M no stuff NV_KJQ-0 F T F Q T F Q0 R F Q R F Q M F Q N F Q L F Q M F Q T0 F Q T F Q R0 F0 Q R F Q0 M0 F Q N F Q L0 F Q M F Q 0 F Q F F Q F0 F Q F Q 0 F Q F0 Q0 0 F Q F Q F Q F F0 Q F F Q F Q F Q F Q F Q Q0 R NV_0_F 00 V V F V F V M V M V V V V V K V K V U_ZQ ZQ V V R R R R N N N N J J RFU 0 /P Minimum 00us delay required prior to applying 0 any executable command after stable power and clock. M M M M0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 U VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T U Mirror function on U_RFU RFU J TP MIL F_0 F_ 0 J F_ L F_ K F_ M F_ F_0 F_ F_[..] L K0 F_ H F_ F_ K F_0 F_ M F_ F_ K F_ F_ H F_ K F_ N FQM N0 FQM 0 FQM FQM F_[..0] FRQ RQ P FRQ RQ P0 R FRQ RQ 0 FRQ M tuff RQ0 R NVP_0_J 00M no stuff F_V R# H F_0# F_ # F F_K W# H F_# # F F_LK K J F_LK F_LK# K# J0 F_LK# F_W# K H VRM_VRF_ VRF0 H FWQ WQ P FWQ WQ P FWQ WQ FWQ WQ0 R NV_0K_F 00 MF MF _VRUN F_R# RFM H0 N V F_RT RT V VRM_VRF_ VRF H NV_KJQ-0 R NV_0K_J 00 F_RT 0,, NV_PWR_MIZR R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm NV_PWR_MIZR VRM_VRF is 0%FVQ for R.V Memory Vref switch controlled by PIO0 _VRUN _VRUN _VRUN _VRUN NV_PWR_MIZR NV_PWR_MIZR NV_PWR_MIZR R0 R R R Q NV_N00PT R NV_.0K_F R NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 N_U_0V_K Q NV_N00PT R NV_.0K_F R NV_.K_F 00 VRM_VRF_ NV_0K_F NV_0.0U_V_K_ 00 N_U_0V_K Q NV_N00PT R NV_.0K_F 00 R 00 NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 0 N_U_0V_K Q NV_N00PT R NV_.0K_F 00 R 00 NV_.K_F 00 VRM_VRF_ NV_0K_F 00 NV_0.0U_V_K_ 00 N_U_0V_K R,R, R,R 0 0 R(NX) ohm 0.0uF 00 F_LK0 R NV F F_LK0# 00 F_LK F_LK# R NV F NVII F suggestion: Update ingle resistor between Fx_LK and Fx_LK* to ohm HON HI PRIION IN. O., LT. FOXONN P - R& ivision VRM (R) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

23 _VRUN _VRUN _VRUN V V R R R R N N N N J J U _VRUN V V R R R R N N N N J J U U Mirror function on F F F0 F F F F F F F0 F F F F F F F F0 F F F F F F F F F F F F F0 F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 R# # W# # K K# K VRF0 WQ WQ WQ WQ0 MF RFM N RT VRF J J L K M K L K0 H K M K H K N N0 0 P P0 0 H F H F J J0 H H P P H0 V V H U_RFU F_ F_0 FQM0 FQM FQM FQM FRQ0 FRQ FRQ FRQ F_R# F_# F_W# F_0# F_LK0 F_LK0# F_K VRM_VRF_ FWQ0 FWQ FWQ FWQ VRM_VRF_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 RFM 00 R NVP_0_J F_RT TP MIL F_ F_0 F_R# F_# F_W# F_0# F_LK0 F_LK0# F_K R NV_0K_J 00 R M stuff M no stuff F_ F F F F F F F0 F F0 F F F F F F F F F F F F F F F F F F F F F F0 F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 Minimum 00us delay required prior to applying Q any executable command Q0 after stable power and clock. Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 RFU 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 R# # W# # K K# K VRF0 WQ WQ WQ WQ0 MF RFM N RT VRF J J L K M K L K0 H K M K H K N N0 0 P P0 0 H F H F J J0 H H P P H0 V V H U_RFU F_0 F_ FQM FQM FQM FQM F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ VRM_VRF_ F_RT VRM_VRF_ F_ F_ F_ F_ FRQ FRQ FRQ FRQ R0 NVP_0_J 00 F_V F_ F_0# F_K F_# F_LK F_LK F_LK# F_LK# F_W# FWQ FWQ FWQ FWQ FMF F_R# TP MIL R NV_0K_F 00 F_RT F_[..0] R0 M tuff M no stuff _VRUN F_[..] F[0:] FQM[..0] FRQ[..0] FWQ[..0] U_ZQ R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 0 L L V V0 J J L L P P P P T T T T NV_KJQ-0 U_ZQ R NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T NV_KJQ-0 R NV_0K_J 00 F_RT 0,, NV_PWR_MIZR R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm NV_PWR_MIZR Q0 NV_N00PT _VRUN 00 R00 R NV_.0K_F 00 R NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 N_U_0V_K VRM_VRF is 0%FVQ for R.V NV_PWR_MIZR Q NV_N00PT R NV_.0K_F 00 _VRUN 00 R0 R NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 N_U_0V_K Memory Vref switch controlled by PIO0 NV_PWR_MIZR Q NV_N00PT R NV_.0K_F 00 _VRUN 00 R R NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 N_U_0V_K NV_PWR_MIZR Q NV_N00PT _VRUN R NV_.0K_F 00 R 00 R NV_.K_F 00 VRM_VRF_ NV_0K_F 0 00 NV_0.0U_V_K_ 00 N_U_0V_K R0,R0, R,R R(NX) ohm 0.0uF 00 F_LK0 F_LK0# R0 NV F 00 F_LK F_LK# R0 NV F HON HI PRIION IN. O., LT. FOXONN P - R& ivision VRM (R) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

24 VRUN VRUN 0/ elete, and change R from 00 to 00 for MIO is used to straps input and the current is very low. VRUN VRUN R NV_0_J 00 R NV_0_J 00 L NV_0R-00MHZ_00 M00 L0 NV_0R-00MHZ_00 M00 0m NV_0.U_V_M_ 00 0m NV_0.U_V_M_ 00 0m NV_.U_0V_Y_Y 00 0m 0 NV_.U_0V_Y_Y 00 R NV_0K_J 00 MIL TP0 MIO_V MIO_V N_0.0U_V_K_ 00 N_0.0U_V_K_ 00 NV V NV V NV VRF NV V NV VRF m M MIO_VQ M MIO_VQ R MIO_VQ T MIO_VQ U MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ 0 T _V NV VRF H0 _VRF V R H U _V _VRF _V _VRF PLLV IFP_PLLV IFP_IOV NV_000P_0V_M_ 00 IFP_IOV IFP_PLLV 0m IFP_IOV -- LV I/O power IFP_IOV -- LV I/O power IFP_IOV -- TM I/O power IFP_IOV -- TM I/O power NX: / change power rail from.v to.v 0m(mm) NV_.U_0V_Y_Y 00 0m L0 NV_0R-00MHZ_00 M00 _VRUN _VRUN NX: / change power rail from.v to.v NV_0.U_V_M_ 00 L0 NV_0R-00MHZ_00 M00 _VRUN NX: hange power rail from.v to.v L0 PX_V NV_0R-00MHZ_00 M00 m NV_PLLV NV_000P_0V_M_ 00 m 00m(0m0m) NV_.U_0V_Y_Y 00 POWR IFP_PLLV IFP_PLLN IFP_IOV IFP_IOV IFP_IOV IFP_IOV IFP_PLLV F F 0 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_U_0V_Y_Y 00 0 NV_.U_0V_Y_Y 00 L0 NV_0R-00MHZ_00 M00 U0 PLLN IFP_PLLN 0 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 T0 VI_PLLV NV_NP- IFP_IOV 0 NV_000P_0V_M_ NV_0.U_V_M_ Q VRUN NV_FNP_NL NV VRF NV_0.0U_V_K_ 00 NV VRF NV_0.0U_V_K_ 00 VLW R NV_0K_J 00 RUN_IFP 0,0,, RUN_ON Q NV_TU HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (POWR) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

25 _VRUN For R FVTT require decoupling capacitor,fv don't require them 0 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 UI FVTT0 FVTT H FVTT H FVTT J0 FVTT J FVTT J FVTT J FVTT K FVTT K FVTT K FVTT0 K FVTT K FVTT K FVTT L FVTT M FVTT T FVTT U FVTT FV0 FV FV FV FV FV FV FV FV FV FV0 FV FV FV FV FV FV FV FV FV F_VRF 0 K F J M R V F_VRF N_0.U_V_M_ 00 R0 N_.K_F 00 _VRUN R N_0K_F 00.V PX_V.V PX_V L NV_0R-00MHZ_00 M00 L NV_0R-00MHZ_00 M00 m(frame uffer nalog Power) NV_.U_0V_Y_Y 00 NV_0.U_V_Y_Y 00 m(frame uffer nalog Power) NV_.U_0V_Y_Y 00 NV_0.U_V_Y_Y 00 0 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 F_PLLV F_PLLV FL_P_VQ FL_PU_N FL_TRM_N 0 K H J F_PLLV F_PLLN F_PLLV F_PLLN FL_P_VQ FL_PU_N FL_TRM_N POWR FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ H H H H H H L L M M R R V V.(Frame uffer core power for I/O) 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 0/ Replace P0 by a higher R cap(0mohm) for cost down _VRUN NV_000P_0V_M_ 00 NV_.U_0V_Y_Y 00 P0 NV_0U_0V_ 0TP0ML NV_NP- FL_P_VQ R00 N_0._F 00 R NV_._F 00 FL_PU_N R N_0_F 00 R0 NV_._F 00 _VRUN NVII 0// update R(NM-T) FL_P_VQ. ohm FL_PU_N. ohm R(NP-). ohm. ohm 0,, NV_PWR_MIZR Q N_N00PT F_VRF R N_.K_F 00 Memory Vref switch controlled by PIO0 FL_TRM_N R NV_0._F 00 FL_TRM_N 0. ohm 0. ohm NVII update NM VRM termination value FL_P_VQ. Ω FL_PU_N. Ω FL_TRM_N 0. Ω HON HI PRIION IN. O., LT. FOXONN P - R& ivision V (POWR) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

26 .V PX_V.V PX_V PX_IOV0 V/VQ:00m (I/O Power) F NV_V PX_IOV L0 F PX_IOV F NV_PLLV m(frame uffer nalog Power) PX_IOV NV_PLLV T PX_IOV NV_0R-00MHZ_00 Place close to L0 PX_IOV NV_0.U_V_Y_Y NV_.U_0V_Y_Y M00 N_000P_0V_K_ NV_0U_.V_M NV_0U_.V_M NV_U_V_K_ NV_0.U_V_M_ NV_0.U_V_M_ _XR 00_XR PX_IOVQ0 PX_IOVQ PX_IOVQ PX_IOVQ NV_V NX.V PX_IOVQ PX_IOVQ.(Internal logic core power) NV_U_V_K_ NV_0.U_V_M_ NV_000P_0V_M_ NV_000P_0V_M_ PX_IOVQ F 00 PX_IOVQ F 0 PX_IOVQ F NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ PX_IOVQ F PX_IOVQ0 V0 K V K V N R circuit.v V N 00 PX_V V N L0 V N /0 F suggest to N 00m PX_PLL_V V N F NVV_N PX_PLLV V N0 N_0.0U_V_K_ 00 N_N NV_0R-00MHZ_00 V P / backup M00 NV_.U_0V_Y_Y NV_0.U_V_M_ V P NV_000P_0V_M_ for MI request 00 V0 P NV_0.U_V_M_ NV_0.U_V_M_ V P NV_0.U_V_M_ close to L0 V P V R V R V T V T.V V T PX_V L V T 0m PX_PLL_V 0 PX_PLLV NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0R-00MHZ_ M00 NV_U_V_K_ NV_0.U_V_M_ V0 U V U V U PX_PLLN V U V U.V V V NV_V V V V W (econdary internal core power) L_NV_V V W P0 R NV_0_J 00 V_LP V W T0 V_LP T NV_U_.V_M_ NV_0.U_V_M_ NV_0.U_V_M_ V0 W NV_000P_0V_M_ V_LP U0 00 V W V_LP U V Y NV_000P_0V_M_ NV_000P_0V_M_ NV_000P_0V_M_ V_LP W0 V_LP V Y V Y VRUN V Y V Y 0m(.V Power rail PIO,I,PU IITL LOI) V Y0 V_0 P V_ NV_U_.V_M_ NV_U_.V_M_ NV_U_.V_M_ NV_0U_.V_ NV_U_0V_Y_Y NV_000P_0V_M_ NV_0.U_V_M_ V_ V_ RTP0M V_ V_ H V_ J V_ K 0 V_ L0 NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ V_ L NFN TP MIL V_0 N M L NFN V_ N V TP MIL M0 NFN TP0 MIL V_ N V H_PLLV is new power rail for NM NFN0 N TP MIL L NFN N TP MIL NFN m(power rail) N N W TP MIL PX_V MIL TP0 H NFN TP MIL NV_0R-00MHZ_00 PIF_PU N N W J NFN TP MIL FM0KF-T0 MIL TP NFN N N0 V NFN VRUN MIL TP NFN N N Y TP0 MIL M NFN TP MIL NV_.U_0V_Y_Y NFN N N F NV_0.U_V_M_ MIL TP M TP_F_PLLV TP MIL 00 MIL TP NFN N N 00 W H_PLLV 0/ Remove 0 for Internal HMI N N MIL TP0 F_VRF PIIF IN don't need Protection MIL TP NFN N N TP MIL TRP R NFN0 N N F TP0 MIL MIL TP V TTMMLK R N_0K_J 00 NFN N0 N MIL TP NFN N_.K_F U MIL TP NFN N N W TP MIL NFN 00_XR V TP MIL 00 N N Y HMI_PIF NV_NP- NV_0.0U_V_M R HON HI PRIION IN. O., LT. The trace impedance of R0 NV_K_F Nx Nx 00 0.V wing.v wing FOXONN P - R& ivision PIF_OUT_HMI N_._F 0nF 0nF should be ohm /- ohm 00 R0. ohm No tuff R No tuff No tuff V (R/I/ROM) OF R No tuff No tuff ize ocument Number Rev (M0--0 )Mainoard (MX-) U_0V_Y_Y N_000P_0V_M_ NV_U_V_K_ 00 0 NV_0.U_V_M_ 00 NV_U_V_K_ 00 NV_0.U_V_M_ 00 U POWR NX: / change power rail from PX_V to NV_V ate: Thursday, May 0, 00 heet of

27 ecoupling for Tright MMORY _VRUN Place around the MM 0 NV_0U_.V_M 00_XR NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 _VRUN. NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 _VRUN ecoupling for Tleft MMORY Place around the MM 0 NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 _VRUN NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision VRM (R) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

28 ecoupling for right MMORY _VRUN Place around the MM NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 _VRUN. NV_000P_0V_M_ 00 0 NV_000P_0V_M_ 00 ecoupling for left MMORY _VRUN Place around the MM 0 NV_0U_.V_M 00_XR 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 _VRUN NV_000P_0V_M_ 00 0 NV_000P_0V_M_ 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision VRM (POWRYP) OF ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

29 _V_T# PN0YR _OUT PN0YR Y_OUT 0 PN0YR These compoent close to -Video connector within 00 mil NV_RN NV_RN R 0_F 00 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 0P_0V_K_ 00 -VIO ONNTOR P_0V_K_N 00 Y_OUT _OUT _V_T# VRUN L NV_HMI_T_ NV_HMI_T_ 0, NV_R NV_R R 0_F 00 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 0P_0V_K_ 00 P0 HP has level shift function, so backup this circuit hange Q,Q,R,R to N emi-pnp ircuit (HMI) VRUN N_MVHFT U0 NV_HMI_T_ XT_V_N XT_V_N 0 emi-pnp( IN) MI R 0_J 00 VRUN 0 P_0V_K_N 00 L N Y N N R VRUN N_.K_J R 00 N_.K_J 00 Q Q N_TU N_TU -VIO RPTL ONN_P FOX_MH--F R 0K_J 00 R0 R0 0 V_RT_T# (RT) V_RT_T# (VIO) _V_T# 0K_J 00 0K_J 00 U MVHFT HON HI PRIION IN. O., LT. FOXONN P - R& ivision -VIO/emi-PnP ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

30 0/ elete R0 for it is no use VRUN _HIFT_VRUN VRUN Q0 V_RT_T# V_RT_T# 0 N_XT_V_N 0 TPT VRUN 0 NV_I_L emi-pnp( out) TU 0 NV_I_ NV_HYN NV_VYN Place near by RT onnector NV_I_L NV_I_ NV_HYN NV_VYN 0 0.U_V_Y 00_YV J_R J_LU J_RN U V_VIO V_ VIO_ V_YN VIO_ VIO_ YP 0 _IN _OUT _IN _OUT YN_IN YN_OUT YN_IN YN_OUT N M00-0QR 0.U_V_Y 00_YV _YV 0.U_V_Y M_RT_LK M_RT_T V_HYN V_VYN 0 0.U_V_Y 00_YV U_0V_K 00_XR ecrease _HIFT_VRUN ripple noise dd a () uf cap for _HIFT_VRUN Layout place close U pin _HIFT_VRUN NV_LU / MOR side suggest to support old RT, so add F,L and F L RT_VRUN_F NV_LU V-0._0 0L0-00MHZ_0 HKF-0T0 RT ONNTOR VRUN _HIFT_VRUN M_RT_LK NV_RN NV_R NV_RN NV_R L R-00MHZ_00 M000 0P_0V_J_N 00 M_RT_LK V_RT_T# TP0MIL TP_V_I VYN RT_VRUN J_LU HYN TP00 MIL M_RT_T J_RN J_R TP_V_I0 V_HYN V_VYN HYN P_0V_J_N 00 VYN P_0V_J_N 00 _HIFT_VRUN 0P_0V_J_N 00 L R-00MHZ_00 M000 N_0.0U_V_K_ 00 N 0 MPT R.K_J 00 R 0_F 00 R 0_F 00 L R-00MHZ_00 M000 0P_0V_J_N PTH NPTH NPTH PTH Z-N0-F R 0._F 00 R 0._F 00 R.K_J 00 M_RT_T R 0_F 00 0P_0V_J_N 00 / hange R,R from 0ohm to 0ohm for meet M00-0 termination pec 0P_0V_J_N 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision RT ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet 0 of

31 INVRTR_V LV ONNTOR Place 0 and close to N. TOUT INVRTR_OOT N_0.U_0V_K_ 00 R0 0_J 0 R0 N_0_J 0 U_V_K 00_XR INVRTR_V ackup Inverter boost circuit and use TOUT as INVRTR_V hange R0 from N to mount hange R0 from mount to N 0 0.U_0V_K_ 00 0 NV_RJ INV_N_ NV_RJ U0,U,U can use ON (MVH0FT) H.H. PN:-MVH-0 U0 VRUN INVRTR ONNTOR H0W INV_NL INV_RJ R 0K_J 00 INVRTR_V N MFIX MFIX TO HR ONN_P FOX_H0 hange net name from LV_PIO to MM_MO MM_MO# NV_O_LKIN- NV_O_LKIN NV_O_RXIN0- NV_O_RXIN0 NV_O_RXIN- NV_O_RXIN NV_O_RXIN- NV_O_RXIN NV_VN_RXIN0- NV_VN_RXIN0 NV_VN_RXIN- NV_VN_RXIN NV_VN_RXIN- NV_VN_RXIN NV_VN_LKIN- NV_VN_LKIN LV MM_N# MM_MO# NV_O_RXIN- NV_O_RXIN NV_O_RXIN0- NV_O_RXIN0 NV_O_LKIN- NV_O_LKIN NV_VN_RXIN0- NV_VN_RXIN0 NV_VN_RXIN- NV_VN_RXIN NV_O_RXIN- NV_O_RXIN NV_VN_RXIN- NV_VN_RXIN NV_VN_LKIN- NV_VN_LKIN NPTH MFIX UMMY P MFIX MFIX UMMY P MFIX NPTH N FP RPTL ONN_0P FOX_0-0-F LV 0, LIIN# 0 NV_INV_N VRUN U LIIN# NV_INV_N H0W INV_N_ LV INV_N_ NV_INV_N VRUN U INV_NL H0W R0 0K_J 00 INV_NL 0, Use H/W selection to enable MM function. hange R,R from.k to 0ohm MM_N# MM_N# H: MM isable L: MM nable R N_0_J 00 R 0_J 00.U_0V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 Place 0 close to N PNL I W K_J 00 YTM_I0 R H0-_W-LI LI0 LI LI R 00K_J 00 VLW urrent limit is from. to.. YTM_I0 0 0 NV_LV_N# VRUN R K_J 00 LV VRUN U IN OUT IN OUT OUT N O R 0.U_V_Y _J 00_YV PU 00 N 00 NV_0.U_V_Y_Y Q FNP_NL IHR R K_J 00 VRUN Q MMT0 R.K_J 00 R 00 0K_J NV_LV_N# Type ize Vender WX " wide L.PHILIP evice Name Lamps(New) Panel I heck[..0] 00 dd R,R for Instant On function been used again WX " wide L.PHILIP LPWP-TLLPWP-TL Lamps(New) 00 WUX " wide HRP LQ0ML Lamps(New) 00 WUX " wide HRP LQ0ML Lamps(Old) 0 HON HI PRIION IN. O., LT. FOXONN P - R& ivision LV ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

32 VRUN VRUN VRUN (TM inputs equalization control) P,P0 onfiguration 00: d, 0: d, 0: d, : 0 d R NV_0K_J 00 R N_0K_J 00 R N_0K_J 00 R NV_0K_J 00 NV_HMI_P0 NV_HMI_P HMI_RT_N# HMI_I_N# 0U_.V_Y 00_YV R0 N_0K_J 00 R NV_0K_J 00 R NV_0K_J P_0V_M 00_XR U_0V_Y_Y U_V_M 00_XR VRUN 0 N_U_0V_Y_Y 00 NV_0.U_V_Y 00_YV NV_0.U_V_Y 00_YV NV_TM_0- NV_TM_0 NV_HMI_TX- NV_HMI_TX NV_TM_- NV_TM_ TM_ TM_- VRUN_HMI NV_0.U_V_Y 00_YV L NV_R-00MHZ_00 FMJHM0-T NV_HMI_P0 NV_HMI_P HMI_I_N# N_ TT0 TT V_ N_ OUT_- OUT_ V_ OUT_- 0 OUT_ N_ OUT_- OUT_ V_ OUT_- OUT_ N_ IN_- IN_ 0 V_ IN_- IN_ N_ IN_- IN_ V_ IN_- IN_ THRML P R NV F 00 NV_HMI_T N# N_ HP_INK 0 _INK L_INK PR N_ V_ P0 P N_ RXT HP L RT_N# V_ N_ NV_HMI_T_ 0 HMI_RT_N# V_ O# U TM_- TM_ NV_TM_0- NV_TM_0 NV_HMI_TX- NV_HMI_TX NV_TM_- NV_TM_ NV_TM_- NV_TM_ NV_P0 NV_0.U_V_Y 00_YV TM_0- TM_0 HMI_TX- HMI_TX TM_- TM_ NV_TM_- NV_TM_ NV_0.U_V_Y 00_YV TM_ TM_- TM_0 TM_0- HMI_TX HMI_TX- NV_0.U_V_Y 00_YV 0.0U_V_M 00_XR HTX HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 HTX HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R NV_0_J 00 HTX HTX- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R0 NV_0_J 00 HTX0 HTX0- L N_0R-00MHZ_0._0.R M0H-00-P-T R NV_0_J 00 R NV_0_J 00 ata line capacitance to N need less than 0pF, so those parts need close to HMI connector 000P_0V_M 00_XR R NV_0_J 00 0U_.V_Y 00_YV 0, NV_HMI_T_ dd HMI equalizer for M0 long trace issue 0 NV_I_L HMI_VRUN R NV_0_J 00 NV_I_L HMI_I_L R NV_0_J 00 NV_I_ HMI_I_ 0 NV_I_ NV_HMI_T_ ost down evaluation hange R,R from N_ to NVPMH_, hange R0,,U from NVPMH_ to N U NV_I_L V NV_I_ 0 O# N N_NTPW R0 NV_00K_J 00 HMI_ HMI_VRUN_MP NV_HMI_T_ VRUN HMI_I_L HMI_I_ HMI capacitance to N need less than 0pF,so those parts need close to HMI connector R N_0_J 00 U LIN N 0 N LIN V N LIN N N LIN NV_Rlamp0M N_U_0V_Y_Y 00 HMI_L 0 HMI_ HMI_I_ HMI_I_L HTX HTX- HTX0 HTX0- HMI_L NV_HMI_T_ VRUN VRUN HMI ONNTOR HMI_ Q NV_UPT HMI_L Q NV_UPT N0 ata TM ata hield ata- ata TM ata hield ata- ata0 TM ata0 hield ata0- TM lock 0 TM lock hield TM lock- Reserved L / round V Power Hot Plug etect PTH 0 NPTH PTH NPTH PTH PTH NV_HMI RPTL_P FOX_QJ-FF-F HMI_ R0 NV_.K_F 00 HMI_L R0 NV_.K_F 00 HTX HTX- HTX HTX- HMI_ HMI_VRUN / hange new HMI connector P/N change from N-0000-MK0 to N-0000-MK0 PVT hange to -HUP-T000 0 NV_HUPT VRUN VRUN HMI_VRUN_F HMI_VRUN HMI_VRUN HON HI PRIION IN. O., LT. FOXONN P - R& ivision HMI F NV_V-0._0 M0P0TF / Replace F by 0. fuse for meet HMI pec 0 NV_HH-0PT L NV_R-00MHZ_00 FMJHM0-T NV_0.U_V_Y 00_YV ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of N_0.U_V_M_ 00

33 MFIX MFIX MFIX MFIX pecial mini stereo jack JTVN_00_J JTVN_00R-00MHZ_00 R 00 LM0N UIO_IN_L UIO_IN_L_ L UIO_IN_R UIO_IN_R_ JTVN_00_J JTVN_00R-00MHZ_00 L VIO_OMP R 00 LM0N JTVN_00R-00MHZ_00 L LM0N VIN_Y VIN_ -VIO IN N_0P_0V_J_N UIO_IN_R UIO_IN_L _W _W0 _RT _N _LK _N _IO _N _V _V 00 N_0P_0V_J_N JTVN_00R-00MHZ_00 LM0N L VIN_Y_ L VIN JTVN_00R-00MHZ_00 LM0N JTVN_PN0YR 00 JTVN_PN0YR 0 N_0P_0V_J_N N N_0P_0V_J_N 00 N_0P_0V_J_N VIO_OMP VIN_T# 00_NPO _W _W0 _RT _N _LK _N _IO _N _V _V LN_FF_0P FOX_RF00-00-F JTVN_P_0V_J 00_NPO N_PN0YR UIO F =.MHz VIO F =.MHz VIN_Y_N _LK _W _W0 _RT _IO _N _V UIO_IN_L_ UIO_IN_R_ JTVN_-VIO RPTL ONN_P PLK_MINI FOX_MH--F N 00 VIN_T#_ VIN_T# R0 N_0_J Y N N VIN N TV tuner "VIN_T#" signal no use. hange R0, to N VIN_Y VIN_ JTVN_PN0YR 0 JTVN_PN0YR JTVN_P_0V_J N LN_FF_0P FOX_RF00-00-F JTVN_PN0YR 00_NPO JTVN_0P_V_K VIO_OMP_ 00_NPO JTVN_0P_V_K 00 VIN_Y_N VIN N V_IN_N V_IN_N INT_PIRQ# VIN_Y_N PI_RQ#, PI_/#, PI_/#, PI_IRY# TV-TUNR not support LKRUN,0,, PM_LKRUN#, PI_RR# FT Test Pad TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP0 tpct_00 N_0P_0V_J_N 00_NPO JTVN_00P_0V_K N JTVN_PN0YR JTVN_PN0YR R L V 0 LN_0.U_V_Y_Y 00 R N J 00 N_P_0V_K_N 00 R0 JTVN_0_J 00, PI_PRR#, PI_/# VRUN_TV (.V) JTVN_UIO JK_P FOX_JL_00_TR VRUN_TV V_IN_N INT_PIRQ# VIN_Y PLK_MINI PI_RQ# PI_ PI_ PI_ PI_ PI_/# PI_ PI_ PI_ PI_ PI_/# PI_IRY# PM_LKRUN# PI_RR# PI_PRR# PI_/# PI_ PI_ PI_0 PI_ PI_ PI_ VIO_OMP PI_ PI_ V_IN_N LN_0.U_V_Y_Y 00 VRUN_TV (.V) LN_0.U_V_Y_Y 00 JTVN_PN0YR VRUN_TV UIO_IN_L LN_0.U_V_Y_Y 00 LN_0.U_V_Y_Y 00 VRUN LN_0.U_V_Y_Y 00 TV TUNR ONN R N_0_J 00.VUX_R N TIP PMJ- PMJ- PMJ- PMJ- L_RNP L_RNN HN INT#.V_ VIN_Y VIN_Y_N LK ROUN_ RQ#.V_ ROUN_ RRV_ /# ROUN_ ROUN_ /# IRY#.V_ LKRUN# RR# ROUN_ PRR# /# ROUN_ 0 ROUN_.V_ VIO_OMP V_ 0 VIO_OMP_N 0 _YN 0 _T_IN 0 _IT_LK 0 _O_I# MO_UIO_MON UIO_N_R Y_UIO_OUT Y_UIO_OUT N UIO_N_L UIO_IN_L V LN_MINI PI ONN_xP FOX_0-N-F LN_0.U_V_Y_Y 00 NPTH MFIX MFIX NPTH VRUN RIN PMJ- PMJ- PMJ- PMJ- 0 L_YLP L_YLN RRV_ V_ INT# 0 VIN_.VUX_ RT#.V_ NT# 0 VIN N PM# RRV_ 0.V_ 0 IL ROUN_ 0 0 PR 0 ROUN_ FRM# TRY# TOP#.V_ 0 VL# ROUN_ 0 ROUN_ /0#.V_ 0 0 THRML_ONTROL VIN_N# 00 ROUN_ 0 MN 0 _T_OUT 0 _O_I0# 0 _RT# 0 UIO_IN_R ROUN_ Y_UIO_IN Y_UIO_IN N UIO_N 0 MPIT#.VUX_ LN_0.U_V_Y_Y 00 VRUN VRUN_TV (.V) INT_PIRQ# VIN_.VUX_R PI_RT# PI_NT# PI_PM# R_L PI_0 PI_ PI_ PI_ MINI_IL PI_0 R LN_00_J 00 PI_ PI_0 PI_PR PI_ PI_PR, PI_ PI_FRM# PI_TRY# PI_TOP# PI_VL# PI_ PI_ PI_ PI_ PI_/#0 PI_ PI_ PI_ PI_0 THRML_TL_ TP0 MIL VIN_T# UIO_IN_R.VUX_R VRUN_TV ate: Thursday, May 0, 00 heet of INT_PIRQ# PI_RT#,, PI_NT# VIN N PI_PM#, R_L PI_FRM#, PI_TRY#, PI_TOP#, PI_VL#, PI_/#0, PI_[..0], HON HI PRIION IN. O., LT. FOXONN P - R& ivision MINI-PI ONN. LN_0.U_V_Y_Y 00 ize ocument Number Rev (M0--0 )Mainoard (MX-)

34 VRUN VRUN VRUN PI_FRM# PI_TOP# PI_RR# PI_TRY# PI_VL# PI_RQ# PI_LOK# PI_PRR# 0_0PR /0 el PI_RQ# Net INT_PIRQ# INT_PIRQ# INT_PIRQ# PI Pullups 0 RP0 0 0 RP0 0_0PR.K.K RP0.K 0_0PR VRUN PI_RQ#0 INT_PIRQF# INT_PIRQ# INT_PIRQ# VRUN PI_RQ# PI_IRY# VRUN INT_PIRQ# INT_PIRQH# PI_RQ# R 0_J 00 INT_PIRQF#_R INT_PIRQ#_R R 0_J 00 /0 el PI_RQ# Net, PI_[..0] INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# U PI_0 0 PI_ 0 PI_ PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 0 PI_ PI_ F PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# F PIRQ# PIRQ# PIRQ# 0 PIRQ# PI RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IRY# PR PIRT# VL# PRR# PLOK# RR# TOP# TRY# FRM# PLTRT# PILK PM# Interrupt I/F IHM-QM_ PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F 0 F F0 0 F F PI_RQ#0 PI_NT#0 PI_RQ# PI_NT# PI_RQ# PI_NT# PI_RQ# PI_NT# PI_/#0 PI_/# PI_/# PI_/# PI_IRY# PI_PR PI_RT# PI_VL# PI_PRR# PI_LOK# PI_RR# PI_TOP# PI_TRY# PI_FRM# PLT_RT# LK_IHPI PI_PM# INT_PIRQ#_R INT_PIRQF#_R INT_PIRQ# INT_PIRQH# ifference IH&IH.el RQ/NT,RQ/NT.hange trap Pin station(nt#-->nt0#) MIL TP MIL TP0 PI_RQ# PI_NT# PI_/#0, PI_/#, PI_/#, PI_/#, PI_IRY#, PI_PR, PI_RT#,, PI_VL#, PI_PRR#, PI_RR#, PI_TOP#, PI_TRY#, PI_FRM#, PLT_RT#,,,,0,,,,,0 LK_IHPI PI_PM#, R 0_J 00 R N_0_J 00 INT_PIRQ# MM_MO# MM_N# PI_RQ#0 PI_NT#0 NT0# is trap Pin For oot IO election. It's used Integrated pull_up / IH trap Pin change from IH NT# trap for oot-io LP(efault) NT0# Hi PI_# Hi PI Hi LOW PI LOW Hi 0/0/0 hange LV_PIO Net to MM_ontrol /0 New add High KU HRP panel MM function / hange R to no stuff VLW U_O# U_O# U_O# U_O# 0 RP 0K 0_0PR PI_# PI_LK PI_MOI PI_MIO LN_RXN LN_RXP LN_TXN LN_TXP 0 XPR_RXN 0 XPR_RXP 0 XPR_TXN 0 XPR_TXP MINI_RXN MINI_RXP MINI_TXN MINI_TXP It's used 0K Integrated pull_up PI_0# is Output Pin PI_# is trap Pin For oot IO election. It's used Integrated pull_up U_O#0 U_O# U_O# U_O# TP MIL VLW R0 0K_J 00 R0 0K_J U_V_M_ U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 0.U_V_M_ 00 TP0 MIL TP0 MIL TP0 MIL TP00 MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL TP0 MIL U_O#0 U_O# U_O# U_O# U_O# U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# LN_TXN_ LN_TXP_ M M XPR_TXN_ L XPR_TXP_ L MINI_TXN_ MINI_TXP_ TP_PI_LK TP_PI_0# TP_PI_# TP_PI_MOI TP_PI_MIO U P PRN P PRP N PTN N PTP PRN PRP PTN PTP K PRN K PRP J PTN J PTP H PRN H PRP PTN PTP F PRN F PRP PTN PTP PRN/LN_RXN PRP/LN_RXP PTN/LN_TXN PTP/LN_TXP PI_LK PI_0# PI_# PI_MOI F PI_MIO J O0# O#/PIO0 O#/PIO O#/PIO F O#/PIO O#/PIO O#/PIO0 J O#/PIO O# H O# PI-xpress IHM-QM_ PI irect Media Interface U MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP URI# URI V V U U Y Y W W T T Y Y H H H H J J K K K K L L M M M M N N F F MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP MI_OMP R URI MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH R._F 00 U_PN0 U_PP0 U_PN U_PP U_PN U_PP MIL TP0 MIL TP0 U_PN U_PP U_PN 0 U_PP 0 MIL TP0 MIL TP0 U_PN U_PP U_PN U_PP U_PN U_PP._F 00 Place within 00 mils of IH and don't routing next to high speed signals Place within 00 mils of IH _VRUN U Port0 -- U Port0 U Port -- U Port U Port -- U Port(udio oard) U Port -- X U Port -- luetooth U Port -- xpress ard U Port -- X U Port -- amera (0/ modify) U Port -- OI U Port -- IR / updata base on MOR side suggest HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( PI/U ) / ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

35 RTRT# VccRT R 0K_J 00 _OUT Min : ms T_L# VRUN R0 0K_J 00 T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP H_UIO_TIN0 H_M_TIN 0 H_UIO_TIN The traces inside this block should be wider. No digital signals routed under XTL 00 0 P_0V_K_N LK_KX V VRT /.KHZ_.P_0PPM R swap from Y R 0M_J mils LK_KXR to LK_KX 00V-0-LF QM U_.V_M_ U 00 P_0V_K_N 00 R LK_KX LK_KX_R RTX F 0_J 00 RTX R K_F 00 RTRT# F RTRT# OPN_JUMP_OPN M_INTRUR# R R U_0V_Y INTRUR# _F 00_YV P INTVRMN F trap Pin 00 M_J LN00_LP INTVRMN LN00_LP 00 RT_T_PWR0 TP_LN_LK TP0 MIL LN_LK TP00 TP_LN_RTYN MIL R0 LN_RTYN _F _V_PI VLW TP_LN_RX0 0/ F suggest TP0 MIL 00 TP_LN_RX LN_RX0 LN_OK#/PIO can be TP0 MIL N TP_LN_RX LN_RX left as N if internal LN is not used TP0 MIL LN_RX HR_P 0 R0 R0 TP_LN_TX0 TP0 MIL N_0K_J TP_LN_TX LN_TX0 TP0 MIL 0 FOX_H0._F 00 TP_LN_TX LN_TX TP0 MIL 0 LN_TX 00 NRY_T H LN_OK#/PIO LN_OMP LN_OMPI IH datasheet error, PIO is not truer PIO Pin, IO can't control it's action LN_OMPO hange _OUT from IH PIO to PIO IH_ITLK J IH pin H(PIO) add TP0 IH_YN H_IT_LK J IH pin (PIO) del TP, link to X-U conn. H_YN IH_RT# H_RT# _OUT H_UIO_TIN0 J H_M_TIN H H_UIO_TIN H TP MIL TP_H_IN IH_TO T_RXN0_ T_RXP0_ T_TXN0_ T_TXP0_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ R R N_0_J 00 N_0_J 00 T_RXN_ T_RXP_ TP_T_TXN TP MIL TP_T_TXP TP MIL LK_PI_T# Place close to IH LK_PI_T Within 00 mils of the IHM,and avoid routing next to clock pins. TP MIL 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 TRI R0._F 00 TP_PIO H_IN0 H_IN H_IN H_IN H_OUT 0 H_OK_N#/PIO H_OK_RT#/PIO F0 TL# F T0RXN F T0RXP H T0TXN H T0TXP TRXN TRXP J TTXN J TTXP F TRXN F TRXP TTXN TTXP T_LKN T_LKP TRI# TRI IHM-QM_ IH LN / LN RT I PU LP T IH-M Internal VR nable trap (Internal VR for Vccus_0, Vccus_, VccL_) INTVRMN FWH0/L0 FWH/L F FWH/L FWH/L F FWH/LFRM# LRQ0# LRQ#/PIO 0T F 0M# PRTP# F PLP# FRR# PUPWR/PIO INN# F INIT# INTR 0 RIN# H NMI MI# TPLK# THRMTRIP# TP 0 V U V T V T T T R 0 T V V U V U 0 # Y # Y IOR# W IOW# W K# Y IIRQ Y IORY Y RQ W Low= Internal VR isabled High= Internal VR nabled(efault) LP_0 LP_ LP_ LP_ LP_FRM# LP_RQ#0 LP_RQ# H_0T H_0M# H_PRTP# H_PLP# H_PWR H_INN# H_INIT# H_INTR H_RIN# H_NMI H_MI# H_TPLK# PM_THRMTRIP_R H_TP I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ INTVRMN LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRM# 0, LP_RQ#0 H_0M# H_PRTP#,, H_PLP# H_INN# H_INIT# H_INTR H_NMI H_MI# H_TPLK# I_P[0..] VRT H_PWR I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ R0 K_F 00 _0VRUN _0VRUN R _J 00 R _J 00 I_P[0..] H_RIN# H_0T IH-M LN00_LP trap (Internal VR for VccLN_0 and VccL_0) LN00_LP H_FRR# Low= Internal VR isabled High= Internal VR nabled(efault) VRUN R0 0K_J 00 H_PRTP# H_PLP# H_INTR H_NMI H_MI# H_TPLK# H_TP LP_RQ# VRUN VRUN R 0K_J 00 VRUN LN00_LP Q N00W--F R N_0_J 00 VRT MIL TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP R00 K_F 00 _RIN# 0 _0T 0 UIO ignal to ircuit Q N00W--F IH_ITLK R0 _J 00 R0 _J 00 R _J 00 H_M_ITLK H_UIO_ITLK H_UIO_ITLK 0 IH_RT# R0 _J 00 R0 _J 00 R _J 00 H_M_RT# H_UIO_RT#, H_UIO_RT# 0 R N_0_J 00 IH_TO R00 _J 00 R0 _J 00 R _J 00 H_M_TOUT H_UIO_TO H_UIO_TO 0 H_M_YN H_UIO_YN 0 H_UIO_YN R0 _J 00 R0 _J 00 R _J 00 R0 00 IH_YN N_K_J VRUN HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M(LP,I,T)/ ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

36 VLW VLW PM_RI# MLINK MLINK0 _RT# R0 0K_J 00 PM_YRT# R0 0K_J 00 M_LRT# R 0K_J 00 TLOW# R.K_J 00 _PI_WK# R K_J 00 LINKLRT# R N_0K_J00 XTMI# R 0K_J 00 WK_I# R 0K_J 00 VRUN RP 0K 00_PR _THRM# R.K_J 00 RUNTIM_I# R.K_J 00 INT_RIRQ R.K_J 00 PM_LKRUN# R.K_J 00 I_LP_PI# R 0K_J 00 R 0K_J 00 PIO U M_LK_U,,,0 M_LK_U J M_T_U MLK,,,0 M_T_U LINKLRT# MT LINKLRT# MLINK0 LINKLRT# VU MLINK MLINK0 MLINK PM_RI# F RI# Q PM_U_TT# PM_U_TT# F PM_YRT# U_TT#/LPP# Y_RT#,,0 PI_WK# PM_MUY# PM_MUY# MUY#/PIO0 N_N00 M_LRT# MLRT#/PIO PM_TPPI# PM_TPPI# 0 TP_PU# TP_PI#/PIO TP_PU# TP_PU#/PIO PM_LKRUN# R 0_J 00,0,, PM_LKRUN# H LKRUN#/PIO 0,, INT_RIRQ _PI_WK# INT_RIRQ WK# F _THRM# RIRQ THRM# VRMPWR J0 VRMPWR TP 0MIL J TP 0/ F suggest 0 Port I/F: TP_PIO TP 0MIL J No stuff R. LINKLRT# can I_LP_PI# TH/PIO H: LP bus I_LP_PI# J be left as N if unused this function. RUNTIM_I# TH/PIO L: PI bus 0 RUNTIM_I# H ee anta Rosa MOW WW XTMI# TH/PIO 0 XTMI# OVT R PIO TP_PIO PIO TP0 0MIL TP_PIO TH0/PIO TP 0MIL H TP_PIO0 PIO TP 0MIL TP_PIO PIO0 TP000MIL 0 INV_N_ LOK/PIO INV_N_ H QRT_TT0/PIO TP00MIL QRT_TT/PIO TLKRQ# LI TLKRQ#/PIO LI F LI LO/PIO J / hange PIO Net from M_PWRN to TP TP_PIO TOUT0/PIO TP 0MIL 0 TOUT/PIO H_PKR H_PKR PKR MH_IH_YN# J MH_YN# TP 0MIL J TP IHM-QM_ M Y PIO PIO MI T PIO locks Power MT ontroller Link T0P/PIO TP/PIO TP/PIO TP/PIO LK LK ULK LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VRF0 L_VRF L_RT# LPIO0/PIO LRT#/PIO0 NTTT/PIO WOL_N/PIO TLOW# LOO_L_N R0 0K_J 00 J LOO_L_N J0 PIO F LI LK_IH LK_U U_LK 0MIL TP LP_# F LP_# LP_# H TP_PIO IMVP_PWR_F R K_J 00 J 0 R 0_J 00 TP_LP_M# L_LK L_T L_VRF0_IH L_VRF_IH TP_PIO WK_I# _RT# R 00_J 00 PM_LP_# 0 R 00_J 00 PM_LP_# 0 R0 0_J 00 PM_LP_# 0 0MIL TP0/ hange PIO from _OUT to TP H0 00 0K_J R0 PM_RMRT_# R K_J 00 LK_PWR_IH R 0_J 00 MPWROK J F F F H J J J F 0MIL TP L_LK0 L_LK L_T0 L_T L_RT#0 0MIL TP IMVP_PH WK_I# 0 _RT# LI0 LI LK_IH LK_U IMVP_PWR,0 PRLPVR, 0/0/0 hange R, R from.k to K PWRTN# 0 PM_RMRT# 0 LK_N MPWROK 0.uF_0% 00 L_VRF ~=0.0V 0/ F suggest onnect LN_RT# to N if no internal LN used. ee anta Rosa design guide table The spec K0 LK_N is high enable, not low enable, correct "#"mark wrong on schematic,hange IH pin /U pin net name from LK_N# to LK_N R.K_F 00 VRUN R N_.K_F 00 VU R _F 00 0/ internal review change VU to VRUN VU=>Power on at VRUN=>Power off at M_LK_U R.K_J 00 M_T_U R.K_J 00 VRUN LI Pull High R 0K_J 00 R 0K_J 00 LI0 LI traps Pin 0, IMVP_OK,0, OVT_# R 0_J 00 R 0_J 00 R0 0_J HH-0PT MPWROK VRMPWR OVT R PM_RMRT_# N_0.U_V_M_ 00 R N F 00 R N_.K_F 00 R N_.K_F 00 eagle not support MT / hange VRUN to VWL VLW VU LI R 0K_J 00 0, LW_PWR 0 HH-0PT IMVP_PWR_F LI R N_0K_J 00 / elete R Pull Low PM_RMRT# R 0K_J 00 IMVP_PWR R0 0K_J 00 INV_N_ R 0K_J 00 VRMPWR R 00K_J 00 M_LK_U M_T_U dds.h U V WP L 0 V PROM_OP-_x HTL0 VRUN 0.U_V_M_ 00 R K_J 00 PM_YRT_J# YUTN PM_YRT# H0-0PT P OPN_JUMP_OPN 0.U_V_M_ 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( PIO) / ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

37 _VRUN VLW R 0_J 00 VRUN VLW _VRUN VRUN _VRUN _VRUN VLNPLL VRUN VRT 00V-0-LF _V_PI VRF_U VRF. for all V_ 0/0 hange LN Power from VU to RUN 0.UF 0% 00V-0-LF 0.U_V_Y_Y 00 R 0_J 00 R _F 00 R0 0_J 00 R 00_J 00 0/ F suggest May remove R, L. ue to no internal LN implemented, VLNPLL can connect to power without filter. 0.U_V_Y_Y 00 L 0UH_00 FI0F-00K R N F 00 L0 0R-00M_0 HKF-T0 P TP0ML 0U_.V_.U_0V_Y 00_YV 0 0U_.V_Y 00_YV L 0/ hange 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 N_UH_00 FI0F-R0K VLNPLL N_0U_.V_Y 00_YV _V_PI 0/ F suggest hange to uf U_.V_M_ 00 U_0V_Y 0_YV 0.U_V_Y_Y 00 0 U_0V_Y 0_YV TP MIL m 0.U_V_Y_Y 00 m m m u VTPLL 0m 0m m 0m m VRUN R _F 00 V._LN_IH / IH dd.vrun Power(VLN_), hange Lan Power from VU to VRUN U_0V_Y_Y 00.U_V_Z 00_YV U_0V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 N_.U_V_Z 00_YV UF VRT VRF[] T VRF[] VRF_U V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] F V [] F V [] V [] H V [] H V [] J V [] J V [] K V [] K V [0] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [0] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V [0] U V [] V V [] V V [] V V [] W V [] Y V [] J VTPLL V [0] F V [0] V [0] H V [0] J V [0] V [0] V [0] V [0] V [0] V [0] 0 V [] V [] V [] V [] V [] V [] H V [] V [] V [] VUPLL F V [0] L V [] L V [] M V [] M V [] W V [] F VLN_0[] VLN_0[] F VLN_[] 0 VLN_[] VLNPLL VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_ IHM-QM_ VRUN OR VP RX TX VP_OR I PI VPU U OR VPU LN POWR V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] F V_0[0] V_0[0] L V_0[0] L V_0[] L V_0[] L V_0[] L V_0[] L V_0[] M V_0[] M V_0[] P V_0[] P V_0[] T V_0[0] T V_0[] U V_0[] U V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V VMIPLL R V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] F V_[0] V_[0] V_[0] V_[0] V_[0] F V_[0] V_[0] U V_[0] V V_[0] W V_[] W V_[] W V_[] Y V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] 0 V_[] V_[] F VH VUH VU_0[] J VU_0[] F0 VU_[] VU_[] J VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] 0 VU_[0] H VU_[0] P VU_[0] P VU_[0] VU_[0] N VU_[] P VU_[] P VU_[] P VU_[] P VU_[] P VU_[] R VU_[] R VU_[] R VU_[] R VL_0 VL_ VL_[] F0 VL_[] R 0_J 00 VU_0 VU_ VccL_0 VccL_ 0.UF 0% m VMIPLL_IH 0.UF 0% 0.UF 0% 0/ hange. m 0m VU m m m MIL TP MIL TP MIL TP0 0.UF 0% 0.UF 0% 0.UF 0% 0.UF 0%.U_0V_Y 00_YV 0.0U_0V_Y 00_YV 0 0.UF 0% N_U_0V_Y_Y 00 R N_0_J 00 0.UF 0% 0.UF 0% L VMIPLL_IH_R UH_00 FI0F-R0K 0U_.V_Y 00_YV 0.UF 0% 0.UF 0% N_0.UF 0% N_0.UF 0% N_0.UF 0% 0.UF 0%.U_0V_Y 00_YV m for all V_ N_0.0U_0V_Y 00_YV U_0V_Y 0_YV 0.UF 0% 0.UF 0% R0 _F 00 _0VRUN _VRUN _VRUN m for all VU_ In non Intel MT systems, these rails should be powered at a minimun in 0-state since PI functionality is power from these wells. _0VRUN VRUN VRUN VLW VLW 0/ F suggest VL_ may connect to VRUN, due to no imt implemented. HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( POWR) / ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

38 U V[00] V[0] V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[] 0 V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[00] V[] V[0] V[] V[0] V[0] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] F V[0] V[] F V[00] V[] F V[0] V[] F V[0] V[0] F V[0] V[] V[0] V[] V[0] V[] H0 V[0] V[] H V[0] V[] H V[0] V[] H V[0] V[] H V[00] V[] F V[0] V[] H V[0] V[0] H V[0] V[] H V[0] V[] H V[0] V[] H V[0] V[] H V[0] V[] J V[0] V[] V[0] V[] V[00] V[] V[0] V[] V[0] V[0] 0 V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[00] V[] V[0] V[] V[0] V[0] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] F V[0] V[] V[00] V[] F V[0] V[] F V[0] V[0] F V[0] V[] V[0] V[] V[0] V[] 0 V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[00] V[] V[0] V[] V[0] V[0] H V[0] V[] H V[0] V[] H V[0] V[] H V[0] V[] H V[0] J V[0] V_NTF[0] J V[0] V_NTF[0] J V[00] V_NTF[0] J V[0] V_NTF[0] J V[0] V_NTF[0] J V[0] V_NTF[0] K V[0] V_NTF[0] K V[0] V_NTF[0] K V[0] V_NTF[0] K V[0] V_NTF[0] K V[0] V_NTF[] V_NTF[] IHM-QM_ K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y U W H H J J J J HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M(N) / ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

39 MFIX MFIX VU 0R-00MHZ_00 LM0000 V LN V LN 0.U_0V_K 00_XR U_V_M 0_XR VRUN R 0_J 00 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0 0.U_0V_K 00_XR VP_T VP_LK 0.U_0V_K 00_XR 0.U_0V_K 00_XR TRL_ V LN R.K_J 00 b e c Q PT null 0.U_V_M_ 00 0U_0V_M 00_XR _V_V_LN.K_J 00 VP_LK VP_T R R.K_J 00 L V N U 0 WP PROM_TOP-_K T0-0TU-. 0.U_0V_K 00_XR _V_V_LN V LN LN_RXP LN_RXN 0.U_V_Y_Y 00 LN_RXP_ 0.U_V_Y_Y 00 LN_RXN_ LN_TXN 0 U TX_P TX_N N N RX_N V VMIN_VLL TTMO VO_TTL V N N VP_T VO_TTL 0 V VP_LK PI_LK PI_ PI_I PI_O V N MIN[] MIP[] N V 0 _V_V_LN MI- MI 0U_.V_Y_Y 00 U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K lose to chip 00_XR 0.U_.V_K 00_XR LN_TXP RX_P MIN[] MI- LK_PI_LN RFLKP MIP[] MI LK_PI_LN# RFLKN N V LN 0 N V L_Tn L_LINK0/00n VO_TTL 0 N V V MIN[] MIP[] 0 MI- MI TRL_ R0.K_J 00 b e c 0.U_V_M_ Q0 PT null 00 0U_0V_M 00_XR _V_V_LN L_LINK000n V V LN L_LINKn N thermal pad VO_TTL V TRL TRL RTn/TTPT WKn V VH(.V) WITH_VUX 0 LOM_ILn WITH_V VUX_VLL V XTLO XTLI RT MIN[0] MIP[0] 0-0-NNP_0 MI0- MI0 Y XTLI XTLO 0 0U_0V_M 00_XR U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00_XR TRL_ TRL_ V LN R 0_J 00 XTLI_hip R.K_F 00 R 0_J 00 XTLI P_0V_J 00_NPO MHZ_0P_0PPM ITTI_L P_0V_J 00_NPO lose to chip,,,,0,,,,,0 PLT_RT#,,0 PI_WK#.K_J R 00 XTLO _V_V_LN L _V_V_LN_ 0R-00MHZ_00 M P_V_K 00_XR 0 0 dd test point for FT Lan test MI MI- MI MI- MI MI- MI0 MI0- R._F 00 R._F 00 R._F 00 R._F 00 R._F 00 R._F 00 R0._F 00 R._F 00 0.U_0V_K 0.U_0V_K 0.U_0V_K 0.U_0V_K 00_XR 00_XR 00_XR 00_XR 0 L TT MT T MX T- MX- TT MT T MX T- MX- TT MT T MX T- MX- TT MT T MX T- MX- :_0UH 0 TR0P_RJ TR0N_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ R0 _J 00 R _J 00 R _J 00 R _J 00 N_TR 00P_KV_K 0_XR FT Test Pad TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TRN_RJ TP0 tpct_00 TRP_RJ TP0 tpct_00 TR0N_RJ TP00 tpct_00 TR0P_RJ TP0 tpct_ U_V_Y_Y 0 0.U_V_Y_Y 0 0.U_V_Y_Y The Resistors and apacitors as close to LN ontroller as possible 0 0.U_V_Y_Y 0 N0 HR_P FOX_H0 TRN_RJ TRP_RJ TRN_RJ TRP_RJ TRN_RJ TRP_RJ TR0N_RJ TR0P_RJ 00P_KV_K 0_XR R M_F 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision LN N_TR ize ocument Number Rev (M0--0 )Mainoard (MX-) Thursday, May 0, 00 ate: heet of

40 V R 00K_J 00 LIIN#,, INT_RIRQ INT_RIRQ LP_FRM# RIRQ XIO#/PIO RT_IR_, LP_FRM# LP_0 LFRM# XIO#/PIO, LP_0 YTM_I0 LP_ L0 XIO#/PIO 0MIL TP0 YTM_I0, LP_ YTM_I RP LP_ L XIO#/PIO, LP_ YTM_I LP_ L XIO#/PIO, LP_ 0 YTM_I 0K RP RP LK_KPI L XIO#/PIO LK_KPI YTM_I VLW 0K 0K PM_LKRUN# LLK XIO#/PIO,,, PM_LKRUN# YTM_I 00_PR 00_PR 00_PR U_PWR_0M LKRUN#/PIO0 XIOF#/PIOF 0,, U_PWR_0M LK_M PIO0 XIO_F[..0] N XIO_F0 KO0 LK_M LK_KM LK_TP PLT_RT# 0 R.K_J 00 TP,,,,,,,,,0 PLT_RT# XIO_F KI0 T_M T_KM T_TP _RIN# LRT#/PIO MFIX tpct_00 XIO_F T_M KI KO _RIN# _0T KRT#/PIO0 TP _0T XIO_F KI PWR RUNTIM_I# 0/PIO0 R.K_J 00 tpct_00 R 00K_J 00 RUNTIM_I# XIO_F KO0 KO PM_LP_# RT# I# TP R 00K_J 00,0 RT# XIO_F KO PM_LP_# RT# 0 tpct_00 R 00K_J 00 XIO_F KO KO PM_LP_# TP R 00K_J 00 XIO_F KI RUN_ON KI0 tpct_00 R 00K_J 00 KI0 XIO_F KO KO U_ON KI KI KI0/PIK0 TP R 00K_J 00 XIO_F KO _PIO KI KI KI/PIK tpct_00 R0 00K_J 00 XIO_F0 KO KO TP RUN_ON KI KI KI/PIK 0 R 00K_J 00 XIO_F KO tpct_00 XIO_F R 00K_J 00 KI KI/PIK XIO_F KO KO KI KI KI/PIK 0 TP XIO_F KO KI RUN_ON KI KI/PIK tpct_00 R0 00K_J 00 XIO_F KI KO KI KI KI/PIK TP XIO_F KO KI 0 KI/PIK 0 0 tpct_00 XIO_F KI KO KO0 TP XIO_F KI V KO KO0/POK0 tpct_00 R00.K_J 00 XIO_F KO0 R 0 KO KO/POK 0 XIO_F KI, PWRW# PWRW# KO KO/POK 0 R K_J 00 _PIO LW_ON,, KO KO KO KO/POK 0/PIO 0 TP XIO_F[..0] KO KO KO/POK tpct_ U_V_Y_Y 00 XIO_F0 For version KO KI KO KO/POK 0 TP 0_J XIO_F signal "IPN_TP" KO KO KO/POK tpct_00 00 XIO_F KO KI TP0 KO KO/POK 0 XIO_F use MFIX tpct_00 KO KO/POK XIO_F V VLW R0 0K_J 00 0 KO0 KO0 KO/POK TP XIO_F VLW KO KO0/POK0 tpct_00 XIO_F KI KO KO/POK TP XIO_F KO KO/POK FP ONN_P tpct_00 R0 FR# FR# KO KO KO/POK R# 0 FOX_0-000-F TP FWR# FWR# XIO_F TT_PR# TT_PR_# KO KO KO/POK WR# tpct_00 IO# KO 0MIL TP KO KO KO/POK IO# K_J 00 TP MM# K NN MM# KO KO KO/POK MM# tpct_00 XIO_F KO KO/POK R0 TP M_THRM_LK M_THRM_LK,0 00 L K_J 00 tpct_00 Q M_THRM_T KO VLW M_THRM_T,0 UNOK_RQ# PWU0 TP0 N00W--F LK_M XT_V_N XT_V_N PWU L tpct_00 KO T_M PORT_T# PWU 0 R 00_J 00 TP PM_THRM# 0 R 00_J 00 tpct_00 R 0K_J 00, LIIN# LIIN# PWU XTMI# XTMI# K_Y_TT# PWU PWM0/POW0 T_WLN_W# WK_I# WK_I# / TT_PR_# PWU PWM/POW R0 0K_J 00 FN_PWM FN_PWM ysi0 "LogoL" definition K_Y_I0# PWU PWU/TIN PWM/POW/FNPWM.elete Mute_L net, INV_NL PWU/TIN/FNF PWM/POW 0MIL TP0 00 nable : YTM_I0 is Low R 0K_J 00 R 0_J 00 _OFF T_00 LK_M PWM/POW isable : YTM_I0 is High 0 dd test point for PIO R K_J 00 T_M PLK PWM/POW 0MIL TP0 IMVP_VR_ON IMVP_VR_ON H(NVP) M(NVMM) L(NVML) LK_00 LK_KM PT PWM/POW 0 LOO_L_N_ VRUN LOO_L_N_ R K_J 00 T_KM PLK PWM/POW/FNPWM ysi 0 00_RT# LK_TP LK_TP PT R 00K_J 00 T_TP T_TP PLK FN_TH FN_TH ysi 0 PORT_T# PT FNF/TOUT/PIO 0/PI0, IMVP_PWR T_PR# /PI W_IR0 000P_0V_K N_000P_0V_K M0, LW_PWR R0 0 /PI 0_J 00 P_L# PWR /PI PLOK#/PIO 00_XR 00_XR ysi 0 Q K_Y_TT# /PI FNLOK#/PIO /PI ROLLLOK#/PIO0F 0MIL TP0 N00W--F ROLL_LOK_L# PWR_IR# NUM_LOK_L# ysi 0 R N_0_J 00 K_Y_I0# /PI NUMLOK#/PIO /PI 00_RT# 00_RT# ysi PIO0 0/PO0 / 0 N_XT_V_N UPN_L PIO0 /PO 00 UPN_L /W request MUT function change,0 R_LRT# POWR_L POWR_L from PIO to Keyboard matris TP MIL TOUT/PIOF /PO 0 TTRY HRIN L# TTRY HRIN L# 0/0 PIO0 /PO 0 00 (el R0 &MUT_W# on pin and ), IMVP_OK R 0_J 00 VIT_MUT# RUN_ON PIO0/FNPWM/TT_TP /PO R N_0_J VLW.dd ystem _I0 pull hign resistor. RUN_ON PIO0/FNF/PLL_TP /PO WLN_N 0MIL TP0.change ystem I/ resistor value 0 T_ON, T_00 T_00 PIO0 /PO 0/0 HW_POP_MUT_ LK_00 PIO0 /PO LK_00 elete ystem _I0 pull hign resistor. PIO0,, OVT_# R 0_J 00 PIO0 IT0/PIO00 PWRLIMIT# NVP_00K_J NVMM_00K_J 0 R 0_J 00 YTM_I VLW OVT_FX# 0 PM_LP_# PM_LP_# PIO IT/PIO0 R 00 R0 00 RX RX NVML_00K_J PM_LP_# PM_LP_# PIO RX/PIO 0 TX TX R 00 PM_LP_# PM_LP_# PIO TX/PIO 0 0 FTUR_RT# FTUR_RT# PM_RMRT# PM_RMRT# PIO #/PIO0 0 NVP_00K_J R NH# NH_# R_PWR R_PWR PIO 00 0 NVMM_00K_J NVML_00K_J PIO KXLKO R YTM_I 0 RUN_ON 0_J 00 R 00 W_IR00 PIO XLKO 0 R 00 W_IR00 RUN_PWR RUN_PWR PIO R YTM_I Q U_ON PIO 00K_J 00 R N_00K_J 00,, U_ON N00W--F NH_# PIO KXLKI YTM_I IN_ PIO XLKI R R 00K_J 00 R N_00K_J 00 VLW RUN_ON PIO R0 YTM_I,0,, RUN_ON N_0M_J 00K_J 00 R PWRTN# PIO N_00K_J 00 R N_0_J 00 PWRTN# PIO 00 Y LO TO HIP HON HI PRIION IN. O., LT..KHZ_.P_0PPM K0F QM00000 FOXONN P - R& ivision, IN IN_ 0 0 P_0V_J_N P_0V_J_N K N00W--F ize ocument Number Rev Q VU VRUN V R 0_J U V N N N N N N N FN_L efinition Hi for FOXONN FN Low for MOR ooling Unit V V V V V V V V N NLO_V U_.V_M_ L 0.U_V_Y_Y 00 0R-00MHZ_00 MMZ00T 0U_.V_Y_Y 00 FOR MI 0.U_V_Y_Y 00 V (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet 0 of R 0.U_V_Y_Y 00 K_J 00

41 0 XIO_F[..0] FLH IO 0 XIO_F[..0] V XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F U 0 V Q0 Q Q Q 0 Q Q Q Q Q 0 Q Q0 Q Q Q Q Q/- # O# N RT# 0 N RY/Y# N W# V YT# V N FLH_TOP-_M NLV00-0TP XIO_F0 XIO_F XIO_F XIO_F XIO_F 0 XIO_F XIO_F XIO_F 0 XIO_F0 MM_M# FR# FLH_RT# FWR# 0 0.U_V_Y_Y 00 0/ hange FR# 0 FWR# 0 U_0V_Y_Y 00 V R 0K_J 00 JI-0 V N MFIX 0/0 elete FWH_INIT# net, ebug card have not use this net LP_0 LP_0,0,0 LP_ LP_ LP_ LP_,0,0 LP_ LP_ LP_FRM# LP_FRM#,0 LP_RQ#0 LP_RQ#0 I_LP_PI# PM_U_TT# 0,,,,,0,,,,0 PLT_RT# PLT_RT# PM_LKRUN# PM_LKRUN#,0, INT_RIRQ INT_RIRQ PLK_JI R,,0, 0, PWRW# N_0_J 00 VRUN 0 VRUN V PI_RT# PI_RT#,, 0 RX RX 0MIL TP 0 TX TX _RT# 0 MFIX MFIX MFIX X-U XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F V XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F MM# FR# FWR# R_INRT _OUT V _OUT N TO ONN_x0P FOX_QT00-L0-F MFIX MFIX NPTH NPTH MFIX MFIX U 0 0.U_V_Y_Y U_V_Y_Y 00 TO ONN_xP FOX_QT00-L0-F R_INRT 0 R 0K_J 00 MM# MM# MM_M# NHVR R N_0_J 00 0/ t M0 MP don't use X-U N,U,R,0 need N R need stuff HON HI PRIION IN. O., LT. FOXONN P - R& ivision Flash ROM Jig-0 XU ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

42 VRUN 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 VRUN VRUN T_TXP T_TXN T_RXN T_RXP T_TXP0 T_TXN0 T_RXN0 T_RXP NPTH MFIX MFIX N MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX MFIX0 NPTH 0 FF ONN_P FOX_-00-F HON HI PRIION IN. O., LT. FOXONN P - R& ivision T H RI ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

43 / MOR side suggest IRQ and IORY pin add pull up resistance by VRUN (N: R and R) Refer to M0 schematics. I_P[0..] I_P[0..] VRUN VRUN VRUN VRUN -ROM ONN O must Master H: lave L: Master VRUN R.K_J 00 R N_.K_J 00 R.K_J 00 0.U_0V_Y_Y U_V_Y_Y 00 I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW# I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW#,,,,,0,,,,0 PLT_RT# 0 O_N_ I_P0 I_P I_P I_P I_P I_P I_P I_P O_RT# O_N_ L O_N_ I_P# I_P TP_PI IO# I_PK# I_PIOR# I_PRQ I_P I_P I_P I_P I_P I_P0 I_P I_P I_P# I_P I_PK# I_PIOR# I_PRQ I_P I_P I_P I_P I_P I_P0 TP_PI N_0.U_V_Y_Y 00 R 0_J 00 TP0MIL N_ L N_ N_ V_ V_ P# FX# 0 INTRQ IORY IOW# N_ 0 RT# UIO_N UIO_L PTH_ NPTH PTH_ NPTH N_ 0 N_ N_ N_ V_ V_ 0 V_ FX# PI# IO# 0 MK# N_ IOR# MRQ N_ UIO_R VR VR 0.U_V_Y_Y 00 00P_0V_K 00_NPO 0 N_0.U_V_Y_Y 00 R 0K_J 00 VR VR R0 _J 00 VR 0 0 N_0.U_V_Y_Y N_0.U_V_Y_Y N FOX_QTH00-HR-F TO ONN_0P VR R N_.K_J P_0V_M_ 00 VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR N_VPORT0000MV0_VR HON HI PRIION IN. O., LT. FOXONN P - R& ivision PT -ROM ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

44 U, PI_[..0], PI_/#0, PI_/#, PI_/#, PI_/#, PI_PR PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_/#0 PI_/# PI_/# PI_/# R P U V W R0 U0 V0 R U V W V U R W W T T R P R R P N N N M M M M M W0 V U P U /0# /# /# /# PR PI interface Multifunction and Miscellaneous RI_OUT#/PM# MFUN0 MFUN MFUN MFUN MFUN MFUN MFUN _U_N# LK_ TT0 PHY_TT_M UPN# PKROUT L H H H J J J 0 F P P J H TP MIL NONTN PI R 0K_J 00 PI PI R0 0K_J 00 R K_F 00 R.K_J 00 VRUN PI_PM#, INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_RIRQ,0, M_PWR_TRL_ M_PWR_TRL_M PM_LKRUN#,,0, LK_ VRUN _PKOUT# PI_,, PI_RT#, PI_FRM#, PI_TRY#, PI_IRY#, PI_TOP#, PI_VL# PI R 00_J 00, PI_PRR#, PI_RR# PI_RQ#0 PI_NT#0 PLK_ NONTN R 0_J 00 R W V V U N R W L L L K K FRM# TRY# IRY# TOP# VL# IL PRR# RR# RQ# NT# PLK PRT# RT# lamp Voltage VP For PI VP (IO V/.V) VR_N# (IN.V/0m) VR_PORT VR_PORT P W K K K PI PI VRPORT 0.U_.V_K 00_XR 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_.V_K 00_XR VRUN 0U_0V_Y 0_YV PIZHK PI R K_J 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision PI (PI U) ize ocument Number Rev ustom (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

45 VRUN _V _V L 0-00MHZ_00 LMN VRUN L 0R-00MHZ_00 M00 PI U P V P V (.V) U V U VPLL_ P R R K_J 00 PI 0U_0V_Y 0_YV 000P_0V_M_ 00 ilink ONN. 0U_0V_Y 0_YV This capacitor must be placed to I pin 000P_0V_M_ 00 ILINK U_V_Y_Y _L _ OTH R.K_F 00 OTH P T T TP0P TP0N TP0P VPLL_ TP0N L R0 R I a TPI0 TPP TPN TPP TPN V NONTN TP MIL W NONTN TP MIL V PI R0 K_J 00 W PI R K_J N_0P_0V_J_N R._F 00 R._F U_V_K_ R R._F._F OTH 00 R.K_F 00 0P_0V_J_N L TP TP- TP V TP0 W TP0- V TP0 W TP0- R TPI0 TP- 0R-00MHZ_0R.0x.x. Place near PI. PTH TP0 TP0# TP0 TP0# PTH N RPTL ONN_P FOX_UV-WRP-F R R U U VPLL N N N TPI XO XI W R R PI PI PI 0.U_V_Y_Y 00 R 0_J 00 PI0 R M_J 00 Y P_0V_J_N P_0V_J_N PIZHK.MHZ_P_0PPM ITTI_L00-.- VRUN R.K_J 00 _L _ R.K_J 00 0.U_V_Y_Y 00 U V WP L 0 V PROM_OP-_x HTL0 L: R/W H: Read only HON HI PRIION IN. O., LT. FOXONN P - R& ivision PI ( ILINK) ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

46 VRUN 000P_0V_K_ P_0V_K_ 00 U F V F V F V F V J V J V L V L V P V P V0 P0 V POWR UPPLY (.V) M_PWR_TRL_0 M_PWR_TRL_/M_R/# _# _LK/M_R# F M_PWR_TRL _PWR_TRL _# FIN _LK R 00 _J V_TRL ONN. _WP _# _T _T0 0_J R 00 0_J R 00 _LK _M _T 0_J R _T 0_J R _J R 00 _R _R _R _R _R N WP OM 0 T T0 V LK V V M /T T NPTH NPTH OM Write Protect ard etect T T0 V LK V V M /T T ase F F0 F H K K M N P P /MM/Memory tick/pro/mart Media/X N N N N N N N N N N0 N M_LK/_LK/M_L_WP# _M/M_L _T0/M T/M T/M T/M_ M_IO(T0)/_T0/M_0 M_T/_T/M_ M_T/_T/M_ M_T/_T/M WP/M_# M_# M_L X_#/M_PHY_WP# M_# M_/_M/M_W# RV0 RV RV RV RV RV RV RV RV F F F FIN M_LK R _J 00 _M _T0 _T _T _T M_IO_T0 M_T M_T M_T _WP M0 TP0 MIL M0 TP MIL M0 TP MIL M_# M_ V_TRLM M_ M_R M_T 0_J R 00 M_R M_IO_T0 0_J R 00 M_R M_T 0_J R 00 M_R M_# 0_J R 00 M_T M_R M_LK 0_J R 00 H_M_TOUT H_M_YN H_M_TIN H_M_RT# M T/UO ONN. M ONN. N N N T_OUT N YN T_IN RT# N N NPTH NPTH 0 ocket_p MOLX_-000 N V T T0 T IN T LK V 0 V Pin efine for M T0M M M M M NPTH NPTH M R O_0P YMIHI_J N N R R.V N N 0 ITLK N0 TO PLU ONN_P FOX_QT0-0-F / hange Net name to H_M_* VRUN 00 0.U_V_Y_Y R0 0 N J 00 H_M_ITLK N_P_0V_K_N 00 PIZHK VRUN VRUN 00 M_PWR_TRL 0U_0V_Y 0_YV R0 U N OUT IN OUT IN OUT N O# TP0 V_TRLM 0//0 PVT hange M Power switch to TP0 R 00K_J 00 0.U_V_Y_Y 00.U_0V_Y 00_YV VRUN _PWR_TRL 0U_0V_Y 0_YV R0 U N OUT IN OUT IN OUT N O# TP0 V_TRL R00 00K_J 00 0.U_V_Y_Y 00.U_0V_Y 00_YV M_# 000P_0V_K_ 00 R.K_J 00 _# K_J 00 K_J 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision PI (M-UO/M) ize ocument Number Rev (M0--0 )Mainoard (MX-) U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0U_.V_M 00_XR 0.U_V_Y_Y 00 R.K_J P_0V_K_ 00 R.K_J 00 _WP 000P_0V_K_ 00 ate: Thursday, May 0, 00 heet of

47 PMI ONN. V V U / V / J V FRM#/ TRY#/ lamp Voltage 0.U_V_Y_Y VL#/ For P R TOP#/0 00 (IO V/.V) LOK#/ RV/ / LK/ IRY#/ PRR#/ PR/ /#/ / /0 / /#/ / 0/ / / / / / /0 / RV/ / / / /0 0/ / / / / / 0/ RV/ / /0 /IOR# /IOWR# /O# NT#/W# 0/# /0#/# /#/R# RT#/RT RR#/WIT# LKRUN#/WP(IOI#) U N INT#/RY(IRQ#) V N UIO/V(PKR#) W N TH/V(TH#/RI#) N V/V# V/V# #/# #/# RQ#/INPK# erial / Parallel T/V/VPP P ard Power witchlth/v/vpp0 LOK/V/V0# RV/V0/V# PIZHK ard U / -it P ard Interface F F H H H F F H K L J H L M M N N 0 0 L M M N P 0 F J J K K L N _R _R _R _R _R _R0 _R _R _R _LK _R _R _R _R _R _R0 _R _R _R _R _R _R _R _R _R _R0 _T _T _T _T _T _T0 _T _T _T _T _T _T _T _T _T _T0 IOR# IOWR# O# W# # # R# RT WIT# IOI# IRQ# PKR# HT# V V # # INPK# TP_T TP_LTH TP_LOK R _J 00 NONTN _R VRUN R K_J 00 VPP N _R _R / _R / _R FRM/ _R TRY/ 0 _R0 VL/ _R TOP/0 _R LOK/ _R RV/ _R / _R LK/ 0 _R IRY/ _R PRR/ _R PR/ _R // 0 _R0 / _R /0 _R / _R // _R / _R 0/ _R / _R / _R / _R / _R0 / _T /0 _T / 0 _T RV/ _T / _T / _T0 / _T /0 _T 0/ _T / _T / _T / _T / _T / _T 0/ _T RV/ _T0 / 0 /0 PMI ONN_xP FOX_WZ--F 0 H0 H H H H H H H H ard U / -it P ard ocket V V VPP VPP N N N N /IOR /IOWR /O NT/W 0/ /0/ //R RT/RT RR/WIT LKRUN/WP INT/RY UIO/V TH/V V/V V/V / / RQ/INPK 0 H H0 H H H H H 0 0.U_V_Y_Y 00 VRUN NPTH NPTH IOR# IOWR# O# W# # # R# RT WIT# IOI# IRQ# PKR# HT# V V # # INPK# 00 0.U_V_Y_Y P_0V_M_ VPP U_0V_Y 0_YV 000P_0V_M_ 00 0.U_V_Y_Y 00.U_0V_Y_Y 00 VRUN 0 U_0V_Y 0_YV N_U_0V_Y 0_YV N PTH PTH ard U / -it P ard ocket Housing PTH PTH R U K_x FOX_-MM-F.V/V,0m 0.U_V_Y_Y U_V_Y_Y V.V/V,000m,,,,,0,,,,0 0U_V_Y 0_YV PLT_RT# TP_T TP_LOK TP_LTH THRML_P U V_ N_ V_ N_ T N_ LOK HN# LTH N_0 0 N_ N_ V_ N_ VPP N_ V_ N_ 0 V_ O# N N_ RT#.V TP0PWPR HON HI PRIION IN. O., LT. FOXONN P - R& ivision PI ( PMI) ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

48 VU T_V 0, T_ON U VIN VOUT N # P/F T_V LN_U_0V_Y_Y 00 LN_IT--T- LN_0.U_V_Y_Y LN_.U_0V_Y_Y / New lue tooth module luetooth connector T_V T_V R00 LN_0_J 00 T_ON Q R0 N_00K_J 00 N_TU T_HLK T_PIO R0 N_0_J 00 R0 LN_0K_J VU 00 FOX_QT00-H-F LN_ to _xp 0 T_V_R N LN_0.U_V_Y_Y 00 T_PN_W_L T_PP_W_L T_T T_PIO# 00 LN_0_J R0 L 0 N_0R-00MHZ_0R 00 R0 LN_0_J T_PN_W T_PP_W 0 T_PR# R0 LN_0_J 00 0/0/0 hange N from NI to FOXONN 0/ Waiting conform /0 hange U0 nable from T_ON to T_V U LO Ton Max is 000us U0 U witch Ton Max is ns / hange luetooch circuit Value to LN_* for M0 VT L KU / hange R from K to.k, dd one K pull up resistance T_V R N_.K_J 00 T_ON R LN_0_J 00 U_T_N R N_K_J 00 U_PP U_PP T_PP_W VU U0 O V O N LN_NQ0PW T_ON T_PN_W U_PN LN_0.U_V_Y_Y 00 U_PN To solve U0 enable pin (net name U_T_N)floating during U (T_V from LO )T_ON desable, dd Pull low K(R) at net U_T_N, hange R from 0K to K. HON HI PRIION IN. O., LT. FOXONN P - R& ivision FN/luetooth ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

49 MFIX MFIX MFIX MFIX VU PTH N MFIX PTH MINI PI_P FOX_0_0K_F W F_W_M TP tpct_00 NPTH NPTH T_WLN_W# 0 Mini-PI ard connector N R 0K_J 00 WIRL_HLK T_V WIRL_T R0 LN_0K_J 00 R LN_00K_J 00 R LN_0_J 00 VU T_V T_HLK /0 hange U Power from T_V to VU R N_0_J 00 R LN_0_J 00 U LN_H0W T_T,,0 PI_WK# MINI_RXN MINI_RXP MINI_TXN MINI_TXP MINI_R_T# LK_PI_MINI# LK_PI_MINI TP TP 0MIL 0MIL L_LK_KRON L_T_KRON L_RT_KRON WIRL_T WIRL_HLK R 0_J R 0_J 00 R 0_J 00 NPTH MFIX WK# _V T_T N T_HLK _V LKRQ# RRV N RRV RFLK- RRV RFLK RRV N RRV RRV N RRV W_IL# N PRT# PRn0 _Vaux PRp0 N N _V N RRV PTn0 RRV PTp0 N N0 RRV0 RRVRRV RRV N RRV N RRV L_WLN# RRV N RRV _V RRV N RRV _V MFIX NPTH R 0_J 00 MINI_PI V MINI_PI V MINI_PI_VUX MIL TP 0MIL TP 0MIL TP 0MIL TP 0 0MIL MINI_R L# 0MIL TP0 R 00K_J 00 / hange luetooch circuit Value to LN_* for M0 VT L KU WLN_N 0 PLT_RT#,,,,,0,,,,0 R N_0_J 00 Q N00PT null MINI_R_L# R N_0_J 00 MINI PI_P FOX_0_0N_F WLN_N / -N change N to mount (MOR side command) / hange WLN L control signal from WLN_N to WLN_L_N VU R0 0_J 00 MINI_PI_VUX 0/ F suggest L_K/L_T/L_VRF can be left as N if unused imt. on't need to connect to WLN card. 0.U_V_Y_Y 00 U_0V_Y 0_YV L_LK L_T L_LK L_T R N_0_J 00 R N_0_J L_LK_KRON 00 L_T_KRON VRUN R0 0_J 00 MINI_PI V LINKLRT# LINKLRT# R N_0_J 00 L_RT_KRON 0.U_V_Y_Y 00.U_0V_Y_Y 00 N_U_0V_Y_Y 0 _VRUN R 0_J 00 MINI_PI V 0.U_V_Y_Y 00.U_0V_Y_Y 00 N_U_0V_Y_Y 0 HON HI PRIION IN. O., LT. FOXONN P - R& ivision Mini-PI ard ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

50 XPR ard V_XPR_IN _V_XPR_IN VU PP# PU# V_XPR_IN LKN _V_PI_OUT _V_PI_OUT _VUX_PI_OUT XPR_TY# PRT# XPR_T# XPR_LKN# PLT_RT#,,,,,0,,,, R 0_J 00 U_PWR_0M 0,, R N_0_J 00 MOR not agree use N chip for second source hange xpress ard Power witch (U) from N PTF to TI TPPW VU VRUN U _Vin Vin Vin Vin_ UXIN PP# PU# 0 R N_0_J 00 R 0_J 00 N_ N TPPW _Vout Vout Vout Vout_ UXOUT TY# HN# O# 0 PRT# RLKN YRT# 0.U_V_M_ 00 Q N00 VU U XPR_TXP XPR_TXN R N_0R-00MHZ_0R 0_J 00 L0 0 LK_PI_XPR LK_PI_XPR# R 0_J 00,, PI_WK#,,, M_T_U,,, M_LK_U U_PP U_PN R 0_J 00 L N_0R-00MHZ_0R XPR_TXP_R XPR_TXN_R 0 R 0_J 00 XPR_RXP XPR_RXN R N_0_J 00 R N_0_J 00 R 0_J 0 00 LK_PI_XPR_R LK_PI_XPR#_R PP# XPR_LKN# _V_PI_OUT U_PP_R U_PN_R L N_0R-00MHZ_0R R 0_J 00 PRT# _VUX_PI_OUT _V_PI_OUT XPR XPRLK PU# _VU _VRUN _V_XPR_IN 0 0.U_V_M_ 00,0,, RUN_ON PP# _VUX_PI_OUT XPR XPRLK N R0 0_J 00 PTH onstant-voltage _VU VU / Load current test fial,.v transfer.v drop Voltage too large./ hange Q0 from -N-N000 to --T00, hange Q0 Power from _VU to VU PTH XPR R HOUIN_P FOX_X0-T N 0 0 R ONNTOR_P FOX_H0-K 0 R N_0_J 00 R 0_J 00 N_MVHTF XPR_TY# R.K_J 00 R.K_J 00 _VU 0m 0 N_0U_0V_Y 0_YV R N_0_J 00 N_I-T- Q0 N_0U_0V_Y 0_YV R N_00K_J 00 R N_K_J 00 U0 _VU_OPOUT _VU_F OUT V _VU_VR IN- OUT IN IN- N IN N_LMR VU VU R N_K_F 00 _VU_VR R0 N_0K_F 00 VU 0 0.U_V_Y_Y 00 upply Max m _VUX_PI_OUT 0.U_V_Y_Y 00.U_.V_K 00_XR upply Max 00m _V_PI_OUT 0.U_V_Y_Y 00.U_.V_K 00_XR 0U_0V_Y 0_YV upply Max 0m _V_PI_OUT 0.U_V_Y_Y 00 0 N_.U_.V_K 00_XR 0U_0V_Y 0_YV _VU TP0 tpct_00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision XPR R ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet 0 of

51 U connector * VU U_V0 F0 V_._ minim0f- U_PN0 U_PP0 R0 N_0_J 00 L 0R-00MHZ_0R R0 0 N_0_J 00 N L 0R-00MHZ_00 M00 U_V0_F U_V0-_F U_V0_F P U_.V_ TPM 0 0P_0V_K_ 00 V V- V N PTH PTH N U ONN_P FOX_U-0-FR 00 U_V_Y 00_YV U_V_Y_Y N N_RJ 0,0, U_PWR_0M U VIN VOUT N FL# RT0P U_V0 U_O#0 U_V L 0R-00MHZ_00 M00 R N_0_J 00 L U_PN U_PP 0R-00MHZ_0R U_V_Y 00 R0 0 00_YV 0.U_V_Y_Y N_0_J 00 U_PWR_0M U VIN VOUT N FL# RT0P U_V U_O# N N N_RJ P U_.V_ TPM U_V_F U_V-_F U_V_F 0P_0V_K_ 00 V V- V N PTH PTH N U ONN_P FOX_U-0-FR HON HI PRIION IN. O., LT. FOXONN P - R& ivision U.0/OKIN ONN. ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of

52 IR Rreceiver connector U_PP U_PN LN_0_J R 00 L 0 VLW 0mils F LN_V-._0 0L0 00m 00_YV LN_.U_V_Z 00 LN_0.U_V_Y_Y N_0R-00MHZ_0R R LN_0_J 00 VU 0mils 00m VU 0 W_IR00 0 W_IR0 0 FTUR_RT# 0 PWR_IR# F LN_V-._0 0L0 VLW F N_V-0._0 0L0 R LN_00K_J 00 R N_00K_J 00 R N_00K_J 00 R N_00K_J 00 U_V_F U_PP_F U_PN_F 00_YV LN_.U_V_Z IR_LP_VPU IR_LP_PWR 00 LN_0.U_V_Y_Y N 0 IR_LP_P R N_0_J 00 MFIX MFIX LN_HR_P FOX_H RT_IR# 0 RT_IR_ TP tpct_00 Q LN_N00 olve W of instant on latter issue for V->V level shift / FOR NW MK IR module compatily.hange stuff to N:F,R,R,R,. Page PIO0(0),PI() pin swape / hange IR circuit Value to LN_* for M0 VT L KU U_V_F U_PP_F U_PN_F IR_LP_VPU W_IR00 W_IR0 FTUR_RT# PWR_IR# IR_LP_PWR TP tpct_00 TP tpct_00 TP tpct_00 TP0 tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 TP tpct_00 t Only U Internal IR, it's U Power HON HI PRIION IN. O., LT. FOXONN P - R& ivision L/LI W#/Touch P ize ocument Number Rev (M0--0 )Mainoard (MX-) ate: Thursday, May 0, 00 heet of