ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωµάτων

ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωµάτων Χειµερινό Εξάµηνο 2007-2008 υναµικές Μνήµες -DRAM ΗΥ220 - Βασίλης Παπαευσταθίου 1

Βασικό Block Diagram Υποσυστηµάτων Μνήµης Word Line Address Decoder Memory cell 2 n word lines n Address Bits RAM/ROM ονοµατολογία: m Bit Lines 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words ΗΥ220 - Βασίλης Παπαευσταθίου 2

Κελί µνήµης µε 1 transistor (DRAM) Εγγραφή -Write: 1. Οδηγούµε τηνbit line 2. Επιλέγουµε γραµµή (row select) Ανάγνωση -Read: 1. Προφορτίζουµε (precharge) την bit line σε Vdd/2 2. Επιλέγουµε γραµµή (row select) 3. Το κελί και η bit line µοιράζονται τα φορτία (charge sharing) 4. Sense στην bit line (sense amplifier) Μπορεί να ανιχνεύει πολύ µικρές αλλαγές 5. Write: επαναφέρουµε τηντιµή Ανανέωση Refresh: Αρκεί ένα απλό read σε κάθε κελί bit row select ΗΥ220 - Βασίλης Παπαευσταθίου 3

Κλασσική Οργάνωση DRAM (τετραγωνική) bit (data) lines r o w d e c o d e r RAM Cell Array Each intersection represents a 1-T DRAM Cell Square keeps the wires short: Power and speed advantages Less RC, faster precharge and discharge is faster access time! word (row) select row address Column Selector & I/O Circuits data Column Address Row and Column Address together select 1 bit a time ΗΥ220 - Βασίλης Παπαευσταθίου 4

Λογική Οργάνωση DRAM (4 Mbit) 4 Mbit = 22 address bits 11 row address bits 11 col address bits A0 A10 11 R O W D E C O D E R 11 Square root of bits per RAS/CAS Column Decoder Sense Amps & I/O Memory Array (2,048 x 2,048) Storage Cell Word Line Row selects 1 row of 2048 bits from 2048 rows Col selects 1 bit out of 2048 bits in such a row ΗΥ220 - Βασίλης Παπαευσταθίου 5

Τα σήµατα της DRAM RAS_L CAS_L WE_L OE_L A 256K x 8 9 DRAM 8 D Σήµατα ελέγχου (RAS_L, CAS_L, WE_L, OE_L) όλα active low Κοινό bus δεδοµένων D - εισόδου κα ι εξόδου (Din & Dout): WE_L ενεργοποιείται (Low), OE_L απενεργοποιείται (High) D χρησιµοποιέιται σαν είσοδος στην DRAM WE_L απενεργοποιείται (High), OE_L ενεργοποιείται (Low) D χρησιµοποιέιται σαν έξοδος από την DRAM Οι διευθύνσεις γραµµής και στήλης µοιράζονται τα ίδια pins (A) RAS_L ενεργοποιείται (low) -> A αποθηκεύεται σαν row address CAS_L ενεργοποιείται (low) -> A αποθηκεύεται σαν column address RAS/CAS edge-sensitive ΗΥ220 - Βασίλης Παπαευσταθίου 6

Απλοποιηµένο διάγραµµα χρονισµού DRAM Read Write Η διεύθυνση δίνεται σε 2 βήµατα ΗΥ220 - Βασίλης Παπαευσταθίου 7

Τυπικός χρονισµός Ανάγνωσης DRAM Κάθε προσπέλαση DRAM ξεκινάει µε: RAS_L CAS_L WE_L OE_L Ενεργοποίηση του RAS_L 2 τρόποι ανάγνωση: early or late A 256K x 8 9 DRAM 8 D DRAM Read Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address Col Address Junk WE_L OE_L D High Z Junk Data Out High Z Data Out Setup Hold Read Access Time Output Enable Delay Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L ΗΥ220 - Βασίλης Παπαευσταθίου 8

Τα βήµατα για Early Read Assert Row Address Assert RAS_L Start read cycle Meet Row Addr setup time before RAS/hold time after RAS Assert OE_L Assert Col Address Assert CAS_L Meet Col Addr setup time before CAS/hold time after CAS Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle ΗΥ220 - Βασίλης Παπαευσταθίου 9

Τα βήµατα για Late Read Assert Row Address Assert RAS_L Start read cycle Meet Row Addr setup time before RAS/hold time after RAS Assert Col Address Assert CAS_L Meet Col Addr setup time before CAS/hold time after CAS Assert OE_L Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle ΗΥ220 - Βασίλης Παπαευσταθίου 10

Τυπικός χρονισµός Εγγραφής DRAM Κάθε προσπέλαση DRAM ξεκινάει µε: RAS_L CAS_L WE_L OE_L Ενεργοποίηση του RAS_L 2 τρόποι εγγραφής: early or late A 256K x 8 9 DRAM 8 D DRAM WR Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address Col Address Junk OE_L WE_L D Junk Data In Junk Data In Junk Setup Hold WR Access Time WR Access Time Early Wr Cycle: WE_L asserted before CAS_L Late Wr Cycle: WE_L asserted after CAS_L ΗΥ220 - Βασίλης Παπαευσταθίου 11

Key DRAM Timing Parameters t RAC : minimum time from RAS line falling to the valid data output. Quoted as the speed of a DRAM A fast 4Mb DRAM t RAC = 60 ns t RC : minimum time from the start of one row access to the start of the next. t RC = 110 ns for a 4Mbit DRAM with a t RAC of 60 ns t CAC : minimum time from CAS line falling to valid data output. 15 ns for a 4Mbit DRAM with a t RAC of 60 ns t PC : minimum time from the start of one column access to the start of the next. 35 ns for a 4Mbit DRAM with a t RAC of 60 ns ΗΥ220 - Βασίλης Παπαευσταθίου 12

SRAM (lower density, higher speed) used in CPU register file, on- and off-chip caches. DRAM (higher density, lower speed) used in main memory Closing the GAP: 1. Caches are growing in size. Memory in Desktop Computer Systems: 2. Innovation targeted towards higher bandwidth for memory systems: SDRAM - synchronous DRAM RDRAM - Rambus DRAM EDORAM - extended data out SRAM multibank DRAM ΗΥ220 - Βασίλης Παπαευσταθίου 13

DRAM with Column buffer A0 A10 R O W D E C O D E R 11 Memory Array (2,048 x 2,048) Word Line Storage Cell Sense Amps Column Latches MUX Pull column into fast buffer storage Access sequence of bit from there ΗΥ220 - Βασίλης Παπαευσταθίου 14

Optimized Access to Cols in Row Often want to access a sequence of bits Page mode After RAS / CAS, can access additional bits in the row by changing column address and strobing CAS Static Column mode Change column address (without repeated CAS) to get different bit Nibble mode Pulsing CAS gives next bit mod 4 Video ram Serial access ΗΥ220 - Βασίλης Παπαευσταθίου 15

More recent DRAM enhancements EDO - extended data out (similar to fast-page mode) RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns) Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) SDRAM - synchronous DRAM clocked interface uses dual banks internally. Start access in one bank then next, then receive data from first then second. DDR - Double data rate SDRAM Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). RDRAM - Rambus DRAM Entire data blocks are access and transferred out on a high-speed buslike interface (500 MB/s, 1.6 GB/s) Tricky system level design. More expensive memory chips. ΗΥ220 - Βασίλης Παπαευσταθίου 16

256 Mbit SDRAM Addressing ΗΥ220 - Βασίλης Παπαευσταθίου 17

Functional Block Diagram 8 Meg x 16 SDRAM ΗΥ220 - Βασίλης Παπαευσταθίου 18

SDRAM Details Multiple banks of cell arrays are used to reduce access time: Each bank is 4K rows by 512 columns by 16 bits (for our part) Read and Write operations as split into RAS (row access) followed by CAS (column access) These operations are controlled by sending commands Commands are sent using the RAS, CAS, CS, & WE pins. Address pins are time multiplexed During RAS operation, address lines select the bank and row During CAS operation, address lines select the column. ACTIVE command opens a row for operation transfers the contents of the entire to a row buffer Subsequent READ or WRITE commands modify the contents of the row buffer. For burst reads and writes during READ or WRITE the starting address of the block is supplied. Burst length is programmable as 1, 2, 4, 8 or a full page (entire row) with a burst terminate option. Special commands are used for initialization (burst options etc.) A burst operation takes 4 + n cycles (for n words) ΗΥ220 - Βασίλης Παπαευσταθίου 19

Mode Register ΗΥ220 - Βασίλης Παπαευσταθίου 20

Command Truth Table ΗΥ220 - Βασίλης Παπαευσταθίου 21

Βασικές Χρονικές Παράµετροι SDRAM t RCD : ACTIVE to READ or WRITE delay CL : CAS Latency t RAS : ACTIVE to PRECHARGE time t RP t WR t RC : PRECHARGE Period : WRITE recovery time : ACTIVE to ACTIVE time ΗΥ220 - Βασίλης Παπαευσταθίου 22

READ burst (with auto precharge) ΗΥ220 - Βασίλης Παπαευσταθίου 23

WRITE burst (with auto precharge) ΗΥ220 - Βασίλης Παπαευσταθίου 24

DDR Read Command (with auto precharge) ΗΥ220 - Βασίλης Παπαευσταθίου 25

DDR Read Command (without auto precharge) ΗΥ220 - Βασίλης Παπαευσταθίου 26

DDR: Consecutive Read Bursts ΗΥ220 - Βασίλης Παπαευσταθίου 27

DDR Write Command (without auto precharge) ΗΥ220 - Βασίλης Παπαευσταθίου 28

DDR: Read Burst Stop - Write ΗΥ220 - Βασίλης Παπαευσταθίου 29

Auto Refresh One autorefresh command every 70us : once every 7000 cycles at 100Mhz ΗΥ220 - Βασίλης Παπαευσταθίου 30

Volatile Memory Comparison The primary difference between different memory types is the bit cell. SRAM Cell DRAM Cell addr word line word line bit line data Larger cell lower density, higher cost/bit No dissipation Read non-destructive No refresh required bit line Simple read faster access Standard IC process natural for integration with logic bit line Smaller cell higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read longer access time Special IC process difficult to integrate with logic circuits Density impacts addressing ΗΥ220 - Βασίλης Παπαευσταθίου 31

SDRAM Recap General Characteristics Optimized for high density and therefore low cost/bit Special fabrication process DRAM rarely merged with logic circuits. Needs periodic refresh (in most applications) Relatively slow because: High capacity leads to large cell arrays with high word- and bitline capacitance Complex read/write cycle. Read needs precharge and writeback bit line word line DRAM bit cell Multiple clock cycles per read or write access Multiple reads and writes are often grouped together to amortize overhead. Referred to as bursting. ΗΥ220 - Βασίλης Παπαευσταθίου 32