M3 System Block Diagram

M System lock iagram M/ M socket LE Panel L Panel (LVS) R-SOMM & R-SOMM & LOK GEN SLGSP.MHz R 0/ MT/s R 0/ MT/s PU M thlon HT-Link N M RS0M PE.0 X 0~ ~ MXM.0 Type MUX PPE - MUX PPE - UM_P UM_P UM_LVS MXM_LVS MXM_P MXM_P L Panel (P) Scalar oard ST Mars R laster.khz ST Gen ST Gen LP MHz -Link S M S0M.KHz P-E_N US.0 P-E_S R laster MHz Rear /O oard O board PWR TN O Eject R oard Mic Quanta omputer nc. PROJET : ZN Size ocument Number Rev System lock iagram Monday, March, 00 ate: Sheet of

LK_GEN_SLGSP V LK_V V. LK_VO L0 L K0HS00 U/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ K0HS00 U/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. Place within 0." of LKGEN U0 - R */F_ V LK_V_US L K0HS00 0.u/0V_ 0uF_00 LK_V U/.V_ 0 VOT VSR VTG VS_SR VST VPU VHTT VREF V 0 PUK_0T PUK_0 0 TG0T TG0 TGT TG PULK_R RP PULK#_R NGFX_LK_R RP0 NGFX_LK#_R LK_PE_MXM_R RP LK_PE_MXM#_R 0X 0X 0X NGFX_LK NGFX_LK# LK_MXM LK_MXM# PULK PULK# PULK PULK# NGFX_LK NGFX_LK# LK_MXM LK_MXM# To PU To N 00 Mhz RS0M for VG 00 P P.U_00 G_XN Y.MHZ/0P G_XOUT LK_VO G_XN G_XOUT 0 0 VSR_O0 VSR_O VTG_O VS_SR_O VPU_O OT SR0 SR TG S_SR ST PU HTT REF X X QFN S_SR0T S_SR0 S_SRT S_SR SR0T SR0 0 SRT SR SRT SR SRT SR SRT SR SRT/STT SR/ST SRT/M_SS SR/M_NS LK_SLNK_R RP LK_SLNK#_R SSR_LK_R RP SSR_LK#_R LK_PE_TV_R RP LK_PE_TV#_R LK_PE_WLN_R RP LK_PE_WLN#_R LK_PE_US.0_R RP LK_PE_US.0#_R LK_PE_LOMP_R RP LK_PE_LOMN_R T T 0X 0X 0X 0X 0X 0X LK_SLNK LK_SLNK# SSR_LK SSR_LK# LK_PE_TV LK_PE_TV# LK_PE_WLN LK_PE_WLN# LK_PE_US.0 LK_PE_US.0# LK_PE_LOMP LK_PE_LOMN LK_SLNK LK_SLNK# SSR_LK - SSR_LK# LK_PE_TV LK_PE_TV# LK_PE_WLN LK_PE_WLN# LK_PE_US.0 0 LK_PE_US.0# 0 LK_PE_LOMP 0 LK_PE_LOMN 0 To N To S To LN ontroller To Mini PE Slot(TV) To Mini PE Slot(WLN) To in ontroller To US.0 00 Mhz 00 Mhz,,,,0,,,,,0, PLK_SM PT_SM SMLK SMT HTT0T/M HTT0/M NHT_REFLK_R NHT_REFLK#_R RP0 0X LK_N_HTREF_PR LK_N_HTREF#_PR LK_N_HTREF_PR LK_N_HTREF#_PR To N HT US 00 Mhz LK_V R.K_ LK_P# LK_P# T0 T T T T P# LKREQ0# LKREQ# LKREQ# LKREQ# LKREQ# SLGSP T0 T T T T 0 T T T T T LK_M_US_R MHz_0 SEL_HTT REF0/SEL_HTT SEL_ST REF/SEL_ST SEL_ REF/SEL_ *0p/0V_ *0p/0V_ R _ Ra R0 /F_ R _ R0 LK_M_US EXT_N_OS Rb 0./F_ EXT_S_OS LK_M_US, EXT_N_OS EXT_S_OS To S US To N Mhz LOK NPUT TLE LK_V R *.K_ SEL_ST SEL_HTT SEL_ SEL_HTT SEL_ST SEL_ MHz.V single ended HTT clock 0 * 00 MHz differential HTT clock * 00 MHz non-spreading differential SR clock 0 0* * default 00 MHz spreading differential SR clock MHz and M SS outputs 00 MHz SR clock LOKS HT_REFLKP HT_REFLKN REFLK_P REFLK_N GFX_REFLK GPP_REFLK GPPS_REFLK RS0 00M FF 00M FF M SE (.V) vref 00M FF(N/OUT)* N or 00M FF OUTPUT 00M FF R.K_ R.K_ R0.K_ Quanta omputer nc. PROJET : ZN Size ocument Number Rev lock Generator Monday, March, 00 ate: Sheet of

PU HyperTransport and ebug U HT_LKNP HT_LKNN HT_LKNP0 HT_LKNN0 HT_TLNP HT_TLNN HT_TLNP0 HT_TLNN0 N P N N V V U V HT_NP U HT_NN V HT_NP T HT_NN T HT_NP R HT_NN T HT_NP P HT_NN P HT_NP M HT_NN M HT_NP0 L HT_NN0 M HT_NP K HT_NN K HT_NP J HT_NN K L0_LKN_H L0_LKN_L L0_LKN_H0 L0_LKN_L0 L0_TLN_H L0_TLN_L L0_TLN_H0 L0_TLN_L0 L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H0 L0_N_L0 L0_N_H L0_N_L L0_N_H L0_N_L L0_LKOUT_H L0_LKOUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_TLOUT_H L0_TLOUT_L L0_TLOUT_H0 L0_TLOUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L Y W W W Y Y F E F F H G H H HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP0 HT_OUTN0 HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_LKOUTP HT_LKOUTN HT_LKOUTP0 HT_LKOUTN0 HT_TLOUTP HT_TLOUTN HT_TLOUTP0 HT_TLOUTN0 HT_OUTP[..0] HT_OUTN[..0] HT_LKOUTP[..0] HT_LKOUTN[..0] HT_TLOUTP[..0] HT_TLOUTN[..0] HT_NP[..0] HT_NN[..0] HT_LKNP[..0] HT_LKNN[..0] HT_TLNP[..0] HT_TLNN[..0] HT_OUTP[..0] HT_OUTN[..0] HT_LKOUTP[..0] HT_LKOUTN[..0] HT_TLOUTP[..0] HT_TLOUTN[..0] HT_NP[..0] HT_NN[..0] HT_LKNP[..0] HT_LKNN[..0] HT_TLNP[..0] HT_TLNN[..0] HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP0 HT_NN0 U U R T R R N P L M L L J K J J L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H L0_N_L L0_N_H0 L0_N_L0 HT LNK L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 Y W E E F E G G H G HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP0 HT_OUTN0 M_SOKET.VSUS L M Top View L PU_REQ# PU_RY PU_TK PU_TMS PU_T PU_TRST# PU_TO R 00/F_ R *K/F_ R *K/F_ R R *K/F_ *K/F_ HT onnector N 0 0 PU_LT_HT_RST# KEY SP-00-0 Use buffered reset HT Header V, PU_LT_RST# Open rain - U R0 0 *LV0 R0 *K/F_ PU_LT_HT_RST# Quanta omputer nc. PROJET : ZN Size ocument Number Rev PU HyperTransport and ebug Monday, March, 00 ate: Sheet of 0

E E M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M M M M M M M M M M M M M 0 M M M 0 M M M M M M M M M M M M 0 M M M M 0 MEM_M_EVENT_L M_LK_R#_ M_LK_R_ M_S#_0 M_S#_ M_OT_0 M_OT_ M RST#, M S#, M WE#, M RS#, M_KE_, M_KE_0, M [..0], M [..0],0 M QS#0, M QS0, M QS#, M QS, M QS#, M QS, M QS#, M QS, M QS#, M QS, M QS#, M QS, M QS#, M QS, M QS#, M QS, M QS0,0 M QS#,0 M QS,0 M QS#,0 M QS,0 M QS#,0 M QS,0 M QS#,0 M QS,0 M QS#,0 M QS#0,0 M QS,0 M QS#,0 M QS,0 M QS#,0 M QS,0 M M0, M M, M M, M M, M M, M M, M M, M M, M M0,0 M M,0 M M,0 M M,0 M M,0 M M,0 M M,0 M M,0 M Q[..0], M Q[..0],0 M_LK_R#_0 M_LK_R_0 M_LK_R#_ M_LK_R_ M_LK_R#_ M_LK_R_ M_LK_R#_ M_LK_R_ M_LK_R#_ 0 M_LK_R_ 0 M_LK_R#_0 M_LK_R_0 M_LK_R#_ 0 M_LK_R_ 0 MEM_M_EVENT_L, M_S#_ M_S#_ M_OT_ M_OT_ MEM_M_EVENT_L,0 M 0, M, M, M_S#_ 0 M_S#_ 0 M_OT_ 0 M_OT_ 0 M_S#_0 M_S#_ M RS#,0 M WE#,0 M RST#,0 M 0,0 M,0 M,0 M_KE_,0 M S#,0 M_KE_0,0 M_OT_0 M_OT_.VSUS.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : PU Memory 0 Monday, March, 00 ZN Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : PU Memory 0 Monday, March, 00 ZN Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : PU Memory 0 Monday, March, 00 ZN PU Memory R Memory nterface R Memory nterface Pin naming for memory pins indicate "R"/"R" connections. Pin naming for memory pins indicate "R"/"R" connections. 0 MEM H PU TO MM0 & MM 0 MEM H PU TO MM0 & MM EVENT pins are for future Mr EVENT pins are for future Mr Route as 0 ohms with /0 W/S from PU pins. Route as 0 ohms with /0 W/S from PU pins. T T T T T T T T R K/F R K/F T T T T M_LK_H G M_LK_L G0 M_LK_H G M_LK_L H M_LK_H U M_LK_L V M_LK_H V M_LK_L W M0_S_L M0_S_L0 M0_OT E M0_OT0 M_LK_H E0 M_LK_L E M_LK_H0 G0 M_LK_L0 G M_LK_H U M_LK_L U M_LK_H W M_LK_L W M_S_L M_S_L0 M_OT E M_OT0 M_RESET_L E0 M_S_L M_WE_L M_RS_L M_NK N M_NK Y M_NK0 M_KE L M_KE0 M M_ M M_ N M_ M_ N M_ P M_0 Y M_ N M_ R M_ P M_ R M_ R M_ R M_ T M_ U M_ T M_0 W M_QS_H M_QS_H G M_QS_H G M_QS_H G M_QS_H M_QS_H M_QS_H E M_QS_H0 F M_QS_L E M_QS_L G M_QS_L G M_QS_L G M_QS_L M_QS_L M_QS_L F M_QS_L0 G M_M F M_M F M_M J M_M H M_M M_M E M_M E M_M0 H M_T E M_T G M_T G M_T0 M_T M_T E M_T G M_T E M_T G M_T E M_T M_T G M_T E M_T0 F M_T F M_T E M_T F M_T E M_T J M_T G M_T E M_T G M_T H M_T0 F M_T J M_T J M_T F M_T E M_T J M_T H M_T G M_T F M_T E M_T0 E M_T M_T M_T G M_T F M_T M_T E M_T F M_T E M_T E M_T0 M_T E M_T M_T G M_T F M_T E M_T E M_T F M_T G M_T G M_T0 F M_T G M_T E M_T G M_T E M_T G M_T H M_T H M_T E M_T E M_T0 G M_QS_H J M_QS_L J M_M J M_HEK K M_HEK J M_HEK G M_HEK G M_HEK L M_HEK K M_HEK H M_HEK0 H M_EVENT_L W0 MEM H U M_SOKET MEM H U M_SOKET T T T T M_LK_H J M_LK_L K M_LK_H M_LK_L M_LK_H V M_LK_L W M_LK_H W M_LK_L W M0_S_L E0 M0_S_L0 M0_OT F M0_OT0 M_LK_H L M_LK_L L M_LK_H0 M_LK_L0 M_LK_H U M_LK_L U0 M_LK_H Y M_LK_L Y0 M_S_L E M_S_L0 M_OT G M_OT0 M_RESET_L M_S_L M_WE_L 0 M_RS_L M_NK N M_NK M_NK0 M_KE M M_KE0 M M_ N M_ N M_ E M_ N0 M_ P M_0 M_ P M_ R M_ R M_ R M_ R0 M_ T M_ T M_ U M_ U M_0 0 M_QS_H K M_QS_L J M_QS_H K M_QS_L J M_QS_H K M_QS_L L M_QS_H L M_QS_L L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H0 M_QS_L0 M_M J M_M H M_M J M_M K M_M 0 M_M M_M M_M0 M_T H M_T L M_T L M_T0 J M_T F M_T G M_T L M_T K M_T L M_T L M_T K M_T L M_T H M_T0 J M_T H M_T L0 M_T J M_T L M_T L M_T K M_T J M_T H M_T H M_T0 J M_T L M_T K M_T H M_T G0 M_T L M_T L M_T J0 M_T J M_T E M_T0 E0 M_T M_T M_T F M_T F M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T 0 M_T M_T M_T M_T0 M_T M_T M_T M_T M_T E M_T F M_T M_T M_T M_T0 M_QS_H J M_QS_L J0 M_M J M_HEK K M_HEK K M_HEK G0 M_HEK G M_HEK L M_HEK L M_HEK H M_HEK0 G M_EVENT_L V MEM H U M_SOKET MEM H U M_SOKET T0 T0 T T T0 T0 T T T T T T T T R K/F R K/F T T

PU ontrol and Miscellaneous V PU_PWRG, LT_STOP#, PU_LT_RST# *0P *0P *0P Layout: Keep trace to resistors less than " from PU pins. Layout: Keep PU_HTREF0 less than." from in length. R 0K Q RHU00N0 PU_THERMTRP#.VSUS - R K/F R K/F PULK PULK# PU_M_VREF 0.u/0V 00p 00p SMR_VREF Layout: Place within 00 mils of the PU socket. 000P NEE XR NEE XR R _00F R 0,,,, R 0 R 0 R 0K/F R PU_T PU_TRST# PU_TK PU_TMS PU_REQ# PU_V_F PU_V_F# PU_VO_PWRG R K/F 0/J_ R *K/F PU_M_VREF T T T T T T0 T T T T T Layout: Keep trace to resistors less than " from PU pins. R R./F.F R /F R /F.VSUS PU_LKN_S PU_LKN_S# PU_PWRG LT_STOP# PU_LT_RST# PU_PRESENT# PU_S PU_S PU_S0 PU_LERT# PU_T PU_TRST# PU_TK PU_TMS PU_REQ# PU_V_F PU_V_F# T PU_M_ZN PU_M_ZP PUV PU_VTT_SUS_SENSE PU_TEST_H_YPSSLK_H PU_TEST_H_YPSSLK_L PU_TEST_PLLTEST0 PU_TEST_PLLTEST PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_SNSHFTEN PU_TEST_NLOG_T PU_TEST_ERKMON PU_TEST_GTE0 PU_TEST_RN0 0 0 L L K K L L0 J0 H0 L G G F E F H J 0 0 F0 E J F E F H E J H J 0 F G G H L L Pin naming for V pins indicate "Serial V"/"Parallel V" connections. U V_ V_ LKN_H LKN_L PWROK LTSTOP_L RESET_L PU_PRESENT_L S S S0 LERT_L T TRST_L TK TMS REQ_L V_F_H V_F_L M_VO_PWRG VR_SENSE M_VREF M_ZN M_ZP TEST_H TEST_L TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV RSV RSV RSV MS. ORE_TYPE V V SV/V SV/V PVEN/V V0 THERM THERM THERMTRP_L PROHOT_L NT. MS. TO RY VO_F_H VO_F_L VN_F_H VN_F_L PS_L HTREF HTREF0 TEST_H TEST_L TEST TEST TEST TEST TEST0 TEST_H TEST_L TEST TEST TEST0 TEST RSV RSV0 RSV RSV RSV RSV RSV RSV G E E E G G K L K0 K L G G F V V K H J L J J0 H K K G L0 L E E J J0 K PU_ORE_TYPE PU_V_R PU_V_R PU_SV PU_SV PU_PVEN PU_V0_R PU_THERM PU_THERM PU_THERMTRP#_. PU_PROHOT#_. PU_TO PU_RY PU_VO_F_H PU_VO_F_L PU_VN_F_H PU_VN_F_L PU_PS# PU_HTREF PU_HTREF0 PU_TEST_H_FLKOUT_H PU_TEST_L_FLKOUT_L PU_TEST_SNLK PU_TEST_TSTUP PU_TEST_SNSHFTEN PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_H_PLLHRZ_H PU_TEST_L_PLLHRZ_L PU_TEST_SNGLEHN PU_TEST_URNN_L PU_TEST0_NLOGOUT PU_TEST_G_T PU_VHT R0./F R./F Layout: Keep PU_HTREF0 less than." from in length. R0./F R R R R R K/F *0_ *0_ *0_ 0/J_.VSUS R 0K R 0K R 0 R0 *0./F_ R *0 PU_ORE_TYPE PU_V PU_V PU_SV PU_SV PU_PVEN PU_V0 PU_PROHOT#_. PU_TO PU_RY PU_VO_F_H PU_VO_F_L PU_VN_F_H PU_VN_F_L PS PU_THERMTRP#_. Layout: Route as 0 ohms diff impedance. Keep trace to resistor < " from PU pins. T T T T T0 T T T T T T Layout: Route PU_TEST_H/L as differential traces and as short as possible. M_SOKET V V LMPGSN(0_00M_)_ L 00U/V LS00-00M-N PUV PUV.VSUS K/F_.u/.V_ 0.u/.V_ 00P/0V_ *0U/.V_ R K/F PU_LERT# R MMT0 Q R K/F_ THERM_LERT# MMT0 Q THERM_LERT#, PU Thermal Senser 0.U THERM_V V *0.U sub-address:h U V SMLK 0 SLK V R 0K 0 00P_00 PU_THERM XP SMT ST PU_THERM XN LERT# THERM_LERT#,0, THERM_LK_E V Q RHU00N0 R0.K_ SLK SYS_SHN#_0 R0 0_ reserve for power shutdown ( if can ) *H00H SYS_SHN# N_THERM N_THERM 0 00P_00 XP XN THERM# G SYS_SHN_# V,0, THERM_T_E Q RHU00N0 R0.K_ ST SYS_SHN_# H0H-0PT PWROK_E_0 Q MMT0 R0 0K/F_ PWROK_E,, V Quanta omputer nc. PROJET : ZN Size ocument Number Rev PU ontrol & Misc Monday, March, 00 ate: Sheet of 0

PU_ORE UE PU_ORE UF Processor Power and Ground uf.vsus PU_ORE uf PU_ORE 0 0uF uf uf 0 0uF E E F F G G H H H J J J J J J0 J J K K K K K K K K K L L L L0 L L L L L0 L M M M M M M M M M M M N N0 N N N N N0 N P P P P P P P P P R R R R0 R R R R R0 R T T T T T T 0 uf uf 0 0uF V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ M_SOKET ottom Side ecoupling 0 0uF 0 uf uf POWER/ 0uF uf 0uF 0 0.0U uf 0uF VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ 0.0U uf 0 0uF 0 0 0 0 E F F F F F0 F F F F F0 G G H H0 H H H H H H H H0 J J J J J J J J J J J K K K K0 K K K K K0 K K K K K0 L L L L L L L L L M M0 0.u uf.u 0.u 0 uf 0.U 0pf uf 00.U T T T T T U U0 U U U U U0 U V V V V V V V V W W W W0 W W W W W0 W Y Y Y Y Y Y Y Y Y Y Y 0 0 0 0 E0 E F F F G G G H H uf 0.0U.VR uf V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 0.u 0.0U POWER/ M_SOKET 0.u 0.u 0pf 0.0U VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_00 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 0 0.0U M M M M M0 M N N N N N N N N N N N P P P P0 P P P P P0 P R R R R R R R R R T T0 T T T T T0 T U U U U U U U U U U U V V V0 V V V V V0 V W W W W W W W W W Y Y0 Y Y Y Y Y0 Y NORE 0uF E E0 F F G0 G H0 E 0uF UG VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_0 VN_ VN_ VN_ VN_ NP/RSV NP/VSS NP/VSS M_SOKET NORE 0uF 0 0uF PU_VHT.uF POWER/ PU_VN_RUN.uF 0.u.uF 0.u 0.u VLT_HT_RUN VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_00 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_0 VSS_ VSS_ VSS_ VSS_ 0.u 0pf 0 0 0 0 E E E F F F F0 F F F 0.0U 0pf L PU_VHT.VR.VSUS.VR 0uF M Top View.VR.uF J J J J M M M M0 P P P P0 T T T T0 V V V V0 Y Y Y Y 0 0 F0 PU_VR.uF L.uF PU_VR UH VLT VLT VLT VLT VR_ VR_ VR_ VR_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_0 VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ VO_ M_SOKET 0.0U.uF 0.u POWER/ 0.u PU_VO_SUS.VSUS.uF.VSUS.uF 0.u 0.uF.uF VLT VLT VLT VLT VR_ VR_ VR_ VR_ VR_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ 0.u 0pf 0pf H H H H G H J K L F F0 F F F F G0 G H H H H0 H H H H H0 K K K K K0 K K K K K0 L Layout: Place across each VO- plane split. VLT_HT_RUN_.VR 0 0uF MMs Layout: Place as close as possible to PU socket..vr.uf PU_VR 0.uF.uF.uF Layout: Place behind the MMs, evenly spaced on VTT fill. NORE uf 0 uf 0.0U 0.0U 0pf Size ocument Number Rev PU Power & Quanta omputer nc. PROJET : ZN Monday, March, 00 ate: Sheet of 0

HT_OUTP0 HT_OUTN0 HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP0 HT_OUTN0 HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_OUTP HT_OUTN HT_LKOUTP0 HT_LKOUTN0 HT_LKOUTP HT_LKOUTN HT_TLOUTP0 HT_TLOUTN0 HT_TLOUTP HT_TLOUTN U Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N Y HT_RXP Y HT_RXN W HT_RXP W0 HT_RXN V HT_RXP V0 HT_RXN U0 HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN M HT_RXTL0P M HT_RXTL0N R HT_RXTLP R0 HT_RXTLN HT_TXP F HT_TXN G HT_TXP G0 HT_TXN H HT_TX0P J0 HT_TX0N J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_NP0 HT_NN0 HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP0 HT_NN0 HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_NP HT_NN HT_LKNP0 HT_LKNN0 HT_LKNP HT_LKNN HT_TLNP0 HT_TLNN0 HT_TLNP HT_TLNN R 0/F_ HT_RXLP HT_TXLP R0 0/F_ HT_RXLN HT_RXLP HT_TXLP HT_TXLN HT_RXLN HT_TXLN RS0M HYPER TRNSPORT PU /F HT_TXLK0P H HT_TXLK0N H HT_TXLKP L HT_TXLKN L0 HT_TXTL0P M HT_TXTL0N M HT_TXTLP P HT_TXTLN R HT_OUTP[..0] HT_OUTN[..0] HT_LKOUTP[..0] HT_LKOUTN[..0] HT_TLOUTP[..0] HT_TLOUTN[..0] HT_NP[..0] HT_NN[..0] HT_LKNP[..0] HT_LKNN[..0] HT_TLNP[..0] HT_TLNN[..0] signals HT_TXLP HT_TXLN HT_RXLP HT_RXLN HT_OUTP[..0] HT_OUTN[..0] HT_LKOUTP[..0] HT_LKOUTN[..0] HT_TLOUTP[..0] HT_TLOUTN[..0] HT_NP[..0] HT_NN[..0] HT_LKNP[..0] HT_LKNN[..0] HT_TLNP[..0] HT_TLNN[..0] RS0M R0 0 ohm % R 0 ohm % Quanta omputer nc. PROJET : ZN Size ocument Number Rev RS0M-HT Link /F ate: Monday, March, 00 Sheet of 0

N_EXP_RX_P0 N_EXP_RX_N0 N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P0 N_EXP_RX_N0 N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N N_EXP_RX_P N_EXP_RX_N PE_RXP0 PE_RXN0 0 PE_RXP - 0 PE_RXN _RXP0 _RXN0 _RXP _RXN _RXP _RXN _RXP _RXN U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RX0P M GFX_RX0N P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN E GPP_RX0P GPP_RX0N E GPP_RXP GPP_RXN GPP_RXP GPP_RXN V GPP_RXP W GPP_RXN U GPP_RXP U GPP_RXN U GPP_RXP U GPP_RXN S_RX0P Y S_RX0N S_RXP Y S_RXN S_RXP S_RXN W S_RXP Y S_RXN RS0M GFX_TX0P PRT OF GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP PE /F GPP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN S_TX0P S_TX0N S_TXP S_TXN PE /F S S_TXP S_TXN S_TXP S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) PE /F GFX E E F F F F H H H H J J K K K K M M M M N N P P Y Y Y Y V V E E E N_EXP_TX_P0-R 0.uF 0% V XR 00 N_EXP_TX_N0-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P-R 0.uF 0% V XR 00 N_EXP_TX_N-R 0.uF 0% V XR 00 N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P0 N_EXP_TX_N0 N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N PE_TXP0_ PE_TXN0_ PE_TXP_ PE_TXN TXP0 TXN0 TXP TXN TXP TXN TXP TXN_ N_PELRP N_PELRN R0 R 00 0 0 0 0 0 0 0 0 0 0 0 0 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR 0.U/0V_XR.K/F_ K/F_ N_EXP_TX_P0 N_EXP_TX_N0 N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N - V. N_EXP_TX_P0 N_EXP_TX_N0 N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P0 N_EXP_TX_N0 N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N N_EXP_TX_P N_EXP_TX_N PE_TXP0 PE_TXN0 PE_TXP 0 PE_TXN 0 _TXP0 _TXN0 _TXP _TXN _TXP _TXN _TXP _TXN Quanta omputer nc. PROJET : ZN Size ocument Number Rev RS0M-PE /F ate: Monday, March, 00 Sheet of 0

Enables ebug us acess through memory /O pads and GPO. 0 : Enable RS0M, efault NT_RT_VSYN_N : isable RS0M (RX use _VSYN) ndicates if memory Side port is available or not 0: Reserved : Required setting. Select with a pull-up resistor on the strap ( RX use _HSYN) NT_RT_HSYN_N V. - R For version R R *./F_ *./F_ V R R0.K/J_ 0/F_ K/J_ V for EXT Gen. LK_SLNK LK_SLNK# R.K/J_ R V R R *K/J_ - 0/F RST#_S N_PWRG LK_N_HTREF_PR LK_N_HTREF#_PR LK_SLNK LK_SLNK# R R K/J_ EXT_N_OS NGFX_LK NGFX_LK# P_UX0P P_UX0N P_UXP P_UXN V *K/F STRP_T *K/F NT_RT_RE NT_RT_GREEN NT_RT_LU 0, NT_RT_HSYN 0, NT_RT_VSYN NT_RT_T NT_RT_LK R 0 0ohm S0F RP N_REFLK_N R *.K R0 *.K R R R R R R R R R R0 R 0m 0m - -, L_LK, L_T V_V_N.V_V_N.V_VQ_N *0/short_ 0/F_ *0/short_ 0/F_ *0/short_ 0/F_ *0/short_ *0/short_ *0/short_ *0/short_ /F_ R.V_PLLV.V_PLLV NT_RT_RE_R NT_RT_GRE_R NT_RT_LU_R.V_VHTPLL.V_VPEPLL _RSET_N N_RST#_N N_PWRG N_LT_STOP# N_LLOW_LTSTOP 0_PR_ T - NT_RT_HSYN_N NT_RT_VSYN_N NT_T_N F NT_LK_N E 0R STRP_T RS0_UX_L U F V(N) E V(N) F V(N) G VSS(N) H VQ(N) H VSSQ(N) E _Pr(FT_GPO) F Y(FT_GPO) F OMP_Pb(FT_GPO) G RE(FT_GPO0) G REb(N) E GREEN(FT_GPO) F GREENb(N) E LUE(FT_GPO) F LUEb(N) G PLLV(N) PLLV(N) PLLVSS(N) H VHTPLL SYSRESETb 0 POWERGOO 0 LTSTOPb LLOW_LTSTOP E REFLK_P/OSN(OSN) F REFLK_N(PWM_GPO) T GFX_REFLKP T GFX_REFLKN U GPP_REFLKP U GPP_REFLKN _LK _T _LK0/UX0P(N) _T0/UX0N(N) _LK/UXP(N) _T/UXN(N) 0 _HSYN(PWM_GPO) _VSYN(PWM_GPO) _SL(PE_RLRN) _S(PE_TLRN) _RSET(PWM_GPO) VPEPLL E VPEPLL HT_REFLKP HT_REFLKN V GPPS_REFLKP(S_REFLKP) V GPPS_REFLKN(S_REFLKN) G STRP_T RSV UX_L(N) RS0M PRT OF RT/TVOUT LOKs PM PLL PWR LVTM TXOUT_L0P(N) TXOUT_L0N(N) TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(G_GPO0) TXOUT_LP(N) TXOUT_LN(G_GPO) TXOUT_U0P(N) TXOUT_U0N(N) TXOUT_UP(PE_RESET_GPO) TXOUT_UN(PE_RESET_GPO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PE_RESET_GPO) TXOUT_UN(N) MS. TXLK_LP(G_GPO) TXLK_LN(G_GPO) TXLK_UP(PE_RESET_GPO) TXLK_UN(PE_RESET_GPO) VLTP(N) VSSLTP(N) VLT_(N) VLT_(N) VLT_(N) VLT_(N) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) VSSLT(VSS) LVS_GON(PE_TLRP) LVS_LON(PE_RLRP) LVS_EN_L(PWM_GPO) TMS_HP(N) HP(N) SUS_STT#(PWM_GPO) THERMLOE_P THERMLOE_N TESTMOE 0 0 0 0 E0 E F G 0 E R N_THERM N_THERM TEST_EN.V_VLTP_N.V_VLT N R0.K R0.K *0/short_ R.K/F_ LVS_TX_L0P LVS_TX_L0N LVS_TX_LP LVS_TX_LN LVS_TX_LP LVS_TX_LN LVS_TX_LP LVS_TX_LN LVS_TX_U0P LVS_TX_U0N LVS_TX_UP LVS_TX_UN LVS_TX_UP LVS_TX_UN LVS_TX_UP LVS_TX_UN LVS_TXLK_LP LVS_TXLK_LN LVS_TXLK_UP LVS_TXLK_UN R0 R R R0.K P_HP P_HP *0/short_ *0/short_ *0/short_ SUS_STT# SUS_STT#_R 0 N_THERM N_THERM V. VPEPLL -PE PLL 0mils width L.V_VPEPLL LMPGSN _ 0mils width L.V_VHTPLL LMPGSN _ NT_LVS_PWREN NT_LVS_RGHT NT_LVS_LON RS0M EUG PN MPPNG EUG_OUT0 EUG_OUT EUG_OUT EUG_OUT EUG_OUT EUG_OUT EUG_OUT EUG_OUT VHTPLL -HT LNK PLL LVS_GON LVS_EN_L LVS_LON TMS_HP UXN UXP HP UX_L.U/.V_.U/.V_ E_LKE_LK E_T R based PU : Level shifted to. V on the Northbridge side using an open-drain buffer and pulled up to.v_s0 through a.k Ohm % resistor on the Northbridge side., LT_STOP# V. U Open rain - LV0 V. R K/F_ N_LT_STOP# R K/F_ V. V L LMPGSN(0,.)_ V. V- nalog PLLV - Graphics PLL L LMPGSN(0,.)_ V_V_N.U/.V_.V_PLLV V. V. LMPGSN(0,.)_ R L 0/J_.V_PLLV.V_V_N PLLV - Graphics PLL.U/.V_ V- igital V. L L LMPGSN(0,.)_.V_VLTP_N LMPGSN(0,00M,)_.V_VLT N 0.U/.V_.U/.V_.U/.V_ VLTP - LVS or V/HM PLL 00 VLT - LVS or V/HM digital 0.U/0V_ LLOW_LTSTOP R0 *0/short_ N_LLOW_LTSTOP 0U/.V_ 0 0.U/0V_ 0.U/0V_ LLOW_LTSTOP O LMPGSN(0,.)_.V_VQ_N L0 VQ- andgap Reference LT_STOP#.V nput * lthough defined as.v /Os, a.v signaling level is supported on LT_STOP#/LLOW_LTSTOP given that Vih is.v..v to.v level translation is not required. 0.U/0V_ Quanta omputer nc. PROJET : ZN Size ocument Number Rev RS0M-System /F ate: Monday, March, 00 Sheet of 0

U PR OF MEM_0(N) MEM_Q0/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_0(N) MEM_(N) MEM_Q(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_0(N) MEM_Q0/VO_(N) E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_0(N) MEM_0(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QS0P/VO_KP(N) MEM_QS0N/VO_KN(N) W MEM_RSb(N) MEM_QSP(N) Y MEM_Sb(N) MEM_QSN(N) MEM_WEb(N) MEM_Sb(N) MEM_M0(N) MEM_KE(N) MEM_M/VO_(N) V MEM_OT(N) OPLLV(N) V MEM_KP(N) OPLLV(N) W MEM_KN(N) OPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) RS0M S_MEM/VO_/F 0 Y V Y 0 E 0 Y W 0 E W E E E E LMPGSN(0,.)_ LMPGSN(0,.)_ SPM_VREF R *0/short_ L L V. V. m m STRP_EUG_US_GPO_ENLEb Enables the Test ebug us using GPO., NT_RT_VSYN NT_RT_VSYN - R R *K/J_ *K/J_ V RS0M isable 0 Enable FT_GPO: LO_EEPROM_STRPS Selects Loading of STRPS from EPROM SUS_STT#_R *S R *K _RST#_N : ypass the loading of EEPROM straps and use Hardware efault Values 0 : Master can load strap values from EEPROM if connected, or use default values if not connected RS0M: Enables Side port memory RS0M:HSYN#, NT_RT_HSYN NT_RT_HSYN - R R *K/J_ *K/J_ V Selects if Memory SE PORT is available or not = Memory Side port Not available 0 = Memory Side port available Register Readback of strap: N_LKFG:LK_TOP_SPRE_[] Quanta omputer nc. PROJET : ZN Size ocument Number Rev RS0M-Spmem/Straps ate: Monday, March, 00 Sheet 0 of 0

V_PE.V_VHTTX.V_VHTRX.V_VHT.V_VG_N.V_VPE V. V_N V V. V. V. V. Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : RS0M-Power 0 Monday, March, 00 ZN Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : RS0M-Power 0 Monday, March, 00 ZN Size ocument Number Rev ate: Sheet of Quanta omputer nc. PROJET : RS0M-Power 0 Monday, March, 00 ZN VG.V OPLLV.V.V PN NME OPLLV.V.V PN NME.V V V RS0M VQ N.V PLLV.V PLLV.V.V VHTPLL RS0M VHT.V RS0M POWER TLE.V/.V.V.V.V VHTRX.V.V VHTTX.V VPEPLL VPE VG VLTP.V V_MEM.V VPE.V VLT V VLT V_MEM.V@0..v@0..V@0..@0. m.u/.v_.u/.v_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ VHT_ J VHT_ K VHT_ L VHT_ M VHT_ P VHT_ R VHT_ T VHTTX_ E VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ Y0 VHTTX_ W VHTTX_ V VHTRX_ H VHTRX_ G VHTRX_ F0 VHTRX_ E VHTRX_ V_ F V_ G V_MEM(N) E V_MEM(N) VPE_ J0 VPE_ P0 VPE_ K0 VPE_0 Y VPE_ VPE_ VPE_ VPE_ E VPE_ W VPE_ H VPE_ VPE_ VPE_ VPE_ VPE_ E VPE_ F VPE_ G VPE_ H VPE_ J VPE_ M0 VPE_ L0 V_ K V_ J V_ U VPE_ M V_ J V_ K VPE_0 K V_ M V_ L V_ L V_ M V_0 M V_ N V_ N V_ P V_ P V_ P V_ R V_ R V_ T V_ T V_0 U V_ T V_(N) H V_(N) H V_MEM(N) E0 V_MEM(N) V_MEM(N) Y V_MEM(N) 0 V_MEM(N) 0 V_MEM(N) 0 VPE_ T0 V_ J VPE_ L VPE_ R0 VPE_ P VPE_ R VPE_ T VPE_ V VPE_ U VPE_ U0 VHTRX_ VHTRX_ VHTTX_ U VHTTX_0 T VHTTX_ R VHTTX_ P VHTTX_ M PRT / POWER UE RS0M PRT / POWER UE RS0M 0.U/0V_ 0.U/0V_ 0 U/0V_ 0 U/0V_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ U/0V_ U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_.U/.V_.U/.V_ L LMPGSN(0,00M,)_ L LMPGSN(0,00M,)_ 0.U/0V_ 0.U/0V_ VSSHT VSSHT VSSHT E VSSHT G VSSHT G VSSHT G VSSHT H VSSHT J VSSHT L VSSHT0 L VSSHT L VSSHT L VSSHT M0 VSSHT N VSSHT P0 VSSHT R VSSHT R VSSHT R VSSHT R VSSHT U VSSHT V VSSHT W VSSHT W VSSHT W VSSHT Y VSSHT VSS VSS G VSS E VSS E VSS J VSS K VSS M VSS0 L VSS L VSS M VSS N VSS P VSS P VSS R VSS R VSS T VSS U VSS0 U VSS U VSS V VSS W VSS W VSS VSS VSS Y VSS VSS VSS0 VSS VSS E0 VSSPE VSSPE VSSPE VSSPE VSSPE E VSSPE G VSSPE G VSSPE G VSSPE H VSSPE0 J VSSPE R VSSPE L VSSPE L VSSPE L VSSPE L VSS K VSSPE M VSSPE N VSSPE P VSSPE R VSSPE0 R VSSPE R VSSPE V VSSPE U VSSPE V VSSPE V VSSPE W VSSPE W VSSPE W VSSPE W VSSPE0 W VSSPE Y VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE E VSSPE E VSSPE0 VSS E VSSHT0 H0 VSS VSS J PRT / GROUN UF RS0M PRT / GROUN UF RS0M H FNSNK H FNSNK 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ SK RX0, RS0, RS0, Socket N SK RX0, RS0, RS0, Socket N 0 0.U/0V_ 0 0.U/0V_ R *0/short_ R *0/short_ 0.U/0V_ 0.U/0V_ L *0/short_ L *0/short_ L *0/short_ L *0/short_ R0 *0/short_ R0 *0/short_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0 0U/.V_ 0 0U/.V_ R 0R R 0R L 0/J_ L 0/J_ U/0V_ U/0V_ 0 0U/.V_ 0 0U/.V_

_RST#_S,,,0 PE_RST#_S 00p/0V_ VG,LN& MN-PE R RST#_S R0 _ PE_RST#_S_R 00p/0V_ - _RST# 0 0 - SSR_LK SSR_LK# PE_S_TXP0 PE_S_TXN0 PE_S_TXP PE_S_TXN SSR_LK SSR_LK# PE_RST#_S_R.V_PE_VR 0.U/0V_XR 0.U/0V_XR 0 0 - - _RXP0 _RXN0 _RXP _RXN _RXP _RXN _RXP _RXN _TXP0 _TXN0 _TXP _TXN _TXP _TXN _TXP _TXN PE_S_RXP0 PE_S_RXN0 PE_S_RXP PE_S_RXN T T T T T T T0 T T T T T T0 T T T R R 0.U/0V_XR 0.U/0V_XR 0 _RST# 0 0.U/0V_XR _RXP0_ 0 0.U/0V_XR _RXN0_ 0.U/0V_XR _RXP_ 0.U/0V_XR _RXN_ 0.U/0V_XR _RXP_ 0.U/0V_XR _RXN_ 0.U/0V_XR _RXP_ 0 0.U/0V_XR _RXN TXP0 _TXN0 _TXP _TXN _TXP _TXN _TXP _TXN 0/F_ PE_LRP_S K/F_ PE_LRN_S PE_S_TXP0_ PE_S_TXN0_ PE_S_TXP_ PE_S_TXN_ SSR_LK SSR_LK# LK_NREFP LK_NREFN LK_N_HTREFP_PR LK_N_HTREFN_PR LK_PU_LKP_PR LK_PU_LKN_PR SLT_GFX_LKP SLT_GFX_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN P L E E Y Y Y Y W W Y W V W W M P U U T T V T V T L L N N M M T V L L P M P P U PE_RST# _RST# _TX0P _TX0N _TXP _TXN _TXP _TXN _TXP _TXN _RX0P _RX0N _RXP _RXN _RXP _RXN _RXP _RXN PE_LRP PE_LRN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RX0P GPP_RX0N GPP_RXP GPP_RXN GPP_RXP GPP_RXN GPP_RXP GPP_RXN PE_RLKP/N_LNK_LKP PE_RLKN/N_LNK_LKN N_SP_LKP N_SP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LK0P GPP_LK0N GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN S00 P EXPRESS NTERFES LOK GENERTOR P LKS Part of PLK0 PLK/GPO PLK/GPO PLK/GPO PLK/M_OS/GPO PRST# 0/GPO0 /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO 0/GPO0 /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO 0/GPO0 /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO /GPO 0/GPO0 /GPO E0# E# E# E# FRME# EVSEL# RY# TRY# PR STOP# PERR# SERR# REQ0# REQ#/GPO0 REQ#/LK_REQ#/GPO REQ#/LK_REQ#/GPO GNT0# GNT#/GPO GNT#/GPO GNT#/LK_REQ#/GPO LKRUN# LOK# P NTERFE NTE#/GPO NTF#/GPO NTG#/GPO NTH#/GPO LPLK0 LPLK L0 L L L LFRME# LRQ0# LRQ#/LK_REQ#/GPO SERRQ/GPO LP W W W W Y V E E F E F G F E F F F H G H 0 E J E F E E E H H J H J G G J H H J J H H G J P_LK0 P_LK P_LK P_LK P_LK T T T T T T T T T0 T T T T T T T T T T T T T T T LP_LK0 LP_LK LRQ0#_S LRQ#_S R T T P_LK P_LK P_LK P_LK *short_vr_.0_en dgpu_vron T0 T0 PG_GPUO_EN R R R T T -.K_ /J_ 0/J_ dgpu_pwrok WRTE_E_ROM V LP_L0, LP_L, LP_L, LP_L, LP_LFRME#, RQ_SERRQ PE_GPO0.P/0V_ P/0V_ PLK_EUG, LK_P_, for EM suggestion T S00_LK_PLK_SM N N T T L GPP_LKP GPP_LKN GPP_LKP GPP_LKN M_M_M_OS LLOW_LTSTP/M_TVE# PROHOT# LT_PG LT_STP# LT_RST# PU G H K G J LLOW_LTSTOP PU_PWRG LT_STOP#, PU_LT_RST#, *0K/F_ R V_S - PU_PROHOT#_. RT_X P/0V_ Y MHZ R M/J_ M_X M_X L M_X L M_X S0M_ RT K_X K_X RTLK NTRUER_LERT# VT_RT_G RT_X RT_X NTRUER_LERT# G *SHORT_P R00 0/F T T_ONN NTRUER_LERT# Left not connected (Southbridge has 0-kohm internal pull-up to VT). 0/J_ R R0-0 *M/F_ VT Y P/0V_ U/V_ R0 *0M/J_.KHZ R 0M/J_ RT_X P/0V_ P/0V_ Quanta omputer nc. PROJET : ZN Size ocument Number Rev S0-PE/P/PU/LP / Monday, March, 00 ate: Sheet of 0

V_S - V V_S - V_S - R R R V MXM_PWREN MXMPWR_EN dgpu_vron N only,an't be install *.K/J_ S_TEST0 *.K/J_ S_TEST *.K/J_ S_TEST SL0/ST0 is V tolerance M datasheet define it R R.K/J_ PLK_SM.K/J_ PT_SM SL/ST is V/S tolerance M datasheet define it R R S_SMLK S_SMT SL/ST is V/S tolerance M datasheet define it R R R R dgpu_vron ms MXM_PWR_EN.K/J_.K/J_.K/J_.K/J_ *.K/J_ *.K/J_ S_SLK S_ST NSWON# SUS_STT# MXMPWR_EN >ms delay is required between all MXM power rail stable and MXM_PWREN(enables the module internal power) V_S R0 lock gen/robson/tv tuner /R/R thermal/ccelerometer R0 00K/F_ R0V-0 V *SW@R0V-0 PE_WKE# SPKR,,,,0, PLK_SM,,,,0, PT_SM S_SMLK S_SMT,, dgpu_prsnt# SUS# SUS# NSWON# S_PWRG_N SUS_STT# SO_0GTE SO_RN# SO_EXT_SM# SO_EXT_S# 0 PE_WKE# R PU_THERMTRP# N_PWRG_N - - *.K/J_ 0 0.u/0V_ - H_RSMRST# - S_GPO_PE_RST# EXT_S_OS V_S -0,,,,0,,,,,,,,,0,,,,,,,,,0,,,,,, T0 T T *0/short_ R0 R *0_ K 0 T T T T S_TEST0 S_TEST S_TEST LNLNK_STTE# SYS_RST# PE_WKE# R_RX S_THERMTRP#.U/.V_ MXM_PWR_EN S_GPO PLK_SM PT_SM S_SMLK S_SMT R_LKREQ# O# T H O# LNK/US_O#/GEVENT# T US_O#/R_TX/GEVENT# T E O# US_O#/R_TX0/GEVENT# T S_JTG_TO US_O#/R_RX0/GEVENT# E S_JTG_TK US_O#/_PRES/TO/GEVENT# F S_JTG_T US_O#/TK/GEVENT# E S_JTG_RST# US_O#/T/GEVENT# F US_O0#/TRST#/GEVENT# H audio interface is VS voltage U J P_PME#/GEVENT# K R#/GEVENT# SP_S#/GE_STT/GEVENT# F SLP_S# H SLP_S# F PWR_TN# H PWR_GOO S00 G SUS_STT# TEST0 Part of TEST/TMS F TEST G0N/GEVENT0# E KRST#/GEVENT# K LP_PME#/GEVENT# J LP_SM#/GEVENT# H GEVENT# J SYS_RESET#/GEVENT# H WKE#/GEVENT# F R_RX/GEVENT0# J THRMTRP#/SMLERT#/GEVENT# N_PWRG G RSMRST# LK_REQ#/ST_S0#/GPO LK_REQ#/ST_S#/GPO SMRTVOLT/ST_S#/GPO0 LK_REQ0#/ST_S#/GPO0 F0 ST_S#/FNOUT/GPO E ST_S#/FNN/GPO F SPKR/GPO SL0/GPO E S0/GPO F SL/GPO F S/GPO H LK_REQ#/FNN/GPO LK_REQ#/FNOUT/GPO E R_LE#/LL#/GPO J SMRTVOLT/SHUTOWN#/GPO H R_RST#/GEVENT# GE_LE0/GPO GE_LE/GEVENT# G GE_LE/GEVENT0# K GE_STT0/GEVENT# 0 LK_REQG#/GPO/OSN V P / WKE UP EVENTS GPO US O V USLK/M_M_M_OS US. US MS US.0 US_ROMP US_FSP/GPO US_FSN US_FS0P/GPO US_FS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HSP US_HSN US_HS0P US_HS0N USLK/M_M_M_OS pin is LK input pin when EXT LKGEN mode. t is output LK source when NT LKGEN mode. 0 G J0 H H J F E E E J J G G G G E E J J R _ US_ROMP_S US_FSP US_FSN R US_RP US_RN US_FSP US_FSN USP0 USP0- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP 0 USP- 0 USP 0 USP- 0 USP 0 USP- 0 USP0 0 USP0-0 LK_M_US,.K/F_ N Z_SOUT_UO MXM_SOUT_HM Z_SYN_UO MXM_SYN_HM Z_TLK_UO MXM_T_LK_HM Z_RST#_UO *S/W JTG EUG MXM_RST#_R Z_SN0 Z_SN V_S S_JTG_TK S_JTG_TO S_JTG_T S_TEST S_JTG_RST# S JTG Z_SOUT_UO MXM_SOUT_HM Z_SYN_UO MXM_SYN_HM Z_TLK_UO MXM_T_LK_HM Z_RST#_UO MXM_RST#_R 0P/0V_ R R _ R /J_ R _ R R _ R /J_ /J_ /J_ R0 _ Z_SN0 Z_SN Z_SOUT *0P/0V_ Z_SYN *0P/0V_ Z_LK 0P/0V_ Z_RST# f the VO_Z_S power rail is configured for.v_s then Z_SN[:0] can not be connected to.-v devices. Z_SOUT V_S - R R R R R R R R R R *0K/F_ *0K/F_ *0K/F_ *0K/F_ *0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ T T Z_LK Z_SOUT Z_SN0 Z_SN Z_SN Z_SN Z_SYN Z_RST# GE_OL GE_RS GE_MO GE_RXERR GE_PHY_NTR P_PRES0 M Z_TLK N Z_SOUT L Z_SN0/GPO M Z_SN/GPO M Z_SN/GPO M Z_SN/GPO0 N Z_SYN P Z_RST# T GE_OL T GE_RS L GE_MK L GE_MO T GE_RXLK U GE_RX U GE_RX T GE_RX U GE_RX0 T GE_RXTL/RXV V GE_RXERR P GE_TXLK M GE_TX P GE_TX T GE_TX P GE_TX0 M GE_TXTL/TXEN P GE_PHY_P M GE_PHY_RST# V GE_PHY_NTR E PS_T/S/GPO E PS_LK/SL/GPO F SP_S#/GE_STT/GPO G F_RST#/GPO0 PSK_T/GPO F PSK_LK/GPO0 F PSM_T/GPO E PSM_LK/GPO S0M_ GE LN H UO EMEE TRL SL/GPO S/GPO SL_LV/GPO S_LV/GPO E_PWM0/E_TMER0/GPO E_PWM/E_TMER/GPO E_PWM/E_TMER/GPO E_PWM/E_TMER/GPO00 EMEE TRL KS_0/GPO0 KS_/GPO0 KS_/GPO0 KS_/GPO0 KS_/GPO0 KS_/GPO0 KS_/GPO0 KS_/GPO0 KSO_0/GPO0 KSO_/GPO0 KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_0/GPO KSO_/GPO0 KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO KSO_/GPO F E F E F E G G E E S_SLK S_ST S_GPO S_GPO GPO GPO00 S_GPO S_GPO R R 0K/F_ 0K/F_ Quanta omputer nc. PROJET : ZN Size ocument Number Rev S0-P/GPO/US / ate: Monday, March, 00 Sheet of 0

ST PORT 0,,, can support H mode U ST ST O Signal Name ST_LRP ST_LRN.V_V_ST ST_TX0 ST_TX0- ST_RX0- ST_RX0 ST_TX ST_TX- ST_RX- ST_RX PLE ST_L RES VERY LOSE TO LL OF S0 Explanation S00 : 00-? % resistor to. P/N:S0F00(0 Ohm) S00 : T-? % resistor to. (K ohm) S00 : -? % resistor to VN ST. S00 : T-? % resistor to VN ST. R R 0/F_ /F_ ST_T# 0 0 V ST_LRP ST_LRN R P/0V_ Y MHZ P/0V_ 0K/F_ ST_X R M/J_ ST_X H J J H H0 J0 G0 F0 G F J H H J G F G F J H J H H J ST_TX0P ST_TX0N ST_RX0N ST_RX0P ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP ST_LRP ST_LRN ST_T#/GPO ST_X ST_X SERL T S00 F_LK Part of F_FLKOUT F_FLKN F_OE#/GPO F_V#/GPO F_WE#/GPO F_E#/GPO F_E#/GPO0 F_NT/GPO F_NT/GPO F_Q0/GPO F_Q/GPO F_Q/GPO0 F_Q/GPO F_Q/GPO F_Q/GPO F_Q/GPO F_Q/GPO F_Q/GPO F_Q/GPO F_Q0/GPO F_Q/GPO F_Q/GPO0 F_Q/GPO F_Q/GPO F_Q/GPO FNOUT0/GPO FNOUT/GPO FNOUT/GPO FNN0/GPO FNN/GPO FNN/GPO TEMPN0/GPO TEMPN/GPO TEMPN/GPO TEMPN/TLERT#/GPO TEMP_OMM HW MONTOR FLSH VN0/GPO VN/GPO VN/GPO VN/GPO VN/GPO VN/GPO0 VN/GE_STT/GPO VN/GE_LE/GPO H G F F G G F E F H J J H H G H J G F H J F OR_0 J OR_ J OR_ G OR_ H OR_ W W Y W V W WWN_ET# PPE_N# R_REQ# TEMPN0 TEMPN M_THRM_S THERM_LERT# T0 T T T00 T T0 T0 T0 T T0 T T T0 T0 T T T T T0 T0 T T T T F THERE S NO E, TEST PONTS FOR EUG US S MNTORY THERM_LERT#, TEMP_OMM R *0/short_ S_GPO S_GPO SE_PORT_0 SE_PORT_ R *0_ S_OS_WP# GPO0 LR_OS_T - LR_PSSW V R R TEMPN0 TEMPN M_THRM_S S_GPO S_GPO SE_PORT_0 SE_PORT_ GPO0 *0K/F_ OR_0 *0K/F_ OR_ R R R0 R R R R R R R 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_ - S_SO S_S S_SK S_SE# T J E K K G SP_/GPO SP_O/GPO SP_LK/GPO SP_S#/GPO ROM_RST#/GPO SP ROM N N G Y R R0 R *0K/F_ *0K/F_ *0K/F_ OR_ OR_ OR_ R0 R R 0K/F_ 0K/F_ *0K/F_ - V_S Mbit, SP S0M_ 0 0 UM " R *0K_ R *K/F_ R *0K_ V iscrete " S_SE# S_SK S_S S_SO S_OS_WP# R R R *R_ *R_ *R_ U E# V SK S SO HOL# WP# VSS *MXL0 U E# V SK S SO HOL# 0 *0.U/V/ LR_OS_T LR_PSSW R0 0K/F_ R 0K/F_ JP ONN RPT x WP# VSS *MXL0 Quanta omputer nc. PROJET : ZN Size ocument Number Rev S0-ST/E/HWM/SP / ate: Monday, March, 00 Sheet of 0

V V. V. - V_S V_S V. R VQ--.V /O power L V V For support US wakeup-->v_s f the VO_Z_S power rail is configured for.v_s then Z_SN[:0] can not be connected to.-v devices. - 00T _ L 00T _ *0/short_ R 0 V_VO_PGP.V_PE_VR L V_VPL_ST LMPGSN(0_.)_.V_V_ST.V_S R0 0.uF.V_VN_US L.V_VN_US LMPGSN(0_.)_ VO_Z U/.V_ 0.U/0V_ 00 0.U/0V_ L LMPGSN(0_.)_ U/.V_ 0 U/.V_ L LMPGSN(0_)_ *0/short_.U/.V_ 0.U/0V_ U/0V_.V_S m 0.U/0V_ m 00m m *0.U/0V_ m U/0V_ m xx m 0.U/0V_.V_US_PHY_R PLE LL THE EOUPLNG PS ON THS SHEET LOSE TO S S POSSLE. V 0m xx m m m xx m m V-- S/ ORE power.v_vr.v_vn_lk V_VPL V_VO.V_VPL.V_VR_ VO_Z.V_VN_US V_HWM_VN 0.U/0V_.V_US_PHY_R V_VPL 0.U/0V_ m m m m.v_vn_us V. L 00T _ S0 without GE: onnected to plane. LOSE PN F 0.u/0V_ U/.V_.u/.V_ R 0_ 0 0U/.V_ R0 V_S - V. *0/short_ V_S - *0/short_.V_S VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSSPL_SYS - V_S L LMPGSN(0_.)_ V_HWM_VN.V_S L LMPGSN(0_.)_.V_VPL 0.U/0V_.U/.V_ R *0 L LMPGSN(0_.)_ U/0V_.U/.V_ U/0V_ 0U/.V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0U/.V_.U/.V_ 0.U/0V_ U/.V_ U/0V_ 0 *0.U/0V_ U/0V_ L *0/short_ 0.U/0V_ 0.U/0V_ H VO PGP_ V VO PGP_ Y VO PGP_ E VO PGP_ VO PGP_ VO PGP_ VO PGP_ VO PGP_ VO PGP_ VO PGP_0 F VO PGP_ VO PGP_ F VO F_ E VO F_ F VO F_ VO F_ E U VN PE_ V VN PE_ V VN PE_ V VN PE_ V VN PE_ V VN PE_ W VN PE_ W VN PE_ J0 VN ST_ F VN ST_ H0 VN ST_ G VN ST_ E VN ST_ VN ST_ E VN ST_ VN US_S_ VN US_S_ 0 VN US_S_ VN US_S_ VN US_S_ 0 VN US_S_ VN US_S_ 0 VN US_S_ VN US_S_ VN US_S_0 0 VN US_S_ E VN US_S_ U POWER VPL PE VPL ST S00 P/GPO /O VN US_S_ VN US_S_ S0M_ 0U/.V_ FLSH /O SERL T P EXPRESS US /O PLL GE LN LKGEN /O ORE S Part of VR N VR R VR N VR U VR U VR V VR V VR W VR W ORE S0 VN LK_ K VN LK_ K VN LK_ J VN LK_ K VN LK_ J VN LK_ J0 VN LK_ K VN LK_ J VRF_GE_S VO GE_S VR GE_S_ L VR GE_S_ L.V_S /O VO_GE_S_ M VO_GE_S_ P VO S_ VO S_ VO S_ VO S_ K0 VO S_ L0 VO S_ J VO S_ T VO S_ T VR S_ F VR S_ G VO_Z_S VR US_S_ VR US_S_ VPL SYS VPL SYS_S VPL US_S VN HWM_S VXL S V M0 M M L F L0 0.U/0V_ *0.U/0V_ *0.U/0V_ 0.U/0V_.U/.V_ *0.U/0V_.U/.V_ U/0V_ U/0V_.U/.V_ U/0V_ L LMPGSN(0_.)_ U/0V_ U/0V_ R0 UE Y VSSO_ST_ Y VSSO_ST_ VSSO_ST_ VSSO_ST_ E VSSO_ST_ E VSSO_ST_ F VSSO_ST_ F VSSO_ST_ F VSSO_ST_ F VSSO_ST_0 G VSSO_ST_ H VSSO_ST_ H VSSO_ST_ H VSSO_ST_ H VSSO_ST_ J VSSO_ST_ J VSSO_ST_ J VSSO_ST_ J VSSO_ST_ VSSO_US_ 0 VSSO_US_ K VSSO_US_ VSSO_US_ 0 VSSO_US_ VSSO_US_ VSSO_US_ VSSO_US_ E VSSO_US_ F VSSO_US_0 F VSSO_US_ F VSSO_US_ F VSSO_US_ VSSO_US_ G VSSO_US_ F VSSO_US_ VSSO_US_ H VSSO_US_ H VSSO_US_ H VSSO_US_0 H VSSO_US_ J VSSO_US_ J VSSO_US_ K VSSO_US_ K VSSO_US_ K VSSO_US_ K VSSO_US_ H VSSO_US_ Y EFUSE VSSN_HWM M VSSXL S00 GROUN P VSSO_PELK_ VSSO_PELK_ P0 VSSO_PELK_ VSSO_PELK_ M VSSO_PELK_ VSSO_PELK_ M VSSO_PELK_ VSSO_PELK_ M VSSO_PELK_ VSSO_PELK_ P VSSO_PELK_ VSSO_PELK_ P VSSO_PELK_ VSSO_PELK_0 P VSSO_PELK_ VSSO_PELK_ T0 VSSO_PELK_ VSSO_PELK_ T VSSO_PELK_0 VSSO_PELK_ T VSSO_PELK_ VSSO_PELK_ V0 VSSO_PELK_ VSSO_PELK_ J VSSO_PELK_ VSSO_PELK_ VSSO_PELK_ Part of S0M_ J E E E F N R R T0 P0 V U M V M L L J P V V W W0 J U Y Y0 Y Y G J G G M F H H V0 P N L L M0 H H Y0 W W0 E L K0,,,,0,,,,,,,,,0,,,,,,,,,0,,,,,, V,,0,,0,, V.,.V_S V V..V_S 0 0.u/0V_ 0.u/.V_ 0 *0.U/0V_.U/.V_ Quanta omputer nc. PROJET : ZN Size ocument Number Rev S0-PWR/EOUPLNG / ate: Monday, March, 00 Sheet of 0

REQURE STRPS - V_S S0M is supported Gen mode only. For internal clock GEN. -0 V V V V V_S V_S V_S - OVERLP OMMON PS WHERE POSSLE FOR UL-OP RESSTORS. R *0K/F_ R *0K/F_ R *0K/F_ R *0K/F_ R 0K/F_ - R *0K/F_ R *0K_ R *.K/F_ GPO00 GPO, LK_P_, PLK_EUG P_LK P_LK P_LK P_LK Z_SOUT R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_ R *0K/F_ - R 0K/F_ -0 R 0K/F_ R0 *.K_ R.K_ Z_SOUT P_LK P_LK P_LK P_LK LP_LK0 LP_LK GPO00 GPO PULL HGH LOW POWER MOE LLOW PE Gen Watchdog Timer Enable USE EUG STRPS non_fusion LOK MOE EFULT E ENLE NT. LKGEN ENLE EFULT H, H=Reserved H, L=SP ROM PULL LOW PERFORMNE MOE EFULT FORE PE Gen EFULT Watchdog Timer isable EFULT GNORE EUG STRPS EFULT Fusion LOK MOE E SLE EFULT EXT. LKGEN ENLE L,H=LP ROM EFULT L, L=FWH ROM - V. V. EUG STRPS S00 HS K NTERNL PU FOR P_[:] internal have pull Hi 0K N_PWRG_N N_PWRG_N R 00/J_ S_PWRG_N U TSZ0FU R 0.U/0V_ /J_ N_PWRG N_PWRG R *0_ R *.K/J_ R *.K/J_ R *.K/J_ R0 *.K/J_ R *.K/J_ V_S R 0K/F_ *.U/.V_ N_PWRG_N: RS0/RX =.V; o NOT share it with S_PWRG when use nternal lk Gen (Need S PLL initialize firstly) R *0/short_ S_PWRG_N S_PWRG_N N/S POWER GOO RUT P_ P_ P_ P_ P_ -,,,, PU_VO_PWRG S PULL HGH USE P PLL EFULT SLE L UTORUN EFULT USE F PLL EFULT SLE ROM EFULT SLE P MEM OOT EFULT,, PWROK_E S PULL LOW YPSS P PLL ENLE L UTORUN YPSS F PLL ENLE ROM use REQ# as S use GNT# as SL ENLE P MEM OOT Quanta omputer nc. PROJET : ZN Size ocument Number Rev S0-STRPS/PWRG ate: Monday, March, 00 Sheet of 0

HNNEL MM 0.VSUS.VSUS,,,,0,,,,,0,, M [:0], M 0, M, M M_S#_0 M_S#_ M_LK_R_0 M_LK_R#_0 M_LK_R_ M_LK_R#_, M_KE_0, M_KE_, M S#, M RS#, M WE#,,,,,,,, PLK_SM PT_SM M_OT_0 M_OT_ M M0 M M M M M M M M M M M M M M, M QS0, M QS, M QS, M QS, M QS, M QS, M QS, M QS, M QS#0, M QS#, M QS#, M QS#, M QS#, M QS#, M QS#, M QS# M 0 M M M M M M M M M M 0 M M M M M M 0 M M M_S#_0 M_S#_ M_LK_R_0 M_LK_R#_0 M_LK_R_ M_LK_R#_ M_KE_0 M_KE_ M S# M RS# M WE# S0 0 S 0 M_OT_0 M_OT_ M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 JM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-MM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q R-MM0_H=._Standard 0 0 0 0 0 0 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[..0],, MEM_M_EVENT_L, M RST# VREF_Q_R VREF R V *0uF 0%.V SM.*. uf 0%.V XR 00 R uf 0%.V XR 00 V 0 0.uF 0% V XR 00 uf 0%.V XR 00 0.uF 0% V XR 00 uf 0%.V XR 00 *0K/F_ V MEM_M_EVENT_L M RST# 0 VREF_Q_R VREF R MEM_M_EVENT_L 00 0 0 0 JM V V V V V V V V V V0 V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS.VSUS P00 R SRM SO-MM (0P) VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT R-MM0_H=._Standard 0 0U/.V_ 0U/.V_ SMR_VTERM.VSUS R.U/.V_ K % /W 00 Place these aps near So-imm0. 0U/.V_ 0 0 0 0 0 0 0 0U/.V_ 0U/.V_ 0 % /W 00 R0 K % /W 00 R 0 % /W 00 R 0 0 0U/.V_ 0.U/V_ R K % /W 00 R0 K % /W 00 0.U/V_ 0.U/V_ 0.U/.V_ 0.U/V_ 0.U/V_ 0.uF 0% V XR 00 0.uF 0% V XR 00 0 0.uF 0% V XR 00 VREF_Q_R 0.uF 0% V XR 00 VREF R 0.0U 0.uF 0% V XR 00 0U/V_ 0 0.uF 0% V XR 00 0.0U 000P/0V/ 000P/0V/ VREF_Q_R VREF R FOX H:. white P Placement V SMR_VTERM SP S0 0 M.U/.V_ 0.U/V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ SP S 0 R 0 % /W 00 R 0 % /W 00 S 0 S0 0 Size ocument Number Rev R H MM 0 Quanta omputer nc. PROJET : ZN ate: Monday, March, 00 Sheet of 0

HNNEL MM, M [:0], M 0, M, M M_S#_ M_S#_ M_LK_R_ M_LK_R#_ M_LK_R_ M_LK_R#_, M_KE_0, M_KE_, M S#, M RS#, M WE#,,,,0, PLK_SM,,,,0, PT_SM,,,,,,,, M_OT_ M_OT_ M M0 M M M M M M M M M M M M M M, M QS0, M QS, M QS, M QS, M QS, M QS, M QS, M QS, M QS#0, M QS#, M QS#, M QS#, M QS#, M QS#, M QS#, M QS# M 0 M M M M M M M M M M 0 M M M M M M 0 M M M_S#_ M_S#_ M_LK_R_ M_LK_R#_ M_LK_R_ M_LK_R#_ M_KE_0 M_KE_ M S# M RS# M WE# S0 S M_OT_ M_OT_ M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 JM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-MM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 0 0 0 0 0 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[..0], *0uF 0%.V SM.*. uf 0%.V XR 00 uf 0%.V XR 00, MEM_M_EVENT_L, M RST# VREF_Q_R VREF R V M RST# uf 0%.V XR 00 uf 0%.V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 0 00pF % 0V NPO 00 V.VSUS MEM_M_EVENT_L M RST# VREF_Q_R VREF R.VSUS 00 0 0 0 0 JM V V V V V V V V V V0 V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-MM (0P) VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT R-MM0_H=._Standard 0 0 0 0 0 0 0 V SMR_VTERM R Place these aps near So-imm0. *0K/F_ MEM_M_EVENT_L VREF_Q_R VREF R 0 SP S0 R-MM0_H=._Standard FOX H:. white P Placement 0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0 0 0U/.V_ 0U/.V_ 0.U/V_ 0.U/V_ V SMR_VTERM 0.U/V_ 0.U/V_ 0 0.U/V_ 0U/V_ 0.uF 0% V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 SP S 0 M.U/.V_ 0.U/V_ U/.V_ U/.V_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ V - R 0 % /W 00 R 0 % /W 00 S S0 Size ocument Number Rev R H MM Quanta omputer nc. PROJET : ZN ate: Monday, March, 00 Sheet of 0

HNNEL MM 0 M Q[:0],0.VSUS,0 M [:0],0 M 0,0 M,0 M M_S#_0 M_S#_ M_LK_R_0 M_LK_R#_0 M_LK_R_ M_LK_R#_,0 M_KE_0,0 M_KE_,0 M S#,0 M RS#,0 M WE#,,,,0, PLK_SM,,,,0, PT_SM M_OT_0 M_OT_,0 M M0,0 M M,0 M M,0 M M,0 M M,0 M M,0 M M,0 M M,0 M QS0,0 M QS,0 M QS,0 M QS,0 M QS,0 M QS,0 M QS,0 M QS,0 M QS#0,0 M QS#,0 M QS#,0 M QS#,0 M QS#,0 M QS#,0 M QS#,0 M QS# M 0 M M M M M M M M M M 0 M M M M M M 0 M M M_S#_0 M_S#_ M_LK_R_0 M_LK_R#_0 M_LK_R_ M_LK_R#_ M_KE_0 M_KE_ M S# M RS# M WE# S0 0 S 0 M_OT_0 M_OT_ M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 JM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-MM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 0 0 0 0 0 0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q V 0 *0uF 0%.V SM.*. uf 0%.V XR 00 uf 0%.V XR 00 uf 0%.V XR 00 uf 0%.V XR 00,0 MEM_M_EVENT_L,0 M RST# 0 VREF_Q_R 0 VREF R V 0 0.uF 0% V XR 00 0.uF 0% V XR 00 V.VSUS 00 0 0 MEM_M_EVENT_L M RST# 0 0 JM V V V V V V V V V V0 V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS.VSUS P00 R SRM SO-MM (0P) VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT R-MM0_H=._Standard 0 0 0 0 0 0 0 SMR_VTERM.VSUS R R VREF_Q_R 0 % /W 00 K % /W 00 R R.U/.V_ K % /W 00 R K % /W 00.U/.V_ 0 R VREF R 0 % /W 00 K % /W 00 Place these aps near So-imm0. 0.uF 0% V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 0.uF 0% V XR 00 00 0.0U 0.uF 0% V XR 00 0.0U 0 000P/0V/ 000P/0V/ VREF_Q_R 0 VREF R 0 R-MM0_H=._Standard M Q----JM.0-----JM.0 M Q----JM.-----JM. M Q----JM.-----JM. M Q----JM.-----JM. M Q----JM.-----JM. M Q0----JM.-----JM. R0 *0K/F_ MEM_M_EVENT_L 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0.U/V_ 0 0.U/V_ 0 0.U/V_ 0.U/V_ 0.U/V_ 0U/V_ SP S0 0 SUYN H:. RVS lack P Placement V SMR_VTERM SP S M.U/.V_ 0.U/V_ U/.V_ U/.V_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ V R0 0 % /W 00 R00 0 % /W 00 S0 0 S 0 - Size ocument Number Rev R H MM 0 Quanta omputer nc. PROJET : ZN ate: Monday, March, 00 Sheet of 0