2002 Journal of Software., Timed Computation Tree Logic,Metric Interval Temporal Logic Real-Time Temporal Logic

HTML
DOWNLOAD

Μέγεθος: px

Εμφάνιση ξεκινά από τη σελίδα:

Download "2002 Journal of Software., Timed Computation Tree Logic,Metric Interval Temporal Logic Real-Time Temporal Logic"

Σκύλλα Παππάς
6 χρόνια πριν
Προβολές:

1 /00/30) Journl of Softwre Vol3, No,,00080) E-mil http//wwwiosccn,0,, Timed Computtion Tree Logic,Metric Intervl Temporl Logic Rel-Time Temporl Logic,,, liner temporl logic with clocks, LTLC) Mnn Pnueli LTLC,, LTLC TP30 A rel-time systems) [~4,,,,,0,, Timed Computtion Tree Logic [5, Metric Intervl Temporl Logic [6,Timed Propositionl Temporl Logic [7 Rel-Time Temporl Logic [8 specifiction lnguges), ), timed trnsition systems [3 ) clocked trnsition systems [4 ) timed utomt [9 ) system description lnguges),, ),,,,,,,, LTLCliner temporl logic with clocks) Mnn Pnueli LTL [ ) ) ZT0-04-) 96 ),,,,,,, 95 ),,,,,,

2 34 Journl of Softwre 00,3) LTLC, LTLC LTLC 3 ), LTLC, LTLC 4 LTLC,,R,R + N {t i } i N, ) 0=t 0 <t <t < <t n < ) {t i } i N, lim = n t n R + ft), {t i } i N, i N, ft) i,t i+ ) ) ft) {0,}, ft) + 3 R ft), {ti} i N 0 = 0 f t) =, t ti ti, ti + t 0,t,t,,t n, 0=t 0 <t <t < <t n, 0 = 0 f t) = t ti ti, ti + t tn > tn,,, =0, ), ) 4 f R + f f ' R + R t 0 R +, f ' t ) = lim f ) 0 t t t 0 +, f f, f f LTLC, LTLC LTLC LTLC ) t ) u,u 0,u,u, 3) p,p 0,p,p, 4) x,x 0,x,x, 5) { m m N} 6) +,,* 7) =, 8), 9) 0), ),[ ),U )

3 35 LTLC e = t m u x x e e + e) e e),t, m,u,x LTLC ϕ = p p' e = e ) e e ) ϕ ϕ ϕ ) uϕ) [ ϕ ϕuϕ ),u,x,e e, ), ) ) <> ) [,<,> ) LTLC, vrϕ) vre) ϕ e vre) V, e V, vrϕ) V, ϕ V LTLC LTLC, R +, R +, p x f p f x, p x f p f x f p f x 3 V I= I,σ V LTLC- ), ) V u, I R u, Iu) R ) V p, σ R + f p p 3) V x, σ R + f x x 4 I= I,σ V LTLC-,e V t 0 R +, t=t 0,e I Ie,t 0 ) ) I t, ) = ) I m, ) = m 3) I u, ) = I u) 4) I x, t ) = f ), 0 x x, ) = f x ) e, ) = I e, e + e, ) = I e, ) + I e, e * e, ) = I e, ) * I e, I 5) I ) 6) I ) 7) I ) 5 I= I,σ V LTLC-,ϕ V t 0 R +, t=t 0,ϕ I ) I t 0 0 p ) I p, t ) = f ) ) I p', t ) = f p ) 0 I e, ) = I e, ) 3) I e = e, ) = I e, ) I e, ) 4) I e e, ) = 5) I t ) = I ) 0 ϕ ϕ, ) = I ϕ, ) I ϕ, 6) I ) t I t) = 7) I[ ) = t I t) = t [, t) I ϕ t) = 0 8) I ϕuϕ, ) =

4 36 Journl of Softwre 00,3) I[ / u ) = 9) I u ) =, I [ / u = I[/u,σ I[/u I w) w V w u I[ / u w) = w u It 0 )=, ϕ t=t 0 ϕ t=0, I ϕ LTLC- 6 ϕ V ) V LTLC I I ϕ LTLC-, ϕ LTLC-, LTLC- ) ϕ LTLC-, ϕ, = ϕ 7 ϕ φ V ϕ V ) φ, φ ϕ,= ϕ φ 8 LTLC ) = [[ϕ [ ϕ, =<><> ϕ <> ϕ ) = [ ϕ <> ϕ, = <> ϕ [ ϕ 3) = [ϕ ϕ, = ϕ <> ϕ 4) = [ ϕ φ) [ ϕ) [ φ) 5) =<> ϕ φ) <> ϕ) <> φ) 6) = [ ϕ φ) [ ϕ) [ φ 7) = ϕ φ, θ = [ θ = [ φ 6, LTLC, LTLC bounded-response) bounded-invrince), [3 6, 3 LTLC, 3,, ), vertex), Green Red),, x 3 x ),,, dely) ),,, 0 jump), 0 x=0 Green x> x=0 x 3, Fig Trffic_light Red timed modules) M x

5 37,,, vrm),ctrm) extlm) M vertex gurd new_vertex ssignment,vertex, new_vertex, gurd enbling condition), ) ssignment,, x 0 x =0), x =x) x e x e x k = = = e k, x,x, x k, i k e i 0 x i, ), vertex invrint vertex invrint,,, module externl controlled init jump dely module_nme {vrible_nmetype}* {vrible_nmetype}* init_cond {vertex gurd new_vertex ssignment}* {vertex invrint}*,type, boolen ) clock )init_cond, =0 ), 4 p q), ), p ), x module controlled init jump dely Trffic-light pboolen xclock p=0 x=0 p=0 x> p = x =0 p= x> p =0 x =0 p=0 x 3 p= x LTLC,, LTLC LTLC, LTLC αvertex gurd new_vertex ssignment, LTLC- vertex gurd new_vertex ssignment α, TLFα) βvertex invrint, LTLC- vertex invrint β, TLFβ) 3 M,α 0,α,,α n M,β 0,β,,β k M LTLC-

6 38 Journl of Softwre 00,3) init_cond [ Vc = V c \/ i n TLF i )))) [\/ j k TLF β j ))) < α < M,init_cond M,V c M V c =ctrm)),v c = V v=v ) TLFM) M c /\ v V c 3 ) TLFtrffic-light) TLF=p=0 x=0) [p =p x =x) p=0 x> p = x =0) p= x> p =0 x =0))) [p=0 x 3) p= x ))) M TLFM), TLFM) M 3 M,ϕ LTLC- TLF M ) = ϕ, ϕ M, M = ϕ, M ϕ TLFM) 33 M M, ctrm ) ctrm )= v vrm ) vrm ),v M M n M,M,,M n, M,M,,M n, [M M M n n TLFM ) TLFM ) TLFM n ) [M M M n TLFM ) TLFM ) TLFM n ) [M M M n 34 TLFM ) TLFM ) TLFM n ) = ϕ [M M M n 3 34) 4rilrod gte control [, ),, 3 Sg=out pssing x Sg=out fr x> x=0 Sg=in, x=0 ner x 4,, Fig Trin fr,ner pssing, fr ner, in ner, ~4 pssing pssing, fr, fr, out fr, ner, open ), in, down,down, closed, closed, out up up in, down, open open, in 3 x y, sg 3 module controlled init jump Trin p{fr,ner,pssing} sg{in,out} xclock p=fr sg=out x=0 p=fr p =ner sg =in x =0 p=ner x p =pssing sg =sg x =0 p=pssing p =fr sg =out x =x dely p=fr true // true ) p=ner x 4 p=pssing x

7 39 module externl controlled init jump dely Gte sg{in,out} q{open,closed,up,down} yclock q=open y=0 q=open sg =in q =down y =0 q=down y q =closed y =y q=closed sg =out q =up y =0 q=up sg =in q =down y =0 q=up y= q =open y =y q=open sg=out 3, q=down sg=in y q=closed sg=in q=up sg=out y y=0 y open sg=out up sg=out y sg =in y=0 sg =in y=0 sg =out y=0 down sg=in y y closed sg=in,,, Fig3 Gte 3 TLFTrin)=p=0 sg=0 x=0) [p =p sg =sg x =x) p=0 p = sg = x =0) p= x p = sg =sg x =0) p= p =0 sg =0 x =x))) [p=0 p= x 4) p= x ))), TLFGte)=q=0 y=0) [q =q y =y) q=0 sg = q = y =0) q= y q = y =y) q= sg =0 q =3 y =0) q=3 sg = q = y =0) q=3 y= q =0 y =y))) [q=0 sg=0) q= sg= y ) q= sg=) q=3 sg=0 y ))) [p= q=)[p=pssing q=closed)) [Trin Gte I TLFTrin) TLFGte), f p, f sg, f q, f x f y p,sg,q,x y I,,, n, f p, < < < n < f p, ) 0 =0, n N, f p n, n+ ) [p =p sg =sg x =x) p=0 p = sg = x =0) p= x p = sg =sg x =0) p= p =0 sg =0 x =x)),f p 3, f p 0,,,,0, f sg 0 3, f sg 0 f p, i N, 0 f p t) = f sg 0 t) = 3i, 3i,,,, 3, ) ) 3 [q=0 sg=0) q= sg=) q= sg=) q=3 sg=0)) ) { 0, 3} f q t) {, } 3i,, 3) f p )= [p =p sg =sg x =x) p=0 p = sg = x =0) p= x p = sg =sg x =0) p= p =0 sg =0 x =x)) f x ), 3 t 0, 3, 3) f q t 0 )= f q t 0 )= f q t 0 )=, [q=0 sg=0) q= sg= y ) q= sg=) q=3 sg=0 y )) f y t 0 ), t 0 t 0 > +, 0, 3 f q t 0 )= ), t 0 R +, f p t 0 )=, f q t 0 )= I [p= q=) I TLFTrin) TLFGte), 34,[p= q=) 3

8 40 Journl of Softwre 00,3) [Trin Gte 4 LTLC,, Timed Computtion Tree Logic [5,Metric Intervl Temporl Logic [6 TLA+ [3,LTLC,, LTLC ),, LTLC, LTLC,, LTLC LTLC LTLC, LTLC, model checking) [,4 LTLC, Leicester, References [ Alur, R, Henzinger, TA Rel-Time system=discrete system+clock vribles Softwre Tools for Technology Trnsfer, 997, /) 86~09 [ de Bkker, JW, Huizing, K, de Rover, W-P, et l, eds Proceedings of the REX Workshop Rel-Time Theory in Prctice Lecture Notes in Computer Science 600, New York Springer-Verlg, 99 [3 Henzinger, TA, Mnn, Z, Pnueli, A Temporl proof methodologies for timed trnsition systems Informtion nd Computtion 994,)73~337 [4 Mnn, Z, Pnueli, A Clocked trnsition systems In Pnueli, A, Lin, H, eds Logic nd Softwre Engineering Singpore World Scientific, 996 3~4 [5 Alur, R, Courcoubetis, C, Dill, DL Model-Checking in dense rel-time Informtion nd Computtion, 993,04)~34 [6 Alur, R, Feder, T Henzinger, TA The benefits of relxing punctulity Journl of the ACM, 996,43)6~46 [7 Alur, R, Henzinger, TA A relly temporl logic Journl of the ACM, 994,4)8~04 [8 Ostroff, JS Temporl logic for rel-time systems Tunton, Englnd Reserch Studies Press Ltd, 989 [9 Alur, R, Dill, DL A theory of timed utomt Theoreticl Computer Science, 994,6)83~35 [0 Mnn, Z, Pnueli, A The temporl logic of rective nd concurrent systems Specifiction New York Springer-Verlg, 99 [ Bjφrner, N, Mnn, Z, Sipm, HB, et l Deductive verifiction of rel-time systems using STeP In Rus, T, Bertrn, M, eds Proceedings of the ARTS 97 Lecture Notes in Computer Science 3, New York Springer-Verlg, 997 ~43 [ Henzinger, TA, Nicollin, X, Sifkis, J, et l Symbolic model checking for rel-time systems Informtion nd Computtion, 994,)93~44 [3 Lmport, L Hybrid systems in TLA+ In Rischel, H, Rvn, AP, Nerode, A, Grossmnn, RL, eds Hybrid Systems Lecture Notes in Computer Science 736, New York Springer-Verlg, ~0 [4 Clrke, EM, Emerson, EA, Sistl, AP Automtic verifiction of finite-stte concurrent systems using temporl-logic specifictions ACM Trnsctions on Progrmming Lnguges nd Systems, 986,8)44~63

9 4 A Liner Temporl Logic with Clocks for Verifiction of Rel-Time Systems LI Gung-yun, TANG Zhi-song Key Lbortory of Computer Science, Institute of Softwre, The Chinese Acdemy of Sciences, Beijing 00080, Chin) E-mil {ligy,cst}@iosccn http //wwwiosccn Abstrct In order to specify rel-time systems, mny temporl logics such s Timed Computtion Tree Logic, Metric Intervl Temporl Logic nd Rel-Time Temporl Logic hve been proposed Although these logics re good t specifying properties of rel-time systems, they re not suitble for describing the implementtions of such systems Thus, the specifictions nd the implementtions re usully described by different lnguges for rel-time systems In this pper, new liner temporl logic with clocks, clled LTLC, is introduced It is n extension of Mnn nd Pnueli s liner temporl logic It cn express both the properties nd the implementtions of rel-time systems With LTLC, systems cn be described t mny levels of bstrction, from high-level requirement specifictions to low-level implementtion models, nd the conformnce between different descriptions cn be expressed by logicl impliction This spect of LTLC will be beneficil to the verifiction nd the stepwise refinements of rel-time systems Key words rel-time system timed utomton liner temporl logic specifiction lnguge system description lnguge property verifiction Received July 0, 000 ccepted June 0, 00 Supported by the Ntionl Nturl Science Foundtion of Chin under Grnt No the Key Sci-Tech Project of the Ntionl Ninth Five-Yer-Pln of Chin under Grnt No the Ntionl High Technology Development 863 Progrm of Chin under Grnt No ZT0-04-

Σχετικά έγγραφα

ER-Tree (Extended R*-Tree)

ER-Tree (Extended R*-Tree) 1-9825/22/13(4)768-6 22 Journal of Software Vol13, No4 1, 1, 2, 1 1, 1 (, 2327) 2 (, 3127) E-mail xhzhou@ustceducn,,,,,,, 1, TP311 A,,,, Elias s Rivest,Cleary Arya Mount [1] O(2 d ) Arya Mount [1] Friedman,Bentley