Spears Intel UMA Block Diagram

pears Intel UM lock iagram 00/0/ PU / IL LK N ILPR Intel PU Merom M F:MHz/00MHz,, Project code :.W00.00 P P/N : 0 Revision : - INPUT OUTPUT TOUT _OR YTM / TP R RT RT INPUT OUTPUT Host U /MHz LV L TOUT 0V_0 V_ RII / RII / lot 0 lot RII hannel R II hannel restline-m TL+ PU I/F R I/F INTRT RHPI LV, RT I/F,,0,,, PI x VIO VO -Vedio (Upsell) ii (Upsell) HMI (Upsell) YTM / TP0 INPUT OUTPUT V_UX_ TOUT V_ V_ MI I/F 00MHz Power W TI TP YTM / TP00 /IO/MM M/M Pro/x, Ricoh R ardreader PI INTL IH-M ZLI PI x PI x & U.0 x 0/00 NI Marvell 00 New ard RJ ONN INPUT V_ OUTPUT 0V_ YTM / LO RJ ONN (Option) igital Mic rray MI IN HP HP Internal nalog MI M MOM (Option) zalia O igmatel T ZLI T 0 U.0/. ports THRNT (0/00/000Mb) High efinition udio T /00 PI. LP I/F PI/PI RI PT,0,, PI U.0 LP us K Winbond WPL PI x & U.0 x PI x & U.0 x PI U.0 x U.0 x Mini-ard X 0.a/b/g T/UW/Robson MR (Option) Right ide: U x U x (Upsell) Lift ide: U x 0 Mini-ard X 0 WWN(Upsell) INPUT V V OUTPUT V V_0 YTM / LO INPUT OUTPUT TOUT V_UX_ V_0 MXIM HRR MX INPUT OUTPUT H PKR OP MP MX H O apacity utton Touch Pad Int. K /W IR Thermal & Fan Flash ROM M <ore esign> + T+ TOUT Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ystem lock iagram ize ocument Number Rev pears-intel - ate: Wednesday, eptember, 00 heet of

PU_OR IL TI TP0 V/V V_0 VI0 VI VI VI VI VI PUOR_ON _N _N TOUT V_0 V_0 PM_LP_# PM_LP_# VI etting VI0(I /.V) VI(I /.V) VI(I /.V) VI(I /.V) VI(I /.V) VI(I /.V) Input ignal N (I /.V) Voltage ense VN(I / Vcore) RN(I / Vcore) Input Power (I) (I) (I) Output ignal VROK() Output Power _OR_PWR(O) TI TP00 0.V/R_VRF_ Input ignal Output Power VRPWR _OR_0(Imax=) PM_LP_# V/V_N TOUT TOUT V_UX OFF _JK V_UX_ Input ignal 0_N 0_N VIN VIN FOR.V FOR.0V Input Power VFILT(I / V) Input ignal (I) Input Power (I) (I) Input ignal N_PV(I / V) dapter Output ignal (O) Output Power TP_V_ (O) Output ignal POUT(O / V) Output ignal POUT(O / V) Output Power _IN V(O) V(O) + PUOR_ON V_UX_ V_UX_ V_ () V_ () HR_OFF T+N T_L T IN V_0 V_ harger_mx Input ignal L (I /.V) L (IO / V) (IO / V) Output ignal LO (O /.V) XTL/P (O/V) TT (I /.V) XTL/P (O/V) P0/MOI/IN0 INPUT VNTL V_ PUOR_ON(Pull High V) VIN POUT(O / V) PM_LP_# V_ V_ PM_LP_# N VNTL VIN N PL V_0 V_0 Output Power (O) (O) VOUT(O) OUT VOUT(O) MX_LO TOUT T+ V_0 PUOR_ON POK V_0 V_0 PUOR_ON POK TOUT V_ Input Power (I) (I) (O) (O) 0V_R_VTT R_VRF_ V_ TOUT PM_LP_# Input Power Output Power V_PWR VIN TP_0V Input ignal Output ignal N_PV(I / V) POUT(O / V) V_ PUOR_ON + Input Power IN (I) <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. V_ TOUT VIN Input Power Output Power 0V_PWR 0V_0 () Power lock iagram ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

INTL IH-M TRP PIN 0, +RT,,,,0,,,0,,,, 0V_0 +RT 0V_0 ignal H_OUT 0 nter XOR hain,,0,,,,,0, V_0 V_0 H_YN NT# PIO0 NT# NT0# PI_# INTVRMN Reserved,,,,,,,, 0,,,,,,,0,,,0,,,,,,,,,,,,,,,,,0,,,,,,,,0,,,,,,,,,,,,,0,,,,, V_0,,,,,,,,,,,,,,0,,,,,, V_LN_ V_NW_0 integrated VccLan_0VccL_0 LN00_LP TL# PKR TP PIO/ H_OK_N# Usage/When ampled XOR hain ntrance/ PI Port onfig bit, Rising dge of PWROK PI Port onfig bit0, Rising dge of PWROK. PI Port onfig bit0, Rising dge of PWROK. Top-lock wap Override. Rising dge of PWROK. oot IO estination election. Rising dge of PWROK. Integrated Vccus_0 Vccus_ and VccL_ VRM nable/isable.lways sampled. Integrated VccLN_0 VccL_0 VRM enable /isable. lways sampled. PI LN RVRL.Rising dge of PWROK. No Reboot. Rising dge of PWROK. XOR hain ntrance. Rising dge of PWROK. Flash escriptor ecurity Override trap Rising dge of PWROK. INTL RTLIN TRP PIN F trap LOW 0 HIH F MI X MI X F Low Power PI xpress Normal Low Power mode F PI xpress raphics Lane Reversal Normal Mode(Lanes Lane Reversal number in order) F F ynamic OT isabled nabled F MI Lane Reserved Normal Operation Reserved Lane F 0 Only PI or VO PI and VO are oncurrent VO/PI is operation operation simultaneous VO_TRL_T NO VO ard VO ard Present Present VO Present F XOR/LL-Z F PI_MIO PULL-UP 0K Wistron orporation LL(00) LH(0) HL(0) HH() Reserved XOR Mode nabled ll Z Mode nabled Normal Operation omment llows entrance to XOR hain testing when TP pulled low at rising edge of PWROK.When TP not pulled low at rising edge of PWROK,sets bit of RP.P(onfig Registers:offset h) ets bit0 of RP.P(onfig Registers:Offset h) ets bit of RP.P(onfig Registers:Offset h) Weak Internal PULL-OWN.NOT:This signal should not be pull HIH. ampled low:top-lock wap mode(inverts for all cycles targeting FWH IO space). Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down. ontrollable via oot IO estination bit (onfig Registers:Offset 0h:bit :0). NT0# is M, 0-PI, 0-PI, -LP. nables integrated Vccus_0,Vccus_ and VccL_ VRM when sampled high nables integrated VccLN_0,VccL_0 VRM when sampled high This signal has weak internal pull-up. set bit of MP.LR(evice:Function0:Offset ) If sampled high, the system is strapped to the "No Reboot" mode(ihm will disable the TO Timer system reboot feature). The status is readable via the NO ROOT bit.(offset:0h:bit) This signal should not be pull low unless using XOR hain testing. Internal Pull-Up.If sampled low,the Flash escriptor ecurity will be overidden.if high,the ecurity measures defined in the Flash escriptor will be in effect. This should only be used in manufacturing environments XOR hain ntrance trap IH_RVtp 0 Z_OUT_IH 0 0 swap override strap PI_NT# OOT IO trap PI_NT#0 PI_# 0 0 LN00_LP FUL HIH No Reboot trap PKR LOW = efaule High=No Reboot.K PULL HIH escription RV Normal Operation(default) et PI port cofig bit low = swap override enable high = default OOT IO Location PI PI LP(efault) integrated Vccus_0,Vccus_,VccL_ M_INTVRMN High=nable Low=isable High=nable Low=isable INTL IH-M INTRT PULL-UP and PULL-OWN INL H_IT_LK H_RT# H_IN[:0] H_OUT H_YN NT[:0] PIO[0] L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PM# PWRTN# TL# PI_# PI_LK PI_MOI TH_[:0] PKR TP[] U[:0][P,N] L_RT# Resistor Type/Value PULL-OWN 0K NON PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN K T V_, V_LN_ V_UX_, V_LN_ V_,,0, V_UX_,,,0,,,,0,,,,, <ore esign> V_0 V_0 V_,, + TOUT,,, R_VRF_0,,, R_VRF_ +LV,, _OR_0 V_0 V_LN_ V_NW_0 V_ V_LN_ V_UX_ V_LN_ V_0 V_ V_UX_ V_0 V_ + TOUT R_VRF_0 R_VRF_ +LV _OR_0 F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Table of ontent -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of

V_0 V_0_K0 R 0R00-P V_0_K0 V_0_K0_IO V_0 U0VKX-P R U0VKX-P 0R00-P 0UVKX-P 0UVKX-P UVZY-P UVZY-P LKTRQ# LKRQ#_ PLK_PM PLK_K LK_PI_IH UVZY-P UVZY-P UVZY-P UVZY-P P0VJN--P LK_M_IH F U_MHZ/FL LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PI_MINI_ LK_PI_MINI_# LK_PI_LN LK_PI_LN# LK_PI_NW LK_PI_NW# RN LK_PI_MINI_ LK_PI_MINI_# LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PI_MINI 0 LK_PI_MINI# 0 LK_PI_LN LK_PI_LN# LK_PI_MINI LK_PI_MINI# LK_PI_NW RN0J--P LK_PI_NW# V_0 R 0KRJ--P R NWR_LKRQ# 0KRJ--P LK_PI_MINI 0 RN--P LK_PI_MINI# 0 LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# LK_M_IH V_0_K0 P0VN-P F F Please place R0 near U pin Main source :.0.0 ILPRKLFT nd source:.00.0 RTMN-0-LF LK_PI_T LK_PI_T# MH_RFLK MH_RFLK# RN RN0J--P LK_MH_RFLK LK_MH_RFLK# RN RN0J--P NWR_LKRQ# :0/ dd, on LK_MH_RFLK -/+ pair. LK_MH_RFLK LK_MH_RFLK# LK_PI_T 0 LK_PI_T# 0 MH_RFLK MH_RFLK# LK_MH_RFLK LK_MH_RFLK# PI_TM 0 Output Overclocking of PU and R allowed Overclocking of PU and R not allowed F_ F_ F_ PU 0 00M 0 0 M 0 0 00M 0 M UVZY-P R H_TP_PI# H_TP_PU#,, IH_MLK,, IH_MT K_PWR RJ--P RN LK_PI_MINI_ RN LK_PI_MINI_# RN0J--P RN--P UVZY-P UVZY-P X LK_XTL_IN LK_XTL_OUT X-M-P R0 RJ--P R RJ--P R RJ--P P0VJN--P V_0_K0_IO LK_XTL_IN P0VN-P LK_XTL_OUT X X 0 UVZY-P RN RN0 RN P0VN-P RN RN0J--P R 0KRJ--P P0VJN-P RN--P RN0J--P P0VN-P 0 R RJ--P P0VJN-P PI_TOP# PU_TOP# LK T K_PWR/P# PI0/R#_ 0 PI_TM PI/R#_ PLK_PM_R PI/TM _L PI ITP_N PI/_LT PI_F/ITP_N VRF V VPI VR VPU VPLL V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO U PUT0 PU0 0 PUT_F PU_F PUT_ITP/RT PU_ITP/R RT/R#_F R/R#_ 0 RT R RT0 R0 RT/R#_H 0 R/R#_ RT R RT R RT/R#_ R/R#_ RN RN RN RN0J--P RN0J--P RN0J--P R 0KRJ--P PI_TM R 0KRJ--P P0VN-P FL/TT_MO RF0/FL/TT_L N# N NPI NRF N NR NR NR NPU N 0 RT/TT R/T MHZ_NON/RT/ MHZ_/R/ N RT0/OTT_ 0 R0/OT_ ILPRKLFT-P _L P0VJN-P ITP_N R0 0KRJ--P ITP_N Output 0 R PU_ITP PU_L PU_L PU_L0 R0 KRJ--P R 0R00-P R KRJ--P R 0R00-P F F F MH_LKL0 _L strap 0:For M, :For PM _L PIN 0 PIN PIN PIN 0 OTT OT RT/LT_00 RT/LT_00 M RT0 R0 M_N M_ PM esign Note:. ll of Input pin didn't have internal pull up resistor.. lock Request (R) function are enable by registers.. Y integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic. R 0R00-P R 0R00-P :00 MH_LKL MH_LKL <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. lock generator ILPR -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of

H_T#0 H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_#[..] H_T# 0 H_0M# 0 H_FRR# 0 H_INN# 0 H_TPLK# 0 H_INTR 0 H_NMI 0 H_MI# TP TP TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP0 TP TP TP TP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_T#0 H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_T# H_0M# H_FRR# H_INN# PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 PU_RV0 J # L # L # K # M # N # J # N 0# P # P # L # P # P # R # M T0# K RQ0# H RQ# K RQ# J RQ# L RQ# Y # U # R # W 0# U # Y # U # R # T # T # W # W # Y # U 0# V # W # # # # V T# 0M# FRR# INN# TPLK# LINT0 LINT MI# M RV#M N RV#N T RV#T V RV#V RV# RV# RV# RV# RV# F RV#F U OF KY_N RRV KT-PUP-P R ROUP 0 R ROUP IH XP/ITP INL ONTROL # H NR# PRI# FR# H R# F Y# R0# F IRR# 0 INIT# LOK# H RT# R0# F R# F R# TR# HIT# HITM# PM0# PM# PM# PM# PR# PRQ# TK TI TO TM TRT# R# 0 THRML PROHOT# THRM THRM THRMTRIP# HLK LK0 LK H_# H_NR# H_PRI# H_FR# H_R# H_Y# H_R0# H_IRR# H_INIT# H_LOK# H_RT# H_R#0 H_R# H_R# H_TR# H_HIT# H_HITM# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# XP_RT# PU_PROHOT H_THRM H_THRM H_THRMTRIP# LK_PU_LK LK_PU_LK# H_# H_NR# H_PRI# H_FR# H_R# H_Y# H_R0# H_INIT# 0 H_LOK# H_RT# H_R#0 H_R# H_R# H_TR# H_HIT# H_HITM# TP TP TP TP TP TP TP TP H_THRMTRIP#,0,, LK_PU_LK LK_PU_LK# layout note:zo = ohm, 0." MX for TLRF 0V_0 R RJ--P R RJ--P 0V_0 H_THRM H_THRM H_THRM, H_THRM routing together, Trace width / pacing = 0 / 0 mil XP_TI XP_TM R R 0RF--P RF-P 0V_0 XP_TRT# XP_TK R R RF-P RF-L-P PU_PROHOT R 0RJ--P PU_PROHOT# <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-TL+/XP ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

H_#[0..] UVKX-P H_TN#0 H_TP#0 H_INV#0 PU_L0 PU_L PU_L H_TN# H_TP# H_INV# V_PU_TLRF TP TP TP TP TP TP H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_TN#0 H_TP#0 H_INV#0 H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TN# H_TP# H_INV# PU_L0 PU_L PU_L PL close to the TT PIN, make sure TT,TT,TT trace routing is reference to N and away other noisy signals PU_L PU_L PU_L PU_L0 00 0 TP TP TP TP 0 0 U OF 0# F # # # F # # # # K # # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# N # K # P # R # L 0# M # L # M # P # P # P # T # R # L # T 0# N # L TN# M TP# N INV# TT TLRF TT TT TT TT TT TT F TT TT F TT TT TT L0 L L KT-PUP-P T RP0 T RP T RP T RP MI # Y # # V # V # V # T # U # U 0# Y # W # Y # W # W # # # TN# Y TP# INV# U # # 0# # # # # 0 # # F # # # 0# # # F # TN# TP# F INV# 0 OMP0 R OMP U OMP OMP Y PRTP# PLP# PWR# PWROO LP# PI# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_TN# H_TP# H_INV# OMP0 OMP OMP OMP H_PRTP# H_PLP# H_PWR# H_PULP# PI# R R R R H_TN# H_TP# H_INV# H_TN# H_TP# H_INV# RF-L-P RF-L-P RF-L-P RF-L-P H_PRTP#,0, H_PLP# 0 H_PWR# H_PULP# PI# Resistor Placed within 0." of PU pin. Trace should be at least mils away from any other toggling signal. OMP[0,] trace width is mils. OMP[,] trace width is mils. H_PWROO 0, _OR_0 U OF 0 0 0 0 0 0 0 0 F F F0 F F F F F F0 0 0 0 0 KT-PUP-P 0 0 0 0 F F0 F F F F F F0 P P V P J P K P M P J P K P M P N P N P R P R P T P T P V P W VI0 VI F VI VI F VI VI F VI N N F _OR_0 PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI _N _N PU_VI[0..] _N _N 0V_0 0 0UVKX-P V_0 0UVKX-P Length match within mils. The trace width/space/other is 0//. _N R0 00RF-L-P-U _N R 00RF-L-P-U layout note: place near PIN 0UVKX-P _OR_0 Place near R and R UVKX-P 0V_0 R KRF--P V_PU_TLRF R KRF--P lose to PU pin Z0= ohm with in 00mils. <ore esign> lose to PU pin within 00mils Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-TL+/PWR -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of

_OR_0 U F F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P OF P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F 0V_0 Place these capacitors on L (North side,econdary Layer) Place these capacitors on L (North side,econdary Layer) UVKX-P UVKX-P _OR_0 0UVKX-P _OR_0 0UVKX-P 0UVKX-P 0 UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P Mid Frequencd ecoupling UVKX-P Place these inside socket cavity on L (North side econdary) KT-PUP-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. Meron(/)-N&ypass ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

H_#[0..] RF-L-P 0V_0 0V_0 U0 OF 0 H_VRF H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WN H_ROMP H_ROMP 0V_0 H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_WN H_# H_T#0 H_T# H_NR# H_PRI# H_R0# H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_#[..] PLT_RT_R# M_ROMP_VOH M_ROMP_VOL H_OMP W H_RQ#0 H_OMP# H_OMP H_RQ#0 M H_RQ#0 W H_RQ# H_OMP# H_RQ# H_RQ# TP H_RQ# H_RQ# H_RT# H_RQ# H_RQ# H_RT# H_RQ# H_PULP# H_PURT# H_RQ# H TP H_RQ# H_PULP# H_PULP# H_RQ# H_RQ# TP TP H_R#0 H_VRF H_R#0 H_R# H_R#0 H_VRF H_R# H_R# H_R# H_VRF H_R# H_R# PM_MUY# N:.M.0U,0, H_PRTP# RTLIN-P-U-NF PM_XTT#0 PM_XTT# layout note : Route H_OMP and H_OMP# with trace width, spacing and impedance ( ohm) same as F data traces,0,, H_THRMTRIP#, PRLPVR Layout Note : H_ROMP / H_VRF / H_WN trace width and spacing is 0/0 R R RF-L-P R KRF--P R KRF--P UVZY-P Layout Note : Place within 00 mils of N H_#0 H_# H_# M H_# H H_# H H_# H_# F H_# N H_# H H_# M0 H_#0 N H_# N H_# H H_# P H_# K H_# M H_# W0 H_# Y H_# V H_# M H_#0 J H_# N H_# N H_# W H_# W H_# N H_# Y H_# Y H_# P H_# W H_#0 N H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# Y H_# H_# H_# H_# H_# J H_# H H_# J H_#0 H_# H_# H H_# J H_# H H_# J H_# H_# J H_# J H_# H_#0 J H_# H H_# H H_# H_WIN H_ROMP R0 RF-L-P HOT 00RF-L-P-U RF--P H_# J H_# H_# H_# M H_# H_# F H_# L H_#0 H_# H_# K H_# H_# L H_# J H_# H_# K H_# P H_# R H_#0 H_# H0 H_# L H_# H_# M H_# N H_# J H_# H_# H_# H_#0 H_# H_# H_# H_# H_# N H_# H_# H_T#0 H_T#0 H H_T# H_T# 0 H_NR# H_NR# H_PRI# H_PRI# H_R0# H_RQ# F H_FR# H_FR# H_Y# H_Y# 0 LK_MH_LK HPLL_LK M LK_MH_LK# HPLL_LK# M H_PWR# H_PWR# H H_R# H_R# K H_HIT# H_HIT# H_HITM# H_HITM# H_LOK# H_LOK# 0 H_TR# H_TR# H_INV#0 K H_INV# L H_INV# H_INV# H_TN#0 M H_TN# K H_TN# H_TN# H H_TP#0 L H_TP# K H_TP# H_TP# J0 pec: H_WIN=0. X VTT +/- % R R UVZY-P Layout Note : Place near pin of N, PM_PWROK, VT_PWR 0 TV_ONL0 0 TV_ONL UVKX-P UVKX-P PM_XTT#0 PM_XTT# TV_ONL0 TV_ONL LKRQ#_ 0UVKX-P 0UVKX-P V_ MH_LKL0 MH_LKL MH_LKL F[:] have internal pull up F[:] have internal pull down R R 0RJ--P R 0RJ--P 00RJ--P RN RN0KJ--P R KRF--P R K0RF--P R KRF--P TP TP TP TP TP TP TP TP TP PM_POK_R PLT_RT#,,,,,0, R 0KRJ--P V_0 PM_MUY# H_PRTP# PM_XTT#0 PM_XTT# PM_POK_R PLT_RT_R# H_THRMTRIP# PRLPVR U0 OF 0 P RV#P P RV#P R RV#R N RV#N R RV#R R RV#R M RV#M N RV#N J RV#J R RV#R M RV#M L RV#L M RV#M 0 RV#0 H0 RV#H0 RV# J0 RV#J0 K RV#K F RV#F H0 RV#H0 K RV#K J RV#J F RV#F RV# RV# RV# H RV#H W0 RV#W0 K0 RV#K0 RV# RV# RV# RV# RV# RV# RV# MH_LKL0 P MH_LKL F0 N MH_LKL F N F F F F F F F N F F F F J0 F F 0 F0 F R F F0 L F F J F F F 0 F K F F M0 F M F F L F F N F0 F L F0 PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# N0 THRMTRIP# PRLPVR J N#J K N#K K0 N#K0 L0 N#L0 L N#L L N#L L N#L K N#K J N#J N# N# N# 0 N#0 0 N#0 N# K N#K RV F PM N RTLIN-P-U-NF R MUXIN N:.M.0U M_LK_R0 M_K0 V M_LK_R M_K M_LK_R M_K M_LK_R M_K V M_LK_R#0 M_K#0 W0 M_LK_R# M_K# M_LK_R# M_K# W M_LK_R# M_K# W R_K0_IMM M_K0 R_K_IMM M_K Y R_K_IMM M_K R_K_IMM M_K R_0_IMM# M_#0 0 R IMM# M_# K R IMM# M_# R IMM# M_# M_OT0 H M_OT J M_OT J M_OT M_ROMP_VOH M_ROMP_VOL M_OT0 M_OT M_OT M_OT LK_MH_RFLK LK_MH_RFLK# MH_RFLK MH_RFLK# LK_MH_PLL LK_MH_PLL# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FT_VI0 FT_VI FT_VI FT_VI FT_VR_N PM_POK_R L_VRF M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# R_K0_IMM R_K_IMM R_K_IMM R_K_IMM R_0_IMM# R IMM# R IMM# R IMM# M_OT0 M_OT M_OT M_OT MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP L_RT# V_ LK_MH_RFLK LK_MH_RFLK# MH_RFLK MH_RFLK# LK_MH_PLL LK_MH_PLL# L_LK0 L_T0 VO_TRLLK VO_TRLT MH_IH_YN# LKRQ#_ MH_IH_YN# <ore esign> FOR alero: 0. ohm restline: 0 ohm M_ROMP M_ROMP L M_ROMP# R 0RF-P M_ROMP# K R 0RF-P R_VRF_ M_VRF#R R R_VRF_ M_VRF#W W PLL_RF_LK PLL_RF_LK# PLL_RF_LK H PLL_RF_LK# H LK MI MI M RPHI VI P_LK K P_LK# K MI_RXN0 N MI_RXN J MI_RXN N MI_RXN N MI_RXP0 M MI_RXP J MI_RXP N MI_RXP N MI_TXN0 J MI_TXN J MI_TXN M0 MI_TXN M MI_TXP0 J MI_TXP J MI_TXP M MI_TXP M FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK M L_T K0 L_PWROK T L_RT# N L_VRF M0 VO_TRL_LK H VO_TRL_T K LKRQ# IH_YN# 0 K M_ROMP_VOH L M_ROMP_VOL TP TP TP TP TP0 TT_MH TT R TT_MH TT R 0R00-P R 0KRJ-L-P V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-TL+/MI/R -Intel - ize ocument Number Rev ustom ate: Wednesday, eptember, 00 heet of UVKX-P R KRF--P R RF-P

R [0..] R [0..] R [0..] R [0..] R M[0..] R M[0..] R Q[0..] R Q[0..] R Q#[0..] R Q#[0..] R M[0..] R M[0..] U0 OF 0 U0 OF 0 R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R W Y R R T W F J 0 H W 0 F H 0 F0 R0 W0 T W W Y V T V T W V U T 0 0 Y 0 W Y T T Y R R R N M N0 T N M N _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q R YTM MMORRY _0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M _M _M _M _M _M _M _M _M0 _M _M _M _M _R# _RVN# _W# K F L T W W Y N T H P T H P R 0 R R R # R M0 R M R M R M R M R M R M R M R Q0 R Q R Q R Q R Q R Q R Q R Q R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# J R M0 0 K R M R M H R M L R M K J J R M R M R M L R M R M R M0 R M 0 R M J R M J R M Y0 R R# _RVN# R W# TP0 R 0 P R 0 R Q0 _0 Y R R R Q _ W0 R R Q _ W R Q R # R # N R Q _# R # N0 R Q V0 R M0 R Q _M0 R0 V R M R Q _M 0 R M R Q _M K 0 R M R 0 _Q _M L R M R Q0 _M H 0 R M R Q _M J R M R Q _M F Y R M R Q _M W F0 R Q F R Q0 R Q _Q0 T0 J0 R Q R Q _Q 0 J R Q R Q _Q K J R Q R Q _Q K L R Q R 0 _Q _Q J K R Q R Q0 _Q L K R Q R Q _Q K R Q R Q _Q V K R Q#0 R Q _Q#0 U0 J R Q# R Q _Q# 0 L R Q# R Q _Q# L J R Q# R Q _Q# K J R Q# R Q _Q# K K R Q# R Q _Q# K J0 R Q# R 0 _Q _Q# F L R Q# R Q0 _Q# V K R Q K R M0 R Q _M0 R M R Q _M K R M R Q _M R M R Q _M W R M R Q _M F R M R Q _M R M R Q _M R M R 0 _Q _M J0 R M R Q0 _M Y L R M R Q _M K R M0 R Q _M0 L R M R Q _M K R M R Q _M K0 R M R Q _M J R M R Q _M J R Q R R# R R# F R Q _R# V _RVN# R R# H TP R 0 _Q _RVN# Y R Q0 R W# R W# R Q _W# R W# K R Q R Q R Q J R Q R Q R Q R R Q T R 0 _Q Y R Q0 Y R Q U R Q T _Q R YTM MMORY RTLIN-P-U-NF N:.M.0U RTLIN-P-U-NF N:.M.0U <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-R / H ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

M_OMP M_LUM M_RM M_LU M_RN M_R 0V_0 For restline :. Kohm For alero :.Kohm -:00 hang R from.0.l to.0.l LKLT_TL MH_L_ON V_0 L_LK L_T LV_N V_TXOUT0+ V_TXOUT+ V_TXOUT+ M_OMP M_LUM M_RM TV_ONL0 TV_ONL M_LU M_RN M_R MH_LK MH_T MH_VYN MH_HYN N_VO_R- V_TXLK- V_TXLK+ V_TXLK- V_TXLK+ V_TXOUT0- V_TXOUT- V_TXOUT- V_TXOUT0- V_TXOUT- V_TXOUT- V_TXOUT0+ V_TXOUT+ V_TXOUT+ R 0RF--P R 0RF--P RN TV_ONL0 TV_ONL RN0KJ--P R KRF--P R 0RF--P R 0RF--P R 0RF--P R 0RF--P LV_I TP RN RT_VYN RT_HYN RNJ--P-U RTIRF R0 KRF--P :0 FOR alero: ohm restline:.k ohm U0 OF 0 J0 L_KLT_TRL H L_KLT_N L_TRL_LK 0 L_TRL_T L LK L T K0 L_V_N L LV_I L LV_V N LV_VRFH N0 LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#0 LV_T# F LV_T# LV_T# 0 LV_T0 0 LV_T F LV_T LV_T LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T TV_ TV_ K TV_ F TV_RTN J TV_RTN L TV_RTN M TV_ONL0 P TV_ONL H RT_LU RT_LU# K RT_RN J RT_RN# F RT_R RT_R# K RT LK RT T RT_VYN RT_TVO_IRF F RT_HYN LV TV V RTLIN-P-U-NF PI_XPR RPHI N:.M.0U P_OMPI N P_OMPO M P_RX#0 J P_RX# L P_RX# N P_RX# T P_RX# T0 P_RX# U0 P_RX# Y P_RX# Y0 P_RX# P_RX# W P_RX#0 P_RX# 0 P_RX# P_RX# H P_RX# P_RX# P_RX0 J0 P_RX L0 P_RX M P_RX U P_RX T P_RX T P_RX W P_RX W P_RX 0 P_RX Y P_RX0 P_RX P_RX H P_RX P_RX H P_RX P_TX#0 N P_TX# U P_TX# U P_TX# N P_TX# R0 P_TX# T P_TX# Y P_TX# W P_TX# W P_TX# P_TX#0 P_TX# P_TX# P_TX# H P_TX# P_TX# H P_TX0 M P_TX T P_TX T P_TX N0 P_TX R P_TX U P_TX W P_TX Y P_TX Y P_TX P_TX0 P_TX 0 P_TX P_TX P_TX 0 P_TX H R RF-L-P POMP N_VO_R+ N_VO_+ N_VO_+ N_VO_+ POMP trace width and spacing is 0/ mils. VO_INT- VO_INT+ N_VO_- 0 N_VO_R- N_VO_- N_VO_- N_VO_- N_VO_- N_VO_- N_VO_R+ 0 N_VO_+ N_VO_+ N_VO_+ U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P F[:0] F Freq select F (MI select) F F (PU trap) F (Low power PI) F[:] trap Pin Table F (PI raphics Lane Reversal) F[:0] F[:] (XOR/LLZ) F[:] F (F ynamic OT) VO_R- VO_- VO_- VO_- VO_R+ VO_+ VO_+ VO_+ 0 = isable nable * Reversed VO_TRLT 0 = No VO evice Present * = VO evice Present F(MI Lane Reversal) F0(PI/VO consurrent) 00 = F 00MHz 0 = F MHz Others = Reserved 0 = MI x = MI x * Reserved 0 = Reserved = Mobile PU * 0 = Normal mode = Low Power mode * 0 = Reverse Lane = Normal Operation * Reserved 00 Reserved 0 XOR Mode nabled 0 ll Z Mode nabled = Normal Operation (efault)* Reserved 0 = Normal Operation * (Lane number in Order) = Reverse lane 0 = Only PI or VO is operational * = PI/VO are operating simu. V_0 RN L_LK L_T RN0KJ--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-V/LV/TV ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet 0 of

V_0 UVZY-P V_0 RT UVZY-P V_0_TV 0UVKX-P V_0_TV 0UVKX-P UVZY-P V_0_TV 0 0UVKX-P R V_0 V_0 V_0 V_0 :0/0 hange R,R from 00 close pad to.00000.00l V_0 Place T near R and R 0UVKX-P 0R-0-U-P R 0UVKX-P _TV R 0R00-P UVZY-P _TV R 0R00-P _TV R 0R00-P UVZY-P 0R-0-U-P T UVMX-P U0VKX-P 0 0UVKX-P V_0 RT V_0 V_0_PLL V_0_PLL V_0_MPLL V_0_TXLV -:00 V_0 U0VKX-P 0 UVZY-P V_0_HPLL UVZY-P V_0_PPLL UVZY-P U0VKX-P V_0_TV V_0_TV V_0_TV V_0 V_0 V_0 V_0_PPLL V_0_LV V_0 V_0 00u 0m V_0_LV 0mil N:.M.0U 0UVKX-P UVZY-P 0UVKX-P KP0VKX-P UVZY-P J _YN _RT RT_ 0 H L M K0 K U _PLL _PLL _HPLL _MPLL _LV _LV _P P P_PLL W _M V _M U _M U _M U _M T _M T _M T _M T _M T _M R _M_NTF R _M_NTF _M_K _M_K _TV TV TV TV TV TV_ M _RT L _TV N N U U0H OF 0 _Q _HPLL _P_PLL J _LV H _LV Place 0,0 0near Pin N R 0R00-P U0VKX-P LV PLL RT P LV TV/RT RTLIN-P-U-NF TV K M V_ X MI M K VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT T VTT T VTT T0 VTT T VTT T VTT T VTT T VTT T VTT T VTT R VTT R VTT R _X T _X U _X U _X T _X T _X T0 _X_NTF XF P V_0_TXLV 0mil R _XF _XF _XF _MI J0 _M_K K _M_K K _M_K J _M_K J _TX_LV HV _HV 0 _HV 0 _P _P W0 _P W _P V _P V0 _RXR_MI H0 _RXR_MI H VTTLF VTT POWR VTTLF VTTLF F VTTLF H 0UVKX-P 0V_0 VTTLF VTTLF VTTLF R 0R00-P KP0VKX-P UVZY-P 0UVKX-P U0VKX-P V_0 V_0_TXLV 0V_0 0mil 0 UVZY-P V_ 0 V_0 V_ 0 UVZY-P UVKX-P UVKX-P UVZY-P U0VKX-P 0 0UVKX-P UVZY-P V_0_HV V_0 UVZY-P UVZY-P V_0 L LMPN-P L nd source.00.0/.00. _TV V_0_PLL V_0_HPLL V_0_PLL 0V_0 0V_0 V_0 V_0 V_0_PPLL L V_0 LMPN-P 0UVKX-P 0UVKX-P 0UVKX-P UVZY-P 0UVKX-P 0 UVZY-P UVZY-P 0 UVZY-P --P L LMN-P 0UVKX-P 0UVKX-P L L-0UH--P UVZY-P L L-0UH--P 0 0UVKX-P V_0 Place,, near Pin,W0,W <ore esign> V_0 0UVKX-P V_ 0UVKX-P V_0 0UVKX-P UVZY-P V_0_MPLL 0V_0_ V_0 R0 R 0R00-P 0RJ--P 0 0UVKX-P UVZY-P 0 V_0 UVZY-P V_0_HV Place,0 near Pin,, 0 UVZY-P 0 Place, near Pin K,K,J,J Place, near Pin M,L Place near Pin N L V_0 LMN-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of UVZY-P UVKX-P

V_ 0UVKX-P T T0UVM-P 0UVKX-P 0UVKX-P 0V_0 U0VKX-P UVZY-P UVZY-P 0V_0 UVZY-P 0UVKX-P T T H K J J H H H F R0 U0F OF 0 OR U _M U _M U _M V _M W _M W _M Y _M _M _M _M _M _M _M _M _M _M _M _M _M F _M F _M _M _M _M H _M H _M H _M J _M J _M J _M K _M K _M K _M K _M L _M U0 _M R0 _X T _X W _X W _X Y _X 0 _X _X _X _X _X _X _X 0 _X _X _X _X _X _X _X 0 _X _X _X _X F _X F _X _X H0 _X H _X H _X H _X H _X _X J0 _X N _X LI POWR M FX RTLIN-P-U-NF FX NTF M LF _X_NTF T _X_NTF T _X_NTF T _X_NTF T _X_NTF T _X_NTF T _X_NTF T _X_NTF U _X_NTF U _X_NTF U _X_NTF U _X_NTF U0 _X_NTF U _X_NTF U _X_NTF U _X_NTF V _X_NTF V _X_NTF V _X_NTF V0 _X_NTF V _X_NTF V _X_NTF V _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF Y0 _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF Y _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF F _X_NTF F _X_NTF H _X_NTF H _X_NTF H _X_NTF H _X_NTF J _X_NTF J _X_NTF J _X_NTF K _X_NTF K _X_NTF L _X_NTF L _X_NTF L _X_NTF L0 _X_NTF L _X_NTF L _X_NTF M _X_NTF M _X_NTF M _X_NTF M0 _X_NTF M _X_NTF M _X_NTF P _X_NTF P _X_NTF P _X_NTF P _X_NTF P0 _X_NTF P _X_NTF P _X_NTF P _X_NTF R0 _X_NTF R _X_NTF R _X_NTF R _X_NTF R _X_NTF V _X_NTF V _X_NTF V _X_NTF Y _M_LF W _M_LF _M_LF _M_LF _M_LF _M_LF W _M_LF T N:.M.0U 0V_0 M_LF M_LF M_LF M_LF M_LF M_LF M_LF 0 UVZY-P UVZY-P UVZY-P 0 U0VKX-P U0VKX-P UVKX-P U0VKX-P UVZY-P U0VKX-P U0VKX-P T T0UVM-P 0UVKX-P 0 U0VKX-P 0 0UVKX-P U0VKX-P -:00 0UVKX-P 0 0V_0 U0VKX-P 0 UVZY-P 0 U0VKX-P 0V_0 0UVKX-P UVZY-P UVZY-P 00 UVZY-P U0 OF 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF F _NTF F _NTF H _NTF H _NTF H _NTF H _NTF J _NTF J _NTF K _NTF K _NTF K _NTF K _NTF _NTF J _NTF M _NTF L _NTF L _NTF _NTF _NTF _NTF P _NTF P _NTF R _NTF R _NTF Y _NTF Y _NTF Y _NTF Y _NTF Y _NTF T0 _NTF T _NTF T _NTF U _NTF U _NTF U _NTF U _NTF U _NTF U _NTF V _NTF V _NTF V _NTF V _NTF NTF NTF L _XM_NTF L _XM_NTF L _XM_NTF M _XM_NTF M _XM_NTF M _XM_NTF M _XM_NTF M _XM_NTF M _XM_NTF P _XM_NTF P _XM_NTF P _XM_NTF P _XM_NTF L _XM_NTF L _XM_NTF L _XM_NTF R _XM_NTF R _XM_NTF R _XM_NTF RTLIN-P-U-NF <ore esign> _NTF T _NTF T _NTF U _NTF U _NTF V _NTF V _NTF _NTF _NTF _NTF _NTF _NTF F _NTF F _NTF K _NTF M _NTF M _NTF P _NTF P _NTF R _NTF R _NTF R POWR XM XM NTF L _ L XM T _XM T _XM K _XM K _XM K _XM J _XM J NTF_U- NTF_U- NTF_U- NTF_U- 0V_0 TP TP TP TP Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR/N -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of

U0I OF 0 U0J 0 OF 0 0 0 0 0 F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T U U U U U U U V V W W W RTLIN-P-U-NF W W W W W Y0 Y Y Y Y Y Y Y0 0 0 0 0 0 0 F F F H H0 H H H J J J J J J K K K K K K0 K K K L L L L L L N:.M.0U 0 0 F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N P P P P P0 R T T T U U U0 V V W W W W W W Y Y Y Y Y Y Y0 Y P T T T R F F T V H0 RTLIN-P-U-NF N:.M.0U <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RTLIN(/)-PWR/N ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

M Layout Note: Place near M R Q#[0..] R [0..] R M[0..] R Q[0..] R M[0..] R [0..] R M0 R M R M R M R M R M R M R M R M R M R M0 R M R M R M R M R MH 0 0 00 0 0 MH 0 0/P _ MH Q0 Q Q Q Q Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# MH 0 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# :00 For MI request M_LK_R0 M_LK_R#0 0P0VJN-P put near connector M_LK_R M_LK_R# 0P0VJN-P V_ Layout Note: Place one cap close to every pullup resistors terminated to +0.V R_VRF_0 R M R M R M R M UVZY-P UVZY-P R M R M0 R 0 R W# R # R M M_OT R IMM# UVZY-P UVZY-P UVZY-P UVZY-P change to PR RN RN RN RNJ--P RNJ--P RNJ--P UVZY-P UVZY-P R_VRF_0 UVZY-P UVZY-P RN RN0 RN 0 RNJ--P RNJ--P RNJ--P UVZY-P UVZY-P UVZY-P R M R R_K0_IMM R M0 R M R M R M UVZY-P M_OT0 R_0_IMM# R R# R UVZY-P 0UVKX-P UVZY-P UVZY-P Layout Note: Place these resistors closely M,all trace length Max=.",,,, R_VRF_ PM_XTT#0 R_0_IMM# R IMM# R_K0_IMM R_K_IMM R R# R # R W# IH_MLK IH_MT M_OT0 M_OT R 0 R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R R R R R R R 0 R R R R_0_IMM# R IMM# R_K0_IMM R_K_IMM R R# R # R W# IH_MLK IH_MT M_OT0 M_OT R_VRF_ 0 0 0 0 0 0 0 0 0 0 0 0 0 M0 0 0 M M M Q0 M 0 Q M Q M 0 Q M Q Q K0 0 Q K0# Q K Q K# Q Q0 0 Q 00 Q Q V_P Q Q Q V Q V Q V Q V Q0 V Q V Q V 0 Q V 0 Q V Q V Q V Q V Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q Q Q Q Q0 Q Q Q N#0 N# N# N#0 N#/TT 0 0# # K0 K R# # W# L OT0 OT 0 VRF N N 0 R M0 R M R M R M R M R M R M R M M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# 0 R 0R00-P R 0R00-P V_ UVZY-P M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# :0 V_0 UVKX-P 0P0VJN-P 0P0VJN-P RN RNJ--P R M R M R M R_K_IMM UVZY-P UVZY-P KT-OIMM00-P Main ource:.00. nd ource:.00. Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom -Intel - Wednesday, eptember, 00 ate: heet of

M_LK_R M M_LK_R# Layout Note: Place near M V_ UVZY-P R_VRF_0 R 0 R M0 R M R M R IMM# R R R# R M0 M_OT R IMM# R # R W# R M0 0 R R# R R# R M 0 R# 0 R W# R Q#[0..] 0 R M W# 0 R W# 00 R # R M # R # R [0..] R M R IMM# R M 0# 0 R IMM# R IMM# R M[0..] R M # R IMM# R M R_K_IMM R Q[0..] R M K0 R_K_IMM R_K_IMM R M K 0 R_K_IMM R M[0..] R M0 put near connector 0 M_LK_R R M 0/P K0 0 M_LK_R M_LK_R# R [0..] 0 R M K0# M_LK_R# M_LK_R R M M_LK_R R M K M_LK_R M_LK_R# M_LK_R# K# M_LK_R# R R M0 :00 For MI request / M0 0 R M R 0 M 0 R M 0 R 0 M 0 R M M R M M 0 R M R 0 M R M R Q0 M 0 R M R Q M 0 0 0 0 R Q R Q IH_MT IH_MT,, R Q IH_MLK IH_MLK,, R Q L R Q V_0 R Q VP R Q R 0R00-P R 0 Q 0 R 0KRJ--P V_0 R Q0 00 :0 UVZY-P UVKX-P R Q 0 PM_XTT# R Q N#0 0 R Q N# R Q N# R Q N#0 0 R Q N#/TT R Q V_ R Q R 0 Q V R Q0 V R Q V R Q V R Q V R Q V R Q V 0 R Q V 0 R Q V R Q V R 0 Q V R Q0 V R Q R Q R Q R Q R Q R Q R Q R Q R 0 Q R Q0 R Q R Q R Q 0 R Q R Q 0 R Q R Q R Q R 0 Q R Q0 R Q R Q 0 R Q 0 R Q R Q R Q R Q R Q R 0 Q 0 R Q0 R Q Layout Note: R Q R_VRF_0 Q Place these resistors R Q#0 RN RN closely M,all R Q# Q0# R M trace length Max=." R Q# Q# R M R Q# Q# R M R Q# Q# R M R Q# Q# R Q# Q# RNJ--P RNJ--P R Q# Q# 0 Q# RN RN R Q0 R M R Q Q0 R M R Q Q R M R Q Q 0 R M R Q Q R Q Q RNJ--P RNJ--P R Q Q R Q Q Q RN RN0 R M M_OT M_OT M_OT R_VRF_ M_OT M_OT OT0 OT R_VRF_ 0 RNJ--P VRF RNJ--P RN 0 0 N N 0 R_K_IMM UVZY-P MH R M UVZY-P MH MH MH R M Layout Note: Place one cap close to every pullup resistors terminated to +0.V UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P RNJ--P RN RNJ--P UVZY-P UVZY-P UVZY-P UVZY-P R_K_IMM R UVZY-P 0UVKX-P UVZY-P KT-OIMM00-P Main ource:.00. nd ource:.00. 0P0VJN-P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RII-OIMM LOT ize ocument Number Rev ustom -Intel - Wednesday, eptember, 00 ate: heet of 0P0VJN-P 0P0VJN-P 0P0VJN-P

HMI I/F & ONNTOR R 0R00-P R 0R00-P HMI_TX# HMI_TX# HMI_TX#_ HMI_TX#0 HMI_TX#0 HMI_TX#0_ V_0 U V_HMI_ L L HH-0PT :0/ dd HH for HMI M0H-00-P M0H-00-P HMI_LK HMI_LK_ M bus clock pull up to V_0. V_HMI_ N00PT :0/ HMI pin connect to V_0 V_0 R HMI_TX HMI_TX_ HMI_TX0 HMI_TX0_ directly. HMI_TX HMI_TX0 :0/ dd 0RJ--P R,R(.R00.L) HMI ONN R 0R00-P R 0R00-P RN RNKJ--P HMI R 0R00-P R 0R00-P :0/ hange R,R from HMI_TX#0_ +V_POWR.R00.L to ZZ.R00.ZZZ HMI_TX# HMI_TX#_ HMI_TX# HMI_TX#_ HMI_TX0_ TM_T0- HMI_TX# HMI_TX# TM_T0+ HMI_T_ HMI_T HMI_T HMI_TX#_ R 0R00-P HMI_TX_ TM_T- HMI_LK_ HMI_LK TM_T+ L HMI_LK R 0R00-P L L0 HMI_TX#_ HMI_ HMI_TX_ TM_T- TP TP M0H-00-P M0H-00-P TM_T+ HMI_N HMI_TX#_ RRV# TP0 TP HMI_TX_ TM_LOK- 0 HMI_P_ HMI_HP TM_LOK+ HOT_PLU_TT HMI_HP R KRJ--P /_ROUN N 0 TM_T0_HIL N R HMI_TX HMI_TX_ HMI_TX HMI_TX_ TM_T_HIL N KRF-P HMI_TX HMI_TX TM_T_HIL N TM_LOK_HIL -:00 R 0R00-P R 0R00-P KT-U--P.00. V_0 R 0KRJ--P HMI_T_ V_0 HMI_T RN RNKJ--P R 0RJ--P HH-0PT :0/ dd R,R(.R00.L) TV OUT ONN (Optional) Move to Right I/O oard <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. HMI/TV onnector ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

RT I/F & ONNTOR 0 M_R 0 M_RN close to the RT-out connector Layout Note: Place these resistors 0 M_LU L RT_ RNKJ--P LM0N-P RT_ R R R JV_H RT_ JV_V 0 MH :0/0 hange,,,,,0 _T_ON from.r.fl to.r.fl VIO---P-U 0.0.0 _LK_ON 0RF--P 0RF--P 0RF--P 0P0-P P0-P L L P0-P LM0N-P LM0N-P P0-P P0-P RT_R RT_ P0-P 0UVKX-P V_RT_0 :00 hange RT from 0.0.0 to 0.0.0. RT_R V_0 V_RT_0 RN Hsync & Vsync level shift V_0 MH RT HH-0PT UVZY-P P0VJN-P P0VJN-P P0VJN-P P0VJN-P V_0 0 MH_HYN HYN_ U THTPW-P RN JV_H VPT-P-U 0 MH_VYN VYN_ JV_V 0 MH_T _LK_ON U V_0 U THTPW-P RN RNKJ--P _T_ON V @ ext. RT side RNJ--P-U V_0 MH_LK 0 <ore esign> N00PT RT_R RT_ RT_ VPT-P-U VPT-P-U Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RT onnector ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

:0/0 dd L (0.F0.00),please check L and L layout overlap possibility. KLITON L_TT :0/ hange L U_MI_LK R R RJ--P U_MI_LK_ pin connection.pin U_MI_IN0_R R RJ--P U_MI_IN0 connect to MR_U- "U_PN", pin MR_U+ connect to LWN00QLUP "U_PP". This L MI_T# change is for 0 <ore esign> layout request. MLX-ON--P P0VJN-P P0VJN-P P0VJN-P U_PP Wistron orporation R 0R00-P F,, ec., Hsin Tai Wu Rd., Hsichih, :0/0 dd (.0.FL) :0/0 dd (.0.FL) :0/0 dd (.0.FL) Taipei Hsien, Taiwan, R.O.. for MI request.efault is UMMY for MI request.efault is UMMY for MI request.efault is UMMY -:0/ L :0/ Rename "L" to :0/0 hange from VL TOUT "L".0.FL to 0 F VL.0.L P0VJN-P P0VJN-P 0 FU-V--P +LV KP0VKX-P U0VKX-P V_0 L_L_T# L_L_T# V_UX_ V_UX_ R V_0 -:0/ hange L pin from N to N 0KRJ--P 0 T_ T_,, T_L T_L,, KLITON LKLT_TL 0 L_TT R 0RJ--P INVRTR POWR L_TT L_LK L_LK 0 -:0/0 dd R0 to L_T L_T 0 prevent power short RIHTN L_T_ R0 00RJ--P R 0RJ--P V_TXOUT0- to N via V_TXOUT0-0 V_TXOUT0+ "L_L_T#" V_TXOUT0+ 0 0 V_TXOUT- V_TXOUT- 0 V_TXOUT+ V_TXOUT+ 0 V_TXOUT0+ V_TXLK+ :0/0 dd (.0.FL) V_TXOUT- V_TXOUT0- V_TXLK- V_TXOUT- 0 V_TXOUT+ for MI request V_TXOUT+ 0.efault is UMMY V_TXLK- V_TXLK- 0 V_TXLK+ V_TXLK+ 0 V_TXOUT0- V_TXOUT0-0 0 V_TXOUT0+ V_TXOUT0+ 0 :0/ dd,(.00.fl), R0,R(.R00.L) place cross LV LK V_TXOUT- V_TXOUT- 0 V_TXOUT+,pair. efault is.this is for RF request. V_TXOUT+ 0 V_TXOUT- V_TXOUT- 0 V_TXOUT+ V_TXOUT+ 0 V_TXOUT+ V_TXLK+ V_TXLK- V_TXOUT- V_TXLK- V_TXLK- 0 V_TXLK+ V_TXLK+ 0 0 0 V_0 00ohm 00MHz 00m 0.ohm Mic Power R 0R00-P IPX-ONN0-R-P 0.F0.00 UVZY-P V_U_MI UVKX-P MR Power +V_RUN_RMR U0VKX-P R 0R00-P V_0 :0/0 dd (.0.FL) for MI request.efault is UMMY UVZY-P U0VKX-P U0VKX-P V_TXOUT+ V_TXOUT- U_MI_LK R U_MI_IN0_R :0/ dd,0,, R,R,R on LV channel each data pairs. This is for RF request -:0/ hange LV channel and channel MI solution. this is for antena team request. 0 :0/0 dd,r connect to U pin and delete R that are for L test function. :0/0 dd.efault is. (.0.FL) for MI request.efault is UMMY :0/0 dd :0/0 dd (..FL) (..FL) for MI request for MI request.efault is UMMY.efault is UMMY 0P0VKX-P P0VN-P P0VN-P P0VN-P P0VN-P P0VN-P P0VN-P 0P0VKX-P P0VN-P P0VN-P P0VN-P P0VN-P UVZY-P LV_N L_TT_N L POWR TPT-P NV R 00KRJ--P UVZY-P +LV U IN# OUT N N N IN# IN# IN# IN# RU-P V_0 UVZY-P +V_RUN_RMR V_U_MI -:0/ MR R 0R00-P U_PN L/Inverter onnector -Intel - ize ocument Number Rev ustom Wednesday, eptember, 00 ate: heet of

V_0 RN RNKJ--P RN RNKJ--P RN RNKJ--P RN RNKJ--P RN0 RNKJ--P RN RNKJ--P PI_NT# PI_RQ# PI_RQ# PI_FRM# PI_PIRQ# PI_RR# PI_PIRQ# PI_PIRQ# PI_IR# PI_NT#0 PI_PRR# PI_PLOK# PI_PIRQ# PI_PIRQ# PI_RQ#0 PI_PIRQH# PI_NT# PI_TR# PI_RQ# PI_PIRQ# PI_NT# PI_VL# PI_PIRQF# PI_TOP# PI_[0..] PI_[0..] PI_PIRQ# PI_PIRQ# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# U OF 0 0 0 0 0 0 F 0 F PIRQ# PIRQ# PIRQ# 0 PIRQ# PI RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO F NT#/PIO 0 RQ#/PIO /0# /# /# F /# IR# PR PIRT# VL# PRR# FRM# PLOK# RR# F0 TOP# TR# PLTRT# PILK 0 PM# Interrupt I/F IH-M--P-U-NF PIRQ#/PIO F PIRQF#/PIO PIRQ#/PIO F PIRQH#/PIO :.IHM.0U PI_RQ# PI_NT# PI_RQ# PI_NT# PI_NT# PI_RQ# PI_IR# PI_PR PI_PIRT# PI_VL# PI_PRR# PI_FRM# PI_PLOK# PI_RR# PI_TOP# PI_TR# PI_PLTRT# LK_PI_IH R 0KRJ--P V_ -:00 PI_PIRQ# PI_PIRQF# PI_PIRQ# PI_PIRQH# PI_RQ#0 PI_NT#0 TP TP PI_/#0 PI_/# PI_/# PI_/# PI_IR# PI_PR PI_VL# PI_PRR# PI_FRM# PI_RR# PI_TOP# PI_TR# LK_PI_IH IH_PM# PI_PIRT# R 00KRJ--P Place closely pin 0 LK_PI_IH P0-P PIRT#, R 0RJ--P swap override trap oot IO trap PI_NT# Low= swap override nable High= efault * PI_NT# R KRJ--P PI_NT0# PI_# oot IO Location 0 PI 0 PI LP * PI_PLTRT# V_ U PLT_RT# LV0PWR-P R 00KRJ--P PLT_RT#,,,,,0, R RJ--P <Variant Name> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/)-PI/INT ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

+RT -:00 LN00_LP R 0KRJ-L-P M_INTRUR# R MRJ--P IH_INTVRMN R 0KRJ-L-P -:00 X-KHZ-0PU X +RT,, H_ITLK,, IH_Z_O_YN IH_Z_M_RT# IH_Z RT# IH_Z_O_RT# IH_IN_M IH_IN_ IH_IN_O,, IH_OUT_O -:0 0 P0VJN-P L=.pF : 00 dd R in "H_ITLK" for MI request. 0 P0VJN-P R0 0KRJ-L-P T_RXN0_ T_RXP0_ T_TXN0 T_TXP0 0 U0VKX-P IH_RTX R 0MRJ-L-P IH_RTX P-OPN R RJ--P R RJ--P R RJ--P R RJ--P R RJ--P R RJ--P T_L# 0 00P0VKX-P 00P0VKX-P -: 00 change to H_ITLK P0VJN-P V_0 IH_RTX IH_RTX LN_OMP H_ITLK_R H_YN H_RT# IH_RTRT# M_INTRUR# T_TXN0_ T_TXP0_ LK_PI_T# LK_PI_T R RF-L-P Within 00 mils Please Place near R +RT RTX F RTX F IH_INTVRMN F LN00_LP R RF-L-P H_OUT P-OPN TP0 U0VZY-P RTRT# INTRUR# INTVRMN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 0 LN_TX 0 LN_TX H LN_OK#/PIO LN_OMPI LN_OMPO J H_IT_LK J H_YN H_RT# J H_IN0 H H_IN H H_IN H_IN H_OUT 0 H_OK_N#/PIO H_OK_RT#/PIO F0 U OF TL# F T0RXN F T0RXP H T0TXN H T0TXP TRXN TRXP J TTXN J TTXP F TRXN F TRXP TTXN TTXP T_LKN T_LKP TRI# TRI IH-M--P-U-NF RT LN/LN IH T :.IHM.0U RT_R R 00RJ--P W=0mils W=0mils LP PU I U0 FWH0/L0 FWH/L F FWH/L FWH/L F FWH/LFRM# W=0mils LRQ0# LRQ#/PIO 0T F 0M# PRTP# F PLP# FRR# PUPWR/PIO HFPT-P INN# F INIT# INTR 0 RIN# H NMI MI# TPLK# THRMTRIP# TP 0 V U V T V T T T R 0 T V V U V U 0 # Y # Y IOR# W IOW# W K# Y IIRQ Y IOR Y RQ W V_UX_ R TT_R KRJ--P LP_L0 LP_L LP_L LP_L LP_LFRM# LP_RQ0# LP_RQ# H_0M# H_PLP# H_FRR# H_PWROO H_INN# H_INIT# KRIN# H_NMI H_TPLK# I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P I_P I_P H_PRTP# THRMTRIP_IH# R RJ-P TT. TP TP W=0mils LP_L[0..] LP_LFRM# K0T H_0M# H_PLP# H_FRR# H_PWROO, H_INN# H_INIT# H_INTR KRIN# H_NMI H_MI# H_TPLK# I_P[0..] I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIOR I_PRQ PWR N MH MH MH MH RT T-ON-U-P <Variant Name> H_PRTP#,, 0V_0 H_FRR# H_PRTP# H_PLP# within " from R R RJ--P H_THRMTRIP#,,, placed within " from IHM R RJ--P TP0 TP0 0V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) LN,H,I,LP ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet 0 of

V_0 V_ R V_0 I# 0KRJ--P R RN R0 RN RN0KJ--P RN R RN RN PM_LKRUN# T0_R T0_R INT_RIRQ RMRT#_K 0KRJ--P U_O# 0KRJ--P T0_R0 T0_R THRM# LKTRQ# :0/ elete RN, add R for "I#" pull up to V_0 PIO PM_TLOW#_R OP# MLINK M_LINK_LRT# PI_WK# IH_RI# U_O#0 PIO U_O# U_O# U_O# RN0KJ--P RN U_O# RT# MI# U_O# RN0KJ--P RN0KJ--P RN0KJ--P RN0KJ--P RN0KJ--P RN MLINK0 U_O# U_O# U_O# WI# 0KRJ--P H_TP_PI# H_TP_PU# :0/ hange RN pin define from"wi#" to "PIO", pin connection from V_ to V_0. :0/ dd R0 for "WI#" pull up to V_ V_0, RN0 RNKJ--P VT_PWR I# MI# WI#, PM_MUY# PM_LKRUN#, PI_WK#, INT_RIRQ THRM# LKTRQ# V_0 TP V_ M_LK M_T M_LINK_LRT# MLINK0 MLINK IH_RI# PM_U_TT# RT# PM_MUY# OP# H_TP_PI# H_TP_PU# INT_RIRQ THRM# VRMPWR R 0RJ--P TP T_TL TP TP TP TP _PKR MH_IH_YN# TP TP TP TP0 TP0 TP0 RN RNKJ--P PIO PIO TP PIO PIO I# MI# LKTRQ# PIO PIO I_RT# _PKR MH_IH_YN# IH_RV PIO0 PIO Low--> default High--> No boot 0KRJ--P R _PKR J F F 0 H F J0 J J J H H 0 H F J 0 J J U MLK MT LINKLRT# MLINK0 MLINK RI# U_TT#/LPP# Y_RT# MUY#/PIO0 MLRT#/PIO TP_PI# TP_PU# LKRUN# WK# RIRQ THRM# VRMPWR TP TH/PIO TH/PIO TH/PIO PIO PIO TH0/PIO PIO PIO0 LOK/PIO QRT_TT0/PIO QRT_TT/PIO TLKRQ#/PIO LO/PIO TOUT0/PIO TOUT/PIO PKR MH_YN# TP OF IH-M--P-U-NF M YPIO PIO MI T PIO LOK POWR MT ontroller Link :.IHM.0U T0P/PIO TP/PIO TP/PIO PIO LK LK ULK LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VRF0 L_VRF L_RT# LPIO0/PIO LPIO/PIO0 LPIO/PIO LPIO/PIO J J0 F F H J IH_ULK PIO PM_PWROK PRLPVR PM_TLOW#_R H0 R _RMRT# J F F F H J J J F L_PWR_R LP_M# L_LK0 L_LK L_T0 L_T L_VRF0_IH L_VRF_IH PIO PIO0 PIO PIO T0_R0 T0_R T0_R T0_R 0R00-P LK_M_IH LK_M_IH PM_LP_#,,,, PM_LP_#,,0,, PM_PWROK, PRLPVR, TP PM_PWRTN# K_PWR R L_LK0 TP0 L_T0 TP0 L_RT# TP TP TP TP00 R R 0KRJ--P 0RJ--P 0RJ--P 0 UVKX-P PM_PWROK UVKX-P Place closely pin LK_M_IH R00 0RJ--P VT_PWR, R R RF--P P0VN-P KRF-P R0 R0 RF--P V_0 KRF-P V_ Place closely pin LK_M_IH R 0RJ--P P0VN-P R PRLPVR U OF 00KRJ--P R0 PIO PI_RXN P MI_RXN0 MI_RXN0 00KRJ--P PRN MI0RXN V PI_RXP P MI_RXP0 MI_RXP0 PI TXN MI_TXN0 LN PI_TXN PRP MI0RXP V N MI_TXN0 PI_TXP UVKX-P PI TXP PTN MI0TXN U N MI_TXP0 MI_TXP0 UVKX-P PTP MI0TXP U PI_RXN M MI_RXN PRN MIRXN Y MI_RXN PI_RXP M MI_RXP PI TXN PRP MIRXP Y MI_RXP MI_TXN Mini ard PI_TXN L MI_TXN PI_TXP UVKX-P PI TXP PTN MITXN W L MI_TXP PTP MITXP W MI_TXP UVKX-P MI_RXN V_0 0 PI_RXN K PRN MIRXN MI_RXN 0 PI_RXP K MI_RXP MI_RXP 0 PI_TXN PI TXN PRP MIRXP MI_TXN Mini ard J MI_TXN 0 PI_TXP UVKX-P PI TXP PTN MITXN 0 J MI_TXP PTP MITXP MI_TXP UVKX-P 0 PI_RXN H MI_RXN PRN MIRXN MI_RXN 0 PI_RXP H MI_RXP MI_RXP RN 0 PI_TXN PI TXN MI_TXN Mini ard PRP MIRXP MI_TXN RNKJ--P 0 PI_TXP UVKX-P PI TXP PTN MITXN MI_TXP MI_TXP UVKX-P PTP MITXP V_0 PI_RXN F LK_PI_IH# PRN MI_LKN LK_PI_IH# PI_RXP LK_PI_IH New ard T F LK_PI_IH PI_TXN PI TXN PRP MI_LKP T PI_TXP UVKX-P PI TXP PTN Within 00 mils UVKX-P PTP MI_ZOMP Y MI_IROMP U MI_IROMP Y V_0 R RF-L-P PRN/LN_RXN PRP/LN_RXP UP0N U_PN0,, IH_MT M_T,,0 PTN/LN_TXN UP0P U_PP0 U PTP/LN_TXP UPN H U_PN UPP H U_PP U PI_LK UPN H U_PN,,0 M_LK IH_MLK,, U_PP U PI_# PI_0# UPP H TP PI_# UPN J U_PN UPP J U_PP U N00PT PI_MOI UPN K U_PN 0 F PI_MIO UPP K U_PP 0 U_PN U_O#0 U_O#0 UPN K J U_PP V_ U_O# U_O# O0# UPP K U_PN K suspend clock output U_O# U_O# O#/PIO0 UPN L U_PP V_0 U_O# U_O# O#/PIO UPP L U_PN TP U_O# O#/PIO UPN M F U U_PP TP U_O# O#/PIO UPP M U_PN V_ R U_O# O#/PIO UPN M U_PP U_O# O#/PIO0 UPP M KRJ--P J U_PN 0 U_O# O#/PIO UPN R N R U_PP 0 U_O# O# UPP N 0KRJ--P H U0 O# URI URI# F 0RJ--P URI F R0 0RF-P IH_KHZ _LK IH_ULK R 0RJ--P _RMRT# IH-M--P-U-NF Within 00 mils TLV0PW--P RMRT#_K PI-xpress PI irect Media Interface :.IHM.0U MINIR lutooth MR New ard MINIR LK_N# :00 hange R0 from. Ohm to Ohm V_0 R 0RJ--P R 0RJ--P R 0RJ--P Q N00PT-U K_PWR VRMPWR Q N00PT-U :0/0 dd N00 Q for "_LK" --P R0 00KRJ--P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. RUN_POWR_ON IH(/) PM,U,PIO ize ocument Number Rev ustom -Intel - Wednesday, eptember, 00 ate: heet of

IH_VRF_U IH_VRF_RUN IHN V_MIPLL_0 IH_VRF_U IH_VRF_RUN IHN _LN_0_INT_IH LN_0_INT_IH_ L_0_IH L IH U IH_ U IH_ IHN IHN V_ +RT V_0 V_0 V_0 V_ V_ V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 0V_0 V_0 V_0 V_0 V_0 V_0 V_0 0V_0 V_0 V_0 V_ V_0 V_0 V_ V_0 ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N Wednesday, eptember, 00 -Intel - <Variant Name> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N Wednesday, eptember, 00 -Intel - <Variant Name> ize ocument Number Rev ate: heet of Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. IH(/) POWR&N Wednesday, eptember, 00 -Intel - <Variant Name> 0 mils 0 mils (T) (MI) 0 mils :.IHM.0U 00 UVZY-P 00 UVZY-P U0VZY-P U0VZY-P UVZY-P UVZY-P TP TP L IN-UH--P L IN-UH--P U0VZY-P U0VZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P 00 0UVKX-P 00 0UVKX-P TP0 TP0 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P UVZY-P UVZY-P TP TP 0UVKX-P 0UVKX-P TP TP TP TP UVZY-P UVZY-P U0VZY-P U0VZY-P UVZY-P UVZY-P TP TP U0VZY-P U0VZY-P UVZY-P UVZY-P 0 --P 0 --P TP TP U0VZY-P U0VZY-P UVZY-P UVZY-P U0VZY-P U0VZY-P U0VZY-P U0VZY-P TP TP 0UVKX-P 0UVKX-P U0VZY-P U0VZY-P UVZY-P UVZY-P UVZY-P UVZY-P 0 U0VZY-P 0 U0VZY-P UVZY-P UVZY-P --P --P TP TP RT VRF T VRF VRF_U V U V U V W Y F F H H J J K K L L L M M N N N P P R R R R T T T T T TPLL J _0 L _0 M _0 P _0 T _0 U _0 V _0 _0 L _0 V _0 _0 _0 _0 _0 _0 _0 F _0 L _0 V _0 L _0 V _0 L _0 V _0 L _0 M _0 P _0 T _0 U _0 V W F H J 0 F L M L M H UPLL LN_0 F LN_0 LN_ F LN_ 0 LNPLL LN_ LN_ LN_ LN_ LN_ LN_ MIPLL R _MI _MI V_PU_IO V_PU_IO _ W _ V F F _ W W _ Y _ 0 _ F _ U _ H UH U_ U_ J U_0 J U_0 F0 U_ U_ 0 U_ U_ U_ H U_ U_ P U_ R U_ P U_ P U_ R U_ P U_ P U_ R U_ P U_ R U_ N U_ P U_ L_ L_ F0 L_ L_0 OF OR P P OR I PI RX TX U OR LN POWR PU PU U IH-M--P-U-NF OF OR P P OR I PI RX TX U OR LN POWR PU PU U IH-M--P-U-NF UVZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P 0 UVZY-P U0VZY-P U0VZY-P TP TP 0 UVZY-P 0 UVZY-P UVZY-P UVZY-P 0 0UVKX-P 0 0UVKX-P 0UVKX-P 0UVKX-P UVZY-P UVZY-P R 0R00-P R 0R00-P R 00RJ--P R 00RJ--P UVZY-P UVZY-P 0UVKX-P 0UVKX-P TP0 TP0 UVKX-P UVKX-P UVZY-P UVZY-P UVZY-P UVZY-P R 00RJ--P R 00RJ--P 0 0UVKX-P 0 0UVKX-P L N M L N L N N M N L M N M N L M N M N M N N M L K N L N M M _NTF _NTF _NTF H _NTF _NTF J _NTF J _NTF _NTF J _NTF _NTF _NTF H _NTF J 0 F F F F F H0 H H H H F H H H H H H J 0 F F F F 0 H H H H H J J J J J J K K K K K N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y U W OF UF IH-M--P-U-NF OF UF IH-M--P-U-NF U0VZY-P U0VZY-P U0VZY-P U0VZY-P TP TP UVZY-P UVZY-P

:0/ hange R,R0,R,R from.0.l to..l HMI_TX# HMI_TX# HMI_TX0 HMI_TX0 HMI_TX#_ HMI_TX#0_0 R 0RJ--P U0VKX-P R0 0RJ--P U0VKX-P HMI_TX HMI_TX HMI_TX#0 HMI_TX#0 HMI_TX# HMI_TX# HMI_TX HMI_TX HMI_TX#_ HMI_TX#_ R 0RJ--P U0VKX-P R 0RJ--P U0VKX-P HMI_TX HMI_TX HMI_TX# HMI_TX# 0 VO_INT+ 0 VO_INT- U0VKX-P _INT+ U0VKX-P _INT- VO_R+ 0 VO_R+ VO_R- R+ N 0 VO_R- R- N 0 R VO_+ 0 VO_+ V_0 VO_- + 0 VO_- - 0R00-P VO_+ 0 VO_+ VO_- + N 0 VO_- 0m R - N V N 0 V_0 0R00-P VO_+ N 0UVKX-P R 0 VO_+ 0 VO_- + O 0 VO_- V_0 0UVKX-P - O 0R00-P XT_R R KRJ--P XT_R P P,,,,,0, PLT_RT# VO_TRLLK VO_TRLT HMI_T HMI_LK R KRJ--P HMI_T HMI_LK U I+ I- TX+ TX- TX+ TX- RT# L L XT_WIN R 0RF-P _PWR P V _PWR HMI_HP :0/ hange R from.00.l to.00.l 0m N LROM N ROM N R P N R V_0 P P V_0 0R00-P 0R00-P : 00 hange R from Ohm to 0 TT PN Ohm IINU-P-U HLK H TX0+ TX0- HRT# HI TX+ TX- HYN 0 0 HTPL XT_WIN PIF/HO LL/N L/PRMP LINT# P. 0 KP0VKX-P 0U0VKX-P KP0VKX-P UVKX-P 0 U0VKX-P U0VKX-P 00P0VJN-P 0UVKX-P KP0VKX-P 0UVKX-P KP0VKX-P U0VKX-P U0VKX-P P R V_0 0R00-P R0 0R00-P 0UVKX-P KP0VKX-P V_0 LYOUT must support connectors from J, Molex, and con U0VKX-P UVKX-P UVKX-P V_0 0,, H_ITLK IH_Z ITLK R 0RJ--P KP0VKX-P KP0VKX-P R 0R00-P V_0 U0VKX-P R0 0R00-P H R0 KRJ--P R0 KRJ--P R KRJ--P U_PIF_OUT R RJ--P IH_Z OUT IH_Z YN IH_Z IN_ R RJ--P IH_Z RT# IH_Z RT# 0 V_0 U_PIF_OUT IH_OUT_O 0,, IH_Z_O_YN 0,, IH_IN_ 0 VO_TRLLK VO_TRLT -:0/0 hange from M to UMMY. <ore esign> IH_Z ITLK P0VJN-P R0 KRJ--P V_0 RN RNKJ--P Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. ii HMI ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of

T H onnector -ROM onnector -:0/0 hange H power net from "V-0" to "O_V_0" for niffer function circuit. 0 T_TXP0 0 T_TXN0 0 T_RXN0_ 0 T_RXP0_ V_0 0UVKX-P H_V_0 0U0VZY-P T_RXN0 T_RXP0 00P0VKX-P 00P0VKX-P UVZY-P UVZY-P NP 0 0 NP H YN-ON-P-U -:0/0 hange O power net from "V-0" to "O_V_0" for niffer function circuit. O_V_0 0 I_PRQ 0 I_PIOR# 0 I_PK# 0 I_P 0 I_P# 0U0VZY-P I_P I_P I_P0 I_P I_P I_P I_P I_P I_P UVZY-P ROM 0 0 0 0 0 FOX-ONN0-R-P I_P[0..] 0 RTRV#_ I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P0 L I_PIOW# 0 V_0 I_P 0 I_P0 0 I_P# 0 N : Master Open: lave O_V_0 RN RNKJ--P I_PIOR 0 INT_IRQ 0 -:0/0 hange O power net from "V-0" to "O_V_0" for niffer function circuit. Main ource:0.0.0 V_0 0 V_0 lose to onnector,,,,,0, PLT_RT# I_RT_MO# RTRV#_ R00 RJ--P U THTPW-P R I_PIOW# KRJ--P V_0 O_V_0 V_ R0 0R-0-U-P V_ V_0 H_V_0 R 00KRJ--P U R 0R-0-U-P R 0R-0-U-P R 0R-0-U-P R 00KRJ--P H_V_N_R U N00PT RUN_POWR_ON H_V_N R 00KRJ--P V_0 H_PWR_N -:00 R 0R-0-U-P R 0R-0-U-P Q FN-P H_V_0 -:0/0 dd H V power control circuit for niffer function, default is O_V_N_R -:0/0 dd O V power control circuit for niffer function, default is -:00 dd for "O_V_N#" N00PT RUN_POWR_ON UVKX-P H_V_N R 00KRJ--P O_PWR_N V_0 <ore esign> -:00 U I00-T O_V_0 Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. H/ROM/U -Intel - ize ocument Number Rev ate: Wednesday, eptember, 00 heet of

V_0 U V_0 RT#_K PLK_PM HIL N 0UVKX-P V_0 UVZY-P 0UVKX-P _ROUT PI_ PI_0 PI_ PI_ PI_ PI_[0..] PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ 0 PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ 0 PI_ PI_ PI_0 PI_PR PI_/# PI_/# PI_/# PI_/# PI_/# PI_/# PI_/#0 V_0 PI_/#0 PI_ R_IL R0 0RJ--P PI_RQ#0 PI_NT#0 R0 PI_FRM# 0KRJ--P PI_IR# R PI_TR# PI_VL# PI_TOP# 0RJ--P PI_PRR# 0 PI_RR# UVZY-P RT#, PIRT# UVZY-P IH_PM#, PM_LKRUN# 0UVKX-P 0UVKX-P 0UVKX-P UVZY-P 0UVKX-P 0UVKX-P 0 R 0UVKX-P 0RJ--P 0 0 0 0 _PI _PI _PI _PI _PI _PI _RIN _ROUT _ROUT _ROUT _ROUT _ROUT 0 0 0 0 PR /# /# /# /0# IL RQ# NT# FRM# IR# TR# VL# TOP# PRR# RR# RT# PIRT# PILK PM# LKRUN# PI / OTHR _V _M N N N N N N N N N N0 N N 0 N 0 N 0 N HWPN# MN XN UIO UIO UIO UIO UIO 0 UIO0/RIRQ# INT# INT# TT 0UVKX-P V_0 R 00KRJ--P R KRJ--P INT_RIRQ, PI_PIRQ# PI_PIRQ# 0 0UVKX-P V_0 RN V_0 RN0KJ--P UVZY-P : INT# in : INT# R 0KRJ--P R-P R 00KRJ--P 0P0VJN-P <ore esign> Wistron orporation F,, ec., Hsin Tai Wu Rd., Hsichih, Taipei Hsien, Taiwan, R.O.. R/PI ize ocument Number Rev -Intel - ate: Wednesday, eptember, 00 heet of