TURBO CODES IN UMTS/ WIMAX/ LTE SYSTEMS: SOLUTIONS FOR AN EFFICIENT FPGA IMPLEMENTATION. Ph. D. Cristian ANGHEL

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1 TURBO CODES IN UMTS/ WIMAX/ LTE SYSTEMS: SOLUTIONS FOR AN EFFICIENT FPGA IMPLEMENTATION Ph. D. Crstan ANGHEL

2 INTRODUCTION Telecm Prtcl Stac Nn-Access Stratum - NAS Rad Resurce Cntrl - RRC Meda Access Cntrl - MAC Rad Ln Cntrl - RLC Physcal Layer - PHY

3 INTRODUCTION Frward Errr Cdng FEC Surce cdng Channel cdng Blc cdes (Hammng, Hadamard, cyclc) Cnvlutnal cdes Nn-systematc cnvlutnal cdes NSC Recursve systematc cvlutnal cdes RSC Turb cdes Systematc cdes used n a pseud-randm manner All cdes are gd, except the nes we can thn f (Jacb Wlfwtz)

4 TURBO CODES Turb cdng prncple Cdng rate R c = 3 [] C. Berru, A. Glaveux, and P. Thtmajshma, Near Shannn lmt errr-crrectng cdng and decdng: Turb Cdes, IEEE Prceedngs f the Int. Cnf. n Cmmuncatns, Geneva, Swtzerland, May 993, pp [] C. Berru and A. Glaveux, Near ptmum errr crrectng cdng and decdng: Turb-Cdes, IEEE Trans. Cmmuncatns, vl. 44, n. 0, pp. 6-7, Oct [3] C. Berru and M. Jézéquel, Nn bnary cnvlutnal cdes fr turb cdng, Electrncs Letters, vl. 35, n., pp. 9-40, Jan. 999.

5 TURBO CODES UMTS/ WMAX/ LTE RSC turb encder

6 TURBO CODES UMTS/ WMAX/ LTE RSC trells 0 00/00 /00 0/ 0/ 00/00 /00 0/ 0/ 3 4 0/ 0/ 00/00 /00 00/0 /0 0/0 0/0 0/0 0/0 00/0 /0 0/00 0/00 / 00/ 0/ 0/ 00/00 /00 00/0 /0 0/0 0/0 0/0 0/0 00/0 /0 0/00 0/00 / 00/ / 00/ 0/00 0/00 0/0 0/0 /0 00/0 /0 00/0 0/0 0/0 / 00/ 0/00 0/00 0/0 0/0 /0 00/0 /0 00/0 0/0 0/0 + +

7 UMTS/ LTE RSC turb decder ( ) X ( ) Z ( X ) ' ( Z ) ' ( X ) ( X )

8 WMAX RSC turb decder ( A B ) ( A B ) ( A B ) 0, 0,, ( A B ) ( A B ) ( A B ) 0, 0,, ( Y, ) ( W, ) ( Y, ) ( W, ) ' ' ( A B ) ' ' ( A B ) ' ' ( A B ) ( ) 0, 0,, A ( B )

9 Decdng algrthm max*( x, y) = ln(e + e ) = x max( x, y) + ln( + e ) max( x, y). y y x

10 Max-Lg MAP WMAX ( =, = ) ( = 0, B = 0) P A a B b a, b ( A, B ) = lg P A ( S S j ) =, ( A, B ) + w ( W ) + y( Y ) γ + a b j j ( S ) = ( S ) + ( S S ) α max j α γ { } ' + + S S j ' j ' 0 ( S ) = ( S ) ( S ) α α α β j j ( S ) = β + ( S + ) + γ + ( S S + ) max j { } ' S S + ( j ) ( ) ( j ) ( j + = α + γ β + + ) Z S S S S S S ( ) t a, b = max Z j SS + : a, b { } ( ) ( A B ) t ( a b) t ( ) a, b, =, 0,0 {,0, } { 0,0 ( A B ) 0, ( A B )} ( A ) max ( A, B ), ( A, B ) = max,,, { 0,, } { 0,0 ( A B ),0 ( A B )} ( B ) max ( A, B ), ( A, B ) = max,,,

11 Max-Lg MAP WMAX γ γ γ γ 0 0 ( S S+ ) = ( S S + ) = ( A, B ) ( ) 0 ( ) ( ) 0 ( ) S S = A, B + ( Y ) + ( W ) S S = A, B + ( Y ) + ( W ) β β β β ( S ) = β + ( S + ) + γ + ( S S + ) ( S ) = β + ( S + ) + γ + ( S S + ) ( S ) = β + ( S + ) + γ + ( S S + ) ( S ) = β + ( S + ) + γ + ( S S + ) a ' b' c ' d ' { } ( S ) = max a ( S ), b ( S ), c ( S ), d ( S ) β β β β β ' 0 ' 0 ' 0 ' 0 ' 0 γ γ γ γ ( ) 0 ( ) ( ) 0( ) 4 ( S S+ ) = ( S S + ) = ( A, B ) S S = A, B + ( Y ) + ( W ) S S = A, B + ( Y ) + ( W ) ( S ) = ( S ) + ( S S ) ( S ) = ( S ) + ( S S ) ( S ) = ( S ) + ( S S ) ( S ) = ( S ) + ( S S ) α α γ a ' α α γ b' α α γ c ' α α γ d ' { } ( S ) = max a ( S ), b ( S ), c ( S ), d ( S ) α α α α α ' 0 ' 0 ' 0 ' 0 '

12 Max-Lg MAP WMAX t ( ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( S+ ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) ( + ) = α ( ) + γ + ( + ) + β+ ( + ) a Z S S S S S S b Z S S S S S S c Z S S S S S S d Z S S S S S S e Z S S S S S f Z S S S S S S g Z S S S S S S h Z S S S S S S ( + ), ( + ), ( + ), ( + ), ( + ), ( + ), ( + ), ( + ) a b c d Z S S Z S S Z S S Z S S 0,0 = max e f g h Z S S Z S S Z S S Z S S

13 Max-Lg MAP LTE ( X ) X ( j) ( Z ) Z ( j) γ = V, +,, V j ( X ) ( Z ) ( X ) ( X ) ( X ) V = + W, fr SISO = ' V ( X ) = IL{ ( X ) W ( X )},fr SISO = ( Z ) ' ( Z ),fr SISO,frSISO { } { 3 3 } { } { } { } { γ 35) } { } { } ( S0 ) ( S ) ( S ) ( S ) ( S ) ( S ) ( S ) ( S ) ( S ) ( S3 ) ( S ) ( S ) ( S4 ) ( S ) ( S ) ( S5 ) ( S ) 5 ( S3 ) ( S6 ) ( S ) ( S ) ( S ) ( S ) ( S ) αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + αˆ = max ( α + γ ),( α + γ ) αˆ = max ( α + γ ),( α + γ ) 7 77 γ γ γ γ 0 3 = 0 = V = ( X ) ( Z ) ( X ) ( Z ) = V + γ = γ ; γ = γ γ = γ ; γ = γ γ = γ ; γ = γ 5 γ = γ ; γ = γ 3 35 γ = γ ; γ = γ 4 46 γ = γ ; γ = γ 5 56 γ = γ ; γ = γ γ = γ ; γ = γ { } { } { } { } { } { γ 56) } { } { } ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) 0 ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) 3 ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) 4 ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + 5 ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) 6 ( S ) ( S ) ( S ) βˆ = max ( β + γ ),( β + γ ) 7 77

14 Max-Lg MAP LTE ( 0,0) = ( S ) + + ( S ) λ α γ β (,4 ) = ( S ) + + ( S ) λ α γ β 4 4 (,5) = ( S ) + + ( S ) λ α γ β 5 5 ( 3,) = ( S ) + + ( S ) λ α γ β 3 3 ( 4,) = ( S ) + + ( S ) λ α γ β 4 4 ( 5,6) = ( S ) + + ( S ) λ α γ β ( 6,7) = ( S ) + + ( S ) λ α γ β 6 67 ( 7,3) = ( S ) + + ( S ) λ α γ β ( 0,4) = ( S ) + + ( S ) λ α γ β (,0 ) = ( S ) + + ( S ) λ α γ β 0 0 (,) = ( S ) + + ( S ) λ α γ β ( 3,5) = ( S ) + + ( S ) λ α γ β ( 4,6) = ( S ) + + ( S ) λ α γ β ( 5,) = ( S ) + + ( S ) λ α γ β 5 5 ( 6,3) = ( S ) + + ( S ) λ α γ β 6 63 ( 7,7) = ( S ) + + ( S ) λ α γ β ( X ) λ ( j) λ ( j) = max {, } max {, }, ( S S ): X = ( S S ): X = 0 j j

15 LTE - Quadratc Permutatn Plynmal (QPP) nterleaver π ( ) = ( f + f ) md K sum (0) = f,sum (0) = 0,sum (0) = 0 π ( ) 0 0 = 0 fr = : K sum ( ) = sum ( ) + f 0 0 sum ( ) = sum ( ) + f sum ( ) = sum ( ) + sum ( ) + sum ( ) + f 0 π ( ) = sum ( ) md K end

16 LTE - Quadratc Permutatn Plynmal (QPP) nterleaver MEM , 38, 37,, 5,4,3,,,0 SISO

17 LTE - Quadratc Permutatn Plynmal (QPP) nterleaver MEM ,34,,8,...,,9,6,3,0 SISO

18 LTE - Quadratc Permutatn Plynmal (QPP) MEM0 nterleaver ,3,,,0 SISO0 MEM ,8,7,6,5 SISO MEM ,3,,,0 SISO MEM ,8,7,6,5 SISO3 MEM MEM MEM ,3,,,0 9,8,7,6,5 34,33,3,3,30 SISO4 SISO5 SISO6 MEM ,38,37,36,35 SISO7

19 LTE - Quadratc Permutatn Plynmal (QPP) nterleaver SISO0 MEM0,9,6,3, SISO MEM 37,4,3,8, SISO MEM,9,36,3, SISO3 MEM3 7,4,,8, SISO4 MEM4 3,39,6,33, SISO5 MEM5 7,4,,38, SISO6 MEM6,9,6,3, SISO7 MEM7 7,34,,8, SISO0 MEM0,9,6,3, SISO MEM 37,4,3,8, SISO MEM,9,36,3, SISO3 MEM3 7,4,,8, SISO4 MEM4 3,39,6,33, SISO5 MEM5 7,4,,38, SISO6 MEM6,9,6,3, SISO7 MEM7 7,34,,8, SISO0 MEM0,9,6,3, SISO MEM 37,4,3,8, SISO MEM,9,36,3, SISO3 MEM3 7,4,,8, SISO4 MEM4 3,39,6,33, SISO5 MEM5 7,4,,38, SISO6 MEM6,9,6,3, SISO7 MEM7 7,34,,8,35

20 LTE - Quadratc Permutatn Plynmal (QPP) nterleaver N pstns per lcatn Index = 0 : K- WA = md(, K/N) RA = WA + WA = wrte address RA = read address WP = wrte pstn PC = pstn cntent IL = nterleaver... K/N lcatns WP = flr(, K/N) PC=IL()

21 LTE rerderng unt: even-dd merge srtng

22 LTE splt wth verlap

23 - - - TURBO DECODER WMAX prpsed archtecture AG ( A B ) ( A B ) ( A B ) 0, 0,, MEM IN MEM IN IL Tcl M U X D M U X ( Y, j ) ( W, j ) Tcl M U X MEM PAR 6Tcl SISO D M U X DLY MEM AUX MEM W Read address Wrte address Wrte enable CONTROL Start trells Data Vald Delay value SISO/ Swtch n.buff Mux Sel Mux Sel LLR BYTE

24 LTE prpsed archtecture ( ) X ( ) Z ( ) X ' ( Z ) ' ( X ) ( X ) Xˆ

25 LTE SISO prpsed archtecture ( X ) V / V ' ( X ) ( Z ) ' ( Z ) / ( X ) ' ( X ) /

26 LTE tmng dagram: seral vs. parallel IL memry (X ) memry (Z ) memry (Z ) memry MODULES frm ARCHITECTURE SISO R(K-:0) R(K-:0) R(0:K-) R(0:K-) R(K-:0) R(K-:0) SISO R(0:K-) R(0:K-) W(X ) memry RESET/W(K-:0) RESET/R(0:K-) V (X ) memry R(K-:0) W(0:K-) R{IL(K-:0)} R{IL(0:K-)} (X ) memry R(K-:0) W{IL(0:K-)} GAMMA ALPHA SISO BETA MEM_BETA W(K-:0) R(0:K-) W(K-:0) R(0:K-) L TIME (clc perds) 0 K K+Delay 3K+Delay 4K+*Delay

27 IL memry (X) memry (Z) memry (Z ) memry MODULES frm ARCHITECTURE R(K/-:0) R(K/-:0) SISO R(0:K/-) R(0:K/-) R(K/-:0) R(K/-:0) SISO R(0:K/-) R(0:K/-) W(X) memry RESET/W(K/-:0) RESET/R(0:K/-) V(X) memry R(K/-:0) W(0:K/-) R{IL(K/-:0)} R{IL(0:K/-)} (X ) memry R(K/-:0) W{IL(0:K/-)} GAMMA ALPHA SISO a BETA MEM_BETA W(K/-:0) R(0:K/-) W(K/-:0) R(0:K/-) L GAMMA ALPHA SISO b BETA MEM_BETA W(K/-:0) R(0:K/-) W(K/-:0) R(0:K/-) L TIME (clc perds) 0 K/ K+Delay 3K/+Delay K+*Delay

28 OBTAINED RESULTS WMAX Number f Iteratns Blc Sze L=48, QPSK / K=, QPSK / K= K= K= 3 K= L= 4 L= 48 L= 40 REB BER REB BER RSZ[dB] SNR[dB] RSZ[dB] SNR[dB]

29 OBTAINED RESULTS WMAX Number f Retransmsns L=4, QPSK ½, K= PER REP transmssn transmse retransmssn retransmse retransmssn retransms 3 retransmssn 3 retransms 4 retransmssn 4 retransms RSZ[dB] SNR[dB]

30 OBTAINED RESULTS 0 0 LTE Number f Iteratns Blc Sze L=5, QPSK / K=3, QPSK / ter= ter= ter=3 ter=4 ter= K=40 K=5 K=644 BER B E R SNR [db] SNR [db]

31 OBTAINED RESULTS LTE Parallel N= Parallel N=4 L=5, QPSK /, K=3 L=04, QPSK /, K=3 0 0 QPSK, 3 ter, 5 bts, N = 0 - seral parallel wth verlap parallel wthut verlap 0 0 QPSK, 04, 3 ter, N = parallel wth verlap parallel wthut verlap seral BER 0-3 BER SNR[dB] SNR[dB]

32 CONCLUSIONS Effcent Max-Lg MAP mplementatn Only ne SISO All latency-reductn prcedures can be appled ver the prpsed decdng scheme Turb decdng seral archtecture adapted fr parallel decdng Only ne nterleaver used n the prpsed parallel decdng archtecture Effcent mplementatn fr the nterleaver Almst dentcal decdng perfrmances fr seral vs. parallel decdng when small verlap accepted

33 THANK YOU

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