IPSJ SIG Tchnical Rport NoC 1,a) 1,2,b) (NoC) NoC 512 NoC 45% 1. SoC (Systms-on-Chip) [1 4] 1,000 [5, 6] NoC (Ntwork-on-Chip) NoC NoC 2 Flattn Buttrfly [7] 1 32256 SoC 1 National Institut of Informatics, 2-1-2 Hitotsubashi, Chiyoa-ku, Tokyo, Japan 101-8430 2 Th Grauat Univrsity for Avanc Stuis a) ikki@nii.ac.jp b) koibuchi@nii.ac.jp 3 (1) 512 NoC (2) (3) 45% 2 3 4 5 2. (QAP, quaratic assignmnt problm) 2.1 N N i j ij i j w ij i ϕ(i) L N N L = w ij ϕ(i)ϕ(j) (1) i=1 j=1 c 2061 Information Procssing Socity of Japan 1
IPSJ SIG Tchnical Rport 1 Tabl 1 imnsions. Φ = ϕ(1),..., ϕ(n) QAP QAP [8] ϵ- *1 [9] 30 QAP [10] 2.2 3 Simulat annaling (SA) Connolly [11] C [12] Tabu sarch (TS) Taillar [13] C++ [12] Gry ranomiz aaptiv sarch procur (GRASP) [14] Rcn GRASP for spars QAP [15] Fortran [16] (Baslin) (1) (2) 1 2 2 3. 3 3.1 SoC 2 8mm 8mm 1mm 1mm 64 1 1 til 1til 1 1til = 1mm 1 N {32, 64, 128, 256, 384, 512, 640, 768, 896, 1024} x y x = N y = N/x N < xy N xy N n (n {6, 7})n (n {6, 7, 8, 9}) ( {6, 7, 8, 9, 10}) 2 2 [17] 2.2 3.47GHz Intl Xon X5690 144GBOS bian GNU/Linux 7.0 Simulat annaling 1 1 10 *1 P = NP c 2061 Information Procssing Socity of Japan 2
IPSJ SIG Tchnical Rport 'ZW 'ZW 'ZW 'ZW E E E E Fig. 1 1 Avrag link lngth vs. numbr of cors. 'ZW 'ZW 'ZW 'ZW E E E E Fig. 2 2 Maximum link lngth vs. numbr of cors. 'ZW 'ZW > > 'ZW 'ZW > > Fig. 3 3 Cumulativ istribution of link lngth. c 2061 Information Procssing Socity of Japan 3
IPSJ SIG Tchnical Rport 'ZW 'ZW 'ZW 'ZW E E E E Fig. 4 4 Excution tim of solvrs vs. numbr of cors. 3.2 64 640 1 2 SA TS TS SA 640 7 SA 45%TS 38% SA TS 10%GRASP SA TS GRASP 512 (Baslin) TS 64 256 3 (Baslin) 256 512 SA, TS, GRASP 3.3 N N = 64 N = 640 4 SA N 256 N > 256 10 1 TS 128 < N < 512 N 512 SA N 384 N 128 GRASP 6 N = 512 SA TS 70 (23%) N TS O(N 2 ) N < 512 TS GRASP N = 512 12 3.2 NoC GRASP 3.4 5 1 SA TS TS SA c 2061 Information Procssing Socity of Japan 4
IPSJ SIG Tchnical Rport Z Fig. 5 5 'ZW Link lngth rlativ to baslin vs. xcution tim of solvrs. SA GRASP GRASP 640 SA 6.3 TS 9.4 GRASP 32 512 NoC 4. NoC NoC 2 (k-ary 2-msh) 2 (fol k-ary 2-torus) NoC Buttrfly [18] Flattn Buttrfly [7] Buttrfly Flattn Buttrfly (2-ary n-cub) Spirgon [19] NoC NoC NoC NoC NoC H-Tr 1 4 NoC Fat tr Fat H-tr [20] 2 H-tr NoC [21, 22] 5. NoC 3 512 NoC 45% 3 SoC #25280043 #25730068 [1] W. J. ally an B. Towls, Rout Packts, Not Wirs: On-Chip Intrconnction Ntworks, in Procings of th sign Automation Confrnc (AC 01), Jun. 2001, pp. 684 689. [2]. Wntzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Ewars, C. Ramy, M. Mattina, C.-C. Miao, John F. Brown III, an A. Agarwal, On-Chip Intrconnction Architctur of th Til Procssor, IEEE Micro, vol. 27, no. 5, pp. 15 31, Sp. 2007. [3] P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivc 2061 Information Procssing Socity of Japan 5
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