HDMI/DVI. HDMI 1.2a DVI v1.0 HDCP 1.1 HDMI TM /DVI 1.8V V 76 CSP_BGA. RGB YCbCr DDR ITU656 CEA- 861B S/PDIF I 2 C HDCP. On Chip HPD S/PDIF HDMI

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1 HDMI/DVI AD9889A HDMI 1.2a DVI v1.0 HDCP 1.1HDMI TM /DVI 1.8V V 76CSP_BGA 80MHz 480i 720p/1,080i XGA-75Hz RGB YCbCr DDR ITU656 CEA- 861B 192kHz LPCM S/PDIF 192kHz 8LPCM I 2 S HDCP EDIDI 2 C On Chip 5VI 2 C HPD S/PDIF I 2 S MPUHDMI DVD A/V HDMI AD9889A-BBCZ80MHz HDMI 1.2a High-Definition Multimedia Interface 720p/1,080i HDTV XGA Hz CG HDCP AD9889AHDCP 1.1 CLK VSYNC HSYNC DE D[23:0] S/PDIF MCLK I 2 S[3:0] LRCLK SCLK SCL SDA I 2 C SLAVE REGISTER CONFIGURATION LOGIC VIDEO DATA CAPTURE AUDIO DATA CAPTURE MCL MDA HDCP CORE COLOR SPACE CONVER- SION 4:2:2 TO 4:4:4 CONVER- SION 1 XOR MASK DDCSDA DDCSCL AD9889AS/PDIF 8 I 2 S 8 I 2 S192kHz 7.1ch S/PDIFLPCM Dolby Digital DTS THX AD9889A HDCPMPU EDID I 2 C 1.8VI 2 C5V CMOSAD9889A 76CSP_BGA CSP_BGA2590 INT INTERRUPT HANDLER HDCP-EDID MICRO- CONTROLLER I 2 C MASTER AD9889A HDMI Tx CORE HPD Tx0[1:0] Tx1[1:0] Tx2[1:0] TxC[1:0] REV. 0 REVISION 2006 Analog Devices, Inc. All rights reserved MT

2 10/06 Revision 0: Initial Version

3 1 Test Parameter Conditions Temp Level 1 Min Typ Max Unit DIGITAL INPUTS Input Voltage, High (V IH ) Full VI 1.4 V Input Voltage, Low (V IL ) Full VI 0.7 V Input Capacitance 25 V 3 pf DIGITAL OUTPUTS Output Voltage, High (V OH ) Full VI V DD 0.1 V Output Voltage, Low (V OL ) Full VI 0.4 V THERMAL CHARACTERISTICS Thermal Resistance θ JC Junction-to-Case V 15.2 /W θ JA Junction-to-Ambient V 59 /W Ambient Temperature Full V DC SPECIFICATIONS Input Leakage Current, I IL 25 VI µa Input Clamp Voltage 16 ma 25 V 0.8 V +16 ma 25 V +0.8 V Differential High Level Output Voltage V AV CC V Differential Output Short-Circuit Current IV 10 µa POWER SUPPLY V DD (All) Supply Voltage Full IV V V DD Supply Voltage Noise Full V 50 mv p-p Power-Down Current With active video applied 25 IV 9 ma Transmitter Supply Current 2 80 MHz, typical random pattern 25 IV ma Transmitter Total Power Full VI mw AC SPECIFICATIONS CLK Frequency 25 IV MHz TMDS Output CLK Duty Cycle 25 IV % Worst Case CLK Input Jitter Full IV 2 ns Input Data Setup Time Full IV 1 ns Input Data Hold Time Full IV 1 ns TMDS Differential Swing VI mv V SYNC and H SYNC Delay VI 1 UI 3 from DE Falling Edge V SYNC and H SYNC Delay VI 1 UI to DE Rising Edge DE High Time 25 VI 8191 UI DE Low Time 25 VI 138 UI Differential Output Swing Low-to-High Transition Time 25 VII ps High-to-Low Transition Time 25 VII ps AUDIO AC TIMING Sample Rate I 2 S and S/PDIF Full IV khz I 2 S Cycle Time 25 IV 1 UI I 2 S Setup Time 25 IV 15 ns I 2 S Hold Time 25 IV 0 ns Audio Pipeline Delay 25 IV 75 µs UI Unit Interval

4 2 Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5 V to 0.0 V 20 ma 40 to to I. 100% II. III. IV V. VI. VII HDMI ESD ESD ESD ESD

5 A B C D E F G H J K 2. BOTTOM VIEW (Not to Scale) 76BGA A1 A10 B1 D[23:0] I RGB YCbCr V B10 C9 CMOS C10 D9 D10 D1 CLK I V CMOS C2 DE I V CMOS C1 HSYNC I V CMOS D2 VSYNC I V CMOS J3 EXT_SW I 887Ω1 K3 HPD I V CMOS E2 S/PDIF I S/PDIF Sony/Philips Sony/ Philips V CMOS E1 MCLK I 128 N f S N f S 256 f S 384 f S 512 f S V CMOS F2 F1 G2 G1 I 2 S[3:0] I I 2 S I 2 S V CMOS H2 SCLK I I 2 S V CMOS H1 LRCLK I V CMOS J7 PD/A0 I I 2 CI 2 C PDAD9889A PD/A V CMOS K1 K2 TxC /TxC+ O TMDS Transition Minimized Differential Signaling K10 J10 Tx2 /Tx2+ O 2 10 TMDS K7 K8 Tx1 /Tx1+ O 1 10 TMDS K4 K5 Tx0 /Tx0+ O 0 10 TMDS H10 INT O CMOS I/O 2kΩ J2 J5 J8 K9 AVDD P TMDS1.8V D5 D6 D7 E7 DVDD P 1.8V I/O I/O

6 1 G4 G5 J1 PVDD P 1.8V PLL AD9889A PLL D4 E4 F4 J4 GND P G6 J6 K6 F7 AD9889A 1 G7 H9 J9 F9 SDA C 2 I/O I/O V CMOS F10 SCL C V CMOS E10 MDA C 2 HDCP EEPROM I/O V CMOS E9 MCL C 2 HDCP EEPROM V CMOS G9 DDCSDA C 2 I/ODDC 5V CMOS G10 DDCSCL C 2 DDC 5V CMOS 1 IOPC 2 2 NDA flatpanel_apps@analog.com

7 NDA EIA/CEA-861B infoframe HDMI E-EDID CEA Consumer Electronics Association HDMI 1.2HDMI v.1.2a HDMI 1.2aHDMI Licensing, LLC HDCP 1.1HDCP v.1.1 Digital Content Protection, LLC xNN 0bNN NN Bit xC 2 20bC

8 PCB AD9889A PC 0.1µF 1 0.5cm AD9889APC PVDD PLL PVDD AVDD and PVDD 1 1 AD9889A V 3.3V CLK 6CLK 720p XGA 75MHz HPDHDMI 10kΩ PD/A0 GND AD9889A PD/A0 PD/A0 0x72 PD/A0 0x7A SCL SDAI 2 C 1.8V 3.3V2kΩ EXT_SWG 887Ω1% EXT_SWGAC TMDS AD9889A3TMDS MHzTMDS 50Ω 100Ω PC TMDS DDCSCL DDCSDA DDCSCL DDCSDA DDCSCL DDCSDA HDMI 50pF DDCSCL DDCSDA HDMI 5V 1.5kΩ 2kΩ INT INT 1.8V 3.3V 2kΩ MCL MDA MCL MDAHDCP HDCP EEPROM 2kΩ

9 SQ 5.90 A1 CORNER INDEX AREA A *1.40 MAX BALL A1 PAD CORNER TOP VIEW DETAIL A 4.50 BSC SQ 0.50 BSC 0.15 MIN 0.75 REF BOTTOM VIEW DETAILA B C D E F G H J K 0.65 MIN D /06(0)-J 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER COPLANARITY 0.08 MAX 3. *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 76CSP_BGA 6mm 6mm 1.4mm BC-76 mm Model Temperature Range Package Description Package Option AD9889ABBCZ to Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-76 AD9889ABBCZRL to Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-76 AD9889A/PCB Evaluation Board 1 Z I 2 CI 2 C I 2 C I 2 C