First International Computer,Inc Portable Computer Group HW Department

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1 irst International omputer,inc Portable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : LM0W. PI & IRQ & M escription : Version : 0. Initial ate : eb, 00. lock iagram :. Nat name escription :. oard tack up escription :. chematic modify Item and istory :. power on & off & equence :. Layout uideline :. switch setting Manager ign by: rawing by : Total confirm by: Jack hen LN ircuit check by: udio ircuit check by: irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

2 . chematic Page escription : LM0W chematic Ver : 0... VT (/)..V/,./.VM/. chematic Page escription. VT (/). VM / VM. lock iagram. VT (/). VP/.VM. NNOTTION. Power ood & an ontroller. V / V / PMU/V. chematic Modify. XPR R. POW-ON ontroller. Timing iagram. RT 0. IN / attery NN. R Layout uideline. MINI PI. harge ircuit / IN. Yonah processor (/) 0. VT0L PY. Inverter ontroller. Yonah processor (/). U NN. udio board 0. POWR (PU OR). -T / -ROM NN. witch transfer board. Thermal / VR_PWR. LP PMU0. M circuit. lock enerator. LP K M. lock uffer. INT K / P onnector. VN (/). M onnector. VN (/). IP witch & L. VN (/). irm Ware ub / LI witch. VN (/). Reset ircuit. R O-IMM 0. OVP / RW. R O-IMM0. X0 udio odec 0. VTL LV Transmitter. 0 udio mplifier. L onnector..p. Out / udio NN. RT onnector. R PWR. PI & IRQ & M escription : UMTR RQ RQ0 / NT0 RQ / NT RQ / NT RQ / NT RQ / NT IL PIINT IRQ IRQ IRQ IRQ IP Mini PI(Wireless LN) IP N MiniPI MiniPI IP IRQ Mini PI(Wireless LN) PI- IRQ hannel IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ esciption ystem timer Keyboard (asacde) LN / MOM erial Port UIO / V / U LOPPY IK LPT RT PI (isable by default) IR (MOM/LN) ardbus P/ mouse PU ROM M hannel M0 evice IR M P M LOPPY IK M UIO M (ascade) M Unused M Unused M Unused (disable by default) (MOM / LN) irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

3 . lock iagram : LK I00L P Thermal ensor MT P Intel Yonah eleron Mz Processor P, PU OR P0 PU VP P LK uffer R Pull up LI/IP W P P,P P, IN P RT L P P RJ- P0 VTL LV Tx LN Phy VT0L U.0 P0 P0 MII U ost us VI VN P~P ub Interface VT P~P Mem us I U -T ROM P P R 00/ INTR P,P PI XPR R zalia O X0 P udio MP PON Mic IN MIN W NN P P V/V P PMUV/V P V/V P VM/VM P.V/M P R 0.VM P VP/.VM P Over Voltage Protect P0 attery charger attery elect P0 T ON P P0 attery Voltage sense P U, Mini PI P U0, P it PI U K/ TRL LP M -Link LP U P INT K/ P P P L ROM ( /W ub) M N NN P RT P RT P P LP PMU0 P MOM X0 udio XT board irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

4 . Nat name escription :.oard tack up escription Voltage Rails IN PMUV PMUV V V V V VM VM Vcore_PU Primary system power supply.0v always on power rail by LT or IN.V always on power rail by LT or IN.0V always on power rail by ON or PU0.V always on power rail by ON or PU0.V power rail.0v power rail.v switched power rail.0v switched power rail ore Voltage for PU P Layers Layer Layer Layer Layer Layer Layer omponent ide, Microstrip signal Layer round Plane tripline Layer(TL,LOK,R) tripline Layer(nalog,LV,other) Power Plane older ide,microstrip signal Layer VP.VM R_0.VM.VM.V.V.V.0V for TL Termination Voltage.V for PU PLL Voltage 0.V R Termination Voltage.V switched power rail.v power rail.v always on power rail.v power rail for R Part Naming onventions N L Q R RP U Y = = = = = = = = = = apacitor onnector iode use Inductor Transistor Resistor Resistor Pack rbitrary Logic evice rystal and Osc Net Name uffix 0 = ctive Low signal ignal onditioning = _Q_ = _L_ = amped (by a resistor) Isolated (by a Q-switch) iltered (by an inductor or bead) irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

5 .chematic modify Item and istory : irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

6 . power on & off & equence : Power On equencing Timing iagram VI VR_ON Tsft_star_vcc Vcc-core Tboot Vboot Vid Tboot-vid-tr PU_UP Tcpu_up Vccp Vccp_UP Tvccp_up Vccgmch MPWR Tgmch_pwrgd LK_NL# IMVP_PWR Tcpu_pwrgd TTRY ONLY POWR ON TIMIN POWW0 PMUV/PMUV UPN N RUM TIMIN POWW0 ON V MINW0_I To VT PMUV/PMUV ON V PM_RMRT0 PM_LP_0 To VT rom VT To VT PM_RTRT0 PM_LP_0/0/0 PU0 UTT_0 VM,V PM_PWROK rom VT rom rom PM_LP_0/0 PU0 UTT_0 V VM PM_PWROK Y_PWROK VRON_VP rom VT rom rom.v N R_PWR Y_PWROK VP,.VM VRON_VP VP/.VM VOR_ON VOR_ON VR_ON VR_ON VOR_PU VOR_PU K0_PWR0 To clock generator To OM and VT K0_PWR0 PM_VT To clock enerator ToVT and OM PM_VT rom VT to PU PU_PWROO rom VT to PU PU_PWR PI_RT0 TL_PURT0 To OM/other PI device PI_RT0 TL_PURT0 To OM/other PI device rom OM to PU rom OM to PU irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

7 . Layout uideline : Montara-M R Layout uidelines Note that all length matching formulas are based on M die-pad to O-IMM pin total length roup locks ata ontrol ommand P R ignal roups eedback ignal Name K[:0] K#[:0] Q[:0] Q[:0] M[:0] K[:0] #[:0] M[:,:0] [:0] R# # W# M[,,,] M[,,,] RVNOUT# RVNIN# lock ignals Topologies and Routing uidelines M Pin P Package Length Range L Min:0." Max:.0" Length Matching ormulas ignal roup Minimum Length Maximum Length ontrol to lock ommand to lock P to lock trobe to lock ata to trobe O-IMM P lock -.0" lock -.0" lock -.0" lock -.0" trobe - mils lock 0." lock.0" lock 0." lock 0." trobe mils mil trace, mil pair space lock length tolerenve within the pair : /- 0 mil lock to lock Length Matching : /- mils Minimum Pair to Pair pacing : 0 mils Minimum pacing to other ignals : 0 mils LOK LKPU[..0] LKN[..0] LKITP[..0] MLK_I MLK_M PLK_TI PLKI PLK PLK PLKU0 PLKOP PLKW PLKIO PLKLN MLK_IO MLK_I MLK_ MLK_I MLK_ LNT " ~ "." ~.0 " MX :."."~.0"."~.0"." ~." TR / P NOT.ifferentials pairs with the same length / 0 mils (within 0 mil) ( mil space.pu & N trace between & - ) mismatch within 0 mil / 0 mils / 0 mils / 0 mils / 0 mils * MLK_I & PLK_M PLK_TI Length mismatch within 00 mils.making PI length with minimum various.max skew = ns ata ignals Topolog ies and Routing uidelines M Pin P Package Length Range L L L L O-IMM0 P O-IMM P ohm % Minimun pacing to Trace Width Ratio, Q/M : to Q : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max 0." L : Min 0.", Max.0" L : Max.0 " Length Matching : Q to K/K# Q OIMM0 PLL Q, OIMM PLLL Min : lock -.0", Max : lock 0." Q/M to Q : /- mils Q/M to Q Mapping ignal Mask Relative To Q[..0] Q[..] Q[..] Q[..] Q[..] Q[..0] Q[..] Q[..] Q[..] M[0] M[] M[] M[] M[] M[] M[] M[] M[] Q[0] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Q[] Mismatching /- mil /- mil /- mil /- mil /- mil /- mil /- mil /- mil /- mil ontrol ignals Topolog ies and Routing uidelines M Pin P Package Length Range L O-IMM0, P ommand ignals To pologies and Routing uidelines M Pin P Package Length Range L L L 0 ohm % L L O-IMM P ohm % ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : TRL(PL) to K/K# Min : lock -.0", Max : lock 0." Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L Min 0.", Max.0" L Max.0" L : Max.0" LL : Max.0" L : Max.0" Length Matching : M to K/K# M OIMM0 PLL M, OIMM PLL Min : lock -.0", Max : lock.0" P ignals Topologi es and Routing uidelines M Pin P Package Length Range L O-IMM0, P L ohm % Trace spacing to trace width ratio : to Minimum pacing to other ignals : 0 mils Trace Length L : Min 0.", Max." L : Max.0" Length Matching : P(PL) to K/K# Min : lock -.0", Max : lock 0." irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- O-IMM0 P LM0W < VI VN VT > ize ocument Number Rev <> 0. Tuesday, October, 00 ate: heet of

8 U Topology : RR# TL_0 J TL_0 []# # TL_0 () L VP L L Rtt Transmission Line TL_0 []# NR# TL_NR0 () M PU Im TL_0 []# PRI# TL_PRI0 () K 0." - " 0" -.0" /-% Micro-strip TL_0 []# M Rtt TL_0 []# R# TL_R0 () N L L 0." - " 0" -.0" /-% trip-line TL_0 []# RY# TL_RY0 () J TL_00 []# Y# TL_Y0 () N TL_0 [0]# P TL_R00 TL_0 []# R0# TL_R00 () P VP VP TL_0 []# L 0 R Ω % /0W MT00 LR TL_0 []# IRR# VP (,,,,,,) P _INIT0 PU IMVP L L L L Rtt Transmission Line TL_0 []# INIT# _INIT0 (,) P Rtt Rtt TL_0[..] TL_0 []# () TL_0[..] R []# LOK# TL_LOK0 () 0." -." 0." -." 0" -.0" 0" -.0" 0 /-% Micro-strip () TL_T00 L T[0]# TL_PURT0 L LL L 0." -." 0." -." 0" -.0" 0" -.0" 0 /-% trip-line TL_RQ00 RT# TL_PURT0 () K TL_RQ0 RQ[0]# R[0]# TL_R00 () TL_RQ0 RQ[]# R[]# TL_R0 () K TL_RQ0 RQ[]# R[]# TL_R0 () J TL_RQ0[..0] TL_RQ0 RQ[]# TRY# TL_TRY0 () () TL_RQ0[..0] L RQ[]# Topology : PWROO Topology : PULP# TL_0 IT# TL_IT0 () Y TL_0 []# ITM# TL_ITM0 () U PU Im L Transmission Line PU M L Transmission Line TL_0 []# R XP_PM0 TL_00 []# PM[0]# W XP_PM 0." - " Micro-strip 0." - " Micro-strip TL_0 [0]# PM[]# U XP_PM L L TL_0 []# PM[]# Y XP_PM 0." - " trip-line 0." - " trip-line TL_0 []# PM[]# U XP_PRY (,,,,,,) VP TL_0 []# PRY# R XP_PRQ TL_0 []# PRQ# T XP_TK Topology : INTR, NMI, 0M#, PLP#, INN#, INIT# MI#,, TPLK# Topology : RT# TL_0 []# TK T XP_TI TL_0 []# TI W XP_TO TL_0 []# TO W XP_TM R PU Im L Transmission Line M PU L Transmission Line TL_0 []# TM Y XP_TRT0 Ω % /W MT00 LR TL_00 []# TRT# W 0 XP_RT0 0." - " Micro-strip " - " Micro-strip TL_0[..] TL_0 [0]# R# () TL_0[..] Y []# L L () TL_T0 V T[]# PROOT# PROOT# 0." - " trip-line " - " trip-line TRM () _0M0 TRM () _0M0 TRM () _RR0 0M# TRM _INN0 RR# () _INN0 R INN# TRMTRIP# VP (,,,,,,) Topology : TRMTRIP# _TPLK0 / hange to VP () _TPLK0 0Ω % /W MT00 LR VP L L LL L L Rss Rtt Transmission Line _INTR TPLK# () _INTR M PU Im _NMI LINT0 () _NMI " - " " - " " - " 0" -.0" 0" -.0" /-% /-% Micro-strip _MI0 LINT LK[0] PU_LK () () _MI0 MI# LK[] PU_LK0 () L Rtt L L Rtt L " - " " - " " - " 0" -.0" 0" -.0" /-% /-% trip-line (,,,,,,) VP RV[0] T RV[0] RV[] RV[0] hould be connect to I and alistoga without T-ing(no stub) RV[0] M R 0Ω % /W MT00 LR(NU) RV[0] RV[] N R0 0Ω % /W MT00 LR(NU) RV[0] RV[] T RV[0] RV[] V R0 RV[0] RV[] _T0N () (,,,,,,) VP No stub on _TPLK test point RV[0] RV[] 0Ω % /W MT00 LR(NU) XP P/U & P/ RV[0] RV[] 0Ω % /W MT00 LR(NU) XP_TO R Ω % /0W MT00 LR RV[] R XP_TM R.Ω % /0W MT00 LR (,,,,,,) VP RV[] RV[0] XP_TI R.Ω % /0W MT00 LR KT Molex ZI MT micro-p 0- Yonah PU Pin LR XP_PRQ R.Ω % /0W MT00 LR(NU) Micro-P XP_PRY R.Ω % /0W MT00 LR(NU) Modify for V0. XP_PM0 R 0Ω % /0W MT00 LR(NU) _0M0 R 0Ω % /0W MT00 LR XP_PM R 0Ω % /0W MT00 LR(NU) PU_PLP0 R0 0Ω % /0W MT00 LR XP_PM R 0Ω % /0W MT00 LR(NU) _INN0 R 0Ω % /0W MT00 LR XP_PM R 0Ω % /0W MT00 LR(NU) _INIT0 R 0Ω % /0W MT00 LR XP_RT0 R 0Ω % /0W MT00 LR(NU) _INTR R 0Ω % /0W MT00 LR Rout to TP via and place gnd via w/in 00mils _TPLK0 R 0Ω % /0W MT00 LR _NMI R 0Ω % /0W MT00 LR XP_TRT0 R 0Ω % /0W MT00 LR _PULP0 R 0Ω % /0W MT00 LR XP_TK R0 Ω % /0W MT00 LR ommon lock ignal Layout uide : _MI0 R 0Ω % /0W MT00 LR #, NR#, PRI#, R0#, Y#, R#, PWR#, RY#, IT#, ITM#, LOK#, PI0 R00 0Ω % /0W MT00 LR(NU) _RR0 R0 Ω % /0W MT00 LR R[..0]#, TRY#, RT#. TL_R00 R0 0Ω % /0W MT00 LR Transmission Line Type Total Trace Length Normal Impedance pacing (mils) TL_PURT0 R0 Ω % /0W MT00 LR PU_PWROO R0 0Ω % /0W MT00 LR #[-], PM#[0-]:Leave escape routing on for future functionality trip-line(int. Layer) & mils.0 ~. inch /-% Micro-strip(xt. Layer) & 0 mils V0. Modify (,0,,,,,,).VM TL_0[..0] U TL_0[..0] () TL_0[..0] TL_0[..0] () TL_00 ource ynchronous ata Length Variation and trobe Matching Requirements : TL_0 TL_0 [0]# []# TL_0 ignals Name ignals Matching trobes associated with the group trobe-to-trobe omplement Matching TL_0 []# []# V TL_0 R TL_0 []# []# V TL_0 Modify Q Library KΩ % /W MT00 LR T#[..0], INV0# /- 00 mils TP0#,TN0# /- mils TL_0 []# []# W TL_0 TL_0 []# []# U TL_0 T#[..], INV# /- 00 mils TP#,TN# /- mils TL_0 []# []# U TL_0 TL_0 []# []# TL_0 Q U T#[..], INV# /- 00 mils TP#,TN# /- mils TL_0 []# []# K TL_00 _RR0 TL_0 []# [0]# RR0 () W TL_0 T#[..], INV# /- 00 mils TP#,TN# /- mils TL_00 []# []# J Y TL_0 TL_0 [0]# []# J TL_0 TL_0 []# []# Y TL_0 TRN NPN MMT 0V 00m OT- PIN PI LR TL_0 []# []# TL_0 ource ynchronous ata ignal Routing Topology# : Y (,,,,,,) VP VP (,,,,,,) TL_0 []# []# K TL_0 R0 ignal Name Transmission Line Type Total Trace Length Normal Impedance Width & pacing (mils) TL_0 []# []# TL_0 0KΩ % /W MT00 LR []# []# () TL_TN00 W TN[0]# TN[]# TL_TN0 () ata-to-ata,trobe-to-strobe trobe-to-ata () TL_TP00 Y TP[0]# TP[]# TL_TP0 () () TL_INV00 J V INV[0]# INV[]# TL_INV0 () INV#[..0] trip-line 0. ~. inch /-% & mils N/ R KΩ % /0W MT00 LR R KΩ % /0W MT00 LR u.v 0% MT00 XR LR TLR R OMP0 R.Ω % /0W MT00 LR TLR OMP[0] MI U OMP R.Ω % /0W MT00 LR OMP[] ignal Name Transmission Line Type Total Trace Length Normal Impedance Width & pacing (mils) U OMP R.Ω % /0W MT00 LR 0mils R _TT OMP[] V OMP R.Ω % /0W MT00 LR ddress#[..] trip-line 0. ~. inch /-% & mils KΩ % /W MT00 LR(NU) TT OMP[] Max : ns R _TT _PRTP0 (,,,,,,) VP _PRTP0 (0) RQ#[..0] trip-line 0. ~. inch /-% & mils Ω % /W MT00 LR TT PRTP# PU_PLP0 PLP# PU_PLP0 () TL_PWR0 () T#[..0] trip-line 0. ~. inch /-% & mils R () _L0 0KΩ % /W MT00 LR PWR# PU_PWROO (,,,,,,) VP PU_PWROO () _L L[0] PWROO _PULP0 R 0Ω % /W MT00 LR () _L L[] LP# _PULP0 (,) PI0 () _L L[] PI# PI0 (0) R 0KΩ % /W MT00 LR KT Molex ZI MT micro-p 0- Yonah PU Pin LR R irst International omputer, Inc. Micro-P V0. Modify Modify Q Library _PRTP0 L.,NO.00,Yang uang t.,neiu R 0KΩ % /W MT00 LR W 0 % /W 00 TIPI, TIWN,RO R omp0, connect with Zo=.ohm, make trace (-)- (0,) PRLPVR Q length shorter than 0." and width is mils. 0Ω % /W MT00 LR LM0W < VI VN VT > TRN NPN MMT0 0V 00m OT- PIN PI LR omp, connect with Zo=ohm, make trace ize ocument Number Rev length shorter than 0." and width is mils Yonah Processor (/) 0. Zo=ohm, 0." max for TLR, pace any other switch signals away from TLR with a minimum of mils. u.v 0% MT00 XR LR () TLR 0p 0V 0% MT00 XR LR TL_0[..0] () TL_TN0 () TL_TP0 () TL_INV0 0 0p 0V 0% MT00 XR LR TL_0[..0] TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 N K P R L L L M P P P T R L T N M N M R ROUP 0 R ROUP RRV ONTROL XP/ITP INL LK TRM []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# TN[]# TP[]# INV[]# T RP 0 T RP on't allow the TLR routing to create splits or discontinuities in the reference planes of the signals T RP T RP []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# TN[]# TP[]# INV[]# 0 0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0[..0] TL_TN0 () TL_TP0 () TL_INV0 () TL_0[..0] () T#[..0] TN#[..0] TP#[..0] ource ynchronous ddress Length Variation and trobe Matching Requirements : ignals Name ignals Matching trobes associated with the group trobe to ssoc. ddress ignal Matching #[..], RQ#[..0] #[..] trip-line trip-line trip-line /- 00 mils /- 00 mils 0. ~. inch 0. ~. inch 0. ~. inch T0# T# /-% /-% /-% *** No length matching requirements exist between T0# and T# ource ynchronous ddress ignal Routing : _PWR rise time : & mils & mils & mils /- 00 mils /- 00 mils N/ & mils & mils Tuesday, October, 00 ate: heet of

9 Place these inside socket cavity on L (North side secondary) Place these inside socket cavity on L (outh side secondary) (0,,) VOR_PU U U P V[00] V[0] 0 P V[00] V[0] >00mils V[00] V[0] P V[00] V[0] V[00] V[0] 0 VP (,,,,,,) R V[00] V[00] V[00] V[0] R V[00] V[0] V[00] V[0] R V[00] V[0] V[00] V[0] R V[00] V[0] V[00] V[0] V[00] V[0] T T00u V ± 0% R=mΩ MT 00R PNONI LR V[00] V[0] T V[00] V[0] V[00] V[00] 0 T V[00] V[0] V[00] V[0] T V[00] V[0] V[0] V[0] U V[0] V[0] V[0] V[0] 0 0 U V[0] V[0] V[0] V[0] U V[0] V[00] V[0] V[0] U V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] V V[0] V[0] V[0] V[0] 0 V V[0] V[0] Place these inside socket cavity on L V[0] V[00] 0 W V[0] V[0] V[00] V[0] 0 (North side secondary) W V[00] V[0] V[0] V[0] W V[0] V[0] V[0] V[0] W V[0] V[0] V[0] V[0] Y V[0] V[00] V[0] V[0] Y V[0] V[0] V[0] V[0] 0 Y V[0] V[0] V[0] V[0] Y V[0] V[0] V[0] V[0] 0 0 V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[] V[00] V[0] V[0] V[] V[0] V[0] V[0] V[] V[0] V[0] V[0] V[] 0 V[0] V[00] V[0] V[] V[0] V[0] V[] 0 V V[0] VP[0] V[0] V[] Place these inside socket cavity on L Place these inside socket cavity on L V[0] VP[0] V[0] V[] J V[0] VP[0] V[0] V[] (North side Primary) (outh side Primary) K V[0] VP[0] V[0] V[0] M V[0] VP[0] V[00] V[] J V[00] VP[0] V[0] V[] 0 K V[0] VP[0] V[0] V[] M V[0] VP[0] V[0] V[] N V[0] VP[0] V[0] V[] 0 N V[0] VP[0] V[0] V[] R V[0] VP[] V[0] V[] R V[0] VP[] T (,0,,).VM V[0] V[] V[0] VP[] lose to PU V[0] V[] T V[0] VP[] V pin V[0] V[0] V[0] VP[] V[00] V[] 0 W V[00] VP[] 0mils V[0] V[] V[0] V[0] V[] V[0] V V[0] V[] 0 V[0] V[0] V[] V[0] V[0] V[] V[0] VI[0] _VI0 (0) 0.0u V 0% MT00 XR LR V[0] V[] V[0] VI[] _VI (0) V[0] V[] V[0] VI[] _VI (0) V[0] V[] V[0] VI[] _VI (0) V[0] V[0] 0 V[0] VI[] _VI (0) V[00] V[] V[00] VI[] _VI (0) J V[0] V[] 0 V[0] VI[] _VI (0) J V[0] V[] 0 J V[0] V[0] V[] J V[0] V[0] V[] K V[0] VN V[0] V[] K V[0] V[0] V[] K V[0] V[0] V[] K V[0] VN V[0] V[] L KT Molex ZI MT micro-p 0- Yonah PU Pin LR V[0] V[0] L Micro-P V[00] V[] L V[0] V[] L V[0] V[] M V[0] V[] M V[0] V[] VN (0) M V[0] V[] M V[0] V[] VN (0) N V[0] V[] N V[0] V[] N V[0] V[0] North side secondary outh side secondary N V[00] V[] P V[0] V[] u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0 u.v ± 0% MT00 XR 0XR0JM TK LR(NU) u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) u.v ± 0% MT00 XR 0XR0JM TK LR(NU) u.v ± 0% MT00 XR 0XR0JM TK LR(NU) u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0 0u.V 0% MT00 XR 0XR0J0K TK LR 0u.V 0% MT00 XR 0XR0J0K TK LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0u.V 0% MT00 XR 0XR0J0K TK LR 0.u V ± 0% M00 XR LR 0.u V ± 0% M00 XR LR 0.u V ± 0% M00 XR LR 0.u V ± 0% M00 XR LR 0.u V ± 0% M00 XR LR Via:. 0u.V 0% 00 XR TK LR mil mil space KT Molex ZI MT micro-p 0- Yonah PU Pin LR Micro-P Route VN and VN traces at. ohms with 0mil spacing. Place PU and P within inch of PU irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev Yonah Processor (/) 0. Tuesday, October, 00 ate: heet of

10 lose L Rn =[Rparallel*(RntcRserial)/(RparallelRntcRserial) =[R*(RR)]/(RRR) =.K ain factor =Rn/[R(eqv)Rn]= Recommend R(eqv)=.K Rfb=[N*Rdroop/(R*)-]*Rin N:no. of phase R=[*.mV/(.m*0.)-]*K=.K Rdroop:Intel spec. -.m Ohms (,,,,,,,0,,,,,,,,,,,,,,,,,) (,,,,,0,) (,,,,,,) VM IN_PU V PU lose L IMVP IV Load line slope : -.mv/ VOR_PU or Yonah PU R0 R0 R0 0 u 0V 0% MT00 XR 0XR0KT TK LR 0Ω % /W MT00 LR 0Ω % /W MT00 LR 0Ω % /W MT00 LR V V 0 VIN 0 0.u 0V 0-0% 00 YV LR oost Voltage.V eeper leep Voltage 0.V L hange to Mag.Layer (,,,,,0,) IN_PU Q L 0, 000mils IRR0Z 0V TO- IR LR PI 0.u ± 0%.*0* MM-00-RM M.LYR LR 00mil (,,,,,0,) IN VOR_PU (,,) V POO 0.u 0V 0% 00 XR LR UT OOT V0. R0 0KΩ % /W MT00 LR(NU) R0 W 0 % /W 00 0u V 0% 0 φ0 0.Ω N LR(NU) 0u V 0% 0 φ0 0.Ω N LR(NU) VOR_P () 0 0.u 0V 0% MT00 XR LR 0u V 0% 0 φ0 0.Ω N LR U0 LNR-I ILRZ-T QN PIN INTRIL LR R0 PWR 0 % /W 00 u V ± 0% mω φ.*. N LR u V ± 0% mω φ.*. N LR.u V ± 0% 0 XR TK LR(NU).u V ± 0% 0 XR TK LR(NU).u V ± 0% 0 XR TK LR(NU).u V ± 0% 0 XR TK LR(NU) 0mils Q IRR0Z 0V TO- IR LR Q IRR0Z 0V TO- IR LR(NU) IO TKY 0V O-(M) PIN PI LR 000p 0V 0% 00 XR LR(NU) R0 W 0 % /W 00 R0 W 0 % /W 00 T0u V - to 0% mω MT X0Y PNONI LR(NU) T0u V - to 0% mω MT X0Y PNONI LR T0u V - to 0% mω MT X0Y PNONI LR,,,,,,,) PU () () VM VI PI0 VOR_ON R PWR 0 % /W 00 VI () () () () () () () (,) (,) () () R0 W 0 % /W 00 R0 W 0 % /W 00 R0 KΩ % /0W MT00 LR R0 Ω % 00 LR (NU) TRMO-R 0KΩ % /0=00K± % /=0K MT00 NT RTJ0VJ PNONI LR(NU) R R.0KΩ % /0W MT00 LR(NU) 0.0u V 0% MT00 XR LR PU 0.0u V 0% MT00 XR LR(NU) _VI0 _VI _VI _VI _VI _VI _VI VRON_VP PRLPVR _PRTP0 LK_N R R.KΩ % /0W MT00 LR R0 W 0 % /W 00 R0 W 0 % /W 00 R0 W 0 % /W 00 R00 W 0 % /W 00 R0 W 0 % /W 00 R0 W 0 % /W 00 R0 W 0 % /W 00 R W 0 % /W 00 R0 W 0 % /W 00 R W 0 % /W 00 R0 W 0 % /W 00.KΩ 0.% /0W MT00 LR 0p 0V 0% MT00 XR LR R KΩ % /W MT00 LR(NU) 0.0u V ± 0% MT00 XR LR R 0.KΩ % /W MT00 LR 0p 0V 0% MT00 XR LR R.KΩ % /W MT00 LR p 0V % MT00 NPO LR 0.0u V 0% MT00 XR LR 0.0u V 0% MT00 XR LR 0 0 PU PI# P_IN RI VR_TT# NT OT VI0 VI VI VI VI VI VI VR_ON PRLPVR PRTP# LK_N# VI OMP VW RTN VN ROOP P LT R.KΩ % 00 LR PU P IN PV UT OOT P LT P IN N OT VUM VO 0 0.u 0V 0% MT00 XR LR 0 PU R 0.0u V 0% MT00 XR LR R R 0KΩ % /W MT00 LR(NU) 0.u 0V 0% MT00 XR LR.KΩ % /0W MT00 LR VUM KΩ % /W MT00 LR 0 0p 0V % MT00 NPO LR 000p 0V 0% MT00 XR LR R0 0KΩ % /W MT00 LR(NU) lose L 0.u 0V 0% MT00 XR LR V (,,,,,,) R PWR 0 % /W 00 (,,,,,0,) 0.u 0V 0-0% 00 YV LR 0.u 0V 0% MT00 XR LR 0.u V ± 0% MT00 XR LR 0.0u V ± 0% MT00 XR LR R0 KΩ % /W MT00 LR R.KΩ % /0W MT00 LR VUM VUM IN_PU 0mils 0mils R0 R0 R0 0 u V ± 0% mω φ.*. N LR(NU).KΩ % /0W MT00 LR 0KΩ % /W MT00 LR Ω % /W MT00 LR 00mil R TRMO-R 0KΩ % /0=0K± % /=00K MT00 NT RTJVR0J PNONI LR R R R.KΩ % /0W MT00 LR 0KΩ % /W MT00 LR Ω % /W MT00 LR.u V ± 0% 0 XR TK LR(NU) 0.u V ± 0% 0 XR TK LR(NU) Q IRR0Z 0V TO- IR LR 0.u V ± 0% 0 XR TK LR(NU) 0mils 0, 000mils Q IRR0Z 0V TO- IR LR PI Q IO TKY 0V O-(M) PIN PI LR IRR0Z 0V TO- IR LR(NU) 000p 0V 0% 00 XR LR(NU) 0, 000mils L 0.u ± 0%.*0* MM-00-RM M.LYR LR R R0 W 0 % /W 00 W 0 % /W 00 0 T0u V - to 0% mω MT X0Y PNONI LR 0 T0u V - to 0% mω MT X0Y PNONI LR T0u V - to 0% mω MT X0Y PNONI LR(NU) () VN VOR_PU (,,) () VN mil mil space R W 0 % /W 00 R0 W 0 % /W 00 R0 0Ω % /W MT00 LR R0 0Ω % /W MT00 LR lose Output ap IO*Rdroop=Roc*0u If OP= R0=Roc=.Kohm alculation formula ssume R=Rin=K Ohm R=Rfb=[N*Rdroop/(R*)-]*Rin=.K ~.K Rdroop:Intel spec. -.m Ohms L/R=[Rn//R(eqv)]*n =n=l/r/[rn//r(eqv)]=0.u irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W< YonahVNVT > ize ocument Number Rev ustompu ore Power 0. Tuesday, October, 00 ate: heet of 0

11 (,,,,,,,,,,,,, ) VM TRML NOR (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM MLK_PMU Q0 TRN M-T-N N00 0V m OT- PIN PI LR L_T RP p 0V % MT00 NPO LR(NU) R 0KΩ % /W MT00 LR.KΩ % 00 /W PR LR p 0V % MT00 NPO LR(NU) (0,,,,,,,0,,,,,,,,,,,,,,,,,) from OVP & ON_OTOWN (,0) (,0) MLK_PMU MT_PMU (,,,,,,,0,,,,,,,,,) OT_OWN0 V VM (,,,,,,,0,,,,,,,,,) 0.u 0V 0% MT00 XR LR(N U) R R 0KΩ % /W MT00 LR(NU) KΩ % /W MT00 LR R 0KΩ % /W MT00 LR(NU) () V R0 0KΩ % /W MT00 LR N_ON VM 0mil L_T _T ULK 0.u 0V 0% MT00 XR LR L UTT_0 (,,,,,,, ).u 0V ± 0% MT00 XR 0XRKT TK LR PWR 0 % /W U LNR-I U OP PIN MT LR Test V TRM# L LRT# LK N V TRM_T XP XP MT_PMU VM R XP R 0KΩ % /W MT00 LR TR 0MIL 0MIL Q0 0KΩ % /W MT00 LR _T TRN M-T-N N00 0V m OT- PIN PI LR N 000p 0V 0% MT00 XR LR R 00Ω % /0W MT00 LR 00p 0V 0% MT00 XR LR W 0 % /W 00 OR N good signal V0..u 0V 0-0% MT00 YV 0YVZT TK LR PWR 0 % /W 00 R 00..Modify IO ZNR LZ..V 0m MINI-ML PIN PI LR 0.u V 0-0% MT00 YV L R P 00.. VM (,,,,,,,,,,,,, ) TRM () Trace=0mil and together TRM () 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR L L N 0--0 ON NTRY MT PIN P=. 0-0 u 0V 0-0% MT00 YV LMK00Z-T TIYO LR.ar away the RT,clock generator,memory bus,pi bus..s close PU as possible. 0 mil 0 mil () ULK_ U R Ω % /W MT00 LR n ULK L-I NZPX -0 PIN IRIL LR Place this TR closed to V hip. mil V0 () OT_OWN0 Q TR NPN TUT0 0V 00m UMT(-0) PIN ROM LR (,,,,,,,,,,,,, ) VM VM (,,,,,,,0,,,,,,,,, ) V V irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <Thermal / RT> 0. Tuesday, October, 00 ate: heet of

12 OT lock LK lock LK lock PI lock LK lock lock Latout uideline LOK PU_LK[..0] M_LK[..0] ITP_LK[..0] LK_I LK_M LK_P LK_IPI LK_IOPI LK_WPI LK_MINIPI LK_PI LK_PMU0PI LK_PI LK_IO LK_I LK_TV LK_I LK_M LNT " ~ "." ~.0 " MX :."." ~.0 "."~.0".0"~.0"." ~." hielding IPLKI, IPLKO hielding (,,,,) I_MT (,,,,) I_MLK (0,,,,,,,0,,,,,,,,,,,,,,,,,) TR / P / 0 mils ( mil space between & 0) / 0 mils / 0 mils / 0 mils / 0 mils / 0 mils 0 mil space 0 mil space VM NOT. ifferentials pairs with the same length (within 0 mil).pu & N trace mismatch within 0 mil Length mismatch within 00 mils Length same as LK lock Length mismatch within 00mils.Making PI length with minimum various. Length Require LK-.". Length mismatch /-.0". Length mismatch /- 00 mils L PWR 0 % /W 00 VM (0) mil space mil space mil space LK_N VM_LK >0mil (0,,,,,,,0,,,,,,,,,,,,,,,,,) p 0V % MT00 NPO LR(NU) 0 R 0 0u 0V 0-0% MT00 YV LR 00 p 0V % MT00 NPO LR(NU) u 0V 0-0% MT00 YV LMK00Z-T TIYO LR.KΩ % 00 /W PR LR(NU) IO not ready.kω % /W MT00 LR VTTPWR R0 IR Ω % /0W MT00 LR lock Package Length anais Processor Package Length mils Montara-M M Package Length mils PU ocket quivalent Length mils R0 R0 or X"TL fin tunv0. 0.0u V 0% MT00 XR LR 0.0u V 0% MT00 0.0u XR LRV 0% MT00 XR LR VM RP W 0 % /W 00 T LK W 0 % /W 00 0 PI_ PI_ PI_ PI_ MO L_M LK T X_LK X_LK PI Q VTTPWR TR NPN TUT0 0V 00m UMT(-0) PIN ROM LR IR p 0V % MT00 NPO LR 0.0u V 0% MT00 XR LR RQ XTL.0Mz -/U- M PIN p ± 0ppm NX. NK LR Y X_LK X_LK p 0V % MT00 NPO LR lock Layout :. lose to lock generator. Trace as short as possible and use mil. Place crystal within 00 mils of LK enerator 0 PU P PI PI-X M.M.M 00.00M M.M.M 00.00M M.M.M 00.00M M.M.M 00.00M 0 0 U X X PUT0 PU0 / MI change PUT R0 Ω % /W MT00 LR V PUT 0 PU 0 R Ω % /W MT00 LR VR PU.Ω % /W MT00 LR VPI R MO R Ω % /W MT00 LR VPI PUT/PIXT0 R TURO/PI PU/PIX0 RP.Ω % /W MT00 LR V LK_ R Ω % /W MT00 LR n VV PIXT PXLKP_N () LK_ R Ω % /W MT00 LR n VPIX_ PIX PXLKN_N () VPIX_ Ω % MT00 /W PR RN-R0-JN YNT LR VPU PIXT R Ω % /W MT00 LR PIX RP 0/R0 /R PIXT LK_PI_XPR () /PI0 Ω % MT00 PIX /W PR RN-R0-JN YNT LR LK_PI_XPR# () /PI.Ω % /W MT00 LR R R0 Ω % /W MT00 LR PI/T_N PIXT/PRQ R.Ω % /W MT00 PI_ LR R Ω % /W MT00 LR(NU) PI PIX/PRQ PI_ R Ω % /W MT00 LR PI LKRQ_X0 () PUTP0 PI_ R Ω % /W MT00 LR PI PIXT/PU_top PITP0 PIX/PIX_top PI_ R00 Ω % /W MT00 LR n Mz/Mode0 LKM0 L_#/_Mz V_0 PUT RP /V_ LK_ PU LK ITP_N/V_ Ω % MT00 /W PR RN-R0-JN YNT LR T PUT0 RP0 PU0 R Ω % MT00 /W PR RN-R0-JN YNT LR PI VTTPW/P PI Under RT OR PU into design V mil IR V PIX_ PU PIX_ 0 PUT0 PU0 I LOK-/uffers I00L-T OP PIN I LR L_M R 0KΩ % /W MT00 LR 0.u V 0-0% MT00 YV LR VM_LK 0.u V 0-0% MT00 YV LR MI requst / Under 00mil R R R R Under 00mil Under 00mil hielding LK LK- hielding 0 mil space mil space 0 mil space mil space mil space mil space mil space ( mil width for differential signals and shiekding) Mount these capacitor Modify LKM_ LKM_UI LKM_ LKM_N LKM_ LKM_ LKM_ LKM_PI LKM_K LKM_W LKM_MINI LKM_ () LKM_UI () LKM_ () LKM_N () LKM_ () LKM_ () LKM_ () LKM_PI () LKM_K () LKM_W () LKM_MINI ().Ω % /W MT00 LR PU_LK () PU_LK0 ().Ω % /W MT00 LR LKN () LKN0 ().Ω % /W MT00 LR.Ω % /W MT00 LR 0 p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR () 0 _L0 R R00 R0 VM PU_LK0 0 p 0V ± 0.p - TO MT00 NPO LR or LK set up install V0. (0,,,,,,,0,,,,,,,,,,,,,,,,,) V0. Modify Q TR NPN MMT_NL 0V OT- PIN IRIL LR(NU) R0 _L0 0_ KΩ % /W MT00 LR R R KΩ % /W MT00 LR(NU) R0 KΩ % /W MT00 LR(NU) R 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) 0KΩ % /W MT00 LR(NU) (,) 0 IPLKO VP (,,,,,,) 0KΩ % /W MT00 LR(NU) W V0. Modify W -0T() PIN.mm OPL L(NU) 0KΩ % /W MT00 LR(NU) V0. Modify hange to 0--0 libarary Modify ON () _L (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM R 0KΩ % /W MT00 LR U ON V N ModOUT LKIN V TR NPN MMT_NL 0V OT- PIN IRIL LR R _L _ VM R 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR VP (,,,,,,) R IPLKI (,) Ω % /W MT00 LR I pread pectrum for MI MP-0-OR TOT- PIN L LR 0.u V 0-0% MT00 YV LR Q0 () _L _L (0,,,,,,,0,,,,,,,,,,,,,,,,,) PUTP0 V0. modify V0. Modify Q TR NPN MMT_NL 0V OT- PIN IRIL LR R0 0KΩ % /W MT00 LR(NU) VM _ R 0KΩ % /W MT00 LR R0 0KΩ % /W MT00 LR R 0KΩ % /W MT00 LR(NU) VP (,,,,,,) IO TKY RV-0 0V 00m O- PIN PI LR PITP0 IO TKY RV-0 0V 00m O- PIN PI LR PU_TP0 () PI_TP0 () VM R 0KΩ % /W MT00 LR(NU) MO V0. MOIY / R 0KΩ % /W MT00 LR(NU) R 0KΩ % /W MT00 LR(NU) R 0KΩ % /W MT00 LR R 0KΩ % /W MT00 LR (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM VM PU_LK LKN LKN0 0 _ p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR p 0V ± 0.p - TO MT00 NPO LR R R R R R V0.Modify irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- VM 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) 0KΩ % /W MT00 LR LM0W < VI VN VT > ize ocument Number Rev ustom<lock-en> 0. Tuesday, October, 00 ate: heet of

13 0 INPUT _OUT _IN RLK0 歐姆 0 歐姆 L: " WLKOU L:." 歐姆 0P L:LL-L." 0P L=LMLM L: " VI VN00 IMM IMM (,0,,,,,, ).VM.VM_LK R LOK UR MI solution 00.0 RLK0# RLK U RLK# RLK RLK# _open 0 歐姆 RLK RLK# RLK RLK# RLK RLK# _open R lock uffer L: " RT0 RP V./. Ω % MT00 /W PR RN-R0-JN YNT LR RT0 R0 V./. R0 0 V./. RT RP Ω % MT00 /W PR RN-R0-JN YNT LR RT R R V RT RP Ω % MT00 /W PR RN-R0-JN YNT LR V RT R R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R RT RP Ω % MT00 /W PR RN-R0-JN YNT LR RT R R (,,,, ) I_MT 0 T RT R (,,,, ) I_MLK LK RT R /0 modify T request () LKO U_INT () LKO- U_IN R0 R0 OUT_T LKI () Ω % /W MT00 LR OUT_ 00Ω % /W MT00 LR 00 I LOK-UR IPL-T OP PIN I LR V0. modify del L,L 0p 0V % MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0 0p 0V ± 0.p MT00 NPO LR 0p 0V ± 0.p MT00 NPO LR M_LK_R0 () M_LK_R00 () M_LK_R () M_LK_R0 () M_LK_R () M_LK_R0 () M_LK_R () M_LK_R0 () MI solution 00.0 ().VM Mount these capacitor Modify.VM_LK 0 L PWR 0 % /W 00 >0 mil 0.u V 0-0% MT00 YV LR 0 T0u 0V ± 0% MT R=.0Ω T0M00T KMT LR 0.u V 0-0% MT00 YV LR 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR (,) IPLKO (0,,,,,,,0,,,,,,,,,,,,,,,,,) R0 0KΩ % /W MT00 LR R0.KΩ % /W MT00 LR U LKIN MR ON# V V R0 R ModOUT VM 0mil LNR-I P00-0R OI PIN L LR L 00Ω ±% 00Mz 000m MT00 ML P- N M.LYR LR R0.KΩ % /W MT00 LR R0.KΩ % /W MT00 LR R0 Ω % /W MT00 LR IPLKI (,) 0.u V 0-0% MT00 YV L R irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <clock buffer> 0. 0 Tuesday, October, 00 ate: heet of

14 0 (,,,,,,) VP () TL_0[.. ] () TL_RQ0[..0] () TL_0[..0] () TL_T00 () TL_T0 () TL_0 () TL_NR0 () TL_PRI0 () TL_R00 () TL_Y0 () TL_R0 () TL_RY0 () TL_IT0 () TL_ITM0 () TL_LOK0 () TL_TRY0 () TL_RQ0[..0] () TL_R0[..0] () TL_INV00 () TL_INV0 () TL_INV0 () TL_INV0 () TL_PURT0 () LKN () LKN0 TL_0 M TL_0 N TL_0 R TL_0 T TL_0 R TL_0 P TL_0 P TL_00 N TL_0 R TL_0 U TL_0 U TL_0 U TL_0 T0 TL_0 U TL_0 W TL_0 V TL_0 V TL_00 V TL_0 W TL_0 W TL_0 TL_0 V TL_0 TL_0 Y TL_0 Y TL_0 TL_0 W TL_00 V TL_0 W Y R W L K J M K J K L L J M TL_RQ00 T TL_RQ0 T TL_RQ0 R TL_RQ0 M TL_RQ0 M TL_R00 J TL_R0 N TL_R0 J 0 U # 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# 0# # 0# # 0# # # # # # # # # # # # # # # 0# # # # # 0# # # # # # # # # # # # # # # 0# # # # # Y, no pad on VN 0# # # # # # T0P# # T# # # # # NR# # PRI# 0# RQ0# # Y# # R# # RY# # IT# # ITM# # LOK# # TRY# # # RQ0# 0# RQ# # RQ# # RQ# # RQ# # R0# # R# # R# # # I0# # I# 0# I# # I# # # PURT# T0P# LK T0N# LK- TP# TN# VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_0 TL_00 TL_0 TL_0 TL_0 TL_TP00 () TL_TN00 () TL_TP0 () TL_TN0 () (,,,,,,) VP Place these parts near N. as close as possible. 0u 0V 0-0% MT00 YV LR 0u 0V 0-0% MT00 YV LR 0u 0V 0-0% MT00 YV LR 0u 0V 0-0% MT00 YV LR 0u 0V 0-0% MT00 YV LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR TLVR_N U0 J TP# TN# TL_TP0 () TL_TN0 () (,,,,,,) VP R0 R0 0Ω % /0W MT00 LR 0Ω % /0W MT00 LR TP# TN# TL_TP0 () TL_TN0 () I N VN PIN VR: VI LR Rev. T L R 0Ω % /W MT00 LR TL_PWR0 () _T0N () 0 TLVR0 TLVR TLOMPP TLOMPN T0N# PWR# (,,,,,,) VP lose to all, 0mil width TLVR_N R0.Ω % /0W MT00 LR R0 00Ω % /0W MT00 LR 0 0.0u V 0% MT00 X R LR 0 0.0u V 0% MT00 X R LR 0 0.0u V 0% MT00 X R LR close to N/ Place these parts near N. as close as possible. nd place each capacitor per pin. irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <VN00 host> 0. 0 Tuesday, October, 00 ate: heet of

15 0 (,,,,, ).V_IMM (,,,,, ) R_.V (,) M_[..0] (,) M_QM[..0] M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM J K J K 0 J J K L P L L M T M K L M J K N M M K0 K M R L0 M0 L M R T N N M P M M N N P T T R T R R M P R P N T P 0 N N N0 T P T U M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M M M M M M M M0 M M M QM0# QM# QM# QM# QM# QM# QM# QM# 0 J J K K K L L L0 M M M M N N N N P0 R R T T T T VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM 0 M00 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M M M R# # W# 0# # # # K0 K K K OT0 OT OT OT Q0 Q0- Q Q- Q Q- Q Q- Q Q- Q Q- Q Q- Q Q- MLKI MLKO MLKO- MMVR0 MMVR MMT MOMP R P P T R0 R T0 N0 P R T P N N R T R N R P T P T P T P R N T P R N J R P R P P N P R P0 R0 R R J M M_0 M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_R M_ M_W M_Q_P0 M_Q_N0 M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N M_Q_P M_Q_N RP0 MVR_N MMT MOMP M_[..0] (,) M_R (,) M_ (,) M_W (,) M_[..0] (,) M_K0_R0 (,) M_K_R0 (,) M_K_R0 () M_K_R0 () M_OT0 (,) M_OT (,) M_OT () M_OT () LKI () M_Q_P0 M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P Ω % MT00 /W PR RN-R0-JN YNT LR LKO () LKO- () LKI = L_R ". LKO as short as possible. R0 close to N/, 0mil width M_0_R0 (,) M R0 (,) M R0 () M R0 () M_Q_N0 M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_P[..0] (,) MMT M_Q_N[..0] (,) (,,,,, ) R0 R0.V_IMM 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) (,,,,, ) >0MIL.V_IMM MMT 0 =>R =>R u 0V 0-0% MT0 YV YVZ TK L R.u 0V 0-0% MT00 YV 0YVZT TK LR.u 0V 0-0% MT00 YV 0YVZT TK LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0Ω % /0W MT00 LR I N VN PIN VR: VI LR 0 0 J J J J J (,,,,, ).V_IMM 0Ω % /0W MT00 LR lose to all R0 > 0 mil MVR_N R Ω % /0W MT00 LR 0/ NU u 0V 0-0% MT00 YV LMK00Z-T TIYO LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) 000p 0V 0% MT00 XR LR(NU) 000p 0V 0% MT00 XR LR 000p 0V 0% MT00 XR LR irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <VN00 R> 0. 0 Tuesday, October, 00 ate: heet of

16 0 (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM VM_X u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR P P P P0 P P P RP 0KΩ % MT00 /W PR LR RP0 => port Muxing 0: Two -bit VI interface : One -bit Panel interface => edicate VI Port onfiguration 0: TM : TV ncoder => edicated VI Port election 0: isable : nable => X clock select(vck/lk/k) 0: Refer Internal PLL(efault) : rom xternal 0 => PUK/MK clock select 0: rom N(efault) : rom xternal VM_X 0KΩ % MT00 /W PR LR check with VI () VL_[..] () VL_PR () () () () () R RN LU YN VYN VL_ VL_ VL_0 VL_ VL_ VL_ VL_ VL_ VL_VPR M M T M L L N T M V0 V0 V0 V V V V V VPR R N N N YN VYN VX VX VX U U U0 U U U U U V V V V V V V V V V0 V V V V0 V W W W W W W W W W W0 W W W Y P00 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P VPT VP0V PLK0 U I N VN (0,,,,,,,0,,,,,,,,,,,,,,,, PIN VR: VI LR,) VM P0 0 P P R0 0 P P0 0KΩ % /W MT00 LR(NU ) 0 P R0 0 P P 0KΩ % /W MT00 LR P R0 P P 0KΩ % /W MT00 LR(NU) P R00 P P 0KΩ % /W MT00 LR(NU) P0 R0 P P 0KΩ % /W MT00 LR(NU) VPV () R0 R0 R0 R0 R0 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR 0KΩ % /W MT00 LR(NU) L > 0 mil V_ 00Mz 00Ω % MT00 0 K-0T0 TI-T LR u 0V 0% MT00 XR LR(N U) u 0V 0-0% MT00 YV LMK00Z-T TIYO LR VM V_ V_ R0 RT 0.Ω % /0W MT00 LR > 0mil width (,) PI_INT0 V V RT INT# PN0 PT0 P0 L > 0 mil V_ VM 00Mz 00Ω % MT00 0 K-0T0 TI-T LR u 0V 0% MT00 XR LR(NU ) (0) NV NV POUT PO0 POUT PV0 0 u 0V 0-0% MT00 YV LMK00Z-T TIYO LR PLK PLK L_PLK L_PLK () VLK () () LKM_UI V_PLL V_PLL V_PLL XIN VPLL VPLL VPLL PLL PLL PLL P P UY# IPLKO IPLKI NLT NV L_PT IPLKO_N L_PT () NKL (0) NV (0,) VT () R W 0 % /W 00 P_UY0 () R0 Ω % /W MT00 LR n IPLKO (,) IPLKI (,) L > 0 mil V_PLL 00Mz 00Ω % MT00 0 K-0T0 TI-T LR VM 0 0u.V 0% MT00 XR 0XR0J0 K TK LR 0KΩ % /W MT00 LR 0 0.u 0V 0% MT00 X R LR P P P P P R R R R R R R R R R R R0 R R R R0 R T T T T T T T T T T T0 T T T T T U U U U U U U IPLKI 0 p 0V ± 0.p - TO MT00 NPO LR(NU) IPLKO 0 p 0V ± 0.p - TO MT00 NPO LR(NU) L > 0 mil V_PLL 00Mz 00Ω % MT00 0 K-0T0 TI-T LR VM 0 0.u 0V 0% MT00 X R LR 0 0u.V 0% MT00 XR 0XR0J0 K TK LR VM L > 0 mil V_PLL 00Mz 00Ω % MT00 0 K-0T0 TI-T LR VM (,,0,, ).VM 00 0u.V 0% MT00 XR 0XR0J0 K TK LR 0 0.u 0V 0% MT00 X R LR.KΩ % 00 /W PR LR RP UPPORT "I".VM (,,0,,,,,, ).VM.VM L_PLK () L_PT () (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM VM irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <VN00 vedio> 0. 0 Tuesday, October, 00 ate: heet of

17 0 (,,,,,,) VP (,0,,),,,,,,,,,) V-LINK Vref= 0. 0.KΩ % /0W MT00 LR.VM (,,,,, ) VLR_N > 0 mil () or VN have to stuff VM R0 R0 KΩ % /0W MT00 LR () () () () () () () VL_0 VL_ VL_ VL_ VL_ VL_ VL_ VL_ V0. VL_0 VL_ VL_ VL_ VL_ VL_ VL_ VL_ VLR_N L R0 0Ω % /0W MT00 LRM R0 L 0Ω % /0W MT00 LR L () LKM_N (,0,,).V (,) _PULP0.V_IMM () 0 VL_0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0 VL_UPT VL_UPT0 VL_NT VL_NT0 VL_UPM VL_NM.VM VK.KΩ % /W MT00 LRVMK.V VPX0 VPX VPXK VPX (0,,,,,,,0,,,,,,,,,,,,,,,,,) VL_[..0] (),,,,0,,,,,,,,,,,,,,,,,) VM (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM L0 PWR 0 % /W 00 (0,,,,,,,0,,,,,,,,,,,,,,,, (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM,) VM (0,,,,,,,0,,,,,,,,,,,,,,,,,) VK L PWR 0 % /W 00 L PWR 0 % /W 00 L L VMK PWR 0 % /W 00 VPX0 000p 0V 0% MT00 XR LR(NU) R 000p 0V 0% MT00 XR LR(NU) 0u 0V 0-0% MT00 YV LR R 0Ω % /W MT00 LR () UT0_N or VN no stuff R0.KΩ % /W MT00 LR(NU) (,,,,,, ) PIRT0_N () PWROK_N 0u 0V 0-0% MT00 YV LR P N T R N N P N N T R R T R P M M M M M M0 M M M M N N P P R T T U U V W W Y Y p 0V 0% MT00 XR LR(NU) U V00 V0 V0 V0 V0 V0 V0 V0 V# PXTX00 PXTX00- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX0 PXTX0- PXTX PXTX- PXTX PXTX- PXTX PXTX- PXTX PXTX- PXTX PXTX- UPT UPT- NT NT- UPM NM VLVR VLOMPP VLOMPN VLK VVL VVL VVL V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VU UT# TTIN# RT# PWROK u 0V 0-0% MT00 YV LMK00Z-T TIYO LR N N P R T U V W Y J J J J J J J K K K K K K K PULPIN# VK VMK K MK PX0 PX PXK PX VN only VPX VM VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX0 VPX VPXK VPX VUPX VPXK VP VP VP VP0 VP VP VPLK VP VP VP VP VP VP VP VP0 VP VP VP VP VP VP VM () VPX VPV VP VPLK VP VP VP VP VP VP VP VP VP0 VP VP VP0 VP VP VP VP PI_RXP_X () PI_RXN_X () VPV 0.u 0V 0% MT00 X R LR PI_TXP_X () PI_TXN_X () 0.u 0V 0% MT00 X R LR PXLKP_N () PXLKN_N () INTR# PI_INTR0 () PXT PI_T () PXWK# PI_WK0 (,) PXPI# PI_PI0 () PXPMI# PI_PMI0 () TN# R0 Ω % /0W MT00 LR I N VN PIN VR: VI LR PXOMP0 R0 Ω % /0W MT00 LR PXOMP R0 0.KΩ % /0W MT00 LR PXRXT0 R0 0.KΩ % /0W MT00 LR PXRXT R0 Ω % /0W MT00 LR PXOMP R0 0.KΩ % /0W MT00 LR (0,,,,,,,0,,,,,,,,,,,,,,,, PXRXT,) VM K K K K K K K L L L L L M M M M N N N P P P P P P P P P P P0 000p 0V 0% MT00 XR LR(NU) u 0V 0-0% MT00 YV LMK00Z-T TIYO LR 000p 0V 0% MT00 XR LR(NU) PXRX00/VP0 PXRX00-/VP00 PXRX0/VP00 PXRX0-/VP00 PXRX0/VP00 PXRX0-/VP00 PXRX0/VP0LK PXRX0-/VPTVLKR PXRX0/VP00 PXRX0-/VP00 PXRX0/VP00 PXRX0-/VP00 PXRX0/VP00 PXRX0-/VP000 PXRX0/VP0 PXRX0-/VP0 PXRX0/VP PXRX0-/VP0 PXRX0/VP0 PXRX0-/VP0 PXRX0/VP0 PXRX0-/VP0 PXRX/VPLK PXRX-/VP0 PXRX/VP0 PXRX-/VP0 PXRX/VP0 PXRX-/VP0 PXRX/VP00 PXRX-/VP PXRX/VP PXRX-/VPV 00Mz 00Ω % MT00 0 K-0T0 TI-T LR PXTX PXTX- PXRX PXRX- PXLK PXLK- u 0V 0-0% MT00 YV LMK00Z-T TIYO LR J K L L M M N N P P R T U U V V W W Y Y J K L K L M N M N P R T U T U V W W V Y 00Mz 00Ω % MT00 0 K-0T0 TI-T LR.KΩ % /W MT00 LR L u 0V 0-0% MT00 YV LMK00Z-T TIYO LR Ω % MT00 /W PR LR RP RP RP RP RP L P_LK L L L0 L P_ P_ L L L L L L L L L L Ω % MT00 /W PR RN-R0-JN YNT LR Ω % /W MT00 LR n VP R00 L P_ VP R0 L0 P_LK VP R0 L P_ R.KΩ % /W MT00 LR(NU) R 000p 0V 0% MT00 XR LR(NU) R0 Y Y Y Y Y Y Y Y Y Y0 Y Y Y Y0 Y Y Y (,,,,,,) U P_V (0) VP L[..0] (0) M M M N N N0 N N N N P R T U V W Y VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT (,0,,) P_ (0) P_LK (0) P_ (0).VM (,0,,) VM (,0,,).VM V V V 0 V V V J0 V V J V J J V J V K V V K0 K V K V K V K V L V L V L0 (0,,,,,,,0,,,,,,,,,,,,,,,, V L,) VM V L V L V M V M V M V M0 V M V V M M V V N V N V N V N0 V N P V V P V P V P0 V P V R V R V R V R0 V T V T V T V T0 I N VN PIN VR: VI LR J J0 J J K K K K K L L L L L L L L L M M N N N N N P P P P P P R R R R R T T T T T0 T T T00u V ± 0% R=mΩ MT 00R PNONI LR u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u V 0-0% MT00 YV L R 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR under N/ ( older side).u 0V 0-0% MT00 YV 0YVZT TK LR 0u 0V 0-0% MT00 YV LR.u 0V 0-0% MT00 YV 0YVZT TK L R irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR.u 0V 0-0% MT00 YV 0YVZT TK L R.u 0V 0-0% MT00 YV 0YVZT TK LR.u 0V ± 0% MT00 XR 0XR KT TK LR.u 0V ± 0% MT00 XR 0XR KT TK LR.u 0V ± 0% MT00 XR 0XR KT TK LR.u 0V ± 0% MT00 XR 0XRKT T K LR(NU) 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR.u 0V 0-0% MT00 YV 0YVZT TK L R 0.0u V 0% MT00 X R LR 0.0u V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR 0.u 0V 0% MT00 X R LR.u 0V 0-0% MT00 YV 0YVZT TK L R 0.u 0V 0% MT00 X R LR LM0W < VI VN VT > ize ocument Number Rev <VN00 power> 0. Tuesday, October, 00 ate: heet of

18 0 (,) M_[..0] M_[..0] Place one cap close to every pullup resistors terminated to 0.vddm,,,,0,,,,,,,,,,,,,,,,,) VM R (,) M_[..0] M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ (,) M_[..0] M_ M_ M_0 () M R0 () M R0 () M_LK_R () M_LK_R0 () M_LK_R () M_LK_R0 () M_K_R0 () M_K_R0 (,) M_ (,) M_R (,) M_W 0KΩ % /W MT00 LR (,,,, ) I_MLK (,,,, ) I_MT () M_OT () M_OT (,) M_QM[..0] M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM (,) M_Q_P[..0] M_Q_P0 M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P (,) M_Q_N[..0] M_Q_N0 M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N (,,,,, ).V_IMM or VN no stuff 0/ NU (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM 0 (,) R_VR 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR O IMM 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) N 0 0/P _ 0 0# # K0 K0# K K# K0 K # R# W# 0 L OT0 OT M0 M M M M M M M Q0 Q Q Q Q Q Q Q Q0# Q# Q# Q# Q# Q# Q# Q# V V V V V V V V V V0 V V VP N N N N NTT VR 0 (,) V V V V V V V V V0 V V V V V V V RV TYP M_[..0] Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ KT OXONN MT R O-IMM =. T 0-MN- Lead-free & Ro M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ (,) () 00.. V0. modify for reserve (,) () M_K_R0 M_K0_R0 () (,) NOT: () M R0 Ω % MT00 /W PR RN-R0-JN YNT LR Place one cap close to every pullup resistors terminated to 0.vddm LL terminal close IMM () (,) M R0 M_OT M_OT M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_0 M_ M_ M_ 00 mils MI solution mil Place these.u caps near o-imm NOT: 00 mils LL terminal close IMM (,,,,, ) R_.V.V_IMM (,,,,, ) (,) M_ () M R0 M_0_R0 (,) M_K_R0 (,) M_R (,) M_W (,) M_ (,) M_0 (,) M_OT0 (,) M_ T0u V - to 0% mω MT X0Y PNONI LR(NU) M_K_R0.u 0V ± 0% MT00 XR 0XRKT TK LR M_OT.u 0V ± 0% MT00 XR 0XRKT TK LR RP R_0.VM (,) Ω % MT00 /W PR RN-R0-JN YNT LR RP 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR 0.u 0V ± 0% MT00 XR 0XRKT TK LR(NU).u 0V ± 0% MT00 XR 0XRKT TK LR RP RP RP0 RP RP RP RP.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) RP RP Place these 0.u caps near o-imm R_0.VM (,) 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR 0.mm L R 0.u V 0-0% MT00 YV L R Ω % MT00 /W PR RN-R0-JN YNT LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR u.v ± 0% MT00 XR 0XR0JM TK LR(NU) 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV L R 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR(NU) Place these i-req decoupling caps near M irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <R-dimm-> 0. Tuesday, October, 00 ate: heet of 0

19 0 N (,) M_[..0] (,) M_[..0] M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ M_ (,) M_[..0] M_ M_ M_0 (,) M_0_R0 (,) M R0 () M_LK_R0 () M_LK_R00 () M_LK_R () M_LK_R0 (,) M_K0_R0 (,) M_K_R0 (,) M_ (,) M_R (,) M_W (,,,, ) I_MLK (,,,, ) I_MT (,) M_OT0 (,) M_OT (,) M_QM[..0] M_QM0 M_QM M_QM M_QM M_QM M_QM M_QM M_QM (,) M_Q_P[..0] M_Q_P0 M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P M_Q_P (,) M_Q_N[..0] M_Q_N0 M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N M_Q_N (,,,,, ).V_IMM 0/ NU (0,,,,,,,0,,,,,,,,,,,,,,,,,) VM (,) R_VR 0 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR O IMM 0 0.u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR(NU) 0 M_0 0 Q0 0 M_ Q 00 M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q M_ Q 0 M_0 0/P Q0 0 M_ Q 0 M_ Q M_ Q M_ Q M_ Q M Q M_ Q 0 M_ Q 0 M_ 0 Q 0 M_0 0# Q0 M_ # Q 0 M_ K0 Q M_ K0# Q M_ K Q M_ K# Q M_ K0 Q 0 M_ K Q M_ # Q 0 M_ R# Q 0 M_0 W# Q0 M_ 0 Q 00 M_ Q M_ L Q M_ Q M_ Q M_ OT0 Q M_ OT Q M_ Q 0 M_ M0 Q M_0 M Q0 M_ M Q M_ M Q 0 M_ M Q 0 M_ M Q 0 M_ M Q M_ M Q M_ Q0 Q M_ Q Q M_ Q Q 0 M_0 Q Q0 M_ Q Q M_ Q Q 0 M_ Q Q M_ Q Q M_ Q0# Q M_ Q# Q M_ Q# Q M_ Q# Q M_ Q# Q 0 M_0 Q# Q0 M_ Q# Q M_ Q# Q M_ Q V V V V V V V V V V V V V V V V 0 V0 V V V 0 V V0 V VP V V N V 0 N V 0 N V N V NTT V V (,,,,, ) R_.V VR V0 V 0 0 V 0 V 0 V V V V V V V V V V V V0 V V V V V V V0 V V V 0 V V V V 0 V V V V 0 V V0 RV TYP V V KT OXONN MT R O-IMM =. T 0-NN- Lead-free & Ro Place these resistors near o-imm V0. modify 00.. T0u V - to 0% mω MT X0Y PNONI LR(NU).u 0V ± 0% MT00 XR 0XRKT TK LR 0mil.u 0V ± 0% MT00 XR 0XRKT TK LR.u 0V ± 0% MT00 XR 0XRKT TK LR Place these.u caps near o-imm.v_imm (,,,,, ) MI solution u V 0-0% MT00 YV LR.u 0V ± 0% MT00 XR 0XRKT TK LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR Place these 0.u caps near o-imm V0. MI Modify 0 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR 0.u V 0-0% MT00 YV LR(NU) 0.u V 0-0% MT00 YV LR(NU) Place these i-req decoupling caps near M irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- LM0W < VI VN VT > ize ocument Number Rev <R-dimm-> 0. Tuesday, October, 00 ate: heet of 0

20 0 L[..0] () U L0 L L L L L L L L L L0 L L L L L L L (,,,).VM () P_LK () P_V () P_ () P_ RP VR near to VR VR chip P_ 0KΩ % MT00 /W PR LR P_TYP P_MOL P_P u 0V 0-0% MT00 YV LMK00Z-T TIYO LR LV_TXOUT_L0N () 0 LV_TXOUT_L0P () - LV_TXOUT_LN () 0 LV_TXOUT_LP () - LV_TXOUT_LN () LV_TXOUT_LP () M - T P 0 T LK- LV_TXLK_LN () LK LV_TXLK_LP () V V LVV LVV PLLV PLLV LKIN VYN YN LV LV LV VR LV PLL PLL TYP PLL MOL P# I VTL LV LQP PIN VI LR.VM_LV.VM L 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR L 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR V L0 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR LVV L 00Ω ±% 00Mz 000m MT00 ML P-N M.LYR LR PLLV L PWR 0 % /W 00 PLL L 0Ω ±% 00Mz 00m MT00 ML-00-00P- N M.LYR LR L LV PWR 0 % /W 00 V0. MI Modify V0. MI Modify LVV V PLLV.VM_LV P_LK 0.u V 0-0% MT00 YV LR (NU) 0 u 0V 0-0% MT00 YV LMK00Z-T TIYO LR LV 0.u V 0-0% MT00 YV LR u 0V 0-0% MT00 YV LMK00Z-T TIYO LR VI / recommend 0.u V 0-0% MT00 YV LR (NU) u 0V 0-0% MT00 YV LMK00Z-T TIYO LR PLL 0.u V 0-0% MT00 YV LR (NU) 0u 0V 0-0% MT00 YV LR (NU) Place close to VT 0p 0V ± 0.p MT00 NPO LR(NU) TRPPIN P_ P_TYP P_MOL Powerown ontrol KT VI // recommend PULL-UP alling edge M color mapping bit PULL-OWN Rising edge L color mapping bit.vm_lv (0,,,,,,,,,,,,,,,,,,,,,,,,) VM R.KΩ % /W MT00 LR P_.VM.KΩ % MT00 /W PR L R RP NV0 P_P P_MOL P_TYP P_ NV0 Q TR NPN MMT_NL 0V OT- PIN IRIL LR P_P TRN M-T-N N00_NL 0V m OT- PIN IRIL LR () NV (,) LI0 R.KΩ % /0W MT00 LR () NKL INVN () R0 R.KΩ % /W MT00 LR (NU) (,) NV R () NV KΩ % /W MT00 LR R 0Ω % /W MT00 LR(NU) Q W 0 % /W 00 IO TKY UPT 0V 0.0 OT- PIN NMKO LR R (,,,,,,, ).VM (,,, ) YPWR 0Ω % /W MT00 LR(NU).VM irst International omputer, Inc. L.,NO.00,Yang uang t.,neiu TIPI, TIWN,RO (-)- (0,,,,,,,,,,,,,,,,,,,,,,,,) VM VM LM0W< VI VN VT > ize ocument Number Rev <LV L> 0. 0 Tuesday, October, 00 ate: heet of 0