First International Computer,Inc Protable Computer Group HW Department

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1 First International omputer,inc Protable omputer roup HW epartment oard name : Mother oard chematic. chematic Page escription : Project : P(M). PI & IRQ & M escription : Version : 0. Initial ate : ugust 0, 00. lock iagram :. Net name escription :. oard tack up escription :. chematic modify Item and History :. power on & off & equence :. Layout uideline :. switch setting 0. Original ource Manager ign by : Eric Yang rawing by : Joyce hiu & Winky Hsu ll of heck by : Tin Tang LN ircuit check by : pruce Wu udio ircuit check by : Jimmys Ho Total confirm by : Intel INc. FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev 0. Friday, May 0, 00 ate: heet of

2 . chematic Page escription :.. chematic Page escription. lock iagram. NNOTTION. chematic Modify. Timing iagram. PU Layout uideline. R & LK EN Layout uideline. mfcp othan (/) 0. mfcp othan (/). POWER (PU ORE). Thermal / FN NN. LVIO (/)(LV/PI/V/TV). LVIO (/)(MI/LK/PM). LVIO (/)(R II). LVIO (/)(HOT). LVIO (/)(POWER). LVIO (/)(V/NTF). IH-M (/)(PI/PU/IRQ/LN) 0. IH-M (/)(IE//U/PMU/PIO). IH-M (/)(POWER). IH-M (/)(ROUN). lock enerator. R O-IMM. R O-IMM. TI 0(RU). TI 0(IEE). RU POWER W./NN. RT Port / TV OUT 0. LE /RJ /ITP PORT. L NN. LP PMU0. M NN/-L/R. INTER /MIL W/PEEP. RT / Main W / MU. H / -ROM NN. alexico MINI PI. U NN. Firm Ware Hub (FWH) 0. LP K MX. PI / LP Pull Up/own. IP/LI W; REW. Reset ircuit. UL_LN_EZ. Over Voltage Protect. Power (R.V/ 0.VM/.VM). Power (.V/V/.VM/.VM). IN&IN. MIN TTERY NN 0. attery elect. harge ircuit. attery Voltage ense. Power (PMUV/V). Power (V/V/VM/VM). Power (VP/VORE_MH). Power (LN.0VM). Power (V/V). OE (L). UIO MP / PEKER 0. HEPHONE & PIF. MIIN. II_I0. R ONN. T TO PT ridge. POWER TIMIN. PI & IRQ & M escription : IEL HIP Mini PI(Wireless LN) ardus (TI 0) PIINT IRQ IRQ IRQ IRQ HIP UMTER REQ REQ0 / NT0 REQ / NT REQ / NT REQ / NT LN EZ MiniPI/ardus MiniPI/ardus V/LN IH-M Embeded U.0 HIP MiniPI ardus Mini PI(Wireless LN) LN(EZ) IRQ hannel IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ esciption ystem timer Keyboard (asacde) LN / MOEM erial Port UIO / V / U FLOPPY IK LPT RT PI MOEM/LN ardbus P/ mouse FPU H ROM M hannel M0 M M M M M M M evice MOEM / LN EP FLOPPY IK UIO (ascade) Unused Unused Unused FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev chematic Page & PI & IRQ & M escription 0. Friday, May 0, 00 ate: heet of

3 . lock iagram : IN P PMUV/V V/V V/V VM/VM.VM.V/.VM R_.V R_0.VM LN_V II I0 ard Reader U.VM P P P P P P P P P P P P Thermal ensor MT H P P U U P REERVE U U RT U.0 U0 U P P P TV Port P L P T to PT I/F ridge P U U UIO MP P HEPHONE P0 Mic IN P P K/ TRL T U U0 U0 P LP MX INT K/ ual Layout ZLI OE ' OE L P M NN P0 P Intel othan/yonah P P Processor Host us LVIO MH uf P,,,,, IH-M 0 P,0,, -Link LP U P,0 MI Interface FLH ROM ( F/W Hub) Mb/Mb P Mem us IE U PI_E LI it PI U Mini PI alexico P PU ORE P PU VP MHVRE P RII IMM(ocket) 00MHZ/MHZ RII IMM0(ocket) 00MHZ/MHZ ROM P PMI TI 0 () P, TP P LP PMU0 P P P INTEL UL LN EZ(0/00)/ 0(iga) ual Layout P PMI LOT0 P LK Y PI/LP Pull up/own LI/IP W MIN W NN Over Voltage Protect attery charger T ON attery elect attery Voltage sense FN NN RT REET FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) P P P P P P P P0 P P P P ize ocument Number Rev LOK IRM 0. Friday, May 0, 00 ate: heet of

4 . Net name escription :.oard tack up escription Voltage Rails IN PMUV PMUV V V V V VM VM Vcore_PU VP Vcore_MH.VM.VM.V.V.VM R_.V R_0.VM Primary system power supply.0v always on power rail by LTH or IN.V always on power rail by LTH or IN.0V always on power rail by ON or PU0.V always on power rail by ON or PU0.V power rail.0v power rail.v switched power rail.0v switched power rail ore Voltage.V~0.V for PU.0V for TL Termination Voltage.0V or.v for LVIO core.v for PU PLL Voltage.V switched power rail.v power rail.v always on power rail.v power rail for MH IO.V power rail for RII POWER RIL 0.V RII Termination Voltage VORE_PU ETINTION othan P Layers Layer Layer Layer Layer Layer Layer Layer Layer Layers : epth.mm Impence ohms /- 0% VOLTE 0.~.0V 0 URRENT omponent ide, Microstrip signal Layer round Plane tripline Layer(High peed) round Plane Power Plane tripline Layer(High peed) round Plane older ide,microstrip signal Layer VP othan.0v. VP_MH LVIO.0V 0. VORE_MH LVIO.0V.VM/.VM othan (PLL).V 0. Part Naming onventions N F L Q R RP U Y ignal onditioning Q L_ = = = = = = = = = = apacitor onnector iode Fuse Inductor Transistor Resistor Resistor Pack rbitrary Logic evice rystal and Osc Net Name uffix 0 = = = = ctive Low signal amped (by a resistor) Isolated (by a Q-switch) Filtered (by an inductor or bead) R_.V LVIO (R).V. R MOULE.VM LVIO.V. (LV, TV,PIE) (VM) IHM (ORE)(PLL)(MI)..V IHM.V (U/LN).V IHM (U).V.VM LVIO.V 0. (PIE_,LVIO,RT,HV) 0.VM R RM 0.V VM V V VM IHM (IO) LVIO (TV ) TI0 MiniPI FWH IO LP K OE LK EN LV TI0 MiniPI PMI V IHM (U) MP00 ROM H INT K/ INT M INVERTER.V.V.V (Evaluation) 0.0 (Evaluation) 0.0 (Idle) (Idle) 0. (Run) 0.0 (Idle) 0.~0.(Run) 0.0 (Idle) 0. (Run) 0.0 (Idle) 0. (Run) V V PMI V IHM U m FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- PMUV PMU0 0.0 ize ocument Number Rev PMU0 NNOTTION 0. Friday, May 0, 00 ate: heet of PMUV 0.0 P(M)

5 .chematic modify Item and History : U ROOT UE OLUTION PHE IN HITORY: RT NO display RT NN PIN defined error hnaged RT NN PIN defined V0. T H can't assembly T H NN Reversed Modify T H NN V0. 0 FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev Version Notice 0. Friday, May 0, 00 ate: heet of

6 . power on & off & equence : Power On equencing Timing iagram IHM Timing VI.VM.V VR_ON Vcc-core PU_UP Vccp Vccp_UP Vccgmch Tsft_star_vcc Vboot Vid Tboot Tboot-vid-tr Tcpu_up Tvccp_up.VM MX elta Voltage=00mV.VM(LN).VM(LN) MX elta Voltage=00mV.V MX elta Voltage=00mV.V(LN).V(LN) MX elta Voltage=00mV MHPWR Tgmch_pwrgd.VM VREF_U LK_ENLE# VP V IMVP_PWR Tcpu_pwrgd MX elta Voltage=00mV MX elta Voltage=00mV VREF No Requirement VM MX elta Voltage=00mV VM<--->.VM.VM<--->.VM.VM<--->VREF.VM<--->VREF TTERY ONLY POWER ON TIMIN POWW0 UPEN N REUME TIMIN PMUV/PMUV POWW0 ON V MINW0_IH To IH PMUV/PMUV ON V PM_RMRT0 PM_LP_0 H H H H To IH_M From IH_M PM_RTRT0 PM_LP_0/0/0 PU0 UTT_0 VM,V PM_PWROK To IH From IH From I_0 From I_0 PM_LP_0/0 PU0 UTT_0 V VM PM_PWROK Y_PWROK VRON_VP H H H From IH_M From I_0 From I_0.V N R_PWR Y_PWROK VP,.VM VRON_VP VP/.VM VORE_ON VORE_ON VR_ON VR_ON VORE_PU VORE_PU K0_PWR0 To clock generator To OEM and IH K0_PWR0 PM_VTE To clock enerator ToIH and OEM PM_VTE From IH to PU PU_PWROO From IH to PU PU_PWR PI_RT0 TL_PURT0 To OEM/other PI device PI_RT0 TL_PURT0 To OEM/other PI device From OEM to PU From OEM to PU FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev Montara M power on/off s timing 0. Friday, May 0, 00 ate: heet of

7 . Layout uideline : ystem us ommon lock ignal Layout uide : #, NR#, PRI#, R0#, Y#, EFER#, PWR#, RY#, HIT#, HITM#, LOK#, R[..0]#, TRY#, REET#. Transmission Line Type Total Trace Length Normal Impedance pacing (mils) trip-line(int. Layer) Micro-strip(Ext. Layer).0 ~. inch /-0% & (Int. Layer) & 0(Ext. Layer) Topology : IERR#, FERR# PU L Topology : PROHOT# Receiver R L L VP Rtt L L 0." - " 0" -.0" 0." - " 0" -.0" L L L Rtt R Rtt 0" -.0" /-% /-% 0" -.0" /-% /-% Transmission Line Transmission Line Micro-strip trip-line ource ynchronous T : ignals Name ignals Matching trobes associated trobe Matching with the group T#[..0], INV0# /- 00 mils TP0#,TN0# /- mils T#[..], INV# /- 00 mils TP#,TN# /- mils T#[..], INV# /- 00 mils TP#,TN# /- mils T#[..], INV# /- 00 mils TP#,TN# /- mils PU L Topology : PWROO VP Receiver Rtt L Voltage Translation evice 0." - " 0." - " 0" -.0" 0" -.0" /-% /-% Micro-strip trip-line Topology: T#[..0], INV#[..0], TN#[..0], TP#[..0] Total Trace Length Normal pacing (mils) Transmission ignal Names Impedance Line Type ata to ata trobe to Min Max trobe to ata (inches) (inches) trobe T#[..0] trip-line 0.. /-0% & N INV#[..0] trip-line 0.. /-0% & N IH L Topology : THERMTRIP# MH L PU L PU L IH-M Rss L L VP Rtt VP Rtt L 0." - " 0." - " L 0." - " 0." - " L 0" -.0" 0" -.0" L 0" -.0" 0" -.0" Rtt 0 /-% 0 /-% Rtt /-% /-% Transmission Line Micro-strip trip-line Rss /-% /-% Transmission Line Micro-strip trip-line TN#[..0] TP#[..0] trip-line trip-line Topology: T#[..0], INV#[..0], TN#[..0], TP#[..0] /-0% & /-0% & No trace witdth to trace space ratio requirement relaxation NOTE: allowedcomplementary strobes. The only recommended trace spacing ratio is : & & Total Trace Length Normal pacing (mils) Transmission ignal Names Impedance Line Type ata to ata trobe to Min Max trobe to ata (inches) (inches) trobe T#[..0] trip-line 0..0 /-0% & N INV#[..0] trip-line 0..0 /-0% & N TN#[..0] trip-line 0..0 /-0% & & TP#[..0] trip-line 0..0 /-0% & & No trace witdth to trace space ratio requirement relaxation NOTE: allowedcomplementary strobes. The only recommended trace spacing ratio is : Topology : PULP# IH L L PU L L MH L L Transmission Line 0." - " 0." -.0" 0 Micro-strip 0." - " 0." -.0" 0 trip-line Topology : LINT / NMI, LINT0 / INTR, 0M#, INNE#, PLP#, MI#, TPLK# IH PU Rtest (No tuff) Topology : PU REET# without ITP IH L PU Transmission Line 0." - " Micro-strip 0." - " trip-line L " -." " -." Transmission Line Micro-strip trip-line Rtest Topology: T#[..0], INV#[..0], TN#[..0], TP#[..0] Total Trace Length Normal pacing (mils) Transmission ignal Names Impedance Line Type ata to ata trobe to Min Max trobe to ata (inches) (inches) trobe T#[..0] trip-line 0.. /-0% & N INV#[..0] trip-line 0.. /-0% & N TN#[..0] trip-line 0.. /-0% & & Topology : PU REET# with ITP MH L L VP Rtt Rs L PU ITP L L L L Rs.0" -.0".0" max 0." max. /-% Rtt. /-% TP#[..0] trip-line 0.. /-0% & No trace witdth to trace space ratio requirement relaxation NOTE: allowedcomplementary strobes. The only recommended trace spacing ratio is : & ifferential Impedance Targets for Routing : ource ynchronous RE : ddress#[..], REQ#[..0], T#[..0] Transmission Line Type trip-line Total Trace Length 0. ~. inch Normal Impedance /-0% pacing (mils) & ignal Type Host lock Routing eometry Impedance -mil trace width on - mil spacing 00 Ω /- % MI -mil trace width on - mil spacing 00 Ω /- % ignal Matching /- 0 mils /- mils ignals Name #[..], REQ#[..0] #[.. ignals Matching /- 00 mils /- 00 mils trobes associated with the group T0# T# trobe Matching /- 00 mils /- 00 mils EXT-PI VO -mil trace width on - mil spacing -mil trace width on - mil spacing 00 Ω /- % 00 Ω /- % /- 0 mils /- 0 mils LV -mil trace width on - mil spacing 00 Ω /- % /- 0 mils T -mil trace width on - mil spacing 00 Ω /- % /- 0 mils U.0 PI EXPRE -mil trace width on - mil spacing -mil trace width on - mil spacing 0 Ω /- % 00 Ω /- % /- mil /- mils FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- R -mil trace width on - mil spacing Ω /- % /- 0 mil P(M) ize ocument Number Rev Montara M R Layout uideline 0. Friday, May 0, 00 ate: heet of

8 LVIO R Layout uidelines Note that all length matching formulas are based on MH die-pad to O-IMM pin total length roup locks ata ontrol R ignal roups ommand _M[:0] ; _M[:0] _[:0] ; _[:0] _R# _R# _# ; _# _WE# ; _WE# ompensation MROMPN MROMPP MLEWIN ; MLEWOUT MVREF[:0] Feedback _RVENOUT# ; _RVENOUT# _RVENIN# ; _RVENIN# Length Matching Formulas ignal Name ignal roup Minimum Length Maximum Length K[:0] ontrol to lock lock -.0" lock 0." K#[:0] ommand to lock lock -.0" lock.0" _Q[:0] _Q[:0] _Q[:0] ; _Q[:0] P to lock lock -.0" lock 0." _M[:0] ; _M[:0] trobe to lock lock -.0" lock 0." KE[:0] #[:0] ata to trobe trobe - mils trobe mils M_OT[:0] lock ignals Topologies and Routing uidelines ata trobe ignals Topologies and Routing uidelines // // // //0 O-IMM P L MH Pin P Package Length Range K0-M L L M L M L M R R L M L M L M L L L L L M PU,MH Minimum pacing to other R ignals : mils Minimum pacing to other non-r ignals : 0 mils Trace Width : mils inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : mils Q to Q# pacing : mils outer layerl egment : mils Minmun Q to Q pacing : inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : 0 mils Total Length --LL: Min 0.", Max." Trace Length L : Max 0.", : Max 00 mils Length Matching : Q to K/K# ( lock -.0") </= Q </= ( lock 0.") K0-M M M L L L L PU,MH M L M R MH Pin P Package Length Range // // //0 O-IMM P mil trace, mil pair space L L Min:0." Max:.0" ata ignals Topologies and Routing uidelines MH Pin P Package Length Range L L L O-IMM P ontrol ignals Topologies and Routing uidelines L / / M L L M /0 lock length tolerence within the pair : /- 0 mil lock to lock Length Matching : /- 0 mils Minimum Pair to Pair pacing :? mils Minimum pacing to other R ignals : mils Minimum pacing to other non-r ignals : 0 mils Trace Length L : Max 0.", : Max 00 mils Total Length --LL: Min 0.", Max.0" Minimum pacing to other R ignals : mils Minimum pacing to other non-r ignals : 0 mils Trace Width : mils inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : mils Trace pacing : mils inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : 0 mils Total Length --LL: Min 0.", Max." Trace Length L : Max 0.", : Max 00 mils Q/M to QLength Matching : /- 0 mils LOK HLKPU[..0] HLKN[..0] HLKITP[..0] R LK OT LK LENTH L : Max 0." L : Max 00mils L : Max 0." L : Min " Max " L : Max 0." L : Max 00mils L : Max 00 mils L : Min 00 mils Max " L : Max 0." L : Max 00mils L : Max 00 mils L : Min " Max 0" TRE / PE / mils / mils 0 mils (spacing to other) / mils mils (spacing to other) TRE MUTHIN L/L- : /- 0 mils L/L- /- 0 mils L/L- : /- 0 mils LLL /L- L- L- : /- 0 mils L/L- : 00 /- 0 mils (for P Topology) L/L- : 00 /- 0 mils (for Topology) LLL /L- L- L- : /- mils Rs ohms /- % ohms /- % to ohms /- % /- 0 mils ohms /- % Rt. ohms /- %. ohms /- %. ohms /- % IMPENE 00 ohms /- % differential mode ohms /- % single mode ohms /- % 00 ohms /- % KEW NOTE ifferentials pairs with 0ps Total the same length. (within 0 mil) udget.pu & N trace 00ps for flight mismatch within 0 mil skew 00ps for pin to* MLK_IH & PLK_MH pin skew PLK_TI 0ps for jitter Length mismatch within 00 mils N.Making PI length with minimum various.max skew = ns MH Pin P Package Length Range O-IMM P ommand ignals Topologies and Routing uidelines MH Pin P Package Length Range / / /,/0 L L L L L M L M ohm % L L L L L M L M O-IMM P ohm % Minimum TRL trace pacing : mils Minimum pacing to other R ignals : mils Minimum pacing to other non-r ignals : 0 mils Trace Length L : Max 0." L : Max." Total Length --LL: Min 0.", Max." TRL to K/K# Length Matching : (TRL-.") </= TRL </= ( LK.0") Minimum pacing to other R ignals : mils Minimum pacing to other non-r ignals : 0 mils Trace Width : mils inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : mils Trace pacing : mils inner layerl egment : mils,total Length < /= 000 mils inner layerl egment : mils,total Length > 000 mils outer layerl egment : 0 mils Total Length --LL: Min 0.", Max." Trace Length L Max 0.", : Max 00 mils Trace Length L : Max." LOK U (MHZ) LK PI/PIF LK PLKIH PLKFWH PLKIO PLKLN Length Matching : M to K/K# M OIMM0 PLL M, OIMM PLL Min : lock -.", Max : lock -.0" MLK_IO MLK_IH MLK_ LENTH L : Max 0." L : Min " Max 0" L : Max 0." L : Min " Max 0" L : Z (0" to 0"),Max 0" L : Z (0" to "),Max 0" L : Max 0." L : Max " TRE / PE mils (stripline) 0 mils (spacing to other) mils (stripline) 0 mils (spacing to other) mils (stripline) 0 mils (spacing to other) TRE MUTHIN N N (LL) to IH-M must be within 00 nils to (LL) to IO/ R ohms /- %. ohms /- % ohms /- %. ohms /- % Rt IMPENE ohms /- % ohms /- % ohms /- % KEW NONE NONE NOTE FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev RII/LK en Layout uideline 0. Friday, May 0, 00 ate: heet of

9 E TL_H0[..] TL_H0[..0] TL_H0[..] TL_H0[..0] U- TL_H0 P TL_H0 # U TL_H00 TL_H0 # 0# V TL_H0 TL_H0 # # R TL_H0 TL_H0 # # V TL_H0 TL_H0 # # W TL_H0 TL_H0 # # T TL_H0 TL_H00 # # W TL_H0 TL_H0 0# # Y 0 TL_H0 TL_H0 # # Y 0 TL_H0 TL_H0 # # U TL_H0 TL_H0 # # TL_H00 TL_H0 # 0# Y E TL_H0 TL_H0 # # TL_H0 # # TL_H0 # E TL_H0 # TL_H0 TL_T00 U T0# # TL_H0 # Y TL_H0 TL_0 N # # TL_H0 # T TL_H0 TL_NR0 L NR# # U TL_H0 # V TL_H0 # R TL_H0 TL_R00 N R0# # R TL_H0 # R TL_H00 0# TL_H0 TL_EFER0 L EFER# # U TL_H0 TL_RY0 H RY# # V TL_H0 TL_Y0 M Y# # U V TL_H0 # Y TL_H0 # TL_H0 TL_HIT0 K HIT# # TL_H0 TL_HITM0 K HITM# # Y 0,,,0,,,0, Place testpoint on IERR# with a N 0." away PU_0M0 0M# PU_FERR0_O FERR# PM0# TL_PM00 0 PU_INNE0 INNE# PM# TL_PM0,0 PM# TL_PM0,0 PM# TL_PM0 0 PU_INTR LINT0 PU_NMI LINT R 0 % /W 00(NU) PU_MI0 MI# R# ITP_REET0 0,0 PU_TPLK0 TPLK# THRMTRIP0 should coonect to IH and LVIO without T-ing (No stub) PU_LK PU_LK0 PU_ITP_LK ITP_LK0 Place within " PU_ITP_LK0 ITP_LK R K % /W 00(NU) TET 0 ITP_TK R K % /W 00(NU) R 0 % /W 00 TK TET F 0 ITP_TI TI 0 ITP_TO_O TO 0 ITP_TM TM 0 ITP_TRT0 R. % /W 00 TRT# OMP0 P R. % /W 00 OMP P R. % /W 00 0 TL_PRY0 0 PRY# OMP R0. % /W 00 0 TL_PREQ0 0 PREQ# OMP omp(0,) must be routed width R Less than 0." mils Zo=.ohm,make trace. % /W 00 length shorter than 0." R R KT Foxconn MT PZ0--0 0,,,0,,,0, VP 0 % /W 00. % /W 00 0,,,0,,,0, THERM THERM VP TL_HREQ0[..0] VP,0 THRMTRIP0 0,,,0,,,0, TL_T0,0 PU_INIT0 TL_LOK0 TL_R0[..0] TL_PURT0 PU_PWROO, PU_LP0 PU_PLP0 VP TL_TRY0 TL_PRI0 TL_PWR0 R. % /W 00 R R % /W 00 TL_HREQ00 TL_HREQ0 TL_HREQ0 TL_HREQ0 TL_HREQ0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 PU_IERR0_O TL_R00 TL_R0 TL_R0 00 % /W 00 R P T P T F E E F E F E M J H K L E J REQ0# REQ# REQ# REQ# REQ# # # # 0# # # # # # # # # # 0# # T# IERR# INIT# LOK# R0# R# R# TRY# REET# PWROO LP# PLP# PRI# PWR# THERM THERM THERMTRIP# PROHOT# LK0 LK ddress roup0 ddress roup ontrol ignal Legacy PU Thermal Host LK ITP00 Port ata roup0 ata roup ata roup ata roup INV0# TN0# TP0# # # # # 0# # # # # # # # # # 0# # INV# TN# TP# INV# TN# TP# # # 0# # # # # # # # # # 0# # # # INV# TN# TP# TLREF0/RV TLREF TLREF/PRTP# TLREF/RV RV0 RV RV/EL RV RV/EL0 RV/PI# H L M H F J M J L N M H N K J K L T W W 0 E F F0 E F F F 0 E E E F E TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 PU_N_E PU_N_ PU_N_ PU_N_F PU_N_ TL_INV00 TL_TN00 TL_TP00 TL_INV0 TL_TN0 TL_TP0 TL_INV0 TL_TN0 TL_TP0 TL_INV0 TL_TN0 TL_TP0 TLREF = / VP Max Length : 0." K % /W 00 R R K % /W F 00 PU_EL PU_PRTP0 PU_EL0 PM_PI0 IMVP POWER TTU INITOR omp(,) must be routed width mils Zo= ohm,make trace length shorter than 0." VP 0,,,0,,,0, FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev PU ( othan ) / 0. ate: Friday, May 0, 00 heet of E

10 E, VORE_PU,,,0,,,0, VP U- U- R 0 % /W 00 V0 VP0 0 V0 V00 R V VP V V0 R V VP V V0 R 0 V VP V V0 T V VP E V V0 T E V VP E V V0 T E V VP E 0 V V0 T E V VP F0 V V0 T E V VP F V V0 U E V VP F V V0 U E V0 VP0 F V0 V0 U F V VP K V V U F Intel Recommend Option V VP L V V V F V VP L V V V F0 V VP M V V V F V VP M V V V X 0UF & X 0UF 00 XR V VP N V V V V VP N V V W H V VP P V V W H V VP P V V W J V0 VP0 R 0 V0 V0 W J V VP R V V W K V VP T V V Y U V VP T V V Y V V VP U V V Y V V V V Y W V V V W V VQ0 P Note: othan Processor MHZ V V Y V VQ W TEP use both.v&.v V V Y V V V V0 othan Processor MHZ V0 V0 0 V TEP only use.v V V V V V V V V V 0 % /W 00 R V V V.VM,,,, V V 0 V V V0 F 0 % /W 00(NU) R V V.VM, V V V V V E N V V V V V E V V V V0 V E V0 V0 0 V E0 V V V E V V V E V V V E V V V E V V 0 V E0 V V V E V V V E V V V F V V V0 F V0 V0 V F V V V F V V V F V V 0 V F V V 0 V F V V V F V V V F V V V F V V V VI0 E VR_VI0 F V V E V0 VI F VR_VI F V0 V0 E V VI F VR_VI V V E V VI VR_VI V V E V VI VR_VI V V E V VI H VR_VI V V E V V V F V H V V F0 V H V V F V H V V F V H F V0 Vsense E R V V J F. % /W 00(NU) V0 V0 V J V V E J V V E J V V E J E0 KT Foxconn MT PZ0--0 V V K V V E K V V E K V V E K V V E K V V E0 L V0 V0 E L V V E Layout note : L V V F L F Provide a test point (with no stub) to connect a V V M V V F differential probe between VENE and VENE M V V F M F at the location where the two.ohm resistors V V M V V F terminate the ohm transmission line M V V F N V V F N V0 V0 F N V V F N V Layout note : N V P VENE and VENE lines V P V should be of equal length P V Vsense F R P. % /W 00(NU) V R V R V 0uF.V m ohm RTPE0MF NYO 0uF.V m ohm RTPE0MF NYO 0uF.V m ohm RTPE0MF NYO 0uF.V m ohm RTPE0MF NYO P0uF V 0% EEFX0YR PN(NU) 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0uF.V 0% 00 XR TIYO 0 0.uF V 0% 00 XR 0 0.uF V 0% 00 XR 00 0.uF V 0% 00 XR 0.uF V 0% 00 XR 0 0.uF V 0% 00 XR 0 0.0uF V 0% 00 XR 0 0.uF V 0% 00 XR 0uF.V 0% 00 XR TIYO 0.uF V 0% 00 XR 0 0.uF V 0% 00 XR 0.uF V 0% 00 XR 0.uF V 0% 00 XR T0uF V ±0% mω MT LOW ER EEF0R PNONI KT Foxconn MT PZ0--0 One round One Via FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev PU ( othan ) / 0. Friday, May 0, 00 ate: heet of 0 E

11 VORE_PU F IN _PU,,,,, IN FUE V TR/FF UMN R 0 % /W F MT00 >0mil,,,0,,,,0,,,,,0, VM R0 U 0 % /W V VORE_round 0 V uf 0V 0% 00 XR U0 U 0 U TuF V ±0% 0mΩ TQM NYO(NU) TuF V ±0% 0mΩ TQM NYO.uF V ±0% MT0 XR TMKJKL-T TIYO TuF V ±0% 0mΩ TQM NYO 0.0uF V 0-0% 00 YV.uF V ±0% MT0 XR TMKJKL-T TIYO.uF V ±0% MT0 XR TMKJKL-T TIYO V PN H LX L.uF 0V 0% 00 XR P 0 N Q0 M-FET-N F0 0V TO- PIN FIRHIL IOE TKY HH-0 0V 0.0 O- HENMKO >0mil Q0 >0mil 0.uF 0V 0% 00 XR TR M-FET-N F 0V TO FIRHIL Q0 >0mil TR M-FET-N F 0V TO FIRHIL P N RE mω % W MF MT0 RL0WT-R00-J YNTE L R 0.uH 0 PM0T-RM00 ±0% TK IOE 0V EQ0L NIE Kelvin connections uf 0-0% V 00 YV(NU) For PU Tolerance :tatic:±0mv Ripple:±0mV Voutput:0.00~.0 stepmv Load line slope:mv/ Max urrent : IOE ZENER RLZ..V 0.0 % 0.W VORE_PU 0, VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI OOT0 OOT OOT R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R0 0 % /W T P N R 00 % /0W 00 R 00 % /0W 00 00pF 0V 0% 00 XR R 0 % /W 00 R K % /W 00, VRON_VP R 0 % /W F MT00 HN# OIN OIN- NU_0pF 0V % 00 NPO 0 PM_PRLPVR 0, TPPU0 PM_PI0 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00(NU) MX0_P0 0 0 U PLP# TON R.K % /W 00 00pF 0V % 00 NPO VORE_round F NE,,,0,,,,,,,,,,,,,,0,,,,,,,,, 0, Y_PWROK VORE_ON K0_PWR0,0 PM_VTE VM 0pF 0V % 00 NPO R 0 % /W 00(NU) R 0 % /W 00 R 0 % /W 00 R0 0 % /W 00 R 0K % /W 00 R 0K % /W 00 YPOK LKEN# IMVPOK PO R.K % /W 00 VORE_round VORE_round need VI to N_POWER N TP R 00K % /W 00 VORE_round R 0 % /W 00 MXREF REF 0.uF 0V 0% 00 XR R 00K % /W 00 00pF 0V % 00 NPO R ILIM TIME R K % /W 00 VORE_round.K % /W 00 MX0_P O# I MX0EL QFN 0PIN MXIM VORE_round Vsus:0.V 0 % /W 00 R U0 VORE_round Vboot:.V R 0 % /W 00 OOT0,,,0,,,,0,,,,,0, VM R0 0 % /W 00 U VORE_round R 0 % /W 00 OOT VORE_round R 0 % /W 00(NU) U MXREF R 0 % /W 00(NU) OOT FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev Vcore 0. Friday, May 0, 00 ate: heet of

12 ,,,,,,,,,,,,0 V THERML ENOR R R Thermal Power onsumption: Icc: Max 0u Icc stdby: Max 0u,,,,,,,,,,,,0 V R 0K % /W 00 Trace=0mil and together QMLK_PMU QMT_PMU R 0 % /W 00 R HOT_OWN, K % /W 00 R 00 % /W 00,,,,,,,,,,,,0 V 0K % /W 00 0K % /W 00 0mil N N ddress:00 0X U LNR-I MT OP PIN MT LK 0 0 T LERT# TY# - N TET N N TET N N N V N N R0 K % /W 00 THERM trace0mil and together 00pF 0V 0% 00 XR T=00PF HOUL E PLE LOE POILE TO THE V,,,,,,,,,,,,0 THERM 0.uF V 0-0% 00 YV.Far away the RT,clock generator,memory bus,pi bus..s close PU as possible. 0 mil 0 mil N 0 mil THERM MINIMUM 0 mil THERM N Fan control,,,0,,,,0,,,,,0, 0mil VM R 0 % /W F MT00 uf 0V 0-0% 00 YV U IN OUT 0mil R 0 % /W 00 N 0 Hi_On FN_ON Low_Off Hi_High peed Low_Low peed Hi_.V Low_.V R 0 % /W F MT00 R00 0K % /W 00 Q HN N R K % /W 00 J LNR-I TU J OT- PIN MT R00 % /W 00 TR M-FET-N N00E 0V 0m OT- ILIONIX R K % /W 00 R 0 % /W 00 R0.K % /W 00 uf 0V 0-0% 00 YV Vout R R N F Vout=Vref(R/R) R=R(Vout/Vref-) Vref=.V ON ENTERY W- MT PIN P= FN_TRL R Q TR M-FET-N N00E 0V 0m OT- ILIONIX 0 % /W F MT00 FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev Thermal / FN NN 0. Friday, May 0, 00 ate: heet of

13 0,,,,.VM U0 Note: RT_Red,RT_reen,RT_lue are groud reference MH_LK_PLL0 MH_LK_PLL TV OUT TV OUT TV OUT 0 % /W 00 0 % /W 00 0 % /W 00 VELK VET LUE REEN RE VYN HYN LV_TXOUT_LP LV_TXOUT_LP LV_TXOUT_L0P LV_TXOUT_LN LV_TXOUT_LN LV_TXOUT_L0N TV OUT TV OUT TV OUT LV_ENL, LV_ENKL L_RIHTNE _PT _PLK LV_TXLK_LN LV_TXLK_LP R R R 0 % /W 00 0 % /W 00 0 % /W 00 0 mil 0 mil 0 mil R TVREF J.K % /W MF MT00 R0 R0 R0 R % /W 00 R0 % /W 00 R % 00 LTL_LK LTL_T N_LV_TXLK_UN N_LV_TXLK_UP N_LV_TXOUT_UP N_LV_TXOUT_UP N_LV_TXOUT_U0P N_LV_TXOUT_UN N_LV_TXOUT_UN N_LV_TXOUT_U0N N_LVIO_H N_LVIO_H LI N_LV_LV N_LV_REFH N_LV_REFL R 0 % /W 00(NU) H H E E E 0 0 H J0 F F F F E F F 0 VOTRL_T VOTRL_LK LKN LKP TV_ TV_ TV_ TV_REFET TV_IRTN TV_IRTN TV_IRTN LK T LUE LUE# REEN REEN# RE RE# VYN HYN REFET LI LV LVREFH LVREFL LVEN PNELKLTEN PNELKLTTL PT PLK LTLLK LTLT ILKN ILKP ILKN ILKP LTP LTP LTP0 LTN LTN LTN0 LTP LTP LTP0 LTN LTN LTN0 V TV MI LV PI-EXPRE RPHI EXP_OMPI EXP_IOMPO EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN0 EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXN EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP0 EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_RXP EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN0 EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXN EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP0 EXP_TXP EXP_TXP EXP_TXP EXP_TXP EXP_TXP E0 F 0 H J0 K L0 M N0 P R0 T U0 V W0 Y 0 E F0 H0 J K0 L M0 N P0 R T0 U V0 W E F H J K L M N P R T U V W Y E F H J K L M N P R T U V W N_PE_RXN0 N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN0 N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXN N_PE_RXP0 N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP0 N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_RXP N_PE_TXN0 N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN0 N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXN N_PE_TXP0 N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP0 N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP N_PE_TXP R. % /W MF 00 I LVIO MH F PIN INTEL R LI,,,0,,,,,,,,,,,,,,0,,,,,,,,, VM,,,0,,,,,,,,,,,,,,0,,,,,,,,, VM.K % /W 00,,,,,,.VM,,,,,,.VM R 0K % /W 00 R 0K % /W 00 R.K % /W 00 R.K % /W 00 R.K % /W 00 R0.K % /W 00 Q Q LTL_LK L_LKTL L_LKTL, LTL_T L_LKTL L_LKTL, M-FET-N N00 0V M TO- M-FET-N N00 0V M TO- FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev LVIO(LV/PIE/V/TV/MI) 0. Friday, May 0, 00 ate: heet of

14 ,, VP_MH For ITP Port used only TL_PM0,0 TL_PM0,0 MI_TXN[..0] MI_TXP[..0] MI_RXN[..0] MI_RXP[..0] MH_MLK_R0 MH_MLK_R MH_MLK_R MH_MLK_R MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP N_LVIO_E N_LVIO_0 Y Y M L E J F 0 U0 MIRXN0 MIRXN MIRXN MIRXN MIRXP0 MIRXP MIRXP MIRXP MITXN0 MITXN MITXN MITXN MITXP0 MITXP MITXP MITXP M_K0 M_K M_K M_K M_K M_K MI F/RV F0 F F F F F F F F F F0 F F F F F F F F F F0 RV RV RV RV RV RV RV H F F E J E E H H J H J 0 R00 0K % /W 00 F0 F F F F F F F F0 F F F F F F F F F F0 RV RV RV RV RV RV RV 0 % /W 00(NU) R R 0 % /W 00(NU) MH_EL MH_EL0 T T T T T T T T0 T T T T T T T T T T0 T T T T T T T T T T0 F[:0] 0k ohms pull up or pull down or direct connect form processor MH_MLK_R00 MH_MLK_R0 MH_MLK_R0 MH_MLK_R0 N_LVIO_E0 N_LVIO_0 N K E0 J F 0 M_K0# M_K# M_K# M_K# M_K# M_K# Laout note: Route as short as possible R 0. % /W 00,, MH_M_00 MH_M_0 MH_M_0 MH_M_0 M_OOMP0 M_OOMP MH_OT0 MH_OT MH_OT MH_OT Laout note: Route as short as possible R 0. % /W 00,, MH_M_KE0 MH_M_KE MH_M_KE MH_M_KE R_VREF MH_ROMP0 MH_ROMP P M H K N M H F F P L M N0 K0 K F MH_MXLEW E E MH_MYLEW F F0 M_KE0 M_KE M_KE M_KE M_0# M_# M_# M_# M_OOMP0 M_OOMP M_OT0 M_OT M_OT M_OT MROMPN MROMPP MVREF0 MVREF MXLEWIN MXLEWOUT MYLEWIN MYLEWOUT R MUXIN N LK PM M_UY# EXT_T0# EXT_T# THRMTRIP# PWROK RTIN# REFLKN REFLKP REF_LKN REF_LKP N0 N N N N N N N N N N0 J PM_MUY0 0 J PM_EXTT00 PM_EXTT00 H PM_EXTT0 F THRMTRIP0,0 0 PM_VTE,0 E R PLT_RT0,, 00 % /W 00 MH_REFLK0 MH_REFLK MH_LK0 MH_LK P N_LVIO_P N N_LVIO_N P N_LVIO_P P N_LVIO_P P N_LVIO_P N N_LVIO_N N_LVIO_ N_LVIO_ N_LVIO_ N_LVIO_ N_LVIO_,,,,,,.VM I LVIO MH F PIN INTEL,,,, R_.V R0 PM_EXTT00 0K % /W 00 R PM_EXTT0 0K % /W 00 F F LOW=MIx HIH=MIx R.K % /W 00(NU) F R.K % /W 00 F F (V EL) R.K % /W 00(NU),,,,,, LOW=.0V HIH=.V.VM R K % /W 00(NU) F (R trap) LOW=R N=R F R0 0. % 00 MH_ROMP0 MH_ROMP F F PIE raphics Lane F LOW=Reverse Lane HIH=Normal operation R0.K % /W 00(NU) F (F ynamic OT) R.K % /W 00 LOW=T/Transportable PU HIH=Mobile PU,,,,,,.VM R K % /W 00(NU) F LOW=.0V (VTT EL) HIH=.V F R 0. % 00 F (PU trap) LOW=T/Transportable PU HIH=Mobile PU F[:] have internal pullup resistors F[:] have internal pulldwon resistors FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev LVIO(MI/LK/PM) 0. Friday, May 0, 00 ate: heet of

15 LVIO(UL R) 0. P(M) FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- Friday, May 0, 00 ize ocument Number Rev ate: heet of M_M0 M_QM M_M M_M M_M M_M M_M0 M_M M_M M_QM M_QM M_QM0 M_Q M_QM M_Q M_Q M_Q M_M M_QM M_Q0 M_Q M_M M_M M_Q M_Q M_M M_M M_QM M_QM M_T M_T M_T M_T0 M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T0 M_T M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_M N_M_RVENIN0 N_M_RVENOUT0 M_QM M_T M_T M_T M_T M_M M_M M_T0 M_T M_T M_T M_T0 M_T M_QM M_T M_T M_T M_T M_QM M_M0 M_M M_T M_T M_T M_T0 M_Q M_T M_Q M_M M_Q M_T M_T M_T M_M M_T M_QM M_T M_T M_M M_T M_T0 M_M M_M0 M_Q M_T M_T M_Q M_M M_T M_T0 M_T M_T M_T M_T M_T M_T M_T M_Q M_M M_QM0 M_T M_T M_T M_T M_T M_T M_M M_M M_T M_T M_Q M_T0 M_QM M_T M_T0 M_QM M_T M_T M_T M_T M_T M_T M_T M_M M_T M_T M_T M_Q0 M_T M_QM M_T M_T M_T M_T N_M_RVENIN0 N_M_RVENOUT0 M_QN M_QN M_QN M_QN M_QN M_QN M_QN M_QN0 M_QN0 M_QN M_QN M_QN M_QN M_QN M_QN M_QN M_Q[..0] M_M[..0] M_R0 M_WE0 M_0 M_0 M_00 M_QM[..0] M_T[..0] M_0 M_WE0 M_Q[..0] M_0 M_00 M_T[..0] M_R0 M_QM[..0] M_0 M_M[..0] M_0 M_QN[..0] M_QN[..0] R YTEM MEMORY U0 I LVIO MH F PIN INTEL E E E E F F0 H H K 0 H J K0 J0 H H K H0 H F J K H H J 0 H H H0 J K J K J H K J J K H E H K H J K J K H J0 H0 J 0 F K J K M0 H F H H K F K K J0 K K E F F F K K J L0 H F J Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ Q0 Q Q Q Q Q Q Q WE# # R# M0 M M M M M M M RVENOUT# RVENIN# M_ Q0# Q# Q# Q# Q# Q# Q# Q# 0# # # R YTEM MEMORY U0 I LVIO MH F PIN INTEL H L L H J K L M N P M M M L M N P N P L0 M0 M L P M M M L M N P M L L P P P0 L M N N N P P M L M K K L M H F E F F L P P M N M L P0 M L0 M N0 M0 K P N P M M J E P N P J P P P L P J F F M K P N0 N N M H E K K L Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M_0 M_ M_ M_ M_ M_ M_ M_ M_ M_ M_0 M_ M_ Q0 Q Q Q Q Q Q Q WE# # R# M0 M M M M M M M RVENOUT# RVENIN# M_ Q0# Q# Q# Q# Q# Q# Q# Q# 0# # #

16 ,, VP_MH U0E,,,,,, MH_HXROMP R 00 % /W 00 VP_MH R0 00 % /W 00 R % /W 00 VP_MH MH_HXWIN R % /W 00 MH_HYWIN MH_HXOMP VP_MH MH_HYOMP R. % /W MF 00 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV R. ±% /W 00 R. ±% /W 00 0.* VP 0.* VP TL_H0[..] TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_HREQ0[..0] TL_HREQ00 TL_HREQ0 TL_HREQ0 TL_HREQ0 TL_HREQ0 TL_T00 TL_T0 MH_LK0 MH_LK MH_HYROMP MH_HYOMP MH_HYWIN MH_HXROMP MH_HXOMP MH_HXWIN TL_TN00 TL_TN0 TL_TN0 TL_TN0 TL_TP00 TL_TP0 TL_TP0 TL_TP0 TL_INV00 TL_INV0 TL_INV0 TL_INV0,0 TL_PURT0 MH_HVREF N_MH_HERY0 TL_PWR0 N_MH_HPREQ0 R, PU_LP0 0 % /W 00(NU) E 0 F 0 E0 0 E F0 0 F E F E T L P K R V K R W H K T U H0 J F H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# HREQ0# HREQ# HREQ# HREQ# HREQ# HT0# HT# HLKINN HLKINP HYROMP HYOMP HYWIN HXROMP HXOMP HXWIN HTN0# HTN# HTN# HTN# HTP0# HTP# HTP# HTP# HINV0# HINV# HINV# HINV# HPURT# HVREF HERY# HPWR# HPREQ# HPULP# HOT H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# H# H# H# H# H# H0# H# H# H# H# HTRY# HRY# HEFER# HHITM# HHIT# HLOK# HREQ0# HNR# HPRI# HY# HR0# HR# HR# E E F H E F E K F J J H F K H H H K K J H J L K J P L J P L U V R R P T R R U R T T R T V U W U V W W U U Y Y V Y W W Y Y W F F E E TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H0 TL_H00 TL_H0 TL_H0 TL_H0 TL_H0[..0] TL_0 TL_TRY0 TL_RY0 TL_EFER0 TL_HITM0 TL_HIT0 TL_LOK0 TL_R00 TL_NR0 TL_PRI0 TL_Y0 TL_R00 TL_R0 TL_R0 MH_HYROMP R I LVIO MH F PIN INTEL. % /W MF 00,, VP_MH MH_HVREF R0 00 % /W 00 R0 00 % /W 00 / * VP FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev LVIO(HOT) 0. Friday, May 0, 00 ate: heet of

17 R 0,,,,.VM 0 % /W 00 0.uF V 0% 00 XR R0,,,,.VM 0 % /W 00 0.uF V 0% 00 XR R,,,,.VM 0 % /W 00 0.uF V 0% 00 XR V.VM_LV V.VM_LV V.VM_TXLV,0,,0,,,0, 0 0uF.V 0% 00 XR TIYO, 0.0uF V 0% 00 XR 0,,,, VORE_MH.VM Layot note: V_RT Route caps within 0 mil of LVIO. Route F within " of LVIO VP 0m,, R 0 % /W 00 VP_MH R, VORE_MH P N K % /W 00 IOE RV-0 0V 0m UM ROHM R,,,,,,.VM 0 % /W F MT00 T 0uF.V ±0% mω MT LOW ER PL0EM() NE T 0uF.V ±0% mω MT LOW ER PL0EM() NE(NU) L uh±% m NL0T-R0J TK.uF 0V 0-0% 00 YV R 0 % /W uF.V 0% 00 XR TIYO 0 0uF.V 0% 00 XR TIYO T 0uF.V ±0% mω MT LOW ER PL0EM() NE T 0uF.V ±0% mω MT LOW ER PL0EM() NE UE E 0 OHM L 0 0uF.V 0% 00 XR TIYO 00MHZ 0Ω 00 FM0K-T0 Route V_RT gnd form MH to decoupling cap ground lead and then connect to the gnd plane 0 0.uF V 0% 00 YV 0.uF V 0% 00 YV L uh±% m NL0T-R0J TK T 0uF.V ±0% mω MT LOW ER PL0EM() NE 0.uF V 0% 00 YV L 0uH±% m NL0T-00J TK 0.uF V 0% 00 XR L 0uH±% m NL0T-00J TK T 0uF.V ±0% mω MT LOW ER PL0EM() NE(NU) T 0uF.V ±0% mω MT LOW ER PL0EM() NE(NU) 0.uF V 0% 00 XR 0.uF V 0% 00 XR 0 0.uF V 0% 00 XR 0.uF V 0% 00 XR.VM_RT.VM_YN m 0m 0m 0m 0m 0.uF V 0% 00 XR 0.uF 0V 0% 00 XR m,.vm_pll.vm_pll.vm_hmpll nf V ±0% 00 XR 0 0.uF V 0% 00 XR 0.uF V 0% 00 XR 0.uF 0V 0% 00 XR.VM_MPLL VP_MH_P VP_MH_P VP_MH_P VP_MH_P V_MH U0F T V0 R V N V M V K V J V V V U V T V R V P V0 N V M V L V K V J V H V V V V U V T V0 R V P V N V M V L V K V J V H V K V H V0 K V J V K V K V K V K V W0 V U0 V T0 V K0 V0 V V U V K V W V V V T V K V K V VHPLL VMPLL VPLL VPLL VHMPLL0 VHMPLL F V_RT0 E V_RT V_RT H0 VYN K VTT0 J VTT K VTT W VTT V VTT U VTT T VTT R VTT P VTT N VTT M VTT0 L VTT K VTT W0 VTT V0 VTT U0 VTT T0 VTT R0 VTT P0 VTT N0 VTT M0 VTT0 K0 VTT J0 VTT Y VTT W VTT U VTT R VTT P VTT N VTT M VTT L VTT0 J VTT N VTT M VTT N VTT M VTT N VTT M VTT VTT N VTT M VTT0 N VTT M VTT N VTT M VTT N VTT M VTT VTT V VTT N VTT M VTT0 VTT POWER VTV0 VTV VTV0 VTV VTV0 VTV VTV VTV VTV VQTV VHV0 VHV VHV VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM VM VM0 VM VM VM VM VM VM VM VM0 V0 V V V V V V VTXLV VTXLV VTXLV0 VLV VLV VLV0 VLV VPLL0 VPLL VPLL V V F E F E H H.VM_TV 0m 0m.VM_TV.VM_TV UE E 0 OHM 0m 00MHZ 0Ω 00 FM0K-T0 UE E 0 OHM IOE RV-0 0V 0m UM ROHM 00MHZ 0Ω 00 FM0K-T0 R UE E 0 OHM K % /W 00 0.m 00MHZ 0Ω 00 FM0K-T0 UE E 0 OHM L MV._R_P 0.uF V 0% 00 XR 00MHZ 0Ω 00 FM0K-T0 HV._R_P 0.uF V 0% 00 XR Route VTV gnd from MH P V._R_P to decupling cap ground lead 0.uF V 0% 00 XR and then connect to the gnd plane R P Note: N m ll VM.VM 0,,,, M L pin K 0 % /W 00 J shorted H internally UE E 0 OHM F.V_QTV L E P N M L 00MHZ 0Ω 00 FM0K-T0 K J H m.v_hv R F E.VM,,,,,, E E E 0 % /W 00 E 0uF 0% 0V 0 XR E0 0.uF V 0% 00 XR E E MH_R_.V R E E H. R_.V,,,, E E H. 0 % /W 0 P N M L K J H F E P N M L K J H F E 00MHZ H 0. Note: 00MHZ H 0. ll VM pin shorted internally 0 MHZ H 0. P V._R_P MHZ H 0. M V._R_P 0.uF V 0% 00 XR E V._R_P 0.uF V 0% 00 XR R.VM_RLLL 0.uF V 0% 00 XR 0 % /W 00 F RLL_L.VM 0,,,, F uh±% m NL0T-R0J TK P F0 0.uF V 0% 00 XR T 00uF 0V ±0% MT UE nh E INUTOR W.VM_PIE L R U R PIE_L.VM 0,,,, N 0 % /W 00 L uH ±0% FLM-00-R0MT KIN ORE J T0uF V 0% 0mΩ KEMET 0uF 0% 0V 0 XR 0m 0uF 0% 0V 0 XR V.VM_TXLV Y Y Y F 0uF 0% 0V 0 XR.VM_ 0.uF V 0% 00 XR V.VM_LV nf V ±0% 00 nf XR V ±0% 00 nf XR V ±0% 00 nf XR V ±0% 00 XR nf V ±0% 00 XR nf V ±0% 00 XR.VM_TV.VM_TV 0 0uF 0% 0V 0 XR 0.uF V 0% 00 0.uF XR V 0% 00 0.uF XR V 0% 00 0.uF XR V 0% 00 XR 0.uF V 0% 00 XR 0.uF V 0% 00 XR.VM_PLL V.VM_LV PLL_R_L 0 T 0uF.V ±0% mω MT LOW ER PL0EM() NE(NU) 0 L0 0uF 0% 0V 0 XR 0.uF V 0% 00 XR R 0 0 % /W F MT00 T 0uF.V ±0% mω MT LOW ER PL0EM() NE(NU) L L 0.uF V 0% 00 XR.VM_TV 0.uF V 0% 00 XR L PLL_F_L uh±% m NL0T-R0J TK.VM,,,,,, N 0 R P 0 % /W 00 R 0 % /W 00.VM 0,,,,.VM 0,,,, VM,,,0,,,,,,,,,,,,,,0 0.uF 0V 0% MT00 XR TIYO.uF.V ±0% 00 0XR0JK TK I LVIO MH F PIN INTEL FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev LVIO(POWER) 0. Friday, May 0, 00 ate: heet of

18 LVIO(V/NTF) 0. P(M) FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- Friday, May 0, 00 ize ocument Number Rev ate: heet of MH_R_.V VP_MH,, V_MH, NTF U0H I LVIO MH F PIN INTEL 0 0 W V U T R P N M L W V U T R P N M L W V U T R P N M L W V U T R P N M L W V U T R P N M L W V U T P N M L Y0 R0 P0 N0 M0 L0 Y R P N M L Y R P N M L W V U T P N M L W V U T R P N M L W V U T R P N M L Y Y Y Y Y Y R 0 0 Y R Y W V U T R P N M L Y W V U T R P N M L Y W V U T R P N M L Y Y VMNTF0 VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF0 VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF0 VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF VMNTF0 VMNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VTTNTF0 VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF0 VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VTTNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF0 VNTF VNTF VNTF VNTF VNTF VNTF VNTF VNTF V U0 I LVIO MH F PIN INTEL Y V T P M K H E N L J F E E Y W V U T R P N M L K J H F E N H L F W V U T R P N M L K J H F E N J Y L W V U T R P N M L K J H F E P0 E Y0 0 M J V U P L H F E W E N L J F W E J J F F H L H J E N F F K0 V0 0 F0 E0 0 0 N W T J H L U N J F L K H K N L J W K J F J N L J F Y H F 0 Y0 L0 0 N H E V T K H L Y P L E N K V J E T P L J P L W E N F Y U P L H J N L H E V T P L J E N L J Y V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V VLV V V V0 V

19 PIE ignal Topologies and Routing uidelines,,,,,0,,,,,,,,, VM 0.uF V 0-0% 00 YV,, PLT_RT0 UF_PLT_RT0 U, PI_[..0], PI_/E00, PI_/E0, PI_/E0, PI_/E0, PI_NT00, PI_NT0, PI_NT0 PI_NT0 PI_NT0 0 PI_NT0 0 FM_WP PI_REQ00, PI_REQ0, PI_REQ0 PI_REQ0 PI_REQ0, PNEI, PNEI0 LK_IHPI,, PI_EVEL0,, PI_FRME0,, PI_IRY0, PI_PR,, PI_PERR0, PI_LOK0, PI_Q_PME0 0,, PI_RT0,, PI_ERR0,, PI_TOP0,, PI_TRY0 PLT_RT0 L-I NHT0KR -0 PIN TI,,0 LP_0,,0 LP_,,0 LP_,,0 LP_ LP_RQ00 LP_RQ0,,0 LP_FRME0 LN_MLERT0 IH_MT IH_MLK 0,,0,,,,,,,,, V,,,0,,,,,,,,,,,,,,0,,,,,,,,, VM,,,0,,,,,,,,,,,,,,0,,,,,,,,, VM PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ R 0 % /W 00 R 0 % /W 00 R R 0K % /W 00 0K % /W 00 R R 0K % /W 00 0K % /W 00 R 0K % /W 00 E E F F E F E H J K K L H H H M K K L K J H F E F L M F E J E E P R J J R P N N N N P P W Y W Y U W U /E0# /E# /E# /E# NT0# NT# NT# NT# NT#/PO NT#/PO NT#/PO REQ0# REQ# REQ# REQ# REQ#/PI0 REQ#/PI REQ#/PI0 PILK EVEL# FRME# IRY# PR PERR# PLOK# PME# PIRT# ERR# TOP# TRY# PLTRT# L0 L/F L/F L/F LRQ0# LRQ#/PI LFRME# MLERT#/PIO LINKLERT# MT MLK MLINK MLINK0 MHYN# PI us I/F PU I/F Interrupt I/F LP/FWH EEPROM I/F ystem Managent I/F LN I/F I -IH-M 0PIN INTEL IRET MEI INTERFE PI EXPRE HIN0 HIP0 HON0 HOP0 HIN HIP HON HOP HIN HIP HON HOP HIN HIP HON HIOP MIRXN0 MIRXP0 MITXN0 MITXP0 MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MILKN MILKP MIZOMP MIIROMP 0TE 0M# PLP# PRTP# FERR# INNE# INIT# INT_V# INTR NMI PUPWR/PO RIN# PULP# MI# TPLK# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQE#/PI INT_PIRQF#/PI INT_PIRQ#/PI INT_PIRQH#/PI EEP_ EEP_IN EEP_OUT EEP_HLK LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_RT# LN_RTYN LN_LK H H K K J J M M L L P P N N T T R R V V U U Y Y W W F F F F E F F E F E E N L M L M F E E E V F R0 R TP TP TP TP TP TP0 0 0 MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP 0,,,, MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP,0,,0,,,0, LK_PIE_IH0 LK_PIE_IH R0 0 % /W 00 R 0 % /W 00 R % /W 00 R 0 % /W 00 R 0 % /W 00 VP PI_IRQ0,, PI_IRQ0,, PI_IRQ0, PI_IRQ0 PNEI, PNEI, P0 RII mil mil RP 0Ω % MT MNR /W PR 0.mm LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX PM_LN_ENLE, LN_RTYN LN_PHY_LK 0 % /W 00(NU) 0 % /W 00(NU) 0.uF V 0-0% 00 YV (NU) 0.uF V 0-0% 00 YV (NU) 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV 0.uF V 0-0% 00 YV.VM R0 % /W 00 R0. % /W MF 00 othan- R0 non-stuff othan- R must be stuffed RP IH_0TE 0 PU_0M0 PU_PLP0 PU_PRTP0 PU_FERR0_O PU_INNE0 PU_INIT0 FWH_INIT0 PU_INTR PU_NMI PU_PWROO PU_RIN0 0, PU_LP0, PU_MI0 PU_TPLK0 PIE_LN_RXN0 PIE_LN_RXP0 PIE_LN_TXN0 PIE_LN_TXP0 TP TP TP TP TP TP U ignal V K I OR O N T-0. TMEL PIE Topology IH-M TX Package Length Range PIE evice L Min 0." Max." Topology IH-M TX TRE WITH mils (stripline) mils (microstrip) P P Package Length Range NEWard ONN L Min 0." Max." TX L L L Max." - L L,,,,,,,,,,,,0 LNEE_N R 0K % /W uF V 0% 00 YV PE mils (differential) 0 mils (pair to pair) L Max." - L V L Min 0." Max." L L L L 0 0.uF V 0% 00 YV TRE MUTHIN /- mils L Impedance 00 ohms /-0% PIE evice Package Length Range IH-M RX ap P Max." - L nf ~00nF /-0% 00 or 00 L Min 0." Max " MI ignal Topologies and Routing uidelines EE_ EE_K L L L EE_I EE_O NEWard ONN Package Length Range IH-M RX ap P nf ~00nF /-0% 00 or 00 RX 0.uF V 0-0% 00 YV (NU) R 0K % /W 00 P Package Length Range L L L P Package Length Range,,0 UFF_PIRT0 N_U_ N_U_ U U L-I NPX -0 PIN FIRHIL L-I NPX -0 PIN FIRHIL RX P TX P ignal MI TRE WITH mils (stripline) mils (microstrip) PE mils (differential) 0 mils (pair to pair) 0 mils (non-pie signal) TRE MUTHIN /- mils Impedance 00 ohms /-0% FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev IH (PI / PIE / PU / IRQ / Lan ) / 0. Friday, May 0, 00 ate: heet of

20 ,,,,,,,,,,,,,,,,,0,,,,,,,,,,,0,,,,,,,,, V VM,,0,,,,,,,,, V 0 0.uF V 0-0% 00 YV (NU) U L-I N0PX 0- PIN FIRHIL(NU) IE Layout iude:,,0,,,,,,,,,,0 V ITP_REET0 PM_PRLPVR,,, PU0 R K % /W 00,,,0,, PM_RI0 PM_RMRT0 TPPU0 TPPI0,0 PM_UTT0,,,,,,,,,,,,,,,,,0,,,,,,,,,,,,, PM_MUY0 PM_TLOW0 PI_LKRUN0 MINW00_IH UTT_0,,0, R R R0 R 0 % /W 00 PM_LP_0 VM PIE_WKE0 PI_ERIRQ, PM_VTE 0K % /W 00(NU) 0K % /W 00(NU) R.K % /W 00 R0.K % /W 00 0 % /W 00 R 00 % /W 00 Y_PWROK R 00 % /W 00 R0 00 % /W 00 R0 00 % /W 00 R 0 % /W 00 _THRM0 U V F E0 U T Y T T T W 0 U 0 F U MUY#/PI PM_YRT# PM_TLOW# PM_LKRUN#/PIO PM_PRLPVR PM_PWRTN# PM_PWROK PM_RI# PM_RMRT# PM_LP_# PM_LP_# PM_LP_# PM_TPPU#/PIO0 PM_TPPI#/PIO PM_U_TT#/LPP# PM_THRM# WKE# ERIRQ PM_VTE/VRMPWR Power Managent IT IE P# P# P0 P P P0 P P P P P P P P P P0 P P P P P E F F E E F E IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P IE_P0 IE_P IE_P IE_P IE_P IE_P IE_P[..0] Trace: on (microstrip) on (microstrip ballout) Trace: on (stripline) on (stripline ballout) Must be less than 0 inch The two strob signals must be length matched within 00 mils of each other.the data line must be within /- 0 mils of the averagelength of the two strobes(ior#,iory#). IE_P0 IE_P0 IE_P0 IE_P IE_P IE_P[..0] REF FUNTION EFULT OPTIONL OVERRIE R? No Reboot No tuff tuff R? wap Override No tuff tuff R? oot IO No tuff tuff U.0 Trace Length uide Low-peed ignal round P 0 mil mil mil mil ignals Reference M 0 mil P M mil mil mil lock/ High peed ignal 0 mil M Trace Length ~ inches ignal Mismatch Max mismatch be tween in adata pairs is /- mils No pair to pair length matching requirements URI/URI# Routing on URI,,0,,,,,,,,, Requirements Maximum Trace Length 00 mil URI# Impedance 0 Ohms /- % 00 mil,,0,,,,,,,,, V,,,,,,,,,,,,,,,,,0,,,,,,,,, VM PI,PI (VM) PI,PI (V) U.0 Routing Requirements / Impedance on (stripline) on (microstrip) 0 Ohms /- % ifferential PO (VM) efault: HIH POP[:] (VM) efault: HIH PO (VM) efault: LOW PIO (V) efault: HIH PIO (V) efault: HIH PIO[:] (V) efault: HIH PIO[:] (VM) efault: HIH Q_MI0 E_I0 PM_RI0 LN_ENLE L_ENKL INVEN,, _ITLK, _RT0 _IN0 _IN,, _OUT _YN R 0K % /W 00 R 0 % /W 00 R 0 % /W 00 R 0 % /W 00 R0 0 % /W F MT00(NU) R 0K % /W 00 _OUT R 0K % /W 00(NU) U0_P0 U0_P0- U0_P U0_P- U0_P U0_P- U0_P U0_P- U0_P U0_P- R 0K % /W 00 R 0K % /W 00(NU) 0, O00 O0 O0 V R 0K % /W 00(NU) FN_TRL FN_ON WIRELE_RFON R R M_I0 M_I N_IH_0 0 % /W 00(NU) 0 % /W 00(NU) N_IH_ N_IH_ N_IH_ N_IH_ N_IH_ N_IH_ R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R 0K % /W 00 R. % /W 00 Route U_RI/RI# differentially R0 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R 0K % /W F F E F E F E R M R 0 V P R T F0 Z_ITLK Z_RT# Z_TIN0 Z_TIN Z_TIN Z_TOUT Z_YN U_PP0 U_PN0 U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_O0# U_O# U_O# U_O# U_O#/PI U_O#PI0 U_O#/PI U_O#/PI U_RI U_RI# TP0/PIO TP/PIO TP/PIO0 TP/PIO PI PI PI PI PO PO PO PIO PIO PIO PIO PIO PIO U I/F Unmuxed PIOs PIOs I/F/ZLI I -IH-M 0PIN INTEL Misc locks T REERVE PK# PREQ PIOR# PIOW# PIORY PIEIRQ TLE# T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TLKN TLKP TRI# TRI LK LK ULK LK_RTX LK_RTX INTVRMEN INTPRUER# RTRT# PKR THRMTRIP# RV RV RV RV RV RV RV RV RV E F E F F F E0 V Y Y F E F F U RTRT0 0mil 0mil IE_PK0 IE_PREQ IE_PIOR0 IE_PIOW0 IE_PIORY IRQ,,,,,,,,,,,,,,,,,,0,,,,,,,,, 00pF 0V 0% 00 XR 00pF 0V 0% 00 XR 00pF 0V 0% 00 XR 00pF 0V 0% 00 XR R 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R 00 % /W 00 R0. % /W MF 00 T_LE0 T_RXN0 T_RXP0 T_TXN0 T_TXP0 LK_PIE_T0 LK_PIE_T R M % /W 00 Place within 00mils of IH ball MLK_IH MLK_IH 0mil PF 0V % 00 NPO VM R 0M % /W 00 Y tuff for safe mode R IH_PKR K % /W 00 (NU) tufff for No Reboot R K % /W 00 (NU) R PIO K % /W 00 (NU) tuff for swap override PI_NT0 FM_WP T Layout giude are written in H page FREQ XTL.KHZ T- MO TX PF 0V % 00 NPO,,,,,,,,,,,,,,,,,0,,,,,,,,, VM,,,,,,,,,,,,,,,,,0,,,,,,,,, PowerOK VM Layout Note: R needs to placed within " of IH, R must be placed within " of R w/o stub,0,,,,,0, VP R % /W 00, PM_VTE U L-I NHT0KR -0 PIN TI R 0 % /W F MT00 0.uF V 0-0% 00 YV 0.0uF V 0% 00 XR 00pF 0V 0% 00 XR U V T U N OUT R 0K % /W 00 LNR-I PT OT- PIN MITUMI Y_PWROK R 00K % /W 00 0.uF V 0-0% 00 YV(NU) Y_PWROK, elay ms,, THRMTRIP0 IH_PKR RTRT0 M_INTRUER0 IH_PKR R % /W 00 V~.V(: min V) high accuracy range V~.V RT Layout iude:. Keep the lead lengths as short as possible, trace length less inch on each branch. Trace signal coupling must be limited as much as possible by avoiding the rounting of adjacent PI signal close to RTX and RTX. Put a ground plane under the Xtal component. round guard plane is highly recommendceed.. The Oscillator V should be clean, use a filter, such as an R low pass or a ferrite inductor FI International omputer, Inc. FL.,NO,E.,WENHW nd R. LINKOU HIN, TIPEI, TIWN,RO (-)00- P(M) ize ocument Number Rev IH ( IE / / U / PMU / PIO ) / 0. Friday, May 0, 00 ate: heet of 0