2 HBU Intel UMA Block Diagram. Intel CPU. Penryn SV 3,4,5. FSB 800/1066MHz RGB CRT. Cantiga-GM/GL AGTL+ CPU I/F

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1 /MM M/M Pro/x RJ ONN RJ ONN LIN OUT MI IN INTRNL MI HU- Intel UM lock iagram lock enerator ILPR RII /00 lot 0 RII /00 Realtek RT lot Realtek RTL0T 0/00 MOM MOM X0-Z H UIO O X0-Z RII /00 hannel R II /00 hannel U 0 PI H UIO MIx Intel PU Penryn V F 00/0MHz antiga-m/l TL+ PU I/F R I/F INTRT RHPI LV, RT I/F INTL IH-M U 0/ ports THRNT (0/00/000Mb) High efinition udio PI+U 0 T ports PI ports PI LP I/F PI/PI RI,,,,,,0,,,,0, PI -LINK PI Project code : FQ000 P P/N : 0 Revision : R RT LV(ual hannel) PI U 0 U x T LP us K WINON WPL RT 00X00@ L WX+ HMI WM H O YTM / PL INPUT +V LUTOOTH OUTPUT +V 0 YTM / TP INPUT OUTPUT TOUT +VLW +VL YTM / TP INPUT TOUT OUTPUT +0V +V YTM / RT0 INPUT +VLW MXIM HRR MX INPUT OUTPUT T+ TOUT V 0 ILRZ INPUT TOUT P LYR L: L: L: L: L: L: ignal N ignal ignal V 00m PU / OUTPUT 0~V, ignal +VLW OUTPUT +0V +_OR Thermal Mini-ard Flash ROM Flash ROM Touch Int & Fan 0a/b/g/n K M P K MT 0 0 H PKR <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO lock iagram ize ocument Number Rev HU ate: Monday, July 0, 00 heet of

2 ignal H_OUT IHM Functional trap efinitions IH Rev page Usage/When ampled omment XOR hain ntrance/ llows entrance to XOR hain testing when TP PI Port onfig bit, pulled low When TP not pulled low at rising edge Rising dge of PWROK of PWROK, sets bit of RPP (ofig Registers: offset h) This signal has weak internal pull-down L_RT0# PULL-UP 0K H_YN NT#/ PIO PIO0 NT#/ PIO NT#/ PIO NT0#: PI_#/ PIO = ynamic OT nabled (efault) PI_MOI PIO TL# PKR TP PIO/ H_OK PI config bit0, Rising dge of PWROK PI config bit, Rising dge of PWROK Reserved I trap (erver Only) Rising dge of PWROK Top-lock wap override Rising dge of PWROK oot IO estination election 0: Rising dge of PWROK Integrated TPM nable, Rising dge of LPWROK MI Termination Voltage Rising dge of LPWROK PI xpress Lane Reversal Rising dge of PWROK No Reboot Rising dge of PWROK XOR hain ntrance Rising dge of PWROK Flash escriptor ecurity Override This signal has a weak internal pull-down ets bit0 of PRP (onfig Registers: Offset h) This signal has a weak internal pull-up ets bit of PRP (onfig Registers: Offset h) ignal has weak internal pull-up ets bit of MPLR (evice : Function 0:Offset ) If sampled high, the system is strapped to the "No Reboot" mode (IH will disable the TO Timer system reboot feature) The status is readable via the NO ROOT bit This signal should not be pull low unless using XOR hain testing ampled low: the Flash escriptor ecurity will be The pull-up or pull-down active when configured for native LN_OK# functionality and determined by LN controller _N# trap Rising dge of in effect This should only be enabled in U[:0][P,N] PULL-OWN K PWROK PI Routing This signal should not be pulled high I compatible mode is for server platforms only This signal should not be pulled low for desktop and mobile ampled low: Top-lock wap mode (inverts for all cycles targeting FWH IO space) Note: oftware will not be able to clear the Top-wap bit until the system is rebooted without NT# being pulled down ontrollable via oot IO estination bit (onfig Registers: Offset 0h:bit :0) NT0# is M, 0-PI, 0-PI, -LP ample low: the Integrated TPM will be disable ample high: the MH TPM enable strap is sampled low and the TPM isable bit is clear, the Integrated TPM will be enable The signal is required to be low for desktop applications and required to be high for mobile applications overridden If high, the security measures will be manufacturing environments using an external pull-up resister U Table page page IH Integrated pull-up and pull-down Resistors INL L_LK[:0] L_T[:0] PRLPVR/PIO NRY_TT H_IT_LK H_OK_N#/PIO H_RT# H_IN[:0] H_OUT H_YN LN_OK# NT[:0]#/PIO[,,] PIO0 PIO L[:0]#/FHW[:0]# LN_RX[:0] LRQ[0] LRQ[]/PIO PM# PWRTN# TL# PI_#/PIO/LPIO PI_MOI PI_MIO PKR TH_[:0] TP[] Mus PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K PULL-UP K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K antiga chipset and IHM I/O controller Hub strapping configuration IH Rev Montevina Platform esign guide 0 page Resistor Type/Value Pin Name trap escription onfiguration PULL-UP 0K F[:0] F Frequency elect 000 = F0 0 = F PULL-UP 0K 00 = F00 others = Reserved PULL-UP 0K PULL-UP 0K PULL-OWN 0K PULL-UP 0K PULL-UP 0K PULL-UP 0K F MI Lane Reversal 0 = Normal operation (efault): Lane Numbered in Order = Reverse Lanes MI x mode [MH->IH]: (->0, ->, -> and 0->) MI x mode [MH->IH]: (->0, ->) U Thermal Pair evice LN LN 0 U K LN WLN Miniard FR xternal U TTRY FR xternal U FR MINI <ore esign> WLN LUTOOTH IHM Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, R_RR Taipei Hsien, Taiwan, RO FR 0 MR Table of ontent FR lock enerator F[:] F F[:] F[:] F F F F0 VO _TRLT L T itpm Host Interface Intel Management engine crypto strap PI raphics Lane F0 PI Loopback enable 0 = nable (Note ) = isable (efault) F[:] XOR/LL NOT: Reserved F MI x elect 0 = MI x = MI x (efault) 0 = The itpm Host Interface is enabled (Note ) = The itpm Host Interface is disabled (default) 0 = Transport Layer ecurity (TL) cipher suite with no confidentiality = TL cipher suite with confidentiality(efault) igital isplay Port 0 = Only igital isplay Port or PI is (VO/P/iHMI) operational (efault) oncurrent with PIe = igital display Port and PIe are operating simulataneously via the P port VO Present 0 = Reserved Lanes, ->0, -> ect = Normal operation (efault): Lane Numbered in Order 00 = Reserve 0 = XOR mode nabled 0 = LLZ mode nable (Note ) = isabled (efault) F F ynamic OT 0 = ynamic OT isabled ize ocument Number Rev ate: Tuesday, June 0, 00 heet of 0 = No VO ard Present (efault) = VO ard Present Local Flat Panel (LFP) 0 = LFP isabled (efault) Present = LFP ard Present; PI disabled ll strap signals are sampled with respect to the leading edge of the ()MH Power OK (PWROK) signal itpm can be disabled by a 'oft-trap' option in the Flash-decriptor section of the Firmware This 'oft-trap' is activated only after enabling itpm via F Only one of the F0/F/F straps can be enabled at any time HU

3 H_#[] H_#[] H_T#0 H_RQ#[0] H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# TP-P TP TP-P TP TP-P TP TP-P TP TP-P TP TT TP-P TP0 TP-P TP TP-P TP TP-P TP TP-P TP TP-P TP H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# RV_PU_ J # L # L # K # M # N # J # N 0# P # P # L # P # P # R # M T0# K RQ0# H RQ# K RQ# J RQ# L RQ# H_# Y H_# # U H_# # R H_#0 # W H_# 0# U H_# # Y H_# # U H_# # R H_# # T H_# # T H_# # W H_# # W H_# # Y H_#0 # U H_# 0# V H_# # W H_# # H_# # H_# # # V T# 0M# FRR# INN# TPLK# LINT0 LINT MI# RV_PU_ M RV_PU_ RV#M N RV_PU_ RV#N T RV_PU_ RV#T V RV_PU_ RV#V RV_PU_ RV# RV_PU_ RV# RV_PU_ RV# RV_PU_ RV# RV_PU_0 RV# F RV#F U OF KY_N RRV R ROUP 0 R ROUP IH -KT-PU st: 0000 nd: 000 XP_RT#_R XP_TI XP_TM XP_TO XP/ITP INL ONTROL XP_PM# R # H NR# PRI# FR# H R# F Y# H_R#0 H_R# H_R# PM_THRMTRIP# should connect to IH and MH without T-ing ( No stub) RF-L-P H_# H_NR# H_PRI# H_FR# H_R# H_Y# R0# F H_RQ#0 RJ--P PU_IRR# IRR# 0 R +0V INIT# H_INIT# LOK# H RT# R0# F R# F R# TR# HIT# HITM# PM0# PM# PM# PM# PR# PRQ# TK TI TO TM TRT# R# THRML PROHOT# THRM THRM THRMTRIP# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TO XP_TM XP_TRT# 0 XP_RT#_R HLK LK0 LK R R R R KRJ--P RF-L-P RF-L-P RF-L-P H_LOK# H_TR# H_HIT# H_HITM# +V +0V H_PURT# H_R#[0] PM_THRMTRIP-#, LK_PU_LK LK_PU_LK# Reserve for ITP, when install ITP connector, install R +0V R RF--P H_PURT# H_THRM, H_THRM routing together, Trace width / pacing = 0 / 0 mil R R-P PU_PROHOT#_R +0V H_THRM H_THRM UVZY-P 0RJ--P +0V R ITP ITP onnector 0 +0V ITP_V R +0V XP_RT#_R 0RJ--P XP_RT# XP_PM#0 XP_RT# XP_PM# R 0RJ--P XP_PM# MH_LKL, 0 R 0RJ--P XP_PM# MH_LKL, R 0RJ--P XP_PM# MH_LKL0, H_PURT# H_RT#_R XP_PM# R KRJ--P XP_TK LK_PU_XP# 0 XP_TO_R XP_TO LK_PU_XP R 0RJ--P XP_TK XP_TM XP_TRT# XP_TI MLX-ONN--P XP_TRT# R RF-L-P <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO XP_TK R RF-L-P PU ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

4 H_INV#[0] H_TN#[0] H_TP#[0] H_#[0] H_INV#[0] H_TN#[0] H_TP#[0] H_#[0] PU_L0 PU_L PU_L H_TN#0 H_TP#0 H_INV#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# N H_# # K H_# # P H_# # R H_#0 # L H_# 0# M H_# # L H_# # M H_# # P H_# # Layout notes P H_# # P Z= Ohm 0" MX for TLRF H_# # T H_# # R H_# # L +0V H_#0 # T H_# 0# N # H_TN# L TN# KRF--P H_TP# M TP# R H_INV# N INV# PU_TLRF0 TT TLRF TT TT R PU_TT TT KRF--P KP0VKX-P TT F PU_TT TT F TT TT U OF 0# F # # # F # # # # K # # J 0# J # H # F # K # H # J TN0# H TP0# H INV0# L0 L L # # # # # # # # 0# # # # # # # # TN# TP# INV# # # 0# # # # # # # # # # 0# # # # TN# TP# INV# OMP0 MI OMP OMP OMP PRTP# PLP# PWR# PWROO LP# PI# T RP0 T RP T RP T RP Y V V V T U U Y W Y W W Y U 0 F F F 0 R U Y H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP H_TN# H_TP# H_INV# H_TN# H_TP# H_INV# R RF-L-P R RF-L-P R RF-L-P R RF-L-P H_PRTP#,, H_PLP# H_PWR# H_PWR H_PULP# PI# onnect to V ore -KT-PU TT R KRJ--P TT R KRJ--P R R0 KRJ--P KRJ--P Layout Note: omp0, connect with Zo= ohm, make trace length shorter than 0" omp, connect with Zo= ohm, make trace length shorter than 0" Route the TT and TT signals through a ground referenced Zo = -ohm trace that ends in a via that is near a N via and is accessible through an oscilloscope connection Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO PU ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

5 +_OR U OF F F F0 F F F F F F Please these inside socket cavity on L(North side econdary) F F0 F F F F F F0 P P V P J P K P M P J P K P M P N P N P R P R P T P T P V P W VI0 VI VI VI VI VI VI N N -KT-PU +_OR H_VI0 F H_VI H_VI F H_VI H_VI F H_VI H_VI F H_VI[0] +_OR +_OR Please these inside socket cavity on L(outh side econdary) +_OR +_OR +0V UVMX-P 0 UVMX-P UVMX-P layout note: "V 0" as short as possible R 00RF-L-P-U R 00RF-L-P-U 0 UVMX-P +V 0 0 UVMX-P Please these inside socket cavity on L(North side Primary) UVMX-P UVMX-P T T0UVM-LP 0UVKX-P UVMX-P _N _N UVMX-P +V R 0R00-P 0UVMX-P UVMX-P 0 UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P Layout Note: UVMX-P N and N lines should be of equal length +_OR +_OR +_OR Layout Note: Place as close as possible to the PU pin onnect to V ore 0 UVMX-P Please these outside socket cavity on L(North side econdary) Please these outside socket cavity on L(outh side econdary) Please these inside socket cavity on L(outh side Primary) UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P 0 UVMX-P UVMX-P 0 UVMX-P UVMX-P UVMX-P UVMX-P UVMX-P U OF F F F F F F F F F F H H H H J J J J K K K K L L L L M M M M N N N N P -KT-PU P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F PU_N PU_N PU_N PU_N TP TP-P NTF PIN TP TP-P TP TP-P TP TP-P Layout Note: Provide a test point (with no stub) to connect a differential probe between N and N at the location where the two ohm resistors terminate the ohm transmission line Please these inside socket cavity on L(North side econdary) +0V 0 UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO PU ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

6 H_WIN routing Trace width and pacing use 0 / 0 mil H_WIN Resistors and apacitors close MH 00 mil ( MX ) H_ROMP routing Trace width and pacing use 0 / 0 mil H_WIN U0VKX-P H_ROMP R RF-L-P Place them near to the chip ( < 0") +0V R RF--P +0V R 00RF-L-P-U R KRF--P H_#[0] H_VRF H_VRF H_#[0] H_PURT# H_PULP# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP U F H_#_0 H_#_ F H_#_ H_#_ H_#_ H H_#_ H H_#_ F H_#_ H_#_ H H_#_ M H_#_0 M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ L H_#_0 M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ N0 H_#_0 M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ H_#_0 Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ F H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_WIN H_ROMP H_PURT# H_PULP# H_VRF H_VRF HOT OF 0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_ H_#_0 H_#_ H_#_ H_#_ H_#_ H_#_ H_# H_T#_0 H_T#_ H_NR# H_PRI# H_RQ# H_FR# H_Y# HPLL_LK HPLL_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#_0 H_INV#_ H_INV#_ H_INV#_ H_TN#_0 H_TN#_ H_TN#_ H_TN#_ H_TP#_0 H_TP#_ H_TP#_ H_TP#_ H_RQ#_0 H_RQ#_ H_RQ#_ H_RQ#_ H_RQ#_ H_R#_0 H_R#_ H_R#_ F H M J P R N M P F 0 J 0 H J0 L L J H0 K 0 F K L0 H F 0 H H J F H H J L Y Y L0 M L M K F F H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_#[] H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_R# H_HIT# H_HITM# H_LOK# H_TR# H_INV#[0] H_TN#[0] H_TP#[0] H_#[] H_INV#[0] H_TN#[0] H_TP#[0] H_RQ#[0] H_R#[0] R KRF--P 00 UVZY-P NTI-M-P-U-NF <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

7 +V R 0RF-L-P M_ROMPP M_ROMPN R 0RF-L-P +V R KRF-P F R KRF-P F R K0RF-P F PM_YN#,, H_PRTP# R K0RF-P F0 PM_XTT#0 PM_XTT# R KRF-P F, PM_PWROK,,,, PLT_RT# R KRF-P F R KRF-P F R KRF-P F R K0RF-P F R KRF-P F, PM_THRMTRIP-#, PM_PRLPVR R KRF-P F onnect to V ore R KRF-P F R KRF-P F0 MI Lane Reversal MH_F_ Low = Normal (default) High = Lanes Reversed antiga = K PI xpress raphics Lane MH_F_ Low = Normal (default),,, R 0R00-P 00RJ--P R0 00P0VJN-P F setting MH_LKL0 MH_LKL MH_LKL PM_XTT#0 PM_XTT# PWROK_R RTIN# F F F F F F0 F F F F F F F0 M N R T H H0 H H K L K N M T M Y F H F T R P P0 P N M N P T R0 M0 L H P R T R N P T0 T T0 R F H H F H H H H H F H F F U RRV#M RRV#N RRV#R RRV#T RRV#H RRV#H0 RRV#H RRV#H RRV#K RRV#L RRV#K RRV#N RRV#M RRV#T RRV# RRV# RRV#M RRV#Y RRV# RRV#F RRV#H RRV#F F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 PM_YN# PM_PRTP# PM_XT_T#_0 PM_XT_T#_ PWROK RTIN# THRMTRIP# PRLPVR N# N#F N# N# N#H N# N# N#H N#F N# N#H N#H N#H N#H N# N#H N#F N#H N# N# N# N#F N# N# N#F N# NTI-M-P-U-NF RV F PM N R LK/ ONTROL/OMPNTION LK MI RPHI VI M MI H OF 0 _K_0 _K K_0 _K K#_0 _K# K#_0 _K# K_0 _K K_0 _K #_0 _# #_0 _# OT_0 _OT OT_0 _OT_ M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF M_PWROK M_RXT M_RMRT# PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FX_VI_0 FX_VI_ FX_VI_ FX_VI_ FX_VI_ FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF P_TRLLK P_TRLT VO_TRLLK VO_TRLT LKRQ# IH_YN# TTN# H_LK H_RT# H_I H_O H_YN P T V U0 R R U V0 Y Y Y V R Y F Y H F H V R F F F H 0 H0 H F H F H H N J H N M K H 0 M_ROMPP M_ROMPN M_ROMP_VOH M_ROMP_VOL M_RXT MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVRF M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# TTN# M_LK_R0 M_LK_R M_LK_R M_LK_R M_K0 M_K M_K M_K M_0# M_# M_# M_# M_OT0 M_OT M_OT M_OT Use R need enable RFLK RFLK# RFLK RFLK RFLK# RFLK# RFLK RFLK# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP H_IN_N R0 RJ--P R_VRF_ R0 RF--P LK_MH_PLL LK_MH_PLL# L_LK0 L_T0 M_PWROK L_RT#0 MH_HMI_LK MH_HMI_T MH_LK_RQ# MH_IH_YN# U0VKX-P +V +0V +V _LK _T M_HYN P/VO for HMI used R KRF--P R KRF--P M_VYN H_ITLK_O, H_RT#_O, H_IN H_OUT_O, H_YN_O, TP-P R KRF--P L_KLTTL L_KLT_N _LK _T L_V_N L_VRF ~= 0V R RF--P LV_V TXOUT_L0+ TXOUT_L+ TXOUT_L+ J HMI_L_T- 0 0UVKX-P P_TX#_0 M HMI_L_T- 0UVKX-P TP-P TP TV_ P_TX#_ F M HMI_L_T0-0UVKX-P TP-P TP TV_ TV_ P_TX#_ H M0 HMI_L_LK- 0UVKX-P TP-P TP TV_ TV_ P_TX#_ K M TV_ P_TX#_ R P_TX#_ HMI H N TV_RTN P_TX#_ HMI RN T0 RNKJ--P P_TX#_ U P_TX#_ U0 TV_ONL0 P_TX#_ Y0 TV_ONL TV_ONL_0 P_TX#_0 TV_ONL_ P_TX#_ P_TX#_ 0 P_TX#_ P_TX#_ HMI P_TX#_ HMI TXOUT_L0- TXOUT_L- TXOUT_L- TXLK_L- TXLK_L+ TXLK_L- TXLK_L+ TXOUT_L0- TXOUT_L- TXOUT_L- TXOUT_L0+ TXOUT_L+ TXOUT_L+ M_RN M_R LTL_LK LTL_T LI R R TP M_LU _LK _T MH_H R RJ--P MH_V R RJ--P RT_IRF FOR antiga: 0k_% ohm RT_IRF routing Trace width use 0 mil R KRF--P R K0RF--P KRF--P K0RF--P +V 0UVKX-P 0UVKX-P L M M K J M 0 H 0 0 H F0 0 H J F K J H J J L U L_KLT_TRL L_KLT_N L_TRL_LK L_TRL_T L LK L T L_V_N LV_I LV_V LV_VRFH LV_VRFL LV_LK# LV_LK LV_LK# LV_LK LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ LV_T#_0 LV_T#_ LV_T#_ LV_T#_ LV_T_0 LV_T_ LV_T_ LV_T_ RT_LU RT_RN RT_R RT_IRTN RT LK RT T RT_HYN RT_TVO_IRF RT_VYN NTI-M-P-U-NF M_ROMP_VOH UVMX--P M_ROMP_VOL UVMX--P LV PI-XPR RPHI TV V M_LU R0 M_RN 0RF--P M_R OF 0 P_OMPI P_OMPO P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_0 P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX#_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_RX_0 P_RX_ P_RX_ P_RX_ P_RX_ P_RX_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ P_TX_0 P_TX_ P_TX_ P_TX_ P_TX_ P_TX_ T T H J L L0 N P N T U Y Y Y H J L L N0 P N T U Y W Y 0 J L M M M R N T U U Y Y P_MP P_RXP HMI_L_T+ HMI_L_T+ HMI_L_T0+ HMI_L_LK+ Place lose MH R 0RF--P R 0RF--P R RF-P HMI HMI +_P P_RXP M_LU M_R Place the Ohm resistor within 00 mils ( mm) of the ()MH Place lose MH 0UVKX-P 0UVKX-P 0UVKX-P 0UVKX-P HMI HMI Place lose MH LI LTL_T PM_XTT#0 LTL_LK PM_XTT# R KRF-P R M_RN 0RF--P HMI_T- HMI_T- HMI_T0- HMI_LK- HMI_T+ HMI_T+ HMI_T0+ HMI_LK+ RN RN0KJ--P +V Place lose onnector R 0RF--P R 0RF--P High = Lanes Reversed antiga = K +V RN _LK _T RNKJ--P TTN# +0V R RJ--P R 0R00-P TTN#_ Please lose to U +V Please lose MH R 0KRJ--P TTN#_K Q MMT0WT-P TTN#_K RT Termination/MI Filter L M_R NQ00T-0Y-N-P L M_RN NQ00T-0Y-N-P L M_LU NQ00T-0Y-N-P M_R_M M_RN_M M_LU_M P0VJN-P P0VJN-P Place lose onnector R 0R00-P R R 0R00-P RN R0 0R00-P LU P0VJN-P ize ocument Number Rev Thursday, July 0, 00 ate: heet of Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) HU

8 M Q[0] M Q[0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U J _Q_0 J _Q_ N _Q_ M _Q_ J _Q_ J0 _Q_ M _Q_ M _Q_ N _Q_ N _Q_ U0 _Q_0 T _Q_ N _Q_ N _Q_ U _Q_ U _Q_ V _Q_ Y _Q_ 0 _Q Q_ V _Q_0 Y _Q Q_ 0 _Q_ Y _Q Q_ V _Q_ T _Q_ Y _Q Q_ V _Q_0 W _Q Q_ U _Q Q Q_ U _Q_ V _Q Q Q Q_0 _Q_ U0 _Q_ V _Q Q Q_ Y _Q Q_ V _Q_ V _Q_ T _Q_0 N _Q_ U _Q_ U _Q_ T _Q_ N0 _Q_ M _Q_ M _Q_ J _Q_ J _Q_ N _Q_0 M _Q_ J _Q_ J _Q_ R YTM MMORY NTI-M-P-U-NF OF 0 0 _R# _# _W# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ T 0 0 Y0 M T Y U Y T J J T W U M J T Y U M H F W H H Y M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[0] M Q[0] M Q#[0] M [0] M #0 M # M # M R# M # M W# M M[0] M Q[0] M Q#[0] M [0] M Q[0] M Q[0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U K _Q_0 H _Q_ P _Q_ P _Q_ J _Q_ J _Q_ M _Q_ P _Q_ U _Q_ U _Q Q_0 Y _Q_ T _Q_ R _Q Q Q Q Q Q_ F _Q Q_0 _Q_ F0 _Q_ F _Q Q_ F _Q_ H _Q Q_ H0 _Q Q Q_0 H _Q_ H _Q Q_ H _Q Q_ H _Q_ F _Q_ F _Q Q Q_0 _Q_ Y _Q_ Y _Q_ F _Q_ F _Q Q Q_ V _Q_ U _Q_ R _Q_0 N _Q_ Y _Q_ V _Q_ P _Q_ R _Q_ L _Q_ L _Q_ J _Q_ H _Q_ M _Q_0 M _Q_ H _Q_ J _Q_ R YTM MMORY NTI-M-P-U-NF OF 0 0 _R# _# _W# _M_0 _M M M M M M M Q_0 _Q Q Q Q Q Q Q Q#_0 _Q# Q# Q# Q# Q# Q# Q# M_0 _M M M M M M M M M M_0 _M M M M_ U F M Y 0 F P K L V H U N L V H H T N V U W U W T W Y H U M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M M M M[0] M Q[0] M Q#[0] M [0] M R# M # M W# M #0 M # M # M M[0] M Q[0] M Q#[0] M [0] Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

9 +V U OF 0 +0V TP-P TP TP-P TP P _M N _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M N _M H _M _M F _M 0 _M H _M _M F _M _M _M _M _M Y _M W _M V _M U _M T _M R _M P _M _M/N _M/N _M/N _M/N W _M/N W _M/N T _M/N +0V Y _X _X _X _X _X _X _X Y _X _X _X _X _X J _X _X _X _X _X Y _X H0 _X F0 _X 0 _X 0 _X 0 _X 0 _X T _X T _X M _X L _X _X J _X H _X _X F _X _X _X Y _X V _X U _X N _X M _X U _X T _X _X_N J _X_N _X_N H _X_N NTI-M-P-U-NF POWR M FX FX NTF M LF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _X_NTF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF _M_LF W V W V W V W V W V M L K W V U M0 K0 W0 U0 M L K J H F Y W V U M K H F Y W V M L K J H F Y W V U V M_LF_MH M_LF_MH M0 M_LF_MH V M_LF_MH Y M_LF_MH M0 M_LF_MH M_LF_MH +0V UVZY-P U0VKX-P UVZY-P 0 Place on the dge U0VKX-P Place P where LV and R taps 0UVKX-P U0VKX-P 0 0UVKX-P 0 U0VKX-P UVKX-P 0U0VZY-P FOR M 0 U0VKX-P T T0UVM-P U0VKX-P T T0UVM-P 0 oupling P 0 UVMX-P 0 UVZY-P 0U0VZY-P UVMX-P U0VKX-P UVZY-P +V Place on the dge +0V 0UVKX-P UVZY-P FOR OR 0 UVMX-P oupling P 0 mils from the dge 0U0VZY-P 0UVKX-P UVZY-P oupling P 0UVKX-P UVZY-P 0UVKX-P UF Y V U M K J F Y W V U H F J H F J H F OR R _MH_ T 0R00-P NTI-M-P-U-NF POWR NTF OF 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF +0V M L K J H Y W U M0 L0 K0 H0 0 F Y0 W0 V0 U0 L K J H Y W V L K L K K K K Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) ize ocument Number Rev HU Tuesday, June 0, 00 ate: heet of

10 +0V R 0R00-P +V R VRUN_TV M PLL 0m M +V LO R M R M PLL 0R00-P M PLL F _PLL 0ohm 00MHz 0R00-P M PLL L _PLL M HPLL _HPLL M MPLL +0V _MPLL +V R V_TXLV J _LV R 0R00-P J KP0VKX-P _LV 0R00-P +V R0 FM0KF--P L _P_ M HPLL _P_ 0ohm 00MHz 0R00-P U0VKX-P UVMX-P 0UVKX-P +0V R 0V_RUN_PPLL 0V_M _P_PLL FM0KF--P L 0R00-P 0 0 R0 M MPLL _M P0 _M 0ohm 00MHz N0 _M R 0UVMX-P 0UVKX-P _M P _M N _M T _M R _M P +0V _M +0V L FM0F-T0-P 0ohm 00MHz 0UVMX-P UVZY-P 0UVKX-P U0VZY-P +V LO 0R00-P 0UVKX-P L PY00T-Y-P 0ohm 00MHz 0 0UVKX-P U0VKX-P VRUN_Q 0UVKX-P U0VKX-P U0VKX-P U0VKX-P U0VKX-P 0V_RUN_PPLL 0UVKX-P +V U N N VIN VOUT N# +V LO R0 V_RT_0 0R00-P 0m +V LO VTV L PY00T-Y-P 0ohm 00MHz 0UVKX-P VRUN_TV M _TV +0V VRUN_Q L _Q 0V_RUN_HPLL R F _HPLL 0R00-P 0V_RUN_PPLL 0 _P_PLL 0UVKX-P 0UVKX-P M _LV L _LV 0U0VZY-P +V R _H 0R00-P U0VKX-P 0R00-P 0-0TU-P 0U0VZY-P Reserved for TV ripple 0UVKX-P UVMX-P U0VKX-P 0V_M_K R 0R00-P 0U0VZY-P UVKX-P UVMX--P U0VKX-P U0VKX-P 0UVKX-P UH OF 0 _RT RT_ P _M_K N _M_K P _M_K N _M_K N _M_K M _M_K_NTF M _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF M _M_K_NTF L _M_K_NTF 0UVKX-P _TV TV H _H +V NTI-M-P-U-NF R0 V_U_LV U0VKX-P U0VKX-P RT PLL LV P M TV H LV POWR K TV/RT XF M K MI HV P _XF _XF _XF _M_K _M_K _M_K _M_K _TX_LV LF _HV _HV _HV _P _P _P _P _P _MI _MI _MI _MI LF LF LF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 0 F0 K V U V U U H F H L 0m LF LF LF 0V MI V_M_K V_TXLV_ +V +0V +0V +V +V_HV T--F-P R 0RJ--P R 0R00-P UVZY-P 0m +V_HV UVKX-P UVKX-P 0UVKX-P U0VKX-P m UVKX-P U0VKX-P m UVKX-P U0VKX-P +_P 0UVKX-P m +0V 0V XF R0 0R00-P 0 0UVMX-P 0 UVZY-P 0U0VZY-P KP0VKX-P 0 U0VKX-P 00m R0 0R00-P R0 RF-P 0 0UVMX-P 00m 0U0VZY-P U0VKX-P R0 T T0UVM-LP R +_P R +V +0V Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) ize ocument Number Rev HU ate: Tuesday, June 0, 00 heet 0 of 0R00-P UVMX-P 0R00-P 0U0VZY-P 0R00-P

11 UI U R L W N J F Y T N L Y V R M V R P H F F H Y U T M F V U M J Y T N J N L U M H Y U T M 0 0 V0 N0 H0 0 T M J N L H U H Y U T J F F W T N J H K U OF 0 M P L J F H Y U T F M J F W V R L H P L H N K F N T N K H F V T R J Y P K H F F H F H V R J Y N L J F Y T J H F R L K J F H Y J NTI-M-P-U-NF Modification J to reserved Pin R 0R00-P UJ L W U P N H F R M J 0 0 W0 T0 J0 0 Y0 N0 K0 F0 0 0 W T R M H U N N K W N J N L F V T M J Y N H Y N 0 V0 T0 J0 0 0 M0 F N M H V T NTF N NTI-M-P-U-NF 0 OF 0 _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _NTF _ N# N# N# N# N# N# N# N# N# N# N# N# N# N#F N# N# N# H Y L Y U N J N J V T M M H Y L J H F V L R P F W U R P J H F Y M K M P H U U U U F V J0 M F U U L0 V0 L J U H H F MH_N MH_N MH_N MH_N TP TP-P TP TP-P TP0 TP-P NTF PIN TP TP-P F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO antiga ( of ) Wistron orporation ize ocument Number Rev HU ate: Tuesday, June 0, 00 heet of

12 M M_LK_R0 M_LK_R#0 Layout Note: Place near M +V Layout Note: Place one cap close to every pullup resistors terminated to +0V +0V M M # M #0 M 0 M_OT0 M_0# M M M # M W# UVKX-P UVZY-P UVKX-P UVZY-P UVZY-P U0VZY-P RN RNJ--P RN RNJ--P RN RNJ--P RN RNJ--P RN0 RNJ--P UVZY-P +0V U0VZY-P UVZY-P RN RN UVKX-P 0 RN RN RN UVZY-P M Q#[0] 0 M Q[0] M M[0] M Q[0] M [0] UVZY-P UVZY-P RNJ--P M_K0 RNJ--P M M RNJ--P M M RNJ--P M M UVZY-P RNJ--P M M UVZY-P 0 UVZY-P UVZY-P UVZY-P UVZY-P UVZY-P T UVZY-P T0UVM-LP UVZY-P Layout Note: Place these resistors closely M,all trace length Max=" R_VRF_ M # M #0 M # M_OT0 M_OT R_VRF_ M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT0 M_OT U0VZY-P /P / 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q /Q0 /Q /Q /Q /Q /Q /Q /Q Q0 Q Q Q Q Q Q Q OT0 OT VRF /R 0 /W 0 / /0 0 / K0 K 0 K0 0 /K0 K /K M0 0 M M M 0 M M M 0 M L VP 0 00 N#0 0 N# N# N#0 0 N#/TT V V V V V V V 0 V 0 V V V V M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK RN RN0KJ--P-U M R# M W# M # M_0# M_# M_K0 M_K M_LK_R0 M_LK_R#0 M_LK_R M_LK_R# PM_XTT#0 +V IH_MT,,, IH_MLK,,, +V UVZY-P UMMY- put near connector UMMY- UMMY- UMMY- U0VZY-P M_OT M_# RN RNJ--P RN RNJ--P M # M R# 0 N N 0 R-00P--P-U M_K M RN RNJ--P RN RNJ--P M M 0 UVZY-P <ore esign> M st: 00 nd: 00 nd: 00 Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO RII-OIMM LOT ize ocument Number Rev ustom HU Thursday, July 0, 00 ate: heet of

13 M_LK_R M_LK_R# M Q#[0] M Q[0] Layout Note: Place near M +V +0V M # M W# M M_K M M M 0 M # M M M_# M_OT M_K +0V M M[0] M Q[0] M [0] Layout Note: Place one cap close to every pullup resistors terminated to +0V RN0 UVZY-P 0 UVKX-P RNJ--P UVZY-P RN RN0 RN RN UVKX-P UVZY-P UVZY-P UVZY-P M R# M RNJ--P M M RNJ--P M M RNJ--P M M RNJ--P M 0 M #0 RNJ--P M_# M_OT RNJ--P M # M T T0UVM-LP Layout Note: Place these resistors closely M,all trace length Max=" R_VRF_ M # M #0 M # M_OT M_OT R_VRF_ UMMY- UMMY- UVKX-P UVZY-P RN RN RN RN RN RN UVZY-P U0VZY-P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P RNJ--P UVZY-P UVKX-P RN RN RN RNJ--P UVZY-P UVZY-P 0 UVZY-P UVZY-P UVZY-P UVZY-P 00 UVZY-P UVZY-P UVZY-P M 0 M M M M M M M M M M 0 M M M M M # M #0 M # M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M_OT M_OT U0VZY-P M 0 /R 0 /W 0 / /0 0 / K0 K 0 0/P K0 0 /K0 K /K / M0 0 M 0 M M M 0 Q0 M 0 Q M Q M Q Q Q L Q Q VP Q Q 0 Q0 00 Q Q N#0 0 Q N# Q N# Q N#0 0 Q N#/TT Q Q Q V Q0 V Q V Q V Q V Q V Q V 0 Q V 0 Q V Q V Q V Q0 V Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q /Q0 /Q /Q /Q /Q /Q 0 /Q /Q Q0 Q Q Q Q Q Q Q OT0 OT 0 VRF N N 0 R-00P--P-U M_LK_R M_LK_R# M_LK_R M_LK_R# M M0 M M M M M M M M M M M M M M IH_MT IH_MLK R R +V 0KRJ--P 0KRJ--P PM_XTT# M R# M W# M # M_# M_# M_K M_K M_LK_R M_LK_R# M_LK_R M_LK_R# IH_MT,,, IH_MLK,,, <ore esign> +V UVZY-P UVZY-P UMMY- UMMY- put near connector +V U0VZY-P UVZY-P M st: 00 nd: 00 Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO RII-OIMM LOT ize ocument Number Rev ustom ate: heet of HU Thursday, July 0, 00

14 RT I/F & ONNTOR st: 000 nd: 000 +V_RT LU RN UVZY-P RT RNKJ--P _T_ON V-P +V UVZY-P _LK_ON R R R V-P RN RN _T_ON LU LU JV_H JV_V 0 +V _LK_ON RN YN-ONN-P +V_RT P0VJN-P P0VJN-P P0VJN-P V--F-P +V_RT +V F 0 FFU-P-P st: 000 nd: 000 +V JV_H 0UVKX-P +V_RT H0H-0PT--P-U P0VJN-P Layout Note: * Must be a ground return path between this ground and the ground on the V connector Pi-filter & 0 Ohm pull-down resistors should be as close as to RT ONN R will hit Ohm first, pi-filter, then RT ONN JV_V V-P +V RN RNKJ--P U _T _T_ON +V_RT _LK_ON _LK M_HYN U O# N Y HTW--P UVZY-P HYN_ MN0LW--P ext RT side M_VYN U0 O# N Y HTW--P VYN_ RN RNJ--P-U JV_H JV_V <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO RT onnector ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

15 +V R 0RJ--P, LI_LO# P_L_PWR White L: Lite-On 000 verlight F0 LI_LO# L +VL K L-W--P-U 00RJ--P 0 U0VKX-P R 0KRJ--P R P_L#, LI_LO# OVR_W N N OVR_W 0 KP0VKX-P TP TP--P TP TP--P TP TP--P TP0 TP--P +LV +V UVZY-P 0U0VZY-P UVZY-P UVZY-P +V_MR UVZY-P IZ_T +V _LON _LK _T L / INVRTR INTRF / MR R 00KRJ--P RIHTN_ONN OVR_W U_0+ U_0-0 0 LV 0 0 -ONN--P-U R TXOUT_L+ TXOUT_L- TXOUT_L+ TXOUT_L- TXOUT_L0+ TXOUT_L0- TXLK_L+ TXLK_L- TXOUT_L+ TXOUT_L- TXOUT_L+ TXOUT_L- TXOUT_L0+ TXOUT_L0- TXLK_L+ TXLK_L- 00KRJ--P +V IZ_T0 UVKX-P TOUT IZ_T0 IZ_T (Pin) (Pin) T_L# U0_N0 Q R PTU--P R +V T L T_L +V 0 UVZY-P +V_MR U_0+ U T L_ T_L#_ R0 MN0LW--P 00KRJ--P R U_0-0R00-P U_0- N 0R00-P R Q0 O0-P TP TP--P TP TP--P TP0 TP--P st: 0F0 nd: 0F00 +V_MR RIHTN_ONN " 0" 0 " 0 0" 0 0 R R 0R00-P 0RJ--P RIHTN L_KLTTL U0_P0 R 0R00-P U_0+ TP TP--P 00KRJ--P R0 R 00KRJ--P UVZY-P U0VZY-P R 00KRJ--P +V +LV Layout 0 mil +V U M_PWR# M_PWR# M_PWR_# R 0KRJ--P 0 KP0VKX-P VW--P _LON KP0VKX-P RIHTN_ONN KP0VKX-P +V L_V_N R0 00KRJ--P UVZY-P U0VZY-P IN# N OUT IN# N IN# N IN# IN# RU-P +LV U L_V_N R0 00RJ--P MN0LW--P +V R0 00KRJ--P VW--P 00 - <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO L/Inverter onnector/m/l ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

16 +V K00T-0Y-N-P +V_K0 R 0KRJ--P +V +V_K0 L esign Note: R 0KRJ--P R 0KRJ--P MH_LK_RQ# R0 0KRJ--P ITP_N R 0KRJ--P 0U0VZY-P R-_N/PI- +V_K0 R-_N/PI- PIN, 0 PI_TOP#/PU_TOP# R UVZY-P PI_TM LK_T_O# MH_LK_RQ# PLK_FWH LK_IH ITP_N Output LK_PI_K PLK_IH 0 R PU_ITP PU_L PU_L PU_L0 ll of Input pin didn't have internal pull up resistor lock Request (R) function are enable by registers Y integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic R 0KRJ--P R0 0KRJ--P UVZY-P 0 UVZY-P 0 UVZY-P +V_K0 0 UVZY-P 0 UVZY-P P0VN-P 0 P0VN-P LK_IH LK_ LK_XTL_IN TP_PI# TP_PU#,,, IH_MLK,,, IH_MT K_PWR R RF-L-P R RJ--P R RJ--P R RJ--P P0VN-P R 0R00-P R 0R00-P R 0R00-P P0VN-P R RJ--P 0 P0VJN-P LK_L LK_L LK_L0 LK_XTL_OUT LK_XTL_IN LK_XTL_OUT F R RJ--P R RJ--P PI_TM R-_N/PI- _L ITP_N F F I 00 Realtek V +0V +0V X X-M-P R R 0RJ--P R 0RJ--P RJ--P R R R KRJ--P KRJ--P KRJ--P P0VJN-P X X LK T +V_K0 VRF V VPI VR VPU VPLL U_MHZ/FL PI_TOP# PU_TOP# PI0/R#_ 0 PI/R#_ PI/TM PI PI/_LT PI_F/ITP_N FL/TT_MO RF0/FL/TT_L U K_PWR/P# N# ILPRKLFT-P-U N NPI NRF F_ F_ F_ PU 0 00M 0 0 M 0 M M M R 0KRJ--P R0 0R00-P R KRJ--P R KRJ--P R KRJ--P R KRJ--P N NR NR NR NPU N 0 +V_K0_IO V_IO VPLL_IO VR_IO VR_IO VR_IO VPU_IO F F F MH_LKL, MH_LKL, MH_LKL0, +V_K0 _L +V PUT0 PU0 0 PUT_F PU_F PUT_ITP/RT PU_ITP/R RT/R#_F R/R#_ 0 RT R RT0 R0 RT/R#_H 0 R/R#_ RT R RT R RT/R#_ R/R#_ RT/TT R/T MHZ_NON/RT/ MHZ_/R/ N RT0/OTT_ 0 R0/OT_ R 0KRJ--P R 0KRJ--P L K00T-0Y-N-P LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_XP LK_PU_XP# LK_PI_LN LK_PI_LN# LK_PI_MINI_ LK_PI_MINI_# LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# LK_PI_T LK_PI_T# MH_RFLK MH_RFLK# LK_MH_RFLK LK_MH_RFLK# <ore esign> 0U0VZY-P UVZY-P 0 0 R0 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R0 0R00-P R0 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R 0R00-P R0 0R00-P R 0R00-P R 0R00-P +V_K0_IO LK_PU_LK LK_PU_LK# LK_MH_LK LK_MH_LK# LK_PU_XP LK_PU_XP# LK_PI_LN LK_PI_LN# LK_PI_MINI LK_PI_MINI# LK_MH_PLL LK_MH_PLL# LK_PI_IH LK_PI_IH# LK_PI_T LK_PI_T# RFLK RFLK# RFLK RFLK# _L PIN 0 PIN PIN PIN UVZY-P 0 OTT OT RT/LT_00 RT/LT_00 RT0 R0 M_N M_ Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO lock enerator ILPR ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of UVZY-P R RJ-P R RJ-P R RJ-P R RJ-P UVZY-P UVZY-P 0U0VZY-P

17 +V RN RNKJ--P RN RNKJ--P RN RNKJ--P RN0 RNKJ--P PI_TR# PI_FRM# INT_PIRQ# PI_RQ# PI_PLOK# PI_IR# PI_RR# INT_PIRQ# PI_PRR# PI_RQ0# INT_PIRQ# INT_PIRQH# PI_RQ# PI_RQ# PI_TOP# PI_VL# RN INT_PIRQ# INT_PIRQ# INT_PIRQF# INT_PIRQ# RNKJ--P INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# U F F F0 0 F 0 F F H H 0 H J PIRQ# PIRQ# J PIRQ# PIRQ# OF PI RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IR# PR PIRT# VL# PRR# PLOK# RR# TOP# TR# FRM# PLTRT# PILK PM# Interrupt I/F IHM-P-NF PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F PI_RQ0# PI_NT0# PI_RQ# F PI_RQ# F PI_RQ# F PI_NT# PI_IR# R PI_VL# PI_PRR# PI_PLOK# J PI_RR# PI_TOP# F PI_TR# PI_FRM# PI_PLTRT# R IH_PM# H INT_PIRQ# K INT_PIRQF# F INT_PIRQ# INT_PIRQH# PLK_IH TP TP-P PI_# PI_NT0# R R PI_NT# R KRJ--P KRJ--P KRJ--P U LP +VLW OOT IO trap PI_NT#0 PI_# 0 swap override strap PI_NT# 0 PI OOT IO Location PI LP(efault) low = swap override enable high = default PI_PLTRT# U PLT_RT# Y N LV0W--P R 0R00-P PLT_RT#,,,, <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO IH-M ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

18 IH_RTX +RT R 0MRJ-L-P IH_RTX +RT X X-KHZ-PU 0 R 0KRJ-L-P 0 U0VKX-P R 0KRF-L-P M_INTRUR# IH_INTVRMN P0VJN-P Khz pf 0ppm st: 000 (K) nd: 000 (PON), H_ITLK_O, H_RT#_O, H_YN_O, H_OUT_O +RT LN_OMP place within 00 mil of IHM 00-0R00-P R RJ--P H O H_IN0 TP-P TP H_IN R MRJ--P P0VJN-P R RN RNJ--P-U R 0KRJ-L-P U0VKX-P T_L# T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP P-OPN +V Z_IT_LK Z_YN_R Z_RT#_R Z_TOUT_R T_L# IH_INTVRMN IH_RTX IH_RTX IH_RTRT# RTRT# new signal Pin RTRT# F0 M_INTRUR# LN_OMP R00 RF-L-P 0UVKX-P 0 0UVKX-P 0 0UVKX-P 0UVKX-P T_TXN0_ T_TXP0_ T_TXN_ T_TXP_ RTX RTX RTRT# RTRT# INTRUR# INTVRMN LN00_LP LN_LK LN_RTYN F LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX 0 F H_IT_LK H H_YN H_RT# F H_IN0 H_IN H H_IN H_IN U0 LN_OK#/PIO LN_OMPI LN_OMPO H_OUT H_OK_N#/PIO H_OK_RT#/PIO TL# J T0RXN H T0RXP F T0TXN T0TXP H TRXN J TRXP TTXN F TTXP IHM-P-NF OF RT LP LN / LN PU IH T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# PI TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TRI# TRI K K L K K J J N J J J F L F F H H J F H J 0 F0 H J J H LP_0 LP_ LP_ LP_ PIO H_PRTP# H_FRR#_R LP_[0] H_THRMTRIP_R TRI RF-L-P LP_FRM#, H_0M# H_PWR H_INN# H_INIT# H_INTR H_NMI H_TPLK# LK_PI_T# LK_PI_T Place within 00 mils of IH ball LP_[0], TP-P R TP 0KRJ--P H_MI# +V K0T H_PRTP#,, H_PLP# R0 RJ--P R R0 RF-L-P +V R +0V R0 RJ--P 0KRJ--P R0 RJ--P +0V Placed Within " from IH H_FRR# KRIN# PM_THRMTRIP-#, +VL U0VZY-P +RT integrated Vccus_0,Vccus_,VccL_ INTVRMN W=0mils RT_PWR_L R0 0R00-P W=0mils U HFPT-P W=0mils High=nable Low=isable integrated VccLan_0VccL_0 LN00_LP High=nable Low=isable RT_PWR <ore esign> R KRJ--P TT W=0mils st: 0F000 nd: 0000 nd: 0F00000 Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO IH-M ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of RT -ON-P-U

19 PI_#0 PI_MOO LN PI_RXN PI_RXP PI_TXN PI_TXP WLN PI_RXN PI_RXP PI_TXN PI_TXP PI_LK PI_#0 PI_# PI_MOI PI_MOO R0 R R R PI_WP# PI_RXN PI_RXP U0VKX-P U0VKX-P PI_RXN PI_RXP U0VKX-P U0VKX-P TXN TXP TXN TXP PI_LK_R PI_#0_R PI_# U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O#0 U_O# PI_HOL# X00 (M Flash ROM) R R KRJ--P U # O WP# N HOL# LK IO WXI-P RJ-P RJ-P RJ-P RJ-P RF-L-P PI_MOI_R PI_MOO_R U_RI_PN N N P P L L M M J J K K H H F F F N N N P M N M M N N P P PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN/LN_RXN PRP/LN_RXP PTN/LN_TXN PTP/LN_TXP O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O0#/PIO O#/PIO +V R KRJ--P U0 +VLW +V PI_LK PI_0# PI_#/PIO/LPIO PI_MOI PI_MIO URI URI# IHM-P-NF OF PI-xpress PI U irect Media Interface R PI_LK PI_MOI MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP0N UP0P UPN UPP TP_PI# TP_PU# 0KRJ--P +VLW PI_WK# PM_LKRUN# +V LK_T_O# Norn connect to charger V V U U Y Y W W T T F F W W Y Y W W V V U U U U RN UVZY-P RN0KJ--P MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_IROMP_R +V R KRJ--P TP-P LK_PI_IH# LK_PI_IH U0_N0 U0_P0 U0_N U0_P U0_N U0_P U0_N U0_P U0_N U0_P U0_N U0_P U0_N0 U0_P0 RN RN0KJ--P IH_M_LK IH_M_T R0 KRJ--P TP0 +V U WLN XP_RT# TP_PI# TP_PU# 0RJ--P IH_TP R +V +VLW PM_YN# PIO Reserved for future TP-P TP,, PI_WK# IRQ THRM_I# _I# _WI# _PWR_L ard Reader M R0 0KRJ--P xternal U xternal U luetooth R RF-L-P TP-P TP-P TP-P TP-P TP-P TP-P _PKR MH_IH_YN# TP TP TP TP TP TP TP-P PIO R0 0KRJ--P IH_M_LK IH_M_T LINKLRT# M LK M T IH_RI# XP_RT# TP_PI# TP_PU# PI_WK# IRQ VRMPWR TP-P TP-P TP-P _I# PIO IRQ M_LRT# _PWR_L TP LK_N# PIO PIO PIO0 PIO PIO PIO PIO TP TP TP R0 IH_TP +VLW RN RNKJ--P +V KRJ--P RN OF U0 MLK MT LINKLRT#/PIO0/LPIO MLINK0 MLINK F R M L 0 M J 0 H K F J L F H M J H0 J0 J RI# RN0KJ--P U_TT#/LPP# Y_RT# PMYN#/PIO0 MLRT#/PIO TP_PI# TP_PU# LKRUN# WK# RIRQ THRM# VRMPWR T TH/PIO TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO NRY_TT/PIO TH0/PIO PIO PIO0 LOK/PIO PIO PIO TLKRQ#/PIO LO/PIO TOUT0/PIO TOUT/PIO PIO PIO/LPIO PKR MH_YN# TP PWM0 PWM PWM IHM-P-NF Q +V N00--P +V R Pair 0 U U LUTOOTH R RR VRMPWR xternal U 0 M T PIO locks Y PIO Power MT MI PIO ontroller Link 0KRJ--P evice FR xternal U FR FR WLN FR MR FR T0P/PIO TP/PIO TP/PIO TP/PIO LK LK ULK LP_# LP_# LP_# _TT#/PIO PWROK PRLPVR/PIO TLOW# PWRTN# LN_RT# RMRT# K_PWR LPWROK LP_M# L_LK0 L_LK L_T0 L_T L_VRF0 L_VRF L_RT0# L_RT# PIO/MM_L PIO0/U_PWR_K PIO/_PRNT PIO/WOL_N H F 0 H F P 0 0 M R 0 R R F F F 0 IH_ULK T0P TP TP TP PM_LP_# PIO PM_TLOW#_R LN_RT# M_PWROK PM_LP_M# L_LK0 L_T0 L_VRF0_IH L_VRF_IH L_RT#0 TP TP TP T0P PIO TP TP-P PIO0/U_PWR_K TP TP-P U_O# U_O# IH_RI# XP_RT# +VLW <ore esign> U_O# U_O# U_O# U_O# +VLW LK_IH LK_IH IH_ULK PWRTN#_ R PM_LP_#,,,,,,0 PM_LP_#,0,, TP0 TP-P R TP-P 0KRJ--P TPPM_PWROK RMRT#_ R M_PWROK 0R00-P R 00KRJ--P 0R00-P K_PWR M_PWROK R 0RJ--P TP-P TP U0VKX-P +VLW R RP 0 RN0KJ-L-P R0 KRF-P +VLW PM_TLOW#_R M_LRT# U_O#0 U_O# +VLW U_O#0 U_O# U_O# U_O# +V PM_PWROK, PM_PRLPVR, LL_PWR,,, +V Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO IH-M ( of ) ize ocument Number Rev HU Thursday, July 0, 00 ate: heet of RP 0 RN0KJ-L-P RN RN0KJ--P KRF-P U0VKX-P R RF--P R0 RF--P

20 +V m +V VRF_0 Layout Note: Place near IH m VRF_ R 0R00-P m +V +VLW +V +V_PI +V +VLW +V _LN_ +V +V +V m *Within a given well, VRF needs to be up before the corresponding V rail U0VKX-P U0VKX-P m in 0;0m in // U0VKX-P R0 0R00-P U0VKX-P HH-0PT 0 HH-0PT U0VKX-P UVMX-P R 0RJ--P 0m U0VKX-P m UVMX--P R 0RJ--P +RT T0 R R T0UVM-LP u in _T_U UPLL=0m 0 U0VKX-P 0R00-P U0VKX-P +V 0R00-P 0 +V +V_PLL L IN-UH-0-P R 0R00-P U0VKX-P L IN-UH-0-P U0VKX-P U0VKX-P 0U0VZY-P 0UVMX-P m UVMX--P VRF_0 VRF_ T+U= U0VKX-P U0VKX-P U0VKX-P U0VKX-P U0VZY-P 0U0VZY-P 0UVMX-P R0 0R00-P U0VKX-P V_U_0 LN0 U0VKX-P _LN_PLL V_LN_0 U0F RT VRF VRF_U F H H J J K K L L L M M N N N P P R R R R T T T T U U V V U W W K Y Y J TPLL F H J F 0 H0 J0 0 J UPLL 0 LN_0 LN_0 LN_ LN_ LNPLL LN_ LN_ LN_ LN_ LN_ IHM-P-NF OF P RX TX U OR LN POWR OR PU PU P_OR PI _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 _0 MIPLL MI MI V_PU_IO V_PU_IO H UH U_0 U_0 U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ U_ L_0 L_ L_ L_ F L L L L L L M M P P T T U U V V V V V V R W Y J 0 F0 0 F J J K J J T T T T T T U U V V W W Y Y T V_POR_IH_0 /_PI_P_OR_0 U_0[] U_[] _L_ m 0UVKX-P MI Layout Note: Place near IHM V_MIPLL_IH_0 U0VKX-P 0UVKX-P 0 UVZY-P U0VZY-P U0VKX-P U0VKX-P +V R 0R00-P U0VKX-P 0 U0VKX-P +V 0 R0 U0VKX-P 0R00-P U0VKX-P V_MIPLL_IH_0 0UVKX-P UVMX-P 0 m R +V 0R00-P 0 U0VKX-P 0UVKX-P U0VKX-P m +VLW 0m m _=m m m 0UVKX-P R 0R00-P 0 U0VKX-P U0VKX-P R 0R00-P 0 0UVMX-P F U_0[] U_0[] TP U0VKX-P TP U_[] +V F U_[] U0VKX-P R +VLW _U_ 0R00-P 0 U0VKX-P F U0VKX-P U0VKX-P U0VKX-P 0U0VZY-P U0VKX-P R0 +V 0R00-P IN-UH-0-P L R0 +0V 0R00-P +0V +V _V_PU_IO R +V _H 0R00-P U0VKX-P U0VKX-P +V 0 U0VKX-P Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO IH (/) R +0V 0R00-P ize ocument Number Rev HU ate: Wednesday, July 0, 00 heet 0 of UVMX-P

21 OF U0 0 0 F F F F H F F F F F 0 H H H H H H H H H H J J J J 0 F F F H H H H IHM-P-NF H J J J K K L L L L L L L M M M M M M M M M N N N N N N N N N N P P P P P P P P P P P P R R R R R R R R R T T T T T T T U U U U U U U U U V V V V V V V V W W W Y Y Y Y Y H F H H J J J J IH_N IH_N TP0 TP TP-P TP-P NTF PIN IH_N TP TP-P IH_N TP TP-P,,, IH_MT IH_M_LK RN RNKJ--P +V IH_M_LK U MN0LW--P MU +V IH_M_T IH_M_T IH_MLK,,, Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO IH-M ( of ) ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

22 U PORT +V +V +V_U 00 mil U0_N0 R 0R00-P U0- T U0_P0 R0 0R00-P U0+ T_TXP0 T00U0VM-P T_TXN0 0UVKX-P UVZY-P T_RXN0 0 T_RXN0_ T_RXP0 T_RXP0_ KT-U--P-U 0UVKX-P 00 mil 00 mil U0_P0 U0_N0 U I/O N I/O IP0Z-P +V_U I/O VP I/O 0 UVZY-P KP0VKX-P +V U0VKX-P +V_U +V_U U0_N U0_P U0_N U0_P N +V NUMLK_L_PWM N N TP TP--P TP TP--P TP TP--P TP00 TP--P TP TP--P TP0 TP--P TP0 TP--P TP0 TP--P TP0 TP--P TP0 TP--P TP TP--P NUMLK_L# UVZY-P +V_U U0_N U0_P U0_N U0_P +V NUMLK_L# R 0RJ--P st: 0N nd: 0N nd: 0Z UVZY-P V_U NUMLK_L_PWM 0 U -ON0--P-U T H onnector +V 0U0VZY-P st: 00 nd: 00 LUTOOTH +V_T U0_P U0_N U0_N U0_P +V st: 0F000 nd: 000 nd: 0F000 O onnector T_R_T# T_L T_T# U+ U- +V_T N U+ U- T_L T_R_T# TP TP--P TP TP--P +VLW MX 0m T_TXP T_TXN T_RXP T_RXN +V_T UVZY-P 0UVKX-P T_RXP_ T_RXN_ 0UVKX-P st: 00 nd: 00 nd: 00 O_P O_M TP TP-P U0_N R 0R00-P U- T T00UVM-P U 0 UVZY-P UVZY-P H NP 0 0 NP KT-TP-0-P U I/O N I/O IP0Z-P I/O VP I/O +V U0VKX-P T JT-ON--P 000 UVZY-P UVZY-P R 0RJ--P TP TP--P TP TP--P TP TP--P TP TP--P Q O0-P UVZY-P T0 0U0VZY-P O P +V P +V NP NP NP NP P P M P N N N N P N P N N KT-TP+P--P-U R0 0KRJ--P U0VKX-P R 00KRJ--P 0 U0VKX-P U0VZY-P <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO U0_P R0 0R00-P U+ T_N# K T_N#_ PT-P R T_N#_ 0KRJ--P UVZY-P H/ROM/U/T ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

23 V R 0 mils +V_LN V +VLW 0RJ--P R +V_LN 0R00-P 0U0VZY-P UVZY-P UVZY-P UVZY-P 0 UVZY-P R MRJ--P LN_PY LN_PY R KP0VKX-P 00KRJ--P O-P Q 0 mils V V 0 mils LN_PWR_ON,,,,,,0 PM_LP_# Q N00--P LN_PY UVZY-P UVZY-P PROM L OPTION U '0' (FIN IN P) => L : LINK (reen) => L : T (Yellow) (OTH 0/00 N I HIP) V LK_PI_LN V V RFLK_P LK_PI_LN 0 LK_PI_LN# TRL V RFLK_M LK_PI_LN# V PI_TXP PI_TXP TRL LV_ HIP 0 PI_TXN PI_TXN V LV_ HIN PI_HOP PI_RXP VTX HV HOP U0VKX-P U0VKX-P PI_HON VTX HON U0VKX-P PI_RXN V YLLOW_L# P0VJN--P U0VKX-P LN_X U0VKX-P LN_M# LN_M# V V V R LN_ KRJ--P RN_L# YLLOW_L# LN_X LN_X LN_L_M# R 0R00-P V V V U LNWK# IOLT# LKRQ 0 PRT# LNPIN/K LPIN/I MIP0 LPIN/O MIN0 MIP MIN KXTL KXTL NTX N PO IRF RTL0T-R-P PI_WK# IOLT# PLT_RT# MIP0 MIN0 MIP MIN PI_WK#,, PLT_RT#,,,, MIP0 MIN0 MIP MIN IOLT# +V R KRJ--P R KRF-P R KRJ--P M_IOLT# 0 Q N00--P UVZY-P UVZY-P UVZY-P R0 KR-P R KRF-P X XTL-MHZ-P LN_X <ore esign> P0VJN--P Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO RTL0T ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of

24 +V FN_ *Layout* mil 0U0VZY-P FN_F +V FN_ KP0VKX-P *Layout* mil +V etting T as egree V_R =(((egree-)*00)+0)* *Layout* 0 mil THRM_I# V_R +V M_ M_ V 0 _ULK _LRT# _RT# R 00KRJ--P _XP _XP _XN _XN P-LO _RT# 00P0VKX-P FN_F FN_ N st: 0F00 nd: 0000 nd: 0F00000 TP TP--P N for ystem Q MMT0--P N for IMM Q MMT0--P +V XP:0 egree XP:H/W etting XP: egree +V Place near chip as close as possible H_THRM N for PU H_THRM _RT# _LRT# +V RN RNKJ--P 0 UVZY-P MM-F-P R 0KRJ--P FN -ON--P-U R0 00RF-L-P-U UVZY-P U0VZY-P R KRF-P R 00KRF-L-P UVZY-P R0 0KRJ--P 00 U FN RT# 0 F LK XP THRM# XP THRM_T XP N LRT# N 0 N L N N# N FU-P 00P0VKX-P TP TP--P TP TP--P Q R 0KRJ--P 00P0VKX-P N00--P +VLW M_ U K_ K_L M_ U0 MN0LW--P,,,,,,0 PM_LP_# IH_ULK N Y _ULK R 0R00-P HT0KR-P R 0R00-P <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO Thermal/Fan ontrollor ize ocument Number Rev ustom HU ate: Thursday, July 0, 00 heet of

25 +V LK_ MO_L RT# X_L X_# X_L _T/X_R# _T/X_W# X_R/# _T/X_WP# _VIN R 0R00-P R00 0R00-P R 0R00-P +V_ +V_ U0VZY-P UVZY-P R +V R0 0 U0VKX-P R VR U0_N U0_P _VIN 0R00-P +V_R U R R R UVZY-P 0R00-P V_PLL V_PLL R RRF R0 KRF-P RRF V M P V_OUT V_IN R_V XTLO XTLI _PLL MO_L RT# X_L/F_ X_#/F_ X_L/F_ 0 _T/X_R#/F T/X_W#/F_ X_R/F T/X_WP#/F M _T/X_0/F LK/X_/M_LK/F_ V N _T/X_/M_/F_ 0 F_0# M_IN#/F_IOR# _T/X_/M_/F_IOWR# _M _T/X_0 _LK/X_/M_LK _T/X_/M_ M_IN# _T/X_/M_ R +V_ UVZY-P RT# RT_# R 0R00-P U0VKX-P +V_ R R0 00KRJ--P R R KRF--P R VR U0VKX-P +V_ R UVZY-P 0 VR V_OUT N F_# PIO0 F_0 F_ F_ F_/M_# F_/X_# F_0/M_WPM#/_WP _T0/X_/M_0/F_RT# _T/X_/M_/F_IOR X_/M_/F_ F_0/_# F_MK# F_/X_ F_MRQ _T0/X_/M_0 _T/X_/M R X_/M_ +V_ High is use MHz, N is use rystal R 0R00-P RYTL_L VU_L# X_# 0 _WP _# X_ RT-R-P 000 R 0RJ--P _T/X_/M R X_ R 0R00-P _T MO_L P0VJN-P R R0 0RJ--P +V R R 0RJ--P VU_L_L L K VU_L L-Y--P R VU_L# R0 0RJ--P Q R R R PTU--P +V R0 U uto e-link (*) M Formatter (*) escription 0 N Yes No Recommended N Install Yes Yes N N No No ompatible with RT * U uto e-link mode: If user remove memory card from socket, RT will terminate U bus connection and enter power saving state * M Formatter: MPRO, MPRO UO, MPRO-H or MPRO-H UO card will be formatted as factory default setting if user formatted these card types under "Vista" O IN R-RR (/ IO/MM/MM0/M/M PRO/X) +V_R R R Place close to controler I R0 0R00-P _LK/X_/M_LK _LK/X_/M_LK_R U0VZY-P +V_R UVZY-P R _T/X_/M R _M _LK/X_/M_LK _LK/X_/M_LK_L R0 0R00-P _T0/X_/M_0 _T _T/X_R# _T/X_W# _# _WP _ M_ M M _LK _T0 _T _T _T TT _WP_PROTT L R/# R# # L W# WP# 0 _O 0 _O X_# X_L X_R/# _T/X_R# X_# X_L _T/X_W# _T/X_WP# _T/X_0 _LK/X_/M_LK _T/X_/M T/X_/M R X_ X_/M T0/X_/M_0 _T/X_/M # TP-P TP _WP X_/M T0/X_/M_0 0 M_IN# _LK/X_/M_LK_R _LK/X_/M_LK_R_R R 0R00-P _T/X_/M T/X_/M_ R IO NP NP NP NP NP NP _WP _WP M_ M_IO M_IN M_LK M_RRV#M_ M_RRV#M I/O NP NP NP NP NP NP _P _P _P _P M _ N N 0 N 0 N 0 N N N N _T0/X_/M_0 _T <ore esign> Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO RUP-KT-P 0I0000 U ardreader ontroller-rt ize ocument Number Rev HU Thursday, July 0, 00 ate: heet of

26 HMI RN HMI TX_ HMI TX HMI onnector HMI TX#_ HMI TX# +V HMI TX0_ HMI TX0 Mini ard onnector(0a/b/g) +V HMI TX0#_ HMI TX0# R RN0J--P R KRJ--P HMI HMI +V RN0 +V_MINI P P0 (d) HMI TX_ HMI TX +V HMI TX#_ HMI TX# 0 0 HMI HMI L HMI TX_ HMI TX HMI TX#_ HMI TX# MINI 0 RN0J--P NP PY00T-0Y-N-P 0,, PI_WK# PI_WK# U 0 TP-P TP WL_PRI TP-P TP T_PRI TP-P TP +VLW HMI_T- HMI TX#_ IN_- OUT_- LK_PI_MINI# 0 HMI_T+ HMI TX_ IN_+ OUT_+ LK_PI_MINI R HMI_T- HMI TX#_ IN_- OUT_- 0 0RJ--P HMI_T+ HMI TX_ IN_+ OUT_+ _RX HMI_T0- HMI TX0# TX IN_- OUT_- HMI_T0+ HMI TX0_ OUT_+ RN IN_+ 0 WIFI_RF_N +V PI_RXN PLT_RT# PLT_RT#,,,, HMI_LK- HMI TX#_ PI_RXP +V_P IN_- OUT_- HMI_LK+ HMI TX_ IN_+ OUT_+ R RNKJ-P 0R00-P PI_TXN 0 IH_MLK IH_MLK,,, +V R KRJ--P HMI_P0 MH_HMI_T PI_TXP IH_MT IH_MT,,, R HMI_P P0 KRJ--P P L MH_HMI_LK HP U0_N HMI_HP_L HMI_HP +V_MINI U0_P R HMI HMI RF--P HMI_RXT R KRJ--P R HMI_RT# RXT 0 KRJ--P 0 HP R KRJ--P HMI_O# RT_N# HP_INK 0 TP HMI_ WLN_L# HMI_ O# _INK TP-P HMI_L TP _N L_INK TP-P +V HMI +VL 0 RN R KRJ--P +V_HMI NP P0-P RNKJ-P KT-MINIP--P-U HMI TX_ FILTR--P U0VKX-P 0UVKX-P HMI TX HMI 0 HMI_ HMI_ N N N N N N N N N N N KRJ--P N# N# P000 (R=0L) (R=0L) HMI TX_ FILTR--P HMI HMI TX st: 00 nd: 00 HMI TX#_ HMI TX# HMI TX#_ HMI TX# HMI TX_ HMI TX HMI TX0_ HMI TX0 HMI TX#_ L HMI TX# HMI TX0#_ L0 HMI TX0# +VL +V_MINI +V +VLW +V P_RXP R 0KRJ-L-P HMI_HP HMI TX HMI HMI 0 HMI R 0KRJ-L-P HMI TX# R KRJ-P HMI HMI TX HMI TX# HMI TX0 HMI TX0# HMI TX 0 HMI TX# TP-P TP HMI_ TP-P TP HMI_N HMI HMI_L RUNTRL_PWR RUN_PWR_TLR HMI_ R KRJ-L-P +V_HMI Q HP <ore esign> N00K--P HMI 0 +V_HMI +V UVZY-P Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO KT-HMIP--P R 0RJ--P Q N00--P st: 00 nd: 00 UVZY-P 0U0VZY-P UVZY-P 0U0VZY-P UVZY-P MINI R/HMI ONN ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of UVZY-P

27 0/00M Lan Transformer LN onnector XF XRF_R MIN0 MIN0 RJ- XFR_MT XFR_MT_ MIP0 MIP0 RJ- 0U00VKX-P RJ-P--P XRF_R MIN MIN 0 RJ- R 0RJ--P XFR_RX XFR_RX_ MIP MIP RJ- RN_L# 0U00VKX-P +V_LN 0 RJ- RJ- XFORM-P--P-U RJ- RJ- 00 UVZY-P UVZY-P st: 0(N) nd: H00(H-0-) XFR_MT_ XFR_RX_ RJ- RJ- RN RNJ--P LN_TRMINL 00PKVKX-P +V_LN YLLOW_L# reen : Link up linking : TX/RX activity route on bottom as differential pairs Tx+/Tx- are pairs Rx+/Rx- are pairs No vias, No 0 degree bends pairs must be equal lengths mil trace width,mil separation mil between pairs and any other trace Must not cross ground moat,except RJ- moat R 0RJ--P RJ- RJ- st: 0 nd: 0 PIN : RN PIN : ORN PIN : YLLOW Remark: dd trace width to 0mils for RJ pin, and pin, RJ olden Finger for ebug oard +V_LP PLT_RT#_ P-OPN-PWR P-OPN-PWR PLT_RT#_ LP_FRM#_ LP_FRM#_ LP_N LP_N PLK_FWH_ 0 PLK_FWH_ LP_ LP LP_FRM# LP_FRM#_, LP_FRM# () P-OPN-PWR P-OPN-PWR () LP LP LP 0 LP 00 0 LP LP LP_ LP PLT_RT# PLT_RT#_ LP_0_ LP_0_,,,, PLT_RT# () XT_FWH#_ XT_FWH#_ P-OPN-PWR P-OPN-PWR () +V_LP +V_LP 0 0 LP_ LP PLK_FWH PLK_FWH PLK_FWH_ FOX-F0 OTTOM VIW () P-OPN-PWR P-OPN-PWR TOP VIW () oot evice must have I[:0] = 0000 Has internal pull-down resistors ll may be left floated FPT lec P- +VL R0 U ZZF00XXX Please put near board edge XT_FWH#_R R +V_LP XT_FWH# LP_[0], +V LP_0 00KRJ--P KRJ--P <ore esign> 0 P-OPN-PWR 0 P-OPN-PWR +V_LP LP_0_ LP_N +V XT_FWH# 0 0 P-OPN-PWR +V_LP XT_FWH#_ Wistron orporation F,, ec, Hsin Tai Wu Rd, Hsichih, Taipei Hsien, Taiwan, RO LN ONN/ebug ize ocument Number Rev HU ate: Thursday, July 0, 00 heet of LO TO TRNFORMR