Page. 49 VRAM(BYPASS) 50 SDVO TO LVDS 51 LVDS-Inverter

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1 Page of chematics Page Index Page lock iagram(ystem) LOK N PU HOT / PU THRML / PU POWR / aglelake HOT/PI- / aglelake V/MI / aglelake RII H / aglelake RII H / aglelake POWR / aglelake POWR / aglelake N / RII(H IMM0) / RII(H IMM) / RII Termination IH0 (PIe/U/PI) / IH0 (HOT/T) / IH0 (PM/LN/H) / IH0 (Power) / IH0 (round) / Flash ROM& ebug Power equence / Power equence / INTL LN oazman PIe WLN TV-TUNR PI U (ridge) / PI U(M//iLink) / T H /T O U Port IR&T MR FLI Thermal & L FN L ONN(Pwitch) N9M (PI-) /9 chematics Page Index ( / Revision / hange ate) Rev. ate.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0.0 00/0/0 Page of chematics Page Rev. ate 0 N9M(PI TX) /9.0 00/0/0 N9M (PI RX&TRP) /9.0 00/0/0 N9M (R) /9.0 00/0/0 N9M (RT)/9.0 00/0/0 N9M (LV) /9.0 00/0/0 N9M (XTL/PIO) /9.0 00/0/0 N9M(RYTL&I)/9.0 00/0/0 N9M (ROUN) 9/9.0 00/0/0 VRM(R).0 00/0/0 9 VRM(YP).0 00/0/0 0 VO TO LV.0 00/0/0 LV-Inverter.0 00/0/0 RT.0 00/0/0 UIO lock iagram(ll).0 00/0/0 UIO(O & POWR).0 00/0/0 UIO(HP).0 00/0/0 UIO(PK MP).0 00/0/0 UIO( XT MI & LIN IN).0 00/0/0 UIO (MUT).0 00/0/0 9 UIO(Q).0 00/0/0 0 Power lock iagram.0 00/0/0 IN.0 00/0/0 YPWR(V/V).0 00/0/0 RPWR(_V/0_9V).0 00/0/0 YPWR(_V/_V).0 00/0/0 VPWR.0 00/0/0 VHOR ()---IL.0 00/0/0 VHOR () ---IL0.0 00/0/0 H PWR(V).0 00/0/0 9 YPWR(_V).0 00/0/ 0 OVP Protect.0 00/0/0 Others PWR Plane.0 00/0/0 orwin spring(_/_v_l).0 00/0/0 Hole & O.0 00/0/0 Revision History().0 00/0/0 Revision History().0 00/0/0 Revision History().0 00/0/0 Revision History().0 00/0/0 Revision History().0 00/0/0 P. Leader heck by esign by Project ode & chematics ubject: M0 Main oard P P/N P-00J00-00 FOXONN Index Page HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

2 For debug Int. peaker.0 Watt x Page PK_OUT_R/- PK_OUT_L/-.W MP Y9 Page amera &igital Mic in Module Head Phone Jack Page 0" WX 0 x 00 xt. Mic In Jack Page Wire able RT aughter oard Q R0 Page9 Q R0 Page9 /PIF OUT Page Line In Page RT ONN Page LV ONN Page Video RM0 Page Video RM Page Q R0 Page9 Q R0 Page9 Pre-MP Int. igital MI. ONN (combine into one ONN with amera ). Page /PIF_OUT N9M- (-) P9- MII_L/R MI PK_L HP_OUT_R/L LIN_IN_R/L PK_R VO LV Transmitter H0-TF L9 Page Page 0 udio odec M0 lock iagram VO PIx H_Link PI U Page PU Fan PU Fan hassis Fan (RRV) HOT Processor Wolfdale/onroe HOT PI T North ridge aglelake-p/ -link outh ridge IH0 T Q T Page,, F 00/0/MHz Page,,9,0,,, HOT PI PWM0 TH0 PWM TH PWM TH MI Page,, 9,0, /00MHz /00MHz PIx Tx U.0x PI LI K-0 lock enerator ITV- Page hannel RII O-IMM0 hannel RII O-IMM PI PI PI (-LI) T0 T U.0x Page Page Mini-ard WLN 0.bgn Page MINI TUNR LOT (JP igital TV) -V (-LN) Page T H ONN Page 0 T O ONN Page 0 Page able able Netswap N0P Page U Felica ard ONN. Page. T H Page 0 O lu-ray/-ombo Page 0 FF able RJ Page Felica ard M Pro/UO ard Page 9 i.link Page 9 RIOH R ardreader i.link Page PI U T M-IZL-TR Local N Remote for V Remote for Inverter Remote for O Page T T M-IZL-TR local for R Remote for Inverter(back up) Remote for O(back up) Page Flash IO M (M) Page U 9 U U0- U lue Tooth ONN. Page amera ONN ombine into one with digital mic in U.0 Portx Page IR Page Page / Wire able lue Tooth Module amera &igital Mic Module default case reserved case Only for debug FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision lock iagram(ystem) ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

3 VT:0/0:hange from V_L to VLW V_LK V_K_V_PI V_K_V_ V_LK_IO V_LK T_FL Q R R9 V_K_V_R VT:0/:hange Q 00 0U_.V_M 0U_.V_M 0.U_V_Y 0.U_V_Y 0.U_V_Y V_LK T_FL0 9,, LP_M R9 00_XR 00_XR 00_YV 00_YV 00_YV 00.U_.V_K 0.U_V_Y _0K_J 00_XR K_J 00_YV Q Q 9 00 _I0 H90PT _.U_.V_K T_FL, H_FL R 00_XR R0 R0 V_K_V_PU.K_J 00 _00 00 H90PT For corwin spring 0.U_V_Y 00_YV R, H_FL0 R V_K_V_RF.K_J 00 T_FL0 00 PLK_ N_0P_0V_J 00_NPO 0.U_V_Y K_P_M_IH N_0P_0V_J 00_NPO 00_YV V_LK K_M_U_IH 0P_0V_J 00_NPO R9 K_FL U K_J00 V_K_V_PI K_RF_R V_LK K_M_IH P_0V_J 00_NPO V_K_V_ V_PI RF/F_/Testel 9 R R R R V_ K_PIF_R R _J 00 N_0K_J N_0K_J 0K_J N_0K_J K_P_M_IH K_M_VO V_K_V_R V_PLL PIF/ITP_N 9 K_PI_R R _J 00 R PLK_ V_K_V_PU V_R PI/R_N K_PI_R _P_0V_J 00_NPO V_K_V_RF V_PU PI/FP PI_TRP R _J 00 _J K_PIF_R V_RF PI/TM PLK_JI VT:0/: For corwin spring R V_LK R K_PI_R LK_NL R K_J00 PI/R#_ 00 K_PI0_R K_PI_R LK_NL 0K_J 00 R K_J TTMO_F_K0 KPWR/P# PI0/R#_ K_FL0 PI_TRP, H_FL R VT:0/0:dd N_ M R:H(W)/H(R) 00 F_/TestMode K_J00 K_U_R Q R 00 VT:0/:dd R R U/F_ 0 R,R to 00,,9 M_THRM_T_Q R0 R 00 K0_VOUT K0_VOUT_R pull up pin &,,9 M_THRM_LK_Q R R9 R R9 L IO_VOUT _J 00 Pin 0K_J R KM_XTLOUT_R 9 R V_LK 0K_J 0K_J 0K_J 00 P_0V_J 00 KM_XTLIN_R XTL_OUT R/R#_ 0 R#_H_TUNR 0K_J 00 00P_0V_J PMT _NPO XTL_IN RT/R#_H 00 TV_ 00_PR 00_NPO V_LK_IO R VT:0/:hange the K_P_R0_R_N RP N_0M_J V_IO R0 Y K_P_R0_R_P LK_PI_TUNR# position of R 0 00 V_PLL_IO RT0 LK_PI_TUNR TRP Pin.M_0P_0PPM V_R_IO_ R9 TX_900 V_R_IO_ V_LK_IO V_R_IO_ RT9 0 9 P_0V_J V_PU_IO K_P_R_R_N RP 00_PR NV_ 00_PR K_P_00M_IH_N 00_NPO 00_PR RP9 K_P_R_R_P R/R#_ K_P_R_R_P K_P_R_R_N RP LK_PI_MINI K_P_00M_IH_P LK_PI_P# 9 K_P_R_R_N RT/PU_ITPT RT/R#_F K_P_R_R_P LK_PI_MINI# LK_PI_P 9 RP R/PU_ITP K_P_R_R_N RP 00_PR K_P_00M_MH_N MH_LK_N 00_PR K_H_MH_R_N R 0 0 K_P_R_R_P K_P_00M_MH_P 0/0: orrect MH_LK_P K_H_MH_R_P PU RT N_P_0V_ N_P_0V_ PUT _TP_PU#_R R K_J _TP_PU#_Q V_LK VT net error 00_NPO 00_NPO H_PU_LK# 00_PR K_H_PU_R_N PU_top#/R issue. H_PU_LK K_H_PU_R_P PU0 _TP_PI#_R R0 K_J _TP_PI#_Q RP PUT0 PI_top#/RT VT:0/:dd V_LK R R R and N for RF request. 0K_J V_PU RT 0K_J R0 NV J K_P_R_R_N RP0 _ 00_PR K_RFLK_N 00 R R R/R#_ K_P_R_R_P V_IO RT/R#_ K_RFLK_P K_J K_J V_R_ 9 K_P_R_R_N RP 00_PR R#_H_TUNR V_PLL T/R R T_LKN _F TUNR_LKRQ# J K_P_R_R_P K_PI0_R R9 _F T_LKP T_LKRQ# K_RF_R V_R_ TT/RT R 00 K_M_IH 9 V_R_ K_U_R R0 _J 00 R/ K_M_U_IH V_RF RT/ _ 00_PR V_ K_9M_OT_R_N RP K_9M_RF_N R R V_PI R0/OT9 K_9M_OT_R_P RT0/OT9T K_9M_RF_P VT:0/:dd the MINI_R_T# K_J K_J ITV- VRUN VRUN K_RF_R VRUN R J 00 VLW 0m R 00 N_ 9.U_.V_K 0.U_V_Y 00_XR 00_YV R N_00 K_M_VO 0 R 00 R 00. lock Request Table lock Request lock Request Function PIN PIN PI0/R#_ RT/R#_H TLKRQ# TUNR_LKRQ# 0.U_V_Y 00_YV.U_.V_K 00_XR. lock Request Table F F F PU R[:0] PI U OT RF lock Output R R0 0.U_V_Y 00_YV YT IT 0.U_V_Y 00_YV YT IT R#_ mode R#_H mode ontrol R0 0.U_V_Y 00_YV 9 0.U_V_Y 00_YV R VT:0/:dd this circuit for VRUN leakage in,, stage 9 _TP_PU#, H_FL, H_FL0 Q NK R 0K_J 00 R K_J 00 R N_ 00 R N_ 00 9 _TP_PI# _TP_PU#_Q FOXONN LOK N H90PT Q K_FL K_FL0 _TP_PI#_Q HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev IO- Mother oard MP. N00W--F N00W--F R R N_ 00 N_ 00 PVT:0/:ack up R and R. Q R 0K_J 00 Q H90PT ate: Tuesday, July, 00 heet of 0

4 H_#[..] H_RQ#[..0] H_T0# H_#[..] H_T# H_TLRF0 H_TLRF U H_# L H_# 0# # P H_# 0# NR# M H_# 0# INIT# P L H_# 0# R# M H_# 0# PRI# R H_#9 0# Y# T H_#0 09# RY# U H_# 0# 0M# K T H_# # LOK# U H_# # TRY# U H_# # HIT# V H_# # HITM# V H_# # FRR#/P# R W H_RQ#0 # R0# F K H_RQ# RQ0# INN# N J H_RQ# RQ# LINT L M H_RQ# RQ# LINT0 K K H_RQ# RQ# MI# P J RQ# FR# R T0# IRR# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# # W # TPLK# M Y 9# PWROO N Y 0# RT# # # R0# # R# F # R# # # F # F # 9# 0# OMP T # OMP H # OMP0 H # OMP R J # OMP J # T# R H TLRF0 TLRF 0 H TLRF TLRF F PU OKT_P FOX_P0-0-0 H_R# H_IRR# H_R#0 H_R# H_R# H_OMP H_OMP H_OMP0 H_OMP H_OMP TP_TLRF TP_TLRF VT:0/:hange R from N to stuff H_# H_NR# H_INIT# 00 H_PRI# R H_Y# H_RY# H_0M# H_LOK# H_TRY# H_HIT# H_ITM# H_FRR# H_R0# H_INN# H_NMI H_INTR H_MI# H_FR# H_TPLK# H_PUPWR H_PU_RT# R 9.9_F 00 R 9.9_F 00 R 9.9_F 00 R 9.9_F 00 R.9_F 00 TP tpct TP tpct /0:dd test piont for H_TLRF and H_TLRF H_R#[..0] _Y_RT# 9, VTT_OUT_RIHT R _F 00 VTT_OUT_LFT VTT_OUT_LFT H_# H_PU_RT# H_PUPWR H_TPLK# Layout: onnect test point with no stub R H_PU_RT# _F 00 H_PUPWR H_R0# TP TP9 tpct tpct H_#[..0] H_#[..0] Layout note:place near the proccessor /:hange VTT_OUT_RIHT to VTT_OUT_LFT R N_0 00 R09 _F 00 TP tpct TP9 tpct H_I0# H_TN0# H_TP0# H_I# H_TN# H_TP# _OUT H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# PU INL TRMINTION U 00# 0# 0# 0# 0# 0# 0# 0# 0 0# 09# 0 0# # # # # # I0# TN0# 9 TP0# 9 # F # F9 # 9 9# 0# 0 # 0 # F # F # # # # F # 9# F 0# # I# TN# TP# # # # # # # F # F 9# 0# 9 # F0 # # F # # # # I# 9 TN# 0 TP# 9 F T # 0 9# 0# # # # # # # # # 9# 0# 9 # 9 # # I# 0 TN# TP# PU OKT_P FOX_P0-0-0 H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_I# H_TN# H_TP# PVT:0/:hange this portion from N to stuff for TLRF adjust. H_#[..0] H_I# H_TN# H_TP# H_#[..0] TLRF Voltage: 0.*VTT V_F_VTT VTT_OUT_LFT R0._F 00 R9 N_._F 00 PVT:0/:hange Rand R0 from._f to 9.9_F for TLRF adjust. R TLRF0_IVIR 00 Max:00u H_TLRF0 /:hange VTT_OUT_RIHT to VTT_OUT_LFT V_F_VTT VTT_OUT_LFT R._F 00 R0 N_._F 00 R TLRF_IVIR 00 /:hange R0 Max:00u H_TLRF 9 PU_TLRF_TRL VLW R N_0K_J 00 Q R PU_TL N_K_J 00 R0 N_K_J 00 PU_TL N_MMT90. PU_TL R9 N_ 00 Q N_HM0PT R N_.K_F 00 TLRF_IVIR R N_ 00 R 00_F 00 U_0V_K 00_XR N_0P_0V_K 00_XR R 00_F 00 PVT:0/:dd the _VRUN and N R9 R0 follow R. 9 U_0V_K 00_XR /0:elete H_TLRF and H_TLRF circuit TLRF Layout note:.voltage divider should be within. inches of the processor s TLRF pin;.0p ap should be placed as close to the processor TLRF pin as possible;.i should be within. inches of the;.trace width is mils minimum at breakout and as should be as wide as possible between the breakout and the resistor divider network 0 N_0P_0V_K 00_XR PVT:0/0:N R. PU_TLRF_TRL VLW Note:PIO0 don't pull-h, internal pull- R N_0K_J 00 Q R PU_TL N_K_J 00 _OUT R N_K_J 00 PU_TL N_MMT90. PU_TL R TLRF_IVIR_R N_ 00 N_HM0PT TLRF FUNTION TL PVT:0/0:dd TLRF voltage control circuit PVT:0/0:N TLRF voltage control circuit PU_TLRF_TRL PU_TLRF_TRL Ratio et Q R9 N F X VTT 0. X VTT 0. X VTT 0. X VTT FOXONN PU HOT / HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

5 U tpct TP0 TP_KTO# H_PI H_PI 9 H_THRMTRIP# H_PROHOT# tpct TP TP_PU_THRM tpct TP TP_PU_THRM /0:N THRM THRM use PI V_F_VTT H_PLP# PM_LP# R TTHI_0 _J 00 TTHI_ R TTHI J 00 TTHI_0 R9 00 TTHI_ R9 TTHI_ 00 KTO# PI M THRMTRIP# L PROHOT# L THRM K THRM F TTHI00 W TTHI0 F TTHI0 TTHI0 TTHI0 TTHI0 TTHI0 F TTHI0 H TTHI0 P TTHI L TTHI tpct TP9 TP_PU_RRV V tpct TP TP_PU_RV RRV N tpct TP TP_PU_RV RV P tpct TP TP_PU_RV RV tpct TP TP_PU_RV RV tpct TP9 TP_PU_RV9 RV F9 tpct TP TP_PU_RV RV9 tpct TP TP_PU_RV RV H tpct TP TP_PU_RV RV N RV THRM TTHI RV PU OKT_P FOX_P0-0-0 MI0 MI VRL F F0 F F F F0 F F F F0 F F F F F9 F0 F F F F F F F F9 F0 RV RV RV RV9 RV RV RV RV RV W TP_MI0 V TP_MI L TP_VRL R9 Y F0 _J 00 J TP_F T F TP tpct K H_FORPH TP tpct H9 TP_F TP9 tpct Y PI# TP_F TP tpct TP_F0 TP tpct F F J TP_F TP tpct TP_F TP tpct 9 TP_F TP tpct U TP_F9 TP9 tpct U TP_F0 TP0 tpct J TP_F TP tpct H TP_F TP tpct H TP_F TP tpct J TP_F TP tpct H TP_F TP tpct TP_F TP tpct TP_F TP tpct TP_F9 TP tpct M VRM_PWR_R TP_PU_RV TP_PU_RV 0 TP_PU_RV F TP_PU_RV TP_PU_RV TP_PU_RV TP_PU_RV TP_PU_RV TP tpct TP tpct TP tpct 0/0:dd R F PI# _PRTP#,9 VRM_PWR_R Max: 0m Max: 0m 0/:elete TP,TP for layout TP0 tpct TP tpct TP tpct R9 00 TP tpct TP0 tpct TP tpct TP tpct TP tpct R9 _J 00 VT:0/:hange R~R9 from R F00 to R J00 PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. tpct TP TP_V tpct TP TP_V HVPLL tpct TP TP_VIOPLL H_V_M_R H_V_M_R H_V_N H_V_N tpct TP0 VTT_OUT_LFT VTT_OUT_RIHT, H_FL0, H_FL, H_FL V_F_VTT TP_VTT_L R 00 H_FL0 H_FL H_FL VTT(.0v~.v,Typ.V): Wolfdale--max. Yorkfied--max VTT_OUT_RIHT VTT_OUT_RIHT U N_R_J R 00 TO F TO_M N_R_J R 00 R_J R 00 TI_M TO TO_M U W TK R_J R 00 R_J R90 00 TI TI_M TK XP_LKOUT_P R_J R9 00 TM TI ITPLKOUT0 K XP_LKOUT_N TP tpct R_J R9 00 TRT# TM ITPLKOUT J TP tpct TRT# XP_PM0# XP XP_PMb0# PM0# J XP_PM# XP_PMb# PMb0# PM# J 9 XP_PM# XP_PMb# PMb# PM# XP_PM# XP_PMb# PMb# PM# XP_PM# PMb# PM# F XP_PM# PM# /0:N VI_LT R 00 R 00 V VI_LT N V VI0 M VPLL VI L VIOPLL VI M N V_M_R VI L N V_M_R VI K N VN VI L N VN VI M VI M F VTT_L J VTT_OUT_LFT VTT_OUT_RIHT 9 L0 H0 L 0 L LK0 F LK PU OKT_P FOX_P0-0-0 H_V_N H_V_M_R VI_L /0:Only connect to output of voltage regulator thermal monitor V_N VI0 VI VI VI VI VI VI VI VT:0/0:elete R00~R0 R00 N_00 R0 00 H_PU_LK H_PU_LK# V_N H_V_N H_V_M_R R0 N_ 00 R0 00 V_N V_N 0 PWRLIMIT# R0 K_J 00 Q PWRLIMIT#_QL VRUN VT:0/0:hange Q,add R0 PWRLIMIT#_QR R0 0K_J 00 PMT90. Q VR_HOT VTT_OUT_RIHT R0 N_0_F 00 H_PROHOT# PMT90. R Q_ K_J 00 Q N00PT Q VRUN _THRM R 0K_J 00 Q PMT90. VRUN R 0K_J 00 PMT90. VT:0/:dd this circuit _THRM# 9 VT:0/:change TTHI_,0,, pull up from _VRUN to VTT_OUT_LFT VTT_OUT_LFT VTT_OUT_RIHT R _J 00 R9 _J 00 R N J 00 R N J 00 TTHI_ TTHI_0 TTHI_ TTHI_ R XP_PMb# N J 00 _J R 00 XP_PMb# R0 XP_PMb# _J 00 VT:0/9:hange ohm from R F00 to R J00 R0 XP_PM0# _J 00 R0 XP_PM# _J 00 _J R09 00 XP_PM# R0 XP_PM# _J 00 R XP_PM# _J 00 R XP_PM# _J 00 N_ VI_L R 00 VT:0/:hange R to N following Page 9 _VRUN R 00 R0 00 0U_0V_M 00_XR XP_PMb0# placed within 00 mils of the PU socket Max:0m HVPLL 0.0U_0V_K 00_XR VT:0/:hange HH P/N from -00-K00 to -00-K00 FOXONN PU THRML / HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

6 VHOR VHOR VHOR VHOR V_F_VTT V_F_VTT ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. PU POWR / 0 Tuesday, July, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. PU POWR / 0 Tuesday, July, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. PU POWR / 0 Tuesday, July, 00 VHOR(0.V-.V,V_OOT=.V): Wolfdale--max Yorkfied--max VT:0/:dd P MX=. Wolfdale--max VT:00: dd pcs 0.uF cap for VHOR PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 90 U_.V_M 00_XR 90 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 9 0.U_.V_K 00_XR 9 0.U_.V_K 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 0.U_.V_K 00_XR 9 0.U_.V_K 00_XR VTT UF PU OKT_P FOX_P0-0-0 VTT UF PU OKT_P FOX_P0-0-0 VP F9 VP F VP H VP J VP9 H9 VP90 H9 VP9 H VP9 VP9 L VP9 M VP9 J VP9 J VP9 T VP9 W VP99 J VP00 J VP0 9 VP0 L9 VP0 0 VP0 F VP0 Y VP0 K VP0 J9 VP0 M VP09 F VP0 J0 VP VP VP VP L9 VP 9 VP W VP H VP N VP9 N VP0 J VP K VP F9 VP N VP F VP M VP K9 V 0 V V V K V V N V V9 K V0 V V L0 V K V J V9 0 V0 N0 V F0 V V M V N V H9 V H V H V V9 V0 H V V M V V V J V J V F9 V H V9 V0 H V K V V H V H0 V V H V V M V9 H V0 J0 V J0 V F V K V J V F V K9 V J V F V9 H V90 K0 V9 M0 V9 F V9 J V9 F V9 V9 F0 V9 L V9 VTT9 VTT0 VTT VTT VTT 9 VTT 0 V H V V9 L V0 Y V VTT VTT VTT VTT 0 VTT VTT V V L0 V V9 N V0 K V K0 V M V M V L V L VTT9 VTT0 VTT VTT 0 VTT VTT VTT VTT 9 VTT 0 VTT 9 VTT 9 VTT V0 V L V V L V J V V 9 V L V K V H V F V K V 9 V V H V9 K0 V K V L 0 0.U_.V_K 00_XR 0 0.U_.V_K 00_XR U_.V_M 00_XR U_.V_M 00_XR P 0U_V_T FX0R P 0U_V_T FX0R 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 0 0.U_.V_K 00_XR 0 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 9 N_0U_.V_M 0_XR 9 N_0U_.V_M 0_XR 99 U_.V_M 00_XR 99 U_.V_M 00_XR U PU OKT_P FOX_P0-0-0 U PU OKT_P FOX_P0-0-0 VP VP K9 VP M VP L VP VP VP W VP W VP9 W VP0 T VP Y VP L VP VP W0 VP Y0 VP N VP VP Y VP9 9 VP0 M9 VP U VP J VP VP M VP M9 VP VP VP J VP9 J VP0 T0 VP M9 VP F VP VP VP N VP W9 VP U9 VP VP9 VP0 Y VP N VP N VP N VP N VP Y VP Y VP VP VP9 VP0 N9 VP V VP K VP VP M0 VP 9 VP 0 VP VP M0 VP9 K VP0 M VP N VP T VP VP N VP VP W VP VP M VP9 N0 VP0 VP J VP M9 VP M VP M VP L VP U VP Y VP J VP9 VP0 U VP M VP 9 VP N VP M VP U VP K VP U VP K VP9 VP90 K VP9 H VP9 H VP9 K VP9 H VP9 T9 VP9 M VP9 M VP9 9 VP99 Y9 VP00 K VP0 K9 VP0 VP0 J VP0 T VP0 VP0 M VP0 J VP0 U0 VP09 L VP0 VP J VP J9 VP H0 VP J VP VP J VP J0 VP H VP9 H VP0 W VP L VP N VP H VP U VP T VP R VP K VP N9 VP9 VP0 K VP J0 VP J VP VP N9 VP H VP F VP L VP J VP9 J VP0 J VP VP K VP F VP VP M VP F VP K VP 0 VP9 J VP0 M VP L VP J VP K0 VP L VP N0 VP H VP L VP J9 VP9 K VP0 VP N9 VP L0 VP J VP H9 VP J9 VP J VP K VP P VP9 K VP0 L9 VP M VP T VP N VP H VP L VP N VP J VP U VP9 J9 VP0 T VP K VP N VP 9 VP N 9 U_.V_M 00_XR 9 U_.V_M 00_XR U_.V_M 00_XR U_.V_M 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR U PU OKT_P FOX_P0-0-0 U PU OKT_P FOX_P0-0-0 V H V H V H0 V9 H9 V0 H V V H V J V M V V H V P V V V9 K V0 P V P V M V J V W V P V J0 V W V P V V Y V L0 V L9 V V L V Y V9 L V0 9 V N V N V V N V V V P V V9 V0 P V V V0 V R V V9 V V V R V V V R V9 0 V0 N0 V V V T V V V V V T V L V V V 9 V V V V V J V V9 H V V V V K V 0 V L V L V 9 V M V9 V N V V V N V M V V V9 V0 N V 0 V F V 0 V V F0 V H V F V F9 V9 F V F V F V F V N V N V F V F V V9 F V0 N V H V P V 0 V V V T V R0 V9 J V0 V M V V V V L V F0 V V9 V0 V V0 V 0 V9 R9 V90 R V9 R V9 R V9 R V9 U V9 R V9 R V9 P0 V9 V V99 P9 V00 F V0 0 V0 F V0 H V0 V0 V0 V0 9 V0 V09 V0 V0 V0 L V0 H V09 V0 V J9 V K V K V 0 V M0 V H V V9 H V0 H V V V H V V H0 V00 L V0 L V0 M V0 V0 H0 V99 H P 00U_.V_ FX0J0R P 00U_.V_ FX0J0R 0.U_.V_K 00_XR 0.U_.V_K 00_XR 9 U_.V_M 00_XR 9 U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR

7 H_#[..] H_RQ#[..0] H_T0# H_T# H_TP0# H_TN0# H_I0# H_TP# H_TN# H_I# H_TP# H_TN# H_I# H_TP# H_TN# H_I# H_R#[..0] H_# H_TRY# H_RY# H_FR# H_ITM# H_HIT# H_LOK# H_R0# H_NR# H_PRI# H_Y# H_PU_RT# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_R#0 H_R# H_R# U L F L F J F F0 F H9 F L F L F 9 N9 F 0 N F N F J F N0 F M F R F T F R F R F 9 R F 0 R9 F U F T F U F U0 F T F Y F U F F 9 U F 0 Y F Y F Y F F F H_RQ#0 H_RQ# F_RQ_0 K H_RQ# F_RQ_ J9 H_RQ# F_RQ_ H_RQ# F_RQ_ 9 F_RQ_ J0 F_T_0 T9 F_T_ 9 F_TP_0 9 F_TN_0 0 F_INV_0 K F_TP_ J F_TN_ F F_INV_ J F_TP_ K F_TN_ F F_INV_ F_TP_ F_TN_ 0 F_INV_ F_R_0 L F_R_ F_R_ J F_ L0 F_TRY J F_RY F_FR K F_HITM H F_HIT H0 F_LOK L F_RQ0 J F_NR H F_PRI H F_Y F_PURT LLK-P F OF 0 F 0 F F F F F F F F F 9 F 0 F F F F F F F F F 9 F 0 F F F F F F F F F 9 F 0 F F F F F F F F F 9 F 0 F F F F F F F F F 9 F 0 F F F F F F F F F 9 F 0 F F F F_WIN F_ROMP F_VRF F_VRF F H_#0 H_# H_# H_# H_# H_# 0 H_# H_# H_# F H_#9 H_#0 H_# H_# H_# H_# H_# H_# J H_# H H_# F H_#9 H_#0 J H_# L H_# H_# L H_# M H_# M0 H_# J0 H_# H_# K0 H_#9 M9 H_#0 0 H_# J9 H_# F9 H_# H9 H_# L H_# K H_# L9 H_# J H_# M H_#9 H H_#0 F H_# F H_# H_# H H_# L H_# J H_# N H_# H_# H_#9 F H_#0 H_# H_# H_# H_# H_# H_# F H_# H_# 9 H_#9 0 H_#0 0 H_# H_# H_# 0. xvtt_f HWIN HROMP MH_TLRF 00 mils max H_#[..0] HWIN_ MH_TLRF_ V_F_VTT 0, P_RXP[0..] 0, P_RXN[0..] HWIN:.00 mils max.breakout should be kept as short as possible and should be routed as wide as possible. PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. R 9.9_F 00 R._F 00 R 9.9_F 00 9 N_0P_0V_K 00_XR 0.U_V_Y 00_YV U_0V_K 00_XR R0 0_F 00 R 00_F 00 R._F 00 R 00_F 00 V_F_VTT MI_RXP0 MI_RXN0 MI_RXP MI_RXN MI_RXP MI_RXN MI_RXP MI_RXN U P_RXP0 F P_RXN0 P_RXP_0 P_RXP P_RXN_0 H P_RXN P_RXP_ P_RXP P_RXN_ J P_RXN P_RXP_ J P_RXP P_RXN_ L P_RXN P_RXP_ L P_RXP P_RXN_ N9 P_RXN P_RXP_ N0 P_RXP P_RXN_ N P_RXN P_RXP_ N P_RXP P_RXN_ R P_RXN P_RXP_ R P_RXP P_RXN_ R9 P_RXN P_RXP_ R0 P_RXP P_RXN_ U0 P_RXN P_RXP_ U9 P_RXP9 P_RXN_ U P_RXN9 P_RXP_9 U P_RXP0 P_RXN_9 9 P_RXN0 P_RXP_0 0 P_RXP P_RXN_0 R P_RXN P_RXP_ P P_RXP P_RXN_ P_RXN P_RXP_ P_RXP P_RXN_ 0 P_RXN P_RXP_ 9 P_RXP P_RXN_ P_RXN P_RXP_ P_RXP P_RXN_ 0 P_RXN P_RXP_ P_RXN_ K_J 00 R XP_M H N_K_J 00 R XP_LR XP_M F XP_LR /0:N R MI_RXP_0 MI_RXN_0 9 MI_RXP_ 0 MI_RXN_ MI_RXP_ MI_RXN_ F9 MI_RXP_ F MI_RXN_ LLK-P PI MI OF 0 P_TXP_0 P_TXN_0 P_TXP_ 0 P_TXN_ 9 P_TXP_ 9 P_TXN_ P_TXP_ P_TXN_ P_TXP_ P_TXN_ P_TXP_ P_TXN_ P_TXP_ P_TXN_ P_TXP_ H P_TXN_ P_TXP_ J P_TXN_ K P_TXP_9 K P_TXN_9 L P_TXP_0 P P_TXN_0 M P_TXP_ T P_TXN_ R P_TXP_ U P_TXN_ V P_TXP_ W P_TXN_ V P_TXP_ P_TXN_ Y P_TXP_ P_TXN_ XP_M: 0 = Only VO or PI xpress = oth VO and PI xpress. XP_LR: 0 =TX(LN Reverse) = Normal operation (TX) P_TXP0 P_TXN0 P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP9 P_TXN9 P_TXP0 P_TXN0 P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN P_TXP P_TXN XP_OMP XP_IOMPO Y XP_OMPI Y XP_ROMPO Y XP_RI XP_RI XP_LKP 9 XP_LKN 9 MI_TXP_0 MI_TXN_0 MI_TXP_ MI_TXN_ MI_TXP_ MI_TXN_ F MI_TXP_ F MI_TXN_ R 9.9_F 00 R9 0_F 00 MI_TXP0 MI_TXN0 MI_TXP MI_TXN MI_TXP MI_TXN MI_TXP MI_TXN P_TXP[0..] 0 P_TXN[0..] 0 W = 0 mils = mils spacing for 00 mils 0 mils spacing after that _VRUN K_P_00M_MH_P K_P_00M_MH_N MH_TLRF:.voltage divider should be within. inches of it s MH s TLRF pin..9 should be placed as close to the MH pin as possible..trace width is mils minimum at breakout and as should be as wide as possible between the breakout and the resistor divider network. FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision aglelake HOT/PI- / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

8 PVT:0/:ack up RT function: when use RT,stuff R R R R and N R9 R R R in L sku;use the default setting in H sku. RT_R R9 R N 00 Place V R resistors close to MH, <0mils to MH LLs VT:0/: add option resistor for H KU and L KU RT_RN R R N 00 tpct TP tpct TP tpct TP tpct TP tpct TP9 tpct TP tpct TP tpct TP0 tpct TP tpct TP tpct TP9 tpct TP tpct TP0 tpct TP tpct TP VT:0/0:connect U pin 0, 0,0,F0 to N TP_N_9 W0 TP_N_ U TP_N_ R TP_N_ TP_N_ TP_N_ TP_N_ TP_N_ TP_N_ TP_N_0 W TP_N_9 N TP_N_ N TP_N_ K F0 0 TP_N_ 0 0 TP_N_ U N_9 N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_9 N_ N_ N_ N_ N_ N_ N_ N_ tpct TP9 TP_MH_RV9 U tpct TP9 TP_MH_RV RV_9 U0 tpct TP9 TP_MH_RV RV_ T tpct TP99 TP_MH_RV RV_ T tpct TP00 TP_MH_RV RV_ R tpct TP0 TP_MH_RV RV_ R tpct TP0 TP_MH_RV RV_ R tpct TP0 TP_MH_RV RV_ R tpct TP0 TP_MH_RV RV_ N tpct TP0 TP_MH_RV0 RV_ M tpct TP0 TP_MH_RV9 RV_0 M tpct TP TP_MH_RV RV_9 L tpct TP09 TP_MH_RV RV_ L tpct TP TP_MH_RV RV_ K tpct TP TP_MH_RV RV_ J0 tpct TP TP_MH_RV RV_ J tpct TP TP_MH_RV RV_ J tpct TP TP_MH_RV RV_ tpct TP TP_MH_RV RV_ tpct TP TP_MH_RV0 RV_ tpct TP TP_MH_RV9 RV_0 tpct TP9 TP_MH_RV RV_9 N0 tpct TP0 TP_MH_RV RV_ N9 tpct TP TP_MH_RV RV_ K tpct TP TP_MH_RV RV_ J tpct TP TP_MH_RV RV_ tpct TP TP_MH_RV RV_ tpct TP TP_MH_RV RV_ tpct TP TP_MH_RV RV_ RV_ LLK-P RV N V MI H OF 0 RT_R RT_RN RT_LU _IRF RT_HYN RT_VYN ualx_nable RT_IRTN PL_RFLKINP PL_RFLKINN PL_RFLKINP PL_RFLKINN RT LK RT T P_TRLLK P_TRLT VO_TRLLK VO_TRLT JT_TM JT_TK JT_TO JT_TI RTIN LP PRTP IH_YN PWROK N XORTT LLZTT ITPM_N NTT L L L0 HPL_LKINP HPL_LKINN H_LK H_RT H_I H_O H_YN L L_PWROK L_RT L_VRF L_LK L_T RT_R RT_RN RT_LU _RT RT_HYN R N F 00 RT_VYN R9 N F 00 F0 ualx_nable R0 00 F N_K_J 00 mils max 9 M L N9 N N0 R MH LK MH T J TP_P_TRLLK F TP_P_TRLT J VO_TRLLK VO_TRLT TP_MH_JT_TM TP_MH_JT_TK TP_MH_JT_TO TP_MH_JT_TI N P P MH_PRTP K R J N R0 N _K_J 00 M0 L ITPM_N# R 0 N_K_J 00 P F P9 P0 MH_L MH_L MH_L0 U MH_H_LK V MH_H_RT U MH_H_I V MH_H_O U MH_H_YN N W N Y Y L_VRF_MH VO_TRLLK 0 VO_TRLT 0 PVT:0/0:el R R R and R for cancel RT;hange R9 R R and R from NV to normal stuff. L_PWROK 9, H_L_RT0# H_L_LK0 H_L_T0 RT_R RT_RN RT_LU HYN_V VYN_V PVT:0/0:el the R, R9,and the signal ports for cancel RT function TP9 tpct TP9 tpct TP9 tpct TP9 tpct R9 00 TP90 tpct TP9 tpct TP0 tpct TP0 tpct TP0 tpct R 00 R 00 R 00 R 00 R9 00 K_RFLK_P K_RFLK_N K_9M_RF_P K_9M_RF_N MH LK MH T PLT_RT# 9,,,,9,0 PM_LP# _PRTP#,9 H_MH_YN# 9 _PWROK 9, VT:0/: Mount R0 for corwin spring. MH_LK_P MH_LK_N PVT:0/0:el the MH LK&T port for cancel RT. /:hange R~ R9 L_VRF_MH _V_L RT_LU R R N 00 VT:0/: change R (.0k) from % to % _RT R Place close to MH, R <00mil to MH LL N.0K_F 00 VO_TRLT VO_TRLT /0:hange R R9 from 0 Ohm to Ohm hange R from to K 0.U_.V_K 00_XR L H, H_FL0, H_FL, H_FL VO IL (FULT INTRNL P) VO R PRNT/P IL /:dd R R MH T R.K_J 00 MH LK R.K_J 00 VT:0/:hange R R from 0Kohm to 0ohm R0 K_F 00 R _F 00 VT:0/: for corwin spring:change from _VRUN to _V_L VT:0/0:change R from ohm to ohm ualx_nable: x P port ifurcation: 0=x PIe Ports nable =x PIe Port nable N: Pulldown: nable TN Float: isable TN ITPM_N: Pulldown: nable TPM Float: isable TPM VRUN VO_TRLLK R PVT:0/0:hange R VO_TRLT N.K_J 00 R and R from to N. N.K_J 00 PVT:0/:ack up 0 and 0 for black screen issue. N P_0V_J N P_0V_J 00_NPO 00_NPO VRUN K_9M_RF_P R NV_0K_J 00 K_RFLK_P R NV_0K_J 00 K_9M_RF_N R NV_ 00 K_RFLK_N R NV_ 00 _VRUN R MH_L0 0K_J 00 R MH_L 0K_J 00 R MH_L 0K_J 00 /:hange R R R MH_L_RF:.MH_L_RF=0.V;.Trace width/pacing: mil(min)/0mil(min.) for main route;.reakout area: width>mils, L<00mils;. 0. µf cap placed as close as possible to MH_L_RF pin. FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision aglelake V/MI / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

9 , R M[..0], R 0, R, R, R 0, R, R K0, R K, R OT0, R OT tpct TP9 tpct TP0 tpct TP tpct TP tpct TP tpct TP R M0 R M R M R M R M R M R M R M R M R M9 R M0 R M R M R M R M R 0 R R R 0 R TP_R TP_R R K0 R K TP_R K TP_R K R OT0 R OT TP_R OT TP_R OT U R M_0 R M_ R M_ R M_ R M_ R M_ Y R M_ R M_ R M_ 0 R M_9 W R M_0 0 R M_ 0 R M_ M R M_ R M_ V R 0 Y R R U R 0 R0 R U R M R R K_0 R K_ R K_ Y R K_ R R OT_0 M R OT_ R R OT_ L0 R OT_ R K0 R K0 Y R K#0 R K_0 R K#0 R K R K_0 R K W9 R K# R K_ R K# Y9 R K_ U R K_ V R K_ U R K_ T R K_ T0 R K_ R0 R K_ W R K_ Y R K_ 0/0:elete test piont for layout OF 0 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q0 R Q R Q R Q R Q R Q R Q R Q R Q Y R Q9 R Q0 R Q R Q R Q 0 R Q Y R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q WR Q Y R Q V R Q Y R Q U R Q T R Q9 R R Q0 U R Q L R Q K R Q R Q R Q L R Q K R Q H R Q R Q9 F R Q0 F R Q R Q R Q F0 R Q F R Q R Q R Q R Q R Q9 W R Q0 W R Q R Q R Q Y R Q Y0 R Q V R Q U R Q R0 R Q P R Q9 V R Q0 V R Q R R Q R R Q R Q[..0] R Q[..0] R Q0 R Q R Q R Q R Q R Q R Q R Q 9 R H Y T R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ 9 T H Y T R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# R Q#[..0] R M[..0] R M0 R M R M R M R M R M R M R M 9 V K T R M_0 R M_ R M_ R M_ R M_ R M_ R M_ R M_ R R R R W V U W R R#, R #, R W#, LLK-P R_ FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision aglelake RII H / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet 9 of 0

10 , R M[..0], R 0, R, R, R 0, R tpct TP tpct TP, R K0, R K tpct TP tpct TP, R OT0, R OT R K0 R K#0 R K R K# R Q[..0] R M[..0] R 0 R R R 0 R TP_R TP_R R K0 R K TP_R K TP_R K R OT0 R OT R K0 R K#0 R K R K# 0/0:elete test piont for layout R Q0 R Q R Q R Q R Q R Q R Q R Q R M0 R M R M R M R M R M R M R M U R M0 R M R M_0 R M R M_ R M R M_ R M R M_ R M R M_ R M R M_ R M R M_ 0 R M R M_ 0 R M9 R M_ 0 R M0 R M_9 R M R M_0 9 R M R M_ 9 R M R M_ R M R M_ 9 R M_ R 0 R R R 0 9 R R 0 R R K_0 Y0 R K_ R K_ R K_ R OT_0 9 R OT_ R OT_ R OT_ Y R K_0 W R K_0 V R K_ W R K_ W R K_ Y R K_ T R K_ U R K_ P R K_ P0 R K_ W R K_ V R K_ W R Q_0 T R Q_ R0 R Q_ U R Q_ R R Q_ K R Q_ F R Q_ R Q_ Y R M_0 R R M_ U R M_ V R M_ U9 R M_ L R M_ J R M_ R M_ LLK-P MM R_ OF 0 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_9 R Q_0 R Q_ R Q_ R Q_ R Q_0 R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R Q_ R R R R W R_RP R_RPU R_P R_PU R_VRF R_RM_PWROK R_RMRT R R M0 R W R OT V W 9 U U U W Y9 Y P W T U W P U Y V R V0 P W T0 N0 T V U9 V9 W R P R9 R U N N V9 W9 U0 U L L K J N9 N0 K L9 J J F K0 J0 F W9 U R T R L F R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q R Q R Q R Q R Q R Q9 R Q0 R Q R Q R Q R Q#0 R Q# R Q# R Q# R Q# R Q# R Q# R Q# Y R_RP R_RPU R_P R_PU MH_R_VRF R MH_RM_PWROK TP_RM_PWROK R TP_R 0 TP_R M0 T TP_R W V0 TP_R OT R R#, R #, R W#, R 00 R Q[..0] R Q#[..0] R_RPU R_PU R_RP R_P close to MH Pin as possible /0:Placed on the VM side of the resistor not the MH side MH_R_VRF _VU VT:0/:hange R R from 00 to 00 VT:0/0:dd 0 TP tpct TP tpct TP tpct TP tpct TP9 tpct R 0._F 00 R 0._F 00 R9 0._F 00 R0 9_F P_0V_K 00_XR 0 0.U_V_Y 00_YV _VU 0.U_V_Y 00_YV MH_R_VRF Layout Note: Trace width/pcing: 0 mils (Min.)/0mils(Min.) reakout area Trace width/pcing: mils (Min.)/mils( Min.) for maximum of 00 mils ; 0. µf cap placed as close as possible to the MH MVRF pin. 0.U_V_Y 00_YV R K_F 00 R K_F 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision aglelake RII H / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet 0 of 0

11 VRUN _VRUN /:hange R from ohm to 0ohm N R 9 _VRUN L R U VPLL_XP_L R VPLL_XP_R UH_00 L0-R0K N F 00 9 V_L_ N_0U_.V_M N_0.U_.V_K V_L_ 00_XR V_L_ 00_XR V_L V_L V_L_ VT:0/:hange _VRUN to V_L V_L for corwin spring V_L_ V_HPLL V_L_ R V_L_9 V_L_0 N_.U_0V_M V_L_ V_L_ 00_XR V_L_ F _VRUN /:hange R from ohm to 0ohm N R V_L_ F V_L_ 0 V_L_ IV_HPLL: m R PI xpress* PLL nalog upply V_L_ L J V_L_ J VPLL_XP_L VPLL_XP_R V_L_9 R J9 UH_00 L0-R0K N F 00 V_L_0 J0 V_L_ J V_L_ J N_0U_.V_M V_L_ K 00_XR N_0.U_.V_K V_L_ K V_L_ 00_XR K V_L_ /:hange L L K9 V_L_ K0 _V_L V_L_ K V_L_9 IV_HPLL: K iscrete fx:. m Host PLL nalog upply Voltage(MX..V) V_L_0 L K V_L_ Integrated fx:. K V_HPLL V_L_ K 0.UH_00 V_L_ K TL009-RM N_.U_0V_M V_L_ K V_L_ 00_XR K9 V_L_ IV_MPLL: K0 V_L_ iscrete fx: m K V_L_ Integrated fx: 9m L ystem Memory PLL nalog upply(max..v) V_L_9 L0 L V_L_0 L V_MPLL V_L_ L.UH_00 V_L_ L TL009-RK V_L VRUN R R9 IV_PLL: N F N F iscrete fx:.m Integrated fx: 90.m VPLL_XP_R L V_HPLL VPLL_XP U V_PLL VPLL_XP_R V_HPLL 0UH_00 N_0U_.V_M VPLL_XP L0-00K P 00_XR 0U_.V_ V_HPLL N_0.U_.V_K V_MPLL V_HPLL TP0MI 00_XR V_PLL V_MPLL 0 IV_PLL: V_PLL V_PLL 0 V_PLL iscrete fx:.m Integrated fx: 90.m.m L VRUN 9 V_PLL V_ 0UH_00 _VRUN R V_H L0-00K P N_ 00 R V_H 0U_.V_ N_0.U_.V_K R00 TP0MI 00_XR V_ 9 V 9 V /:hange L L P P. V PI xpress* nalog upply Voltage VT:0/0:change R from ohm to 0. ohm; change R9 from 00 ohm to 9. ohm. L0 V XP R V_XP_R R 00R-00MHZ_00 0._F 00 _F 00 M000 U_0V_K R9 00_XR 9._F 00 L VQ_RT_L _00R-00MHZ_00 M000 R F 00 nalog upply IV_:.m R90 F 00 _U_0V_K 00_XR V_ IV_XP: 0m V_XP IVQ_RT: m VQ_RT /:dd R90 R9 NV_ /:dd R9 PVT:0/:hange R9 from 00 to 00 for intel suggestion. R90 NV_. V isplay Quiet igital upply V_XP V_XP VQ_RT 0 VQ_RT LLK-P POWR OF 0 V_L_ L V_L_ L V_L_ L V_L_ L9 V_L_ L V_L_9 L0 V_L_0 L V_L_ L V_L_ L V_L_ L V_L_ L V_L_ L V_L_ L V_L_ L9 V_L_ L0 V_L_9 L V_L_0 L V_L_ L V_L_ L V_L_ L V_L_ L9 V_L_ M V_L_ M V_L_ M V_L_ M V_L_9 M0 V_L_0 M V_L_ M V_L_ M V_L_ M V_L_ M V_L_ M9 V_L_ M V_L_ M V_L_ P V_L_9 P V_L_0 W V_L_ Y9 V_L_ Y0 V_L_ Y V_L_ Y V_L_ Y V_M_ P V_M_ T V_M_ V V_M_ Y0 V_M_ V_M_ 9 V_M_ V_M_ V_M_9 9 V_M_0 V_M_ V_M_ V_M_ V_M_ V_M_ V_MLK_ K V_MLK_ L V_MLK_ L V_MLK_ M L9 VML_R M0 VML_R 0.09UH_00 WF0F-90NM VVRM_XP VVRM_XP R 00 VT:0/:Open P for corwin spring hort P for no support corwin spring. IV_L: iscrete fx---max.0 Integrated fx--max. _V_L Place in V_L plane as close to ()MH as possible. IV_R: iscrete fx: 0.99 Integrated fx:.09 0U_.V_M 00_XR 0.U_0V_M 00_XR /0:dd 0~0 PL P N L LO TO MH LL VT:0/:elete P R N_ U_.V_M 00_XR.U_0V_M 00_XR.U_0V_M 00_XR _V_L _VRUN _VRUN /:tuff R;N R VT:0/:Reserved for corwin spring..u_0v_m 00_XR _VU IV_KR: 0. L 0NH_00 R0 TW009-RM R 0P_0V_K 00_XR 0.U_.V_K N F 00_XR 00.U_.V_K 00_XR.U_0V_M 00_XR.U_0V_M 00_XR 0.U_0V_M 00_XR U_.V_M 00_XR N_U_.V_M 00_XR.U_0V_M 00_XR 0.U_0V_M 00_XR N_U_.V_M 00_XR 0P_0V_K 00_XR 0P_0V_K 00_XR FOXONN 0P_0V_K 00_XR _VU VT:0/0:dd and for simulation VT:0/:hange L from L-L0-00 to L-TW PVT:0/:hange R from N to stuff and R from stuff to N follow intel. HON HI Precision Ind. o., Ltd. P - R& ivision aglelake POWR / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

12 For MH OR POWR _VRUN V(MX.V): iscrete fx---max. Integrated fx--max.0 /:elete P9 /0:dd P P 0U_.V_M 00_XR ackside cap sites, placed directly underneath the V_ore center-array pins, with sufficient via connections 0 U_.V_M 00_XR 0U_.V_M 00_XR P 0U_V_T FX0R Top-side caps. Place along the ()MH edge. 0.U_.V_K 00_XR P 0U_V_T FX0R 0 U_0V_K 00_XR VT:00: dd pcs 0.uF cap for _VRUN U_0V_K 00_XR U_.V_M 00_XR 9 0U_.V_M 00_XR 0.U_.V_K 00_XR U_.V_M 00_XR 0 0U_.V_M U_0V_K 00_XR 00_XR U_0V_K 00_XR 0.U_.V_K 00_XR U_0V_K 00_XR U_0V_K 00_XR 0.U_.V_K 00_XR 0U_.V_M 00_XR U_0V_K 00_XR U_0V_K 00_XR 0U_.V_M 00_XR U_0V_K 00_XR _VRUN UF 9 V_ V_ V_ V_ V_ 9 V_ 0 V_ 0 V_ V_9 V_0 V_ 9 V_ 0 V_ V_ V_ 9 V_ V_ V_ V_9 V_0 9 V_ V_ V_ V_ 0 V_ V_ V_ V_ 9 V_9 V_0 V_ 9 V_ V_ V_ V_ V_ 9 V_ F V_ F V_9 F9 V_0 F0 V_ F V_ F V_ F V_ F V_ F V_ F V_ F V_ F9 V_9 F V_0 V_ V_ 0 V_ V_ V_ V_ 9 V_ J V_ J V_9 J9 V_0 J V_ J V_ J V_ F9 V_ H V_ L V_ P V_ R V_ R V_9 R V_0 R9 V_ T V_ T V_ T V_ T V_ T V_ T V_ T V_ T9 V_9 U V_0 U V_ U V_ U V_ U V_ U V_ U V_ U9 V_ V V_ W9 V_9 W V_90 W V_9 W V_9 W V_9 W9 V_9 Y0 V_9 Y V_9 Y V_9 Y V_9 LLK-P POWR OF 0 V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_9 V_XP_0 V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_9 V_XP_0 V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_9 V_XP_0 V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ V_XP_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_9 VTT_F_0 VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_9 VTT_F_0 VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_9 VTT_F_0 VTT_F_ VTT_F_ VTT_F_ VTT_F_ VTT_F_ F F J J0 J J J J J J J J J9 K0 K K K K K K K K K K9 U U W Y Y F F H H J J K K L L M M N0 N N P0 P P P R0 R R R R.U_0V_Y 00_YV _VRUN Place in the V_XP plane as close the ()MH as possible VTT_F(MX.V): iscrete fx---max.009 Integrated fx--max ystem us Input Voltage V_F_VTT PI xpress* and MI upply IV_XP: iscrete fx---max.99 Integrated fx--max. 9.U_0V_Y 00_YV.U_0V_Y 00_YV 0.U_0V_Y 00_YV.U_0V_Y 00_YV.U_0V_Y 00_YV as close to the ()MH as possible(00mils from the package.) PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision aglelake POWR / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

13 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. aglelake N / 0 Tuesday, July, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. aglelake N / 0 Tuesday, July, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN IO- Mother oard MP. aglelake N / 0 Tuesday, July, 00 N 9 OF 0 UI LLK-P N 9 OF 0 UI LLK-P V_9 V_9 V_9 V_9 V_99 0 V_00 V_0 9 V_0 V_0 V_0 9 V_0 V_0 0 V_0 V_ V_ V_ V_ V_ V_ V_ V_9 9 V_0 V_ V_ V_ V_ V_ V_ F V_ F V_9 F0 V_0 F V_ F V_ F V_ V_ V_ V_ V_ 9 V_9 V_0 V_ H V_ H V_ H V_ H V_ H V_ H0 V_ H V_ H0 V_9 H V_0 H V_ H V_ H V_ H V_ H V_ H9 V_ J V_ J V_ J V_9 J V_0 J V_ J9 V_ K V_ K V_ K V_ K0 V_ K V_ K9 V_ K V_9 K V_0 L0 V_ L V_ L0 V_ U V_ U V_ U V_ U V_ U V_ U9 V_ U0 V_9 U V_0 U9 V_ U V_ U V_ W V_ W V_ W V_ L V_ L0 V_ L V_ L9 V_ L V_ L V_9 L9 V_0 M V_ M V_ M V_ M V_ N V_ N V_ N V_ N V_ N9 V_9 N0 V_90 N V_9 N V_9 N V_9 N V_9 P V_9 P V_9 P V_9 P V_9 P V_99 R V_00 R V_0 R V_0 R V_0 R9 V_0 R V_0 R0 V_0 R V_0 R V_0 R V_09 R V_0 T0 V_ T V_ T V_ T V_ T V_ T V_ T9 V_ T0 V_ T V_9 T0 V_0 T V_ T V_ T V_ T V_ T V_ T V_ T0 V_ T V_ T V_9 T V_0 T9 V_ U V_ W V_ W0 V_ W V_9 W V_0 W V_ W V_ W V_ W V_ Y0 V_ Y V_ Y V_ Y V_ Y V_9 Y V_0 Y9 V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y9 V_9 Y9 N 0 OF 0 UJ LLK-P N 0 OF 0 UJ LLK-P V_ V_9 V_0 V_ V_9 V_9 V_9 V_9 V_0 V_0 V_09 V_ V_ F V_ N OF 0 UH LLK-P N OF 0 UH LLK-P V_ V_ V_ 9 V_ V_ V_ V_ 0 V_ V_ V_ V_ V_ V_ V_ V_ 0 V_9 V_0 V_ V_ V_ V_ 0 V_ V_ V_ V_ V_9 V_0 V_ 9 V_ V_ V_ V_ V_ V_ V_ 9 V_9 V_0 V_ V_ V_ 0 V_ V_ V_ V_ V_ V_9 V_0 9 V_ V_ V_ V_ V_ V_ V_ V_ 9 V_9 V_0 9 V_ V_ V_ V_ V_ 0 V_ V_ V_ V_9 V_0 V_ 0 V_ V_ V_ F0 V_ F V_ F V_ F V_ F V_9 F V_0 F9 V_ F V_ F V_ 9 V_ V_ V_ V_ V_ V_9 V_90 H V_9 H V_9 H V_9 J0 V_9 J V_9 J V_9 J V_99 J V_00 J V_0 K V_0 K V_0 K9 V_0 L V_0 L V_0 L V_0 N V_0 N V_09 N V_0 N V_ N V_ N V_ N V_ N V_ N V_ P0 V_ P V_ P V_9 P V_0 P V_ P9 V_ P V_ R0 V_ R V_ R V_ R V_ R V_ R V_9 R V_0 R V_ R V_ R9 V_ R V_ R9 V_ T V_ T V_ T V_ T V_9 T V_0 T V_ T9 V_ T V_ U0 V_ U V_ U V_ U0 V_ U V_ U V_9 U V_0 U9 V_ V V_ V V_ V V_ V V_ V V_ V V_ V0 V_ V V_9 V V_0 V V_ V V_ V9 V_ W V_ W V_ W0 V_ W V_ W V_ W V_9 W V_0 W0 V_ Y V_ Y V_ Y V_ Y V_ Y V_ Y0 V_ Y V_ 0 V_0 V_ V_ 9 V_ V_ V_ F V_ V_ V_9 V_90 V_9 J V_9 J9 V_9

14 R_VRF VT:0/:elete the P PJ 0. µf and. µf placed close to VRF pins 9, R K0 9, R 9, R 0 9, R W# 9, R # 9, R 9, R OT 0/ Reserved,need to Open to support corwin spring VT:0/: For corwin spring,,9 M_THRM_T_Q,,9 M_THRM_LK_Q VRUN R9 N V_L 9 0.U_V_M_ 00 For corwin spring R0 _ 90.U_0V_M 00_XR 9.U_0V_M 00_XR R_VRF R Q0 R Q R Q#0 R Q0 R Q R Q R Q R Q9 R Q# R Q R Q0 R Q R Q R Q R Q# R Q R Q R Q9 R Q R Q R M R Q R Q R M R M9 R M R M R M R M R M0 R Q R Q R Q# R Q R Q R Q R Q0 R Q R M R Q R Q R Q R Q9 R Q# R Q R Q0 R Q R Q R Q R M R Q R Q9 9 0.U_V_Y 00_YV _VU.V per IMM=.0 N VRF V Q0 Q 9 V Q#0 Q0 V Q 9 Q V Q Q9 V9 9 Q# Q V9 Q0 Q 9 V0 0 0 MFIX MFIX V V0 Q Q0 Q Q V V 9 Q# N 0 Q M V9 V Q Q Q9 Q 9 V V 0 Q Q Q Q9 V V M Q# 9 N Q 0 V9 V0 Q Q0 Q Q V V 9 K0 K 0 V V N _ V9 V V V V0 V 0 0 0/P R# 0 09 W# 0# 0 V V # OT0 # V V 9 OT N 0 V V Q Q Q Q V V 9 Q# M 0 Q mm V V Q Q Q9 Q V 9 V Q 0 Q0 Q Q V V9 Q# M Q 9 V V 0 Q Q Q Q V0 V Q Q 9 Q9 Q 0 V V NTT K V0 K# Q# V 9 Q M 0 V V Q0 Q Q Q V V 9 Q Q0 0 Q Q V V M Q# V Q 9 Q V 90 9 Q9 Q 9 9 V Q 9 9 V 9 9 L V(P) 00 R RM O-IMM (00P) NPTH NPTH 0 0 IMM_0 V Q Q V M0 0 V Q Q V Q 0 Q V M V K0 0 K0# V Q Q V 0 _VU R_00P FOX_0-NN-F R Q R Q R M0 R Q R Q R Q R Q R M R Q R Q R Q0 R Q R_XTT#0 R M R Q R Q R Q R Q9 R Q# R Q R Q0 R Q R M R M R M R M R M R M R M0 R M R Q R Q R M R Q R Q9 R Q R Q R Q# R Q R Q R Q R Q R Q R M R Q R Q R Q0 R Q R Q# R Q R Q R Q 0_IM0 _IM0 R K0 9 R K#0 9 TP tpct R K 9, R 9, R R# 9, R 0 9, R OT0 9, R K 9 R K# 9 R M[..0] 9 R Q[..0] 9 R Q[..0] 9 R Q#[..0] 9 R M[..0] 9, Mus ddress: 0H(W)/H(R) R9 0K_J 00 R9 0K_J 00 Place IMM_0 near MH R_VRF R_VRF (0 mil) Place these aps near o-imm0 Place these aps near o-imm0 99.U_0V_Y_Y U_.V_K 00_XR VT:0/:elete the R9 and it's power RIMM_VRF _VU /:hange 0~ _VU VT:0/0:N R9,stuff R,R 00.U_0V_Y_Y 00 0.U_.V_K 00_XR 09 0.U_V_M_ 00 0.U_0V_Y_Y 00 0.U_.V_K 00_XR R K_F 00 R K_F 00 0.U_0V_Y_Y 00 0.U_.V_K 00_XR _VU 0P_0V_K 00_XR FOXONN VT:0/09:Reserved 9 for sinulation. 9 N_.U_0V_Y_Y 00 0.U_0V_Y_Y 00 0P_0V_K 00_XR VT:0/0:dd and for simulation. HON HI Precision Ind. o., Ltd. P - R& ivision RII(H IMM0) / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

15 R_VRF U_V_M_.U_0V_M 00 00_XR 0. µf and. µf placed close to VRF pins.v per IMM=.0 R Q0 R Q R Q#0 R Q0 R Q R Q R Q R Q9 R Q# R Q R Q0 R Q _VU N VRF V Q0 Q 9 V Q#0 Q0 V Q 9 Q V Q Q9 V9 9 Q# Q V9 Q0 Q 9 V0 0 0 MFIX MFIX V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V _VU R Q R Q R M0 R Q R Q R Q R Q R M R Q R Q R K0 0 R K#0 0 R M[..0] 0 R Q[..0] 0 R Q[..0] 0 R Q#[..0] 0 R M[..0] 0, 0.U_0V_Y_Y 00 Place these aps near o-imm. 0.U_0V_Y 00_YV 0.U_0V_Y_Y 00 0.U_0V_Y_Y 00 _VU 0.U_0V_Y_Y 00 0, R K0 0, R 0, R 0 0, R W# 0, R # 0, R 0, R OT VT:0/: For corwin spring R Q R Q R Q# R Q R Q R Q9 R Q R Q R M R Q R Q R M R M9 R M R M R M R M R M0 R Q R Q R Q# R Q R Q R Q R Q0 R Q R M R Q R Q R Q R Q9 R Q# R Q R Q0 R Q R Q R Q R M R Q R Q9,,9 M_THRM_T_Q VRUN,,9 M_THRM_LK_Q R N_ P_PWR 9 9 _V_L R _.U_0V_M 0.U_V_Y 00_XR 00_YV For corwin spring V V0 Q Q0 Q Q V V Q# N 0 Q M V9 V Q Q Q9 Q V V 0 Q Q Q Q9 V V M Q# N Q 0 V9 V0 Q Q0 Q Q V V K0 K 0 V V N _ V9 V V V V0 V 0 0/P 0 0 R# 0 W# 0# 0 V V # OT0 # V V OT N 0 V V Q Q Q Q V V Q# M 0 Q mm V V Q Q Q9 Q V V Q 0 Q0 Q Q V V9 Q# M Q V V 0 Q Q Q Q V0 V Q Q Q9 Q 0 V V NTT K V0 K# Q# V Q M 0 V V Q0 Q Q Q V V Q Q0 0 Q Q V V M Q# V Q Q V 90 Q9 Q 9 V Q 9 V 9 L 0 9 V(P) 00 R RM O-IMM (00P) NPTH NPTH 0 0 IMM_ R_00P FOX_0-NN-F R Q0 R Q R_XTT# R M R Q R Q R Q R Q9 R Q# R Q R Q0 R Q R M R M R M R M R M R M R M0 R M R Q R Q R M R Q R Q9 R Q R Q R Q# R Q R Q R Q R Q R Q R M R Q R Q R Q0 R Q R Q# R Q R Q R Q TP tpct 0_IM R9 0K_J 00 _IM R9 0K_J 00 Mus ddress: (W)/(R) R K 0, R 0, R R# 0, R 0 0, R OT0 0, R K 0 R K# 0 P_PWR IMM_ is placed farther from the MH than IMM_0 Place these aps near o-imm. 0.U_.V_K 00_XR VT:0/:elete the R&R For corwin spring 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR 0P_0V_K 00_XR FOXONN 0P_0V_K 00_XR _VU 9 0P_0V_K 00_XR VT:0/0:dd and for simulation. VT:0/0:dd 9. HON HI Precision Ind. o., Ltd. P - R& ivision RII(H IMM0) / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

16 0_9VRUN 0.U_.V_K 00_XR U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR /:hange these caps 0_9VRUN Layout note: Place cap close to every Rtt to 0_9VRUN 0.U_.V_K 00_XR 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 0.U_.V_K 0.U_.V_K 00_XR 00_XR U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR Layout note: Place cap close to every Rtt to 0_9VRUN 9, R M[..0] /:hange RP RP RP9 RP RP0 RP RP RP RP RP 0, R M[..0] 9, R R# 9, R W# 9, R # 9, R 0 9, R j RP 00 R M R M R M R M _j RP 00 R R# R W# R # R 0 _j RP9 00 R M R R M R M R M R9 _J 00 0_9VRUN 9, R 0 9, R OT 9, R 9, R OT0 0_9VRUN 9, R 0_9VRUN 0_9VRUN 9, R K 9, R K0 VT:0/:hange ohm resistor from _F to _J R 0 R0 _J00 R OT R0 R R0 _J00 _J00 R OT0 R0 _J00 _j RP 00 R M R R M0 R M0 R M R M R M R M9 _j RP0 00 R K R09 _J00 R K0 R09 _J00 0_9VRUN 0_9VRUN 0_9VRUN 0_9VRUN 0, R K 0, R K0 0, R R K R090 _J00 R K0 R09 _J00 R R99 _J00 0_9VRUN R 0 0, R 0 R0 _J00 R OT 0, R OT R0 _J00 R 0, R R0 _J00 R OT0 0, R OT0 R0 _J00 0, R j 0_9VRUN RP 00 R M R M R M9 R M _j 0_9VRUN RP 00 R 0 0, R 0 R M0 0, R W# R M 0, R # R M 0_9VRUN 0, R R# 0_9VRUN 0/0:elete RP;dd RP RP R M R M R M0 R j RP 00 R M R M R M R M R W# R # R M R R# 00_PR _j RP 00 RP 00_PR RP 0_9VRUN 0_9VRUN 0_9VRUN 0_9VRUN /0:hange PR PR PR PR9 PR0 from Ohm to Ohm hange PR fom Ohm to Ohm *R hange PR from Ohm to Ohm *R hange R9 from Ohm to Ohm /0:hange PR PR PR PR PR from Ohm to Ohm hange PR fom Ohm to Ohm *R hange PR from Ohm to Ohm *R hange R99 from Ohm to Ohm FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision RII Termination ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

17 U IP_W PI_PR PI_VL# K_P_M_IH PI_RT# PI_IRY# PI_PM# PI_RR# PI_TOP# PI_TRY# PI_PRR# PI_FRM# R K_J 00 PI_NT#0 PI_NT#0 H _FLH_N# oot evice *NT0 *PI_# tpct TP0 TP_PIO PI 0 tpct TP TP_PIO F PI 0 LP PI_RQ#0 PI_RQ#0 K PIO0 PIO F PIO VT:0/0:elete I_T VRUN R00 0K_J 00 R N_K_J 00 IP_W H:L;L:RT INT_PIRQ# INT_PIRQ#, INT_RIRQ, PNL_I0 U PI_PR PI_VL# PR K_P_M_IH VL# PI_RT# PILK R PI_IRY# PIRT# J PI_PM# IRY# R PI_RR# PM# K PI_TOP# RR# F0 PI_LOK# TOP# H PI_TRY# PLOK# PI_PRR# TRY# F PI_FRM# PRR# FRM# NT0# NT#/PIO NT#/PIO NT#/PIO RQ0# RQ#/PIO0 RQ#/PIO RQ#/PIO INT_PIRQ# J INT_PIRQ# PIRQ# INT_PIRQ# PIRQ# F INT_PIRQ# PIRQ# PIO PIRQ# K PIO PIRQ#/PIO L IP_W PIRQF#/PIO F PIO PIRQ#/PIO PIRQH#/PIO INT_RIRQ N RIRQ IH0 PI OF VRUN RP INT_RIRQ 0 PNL_I0 9PI_RQ#0 PIO0 VRUN PIO PIO /0# /# /# /# PI_[..0] 0 PI_0 PI_ 9 PI_ 9 PI_ PI_ PI_ 0 PI_ PI_ PI_ PI_9 PI_0 PI_ H PI_ F PI_ PI_ PI_ PI_ PI_ PI_ 0 PI_9 PI_0 PI_ H PI_ PI_ PI_ PI_ PI_ PI_ J PI_ F PI_9 PI_0 H PI_ F PI_/#0 9 PI_/# PI_/# PI_/# PI_/#0 PI_/# PI_/# PI_/# PI_[..0] MI_TXN0 MI_TXP0 MI_TXN MI_TXP MI_TXN MI_TXP MI_TXN MI_TXP MI_RXN0 MI_RXP0 MI_RXN MI_RXP MI_RXN MI_RXP MI_RXN MI_RXP K_P_00M_IH_N K_P_00M_IH_P V_P_IH 00'0/: el Marvel Lan& add Intel OZMN LN LN_RXN LN_RXP LN_TXN LN_TXP Wireless- MINI_RXN LN MINI_RXP MINI_TXN MINI_TXP TV TV_RXN TV_RXP TV_TXN TV_TXP tpct TP9 tpct TP0 tpct TP tpct TP tpct TP0 tpct TP0 tpct TP0 tpct TP09 tpct TP0 tpct TP tpct TP tpct TP R9.9_F 00 /:dd net LN_RXN LN_RXP LN_TXN LN_TXP;add W MI0RXN W MI0RXP MIRXN MIRXP MIRXN MIRXP F MIRXN MIRXP V0 MI0TXN V9 MI0TXP Y0 MITXN Y9 MITXP 0 MITXN 9 MITXP 9 MITXN 0 MITXP U MI_LKN U MIOMP MI_LKP F MI_IROMP F0 MI_ZOMP 9 0.U_V_M PRn/LN_RXN 0 LN_TXN_ PRp/LN_RXP LN_TXP_ PTn/LN_TXN 0.U_V_M PTp/LN_TXP P0 0.U_V_M PRn P9 MINI_TXN_ PRp R MINI_TXP_ PTn R 0.U_V_M PTp M0 TV_0.U_V_M PRn M9 0 TV_TXN_ PRp N 0 TV_TXP_ PTn N TP_PRN TV_0.U_V_M PTp K0 TP_PRP PRn K9 TP_PTN PRp L TP_PTP PTn L TP_PRN PTp H0 TP_PRP PRn H9 TP_PTN PRp J TP_PTP PTn J TP_PRN PTp F0 TP_PRP PRn F9 TP_PTN PRp TP_PTP PTn PTp IH0 MI PI- U OF UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP TP_UPN TP_UPP UPN UPP UPN UPP UPN UPP UP9N UP9P TP_UP0P TP_UPN TP_UPP U_O#0 U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# IO_RII#_R R 00 IO_RII# U_O# U_O# U_O#9 U_O#0 U_O# URI_IH K_M_U_IH UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP TP9 tpct TP9 tpct UPN UPP UPN UPP UPN UPP UP9N UP9P TP tpct TP tpct TP tpct ide U X Rear U X Felica IR amera lue Tooth 0/0:elete TP for layout VT:0/0: hange R_PR# from O#/PIO to PIO R 00._F K_M_U_IH /:Place IO_RII# at the side /0 change IO_RT# to PIO0 and N Pull up R VRUN PI_FRM# PI_TOP# PI_RR# PI_TRY# 9 0.K 0_0PR 0_0PR.K RP PIO PIO PIO PI Pull up VRUN VRUN PI_VL# PI_LOK# PI_PRR# PI_IRY# VT:0/0:hange R99 from 0K to 0K _FLH_N# IO_RII# VRUN R99 0K_J 00 VT:0/0:dd R PJ OPN_JUMP_OPN VRUN R 0K_J VT:0/:Remove IP_W from PIO to PIO M_FLH_N VT:0/:dd this portion VT:0/0:dd R. VLW RP U_O# U_O# IO_RII#_R U_O# VLW.K 0_0PR 0 9 VLW U_O# U_O#9 U_O#0 U_O# RP9 U_O#0 U_O# U_O# U_O#.K 00_PR VT:0/:hange the circuit for U power switch change to MO and cost down. UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP9N UP9P UP0N UP0P UPN UPP O0#/PIO9 O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO9 O#/PIO0 O#/PIO O#/PIO O9#/PIO O0#/PIO O#/PIO URI# URI LK Y Y Y Y V V W W V V P N P R N N N M P R T P 0_0PR.K INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# 9 VRUN 0 RP Q N00PT /:change the pad style VT:0/:elete R put the pad near the IMM door. short the pad, IO will perform crisis recovery. FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH0 (PIe/U/PI) / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

18 V_F_VTT PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. R0 _F 00 VLW VRUN 9 IH_M_UY H_FRR# 0K_J POWR_L# R R IH_M_UY_R N_0K_J R HW_POP_MUT_IH N_0K_J R 0K_J 00 R 0K_J R 0K_J 00 R 0K_J 00 R 00 0K_J Layout note: place these ap close to IH0 ball. 00P_V_K 00_XR R 0K_J R N_0K_J 00P_V_K 00_XR VRUN PIO9 _RIN# _0T _T FN_TH_R FN_TH_R FN_TH_R FN_TH_R FN_TH_R FN_TH_R R 0K_J 00 Q N00PT N_ R 00 00P_V_K 00_XR VT:0/:Remove WLN_N# to PIO HW_POP_MUT_IH T_ON VT:0/0:dd R. PU_TLRF_TRL IH_M_UY_R H_0M# H_FRR# H_INN# H_INIT# H_INTR H_NMI H_MI# H_TPLK# VT:00: Reserve pull up for HW_POP_MUT_IH H_PUPWR H_PLP# VT:00: add pull up for PIO9 tpct TP H_L_LK0 H_L_T0 H_L_RT0# VT:0/: tuff R0,R0 FN_PWM FN_PWM FN_PWM FN_TH FN_TH FN_TH _T H_PI VT:0/0:Remove L_OFF# VT:0/:hange PIO to T_ON POWR_L# tpct TP0 WLN_T_W# PVT:0/0:dd PU_TLRF_TRL for adding TLRF voltage control circuit PVT:0/0:dd Q R and N R for /VRUN leakage. U J 0M# J FRR# INN# INIT# H INTR F NMI H MI# J9 _RIN# TPLK# L _0T RIN# P 0T PUPWR TP_INIT_V# PLP# M INIT_V# L_VRF_IH IH_M_UY_R L_LK0 H L_T0 0 L_RT0# L_VRF0 R0 00 FN_PWM_R J R0 FN_PWM_R PWM0 00 J R0 FN_PWM_R PWM 00 K R0 FN_TH_R PWM 00 H R0 FN_TH_R TH0/PIO 00 K R0 00 FN_TH_R TH/PIO H Y_I TH/PIO K R IH_T TH/PIO 9 00 IH_PI T R 00 PI tpct TP tpct TP POWR_L# F PIO9 PIO J TP_PIO PIO9 H FLH_TRP_ PIO F TP_PIO PIO K PIO _T_ON PIO R 00 PIO F TP_PIO PIO0 K PIO 9 PIO HOT OF L T IQT PIO T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP T_LKN T_LKP TL# TRI# TRI T0P/PIO TP/PIO9 TP/PIO TP/PIO TP TP TLKRQ#/PIO LOK/PIO 9 PIO/JTTI/QT_MUY# LO/PIO TOUT0/PIO9 TOUT/PIO VT:00: hange the T Port to port for MOR request K J K9 J9 J TP_TRXN K TP_TRXP H TP_TTXN F TP_TTXP J K H F J TP_TRXN K TP_TRXP F TP_TTXN H TP_TTXP J9 TP_TRXN K9 TP_TRXP F0 H9 TP_TTXP J TP_TRXN K TP_TRXP F TP_TTXN H TP_TTXP F F9 K TRI.9_F J R0 00 K PNL_I PNL_I 0 PIO9 PNL_I0, VRUN Y_I PNL_I0 TP R 0K_J TP R 0K_J L J K H 0 Y_I0 Y_I Y_I Y_I T_RXN0 0 T_RXP0 0 H T_TXN0 0 T_TXP0 0 TP9 tpct TP0 tpct TP tpct TP tpct T_RXN 0 T_RXP 0 O T_TXN 0 T_TXP 0 TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct TP tpct T_LKN T_LKP 00: elete TP0 TL# for layout request T_LKRQ# VRUN R N_ 00 _V_L R 00 R.K_F 00 R _F 00 VT:0/0:onnect L_VRF_IH from VRUN to _V_L for orwin pring VT 0/ Mount R and no mount R to support Wake up on Intel LN 0.0V L_VRF_IH 0.U_V_Y 00_YV /:dd N N HR_P FOX_H0 VRUN R0.K_J 00 FLH_TRP_ IH0 Projet name Y_I Y_I Y_I Y_I0 M0 M0 M0 M0 Model name Y_I Y_I H M L VRUN R0 N_0K_J Y_I0 R09 N_0K_J R00 N_0K_J R0 N_0K_J Y_I Y_I Y_I R NV_0K_J Y_I R _0K_J Y_I R 0K_J PNL_I R 0K_J PIO9 /:dd R R R0 0K_J R0 0K_J R0 0K_J R0 0K_J Y_I0 Y_I Y_I Y_I R _0K_J Y_I R NV_0K_J Y_I PVT:0/09:hange R from.k to.k for system voltage fail. PVT:0/:hange the R back to.k. Panel Type PNL_I0 P 0 P 0 P P VT:0/0:NV R,R for M0 H; R,R for M0 L PNL_I 0 0 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH0 (HOT/T) / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet of 0

19 VLW 00_NPO 9 N_P_0V_J VLW VRUN R 0K_J R K_J 00 R 0K_J R9 0K_J 00 R 0K_J 00 R 0K_J LP_M 00_NPO 9 N_P_0V_J M_THRM_LK M_THRM_T 00_NPO 9 N_P_0V_J VLW _RI# _WK# _TP0 MLINK0 MLINK IR_WK# IH_U_IN0 IH_U_OUT IH_U_YN IH_U_RT# VT:0/:hange R & R9&R from.k to 0k following IO-&IO- R 0K_J 00 _Y_RT# VT:0/:elete R R 0K_J 00 R 0K_J 00 R9 N_0K_J 00 R9.K_J 00 R0.K_J 00 R 00_NPO 9 R _K_J 00 Q N00PT N_P_0V_J 0K_J Q0 LP_0 LP_ LP_ LP_ LP_RQ#0 TP_PIO LP_FRM# R IH_U_LK _J 00 IH_U_IN0 tpct TP9 TP_H_IN PVT:0/:ack up 9 tpct TP TP_H_IN 9 9 and 9 for MI tpct TP TP_H_IN R IH_U_OUT _J 00 R _J 00 IH_U_YN R _J 00, IH_U_RT# K_M_IH PU_TLRF_TRL T_PR# PIO M_THRM_LK M_THRM_T LP_0 LP_ LP_ LP_ LP_RQ#0 tpct TP LP_FRM# IH_LN_RTYN IH_LN_RX0 IH_LN_RX IH_LN_RX IH_LN_TX0 IH_LN_TX IH_LN_TX LN_IL# IH_LN_LK V_P_IH _RTRT# _RTRT M_THRM_LK M_THRM_T WLN_N# IH_M_UY VT:0/:hange PIO to WLN_N#. _TP00K-T- R _K_J 00 Q N00PT VRUN VT:0/0:elete I_LK and add TP R N_K_J 00 VRT R 00 PU_TLRF_TRL Q WOL_N IR_WK# T_PR# VRUN R K_J 00 N00PT K FWH0/L0 PLTRT# H FWH/L THRM# M FWH/L THRMTRIP# J FWH/L LP_# L LRQ0# LP_# J LRQ#/PIO LP_#/PIO L FWH/LFRM# LP_M# _TT#/PIO PWROK H H_IT_LK PWRTN# K H_IN0 RI# H H_IN Y_RT# H H_IN RMRT# J H_IN LN_RT# J H_OUT WK# K H_YN MH_YN# J H_RT# VRMPWR M LK LPWROK PRTP# K_PWR LN_RTYN LN_RX0 H LN_RX U_TT#/LPP/PIO LN_RX ULK/PIO F LN_TX0 RMPWROK/PIO F LN_TX PIO0 R 00 PIO_IH LN_TX TP_PI#/PIO PIO TP_PU#/PIO F LN_LK PIO/PRLPVR 9 LN_OMP LN_OMPO R _F LN_OMPI INTVRMN IH_RTX LN00_LP IH_RTX RTX PKR _RTRT# RTX PIO/TP0 _RTRT RTRT# TP H0 RTRT# TP TP M_THRM_LK TP H M_THRM_T MLK TP WLN_N# MT MLRT#/PIO/JTTO PI_LK MLINK0 PI_MIO MLINK MLINK0 PI_MOI M_J INTRUR# MLINK PI_0# INTRUR# PI_#/PIO F PIO LINKLRT#/PIO0/JTRT# PIO IR_WK# PIO9 T_PR# PIO0/PU_MIIN/JTTM PIO/TPM_PP/JTTK VT:0/:hange PIO9 from WLN_N# to WOL_N of PVT:0/0:dd PU_TLRF_TRL for adding TLRF voltage control circuit VT:0/:dd R R. VRUN VT:0/: dd this circuit for corwin spring,efault not Q support. N00PT R R 0K_J 0K_J U IH0 M/MI RT LN UIO LP PI MI PM VT:0/: support corwin spring need N K F T 9 F9 F 0 H T K T R R 0 N M N F0 9 F _THRMTRIP# _LP_# _LP_# _LP_# _LP_M# UPN_L# _PWROK PWRW_R# _RI# _RMRT# _LN_RT# _WK# H_MH_YN# _VRMPWR L_PWROK _PRTP# _K_PWR PM_U_TT# IH_M_UY _TP_PI# _TP_PU# TP_INV_NL _INTVRMN _LN00_LP H_PKR _TP0 _TP _TP _TP _TP _TP WOL_N _PI_LK_R PI_MIO_R _PI_MOI _PI_0# PI_# VLW R _0K_J R N_00K_J 00 R _F 00 R _F R 00 _F 00 TP tpct R0 0K_J R 0K_J TP tpct TP90 tpct TP9 tpct TP9 tpct TP9 tpct TP9 tpct _THRM# _LP_#, _LP_# _LP_# UPN_L# _PWROK, PWRW_R# PLT_RT#,,,,9,0 _Y_RT#, _RMRT# _LN_RT# _WK#, H_MH_YN# _VRMPWR L_PWROK, _PRTP#, _K_PWR PM_U_TT# WLN_T_OFF IH_M_UY _TP_PI# _TP_PU# VRT VRT H_PKR To udio, internal pull low for reboot enable. PI_LK_R PI_MIO_R PI_MOI_R PI_0# R PI_# N_K_J 00 V_F_VTT 00:dd /0: dd R pull down PI_#, and N it. internal pull up VT:dd this circuit for orwin spring, support stuff R R _F 00 R 00 0.U_V_Y 00_YV PVT:0/0:hange _VRUN to _VRUN by Intel's suggestion. H_THRMTRIP# VT:0/0:hange UPN_L to UPN_L# VT:0/0: hange IH_RMRT# to _RMRT# 0/0:elete TP0 for layout VT:0/0:onnect WLN_T_OFF to PIO VT:0/:onnect WLN_T_OFF to PIO VT:0/:elete the net 'INV_NL', and add a TP 00'00:elete PROM U for cost down.io will use other methodology to store those ystem Information in PI Flash ROM instead of PROM,, M_THRM_T_Q M_THRM_T_V,, M_THRM_LK_Q M_THRM_LK_V VT:0/: elete R,R and add R,Q for layout routing issue VLW R PVT:0/0:hange the from pf to pf, from pf to pf. VT:0/0:hange, from PF to PF VT:0/0:hange Y from F-XM-000 to F-XK-000,the same as M0. P_0V_J 00_NPO P_0V_J 00_NPO Y.KHZ_.P_0PPM QM00000 R99 IH_RTX R 0M_J 00 IH_RTX 00 VT:0/:hange R99 from R. and Y., to R. and Y., VT:0/:hange the Q9 to MO _LP_M# R _0K_J 00 _ 00 VT:0/:dd this circuit for corwin spring 0 _U_.V_M 00_XR Q9 _N00PT LP_M,, FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH0 (PM/LN/H) / ize ocument Number Rev IO- Mother oard MP. ate: Tuesday, July, 00 heet 9 of 0