Title of Schematics Page ICH8-M( GND) 5/5 SATA HDD/CD-ROM EC+KBC Flash ROM/XBUS
|
|
- Ê Παπανικολάου
- 6 χρόνια πριν
- Προβολές:
Transcript
1 Page of chematics Page chematics Page Index lock iagram Merom(HOT U) / Merom(HOT U) / Merom(Power/nd) / LOK N restline (HOT) / restline (MI) / restline (RPHI) / restline (RII) / restline (POWR,V) / restline (V OR) / restline (V) / RII(O-IMM_0) / RII(O-IMM_) / RII(Termination) / V(PI-) V(TRP) V(R)# V(MULTIU) V(LV/V ) VRM(R)# / VRM(R)# / V(POWR) / V(POWR) / V(POWR) / VRM(YP) / VRM(YP) / TVIN and OUT/emi-PnP# RT LV IH-M( PI/U ) / IH-M( LP,I,T )/ IH-M( PIO) / IH-M( POWR) / chematics Page Index ( / Revision / hange ate) Rev. ate Page. 0'0'.0 0'0'0. 0'0'.0 0'0'0. 0'0' 0. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'.0 0'0' '0'0. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0' 0. 0'0'.0 0'0'0.0 0'0'0. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0'. 0'0' 0 of chematics Page Rev. ate IH-M( N) /. 0'0' T H/-ROM. 0'0' +K. 0'0' Flash ROM/XU.0 0'0'0 Mini-PI ard. 0'0' luetooth/m/oi. 0'0' XPR. 0'0' T to udio/m. 0'0' FN/Thermal-ensor. 0'0' PI (PI U). 0'0' PI (i.link). 0'0' PI (/M-UO).0 0'0'0 U.0.0 0'0'0 LN (0).0 0'0'0 Power esign iagram.0 0'0'0 IN&harger. 0'0' Y Power (+_V/+V). 0'0' Y Power(+_V/+_0V). 0'0' R Power(+_V/+0_V). 0'0' PU_Vcore---IL. 0'0' Others power plane.0 0'0'0 OVP protection.0 0'0'0 V POWR(+_V/ +_V). 0'0' MH power.0 0'0'0 HOL. 0'0' +K().0 0'0'0 HMI. 0'0' ROON to onnector..0 0'0'0 L/Touch/Lid. 0'0' History ( ).0 0'0'0 History ( ).0 0'0'0 History ( ).0 0'0'0 History ( ).0 0'0'0 History ( ).0 0'0'0 History ( ).0 0'0'0 History ( ). 0'0' History ( ). 0'0' P. Leader heck by esign by Project ode & chematics ubject: M0 Main oard P P/N: P (FUI) P (HNNTR) P (NN Y) FOXONN Index Page HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Wednesday, March, 00 heet of
2 -OUT P LV X+ P V -type-p P 0 HMI P INTRNL Mic MI oard M0(restline PM/M+fx lock iagram) -OUT/LV/V/HMI udio & U oard Int. peaker.0 Walt x P RJ M/M UO / P xt. Mic In Jack H PHON JK M. Modem pin P nvii NM R Mxbxpcs P ~ -OUT/LV/V U.0 ONN.X TP0 TI PI0ZHK ardreader i.link PI X U.0 XK odec MHZ,.V PI U ZLI PI PU Merom Processor Micro-F- ( -pin socket P) P ~ North ridge restline PM/M F- P ~ -Link0 outh ridge IH-M m P ~ F /00 MHZ X MI (irect Media Interface) LP MHZ MHZ U.0 PI + U.0 -Link PI U.0 lock en. ILPRYLFT MLF P O-IMM 0 MHZ R(II) 00 pin P O-IMM MHZ R(II) 00 pin P X,TL.MHZ U.0 ONN.X P xpress ard P Mini-ard PI P 0 Robson ONN i.link P RJ HK P ~ Netswap N0P Marvell 0/00 thernet 0 QFN- P PWM N K0F +K +K(co-lay) LQFP- - P P XU M hannel I T 00 PT O P T.b/s T H P P M(0.M) P luetooth P Oide P OM configuration ymbol ahead of value for N components witch oard witch oard FN P Lid witch & L Touchpad P/ Flash IO M P P P M hannel TT ONN. P Thermal ensor -Pf (PU/MH) MOP- P Thermal ensor Pf (V) MOP P Thermal ensor MX0HUK-T+ (H/W) OT- P OTH PM+NM M/ML N NV_ FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision lock iagram ize ocument Number Rev ustom M ate: Tuesday, March, 00 heet of
3 Layout note: no stub on H_TPLK TP. H_TPLK# to be routed in daisy chain fashion from IH to LP slot and then to PU. H_#[..] H_T#0 H_RQ#[..0] H_#[..] H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# R 0_J 00 TP 0MIL TP 0MIL TP0 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP0 0MIL TP 0MIL H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_TPLK#_R TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 TP_PU_RV0 U0 J []# L []# L []# K []# M []# N []# J N P P L P P R M K H K J L Y U R W U Y U R T T W W Y U V W V []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# R ROUP 0 T[0]# RQ[0]# RQ[]# RQ[]# RQ[]# RQ[]# R ROUP [0]# []# []# []# []# []# T[]# 0M# FRR# INN# TPLK# LINT0 LINT MI# M RV[0] N RV[0] T RV[0] V RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] F RV[0] IH RRV XP/ITP INL ONTROL # H NR# PRI# FR# H RY# F Y# PM[0]# PM[]# PM[]# PM[]# THRML H LK R0# LK[0] LK[] F IRR# 0 INIT# LOK# RT# R[0]# R[]# R[]# TRY# HIT# HITM# PRY# PRQ# TK TI TO TM TRT# R# PROHOT# THRM THRM THRMTRIP# H F F 0 H_IRR# H_R#0 H_R# H_R# XP_PM#0 XP_PM# XP_PM# XP_PM# XP_PM# XP_PM# XP_TK XP_TI XP_TM XP_TRT# 00 PROHOT# H_THRM H_THRM PM_THRMTRIP# +_0VRUN R _J 00 XP_TRT# +_0VRUN R 0_J 00 H_TRY# XP_TI H_HIT# R _ 00 H_HITM# XP_TM 0MIL TP R N_._F 00 0MIL TP XP_PM# 0MIL TP 0MIL TP 0MIL TP R _J 00 XP_TK 0MIL TP H_THRM H_THRM H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_RQ#0 H_INIT# H_LOK# H_PURT# H_R#[..0] PM_THRMTRIP# LK_PU_LK LK_PU_LK# R0 _F 00 ebug port not used. resistors close to PU. PM_THRMTRIP# should connect to IH-M and MH without T-ing (No stub) PU OKT_P FOX_PZ-M-0,,,, OVT_# OVT_# Q +VRUN R.K_J TU +_0VRUN R K_F 00 Q0 N00 PROHOT# IHM's PIO: VIL---> -0.V ~ 0.V VIH--->.0V ~.+0.V MROM's PROHOT#: VIL---> -0.V ~ 0.*VP VIH---> 0.*VP ~ VP+0.,,,,,,,0,,,, PLT_RT# +_0VRUN Q R.K_J MMT0 00 PM_THRMTRIP# Q N00 00 N_-0LM-XT N N_0P_0V_K 00_XR V V OUT U R0 N_0_J 00 +V When use U, R0 and need change to N. R K_J 00 0.U_V_M_ 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision Merom(HOT U) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of RT#,
4 Place close to PU +_0VRUN R K_F 00 R K_F 00 Layout Note: Zo= ohm, 0." max for TLRF. H_#[..0] H_TN#0 H_TP#0 H_INV#0 H_#[..0] H_TN# H_TP# H_INV# PU_L0 PU_L PU_L Place close to the PU_TT pin. Make sure PU_TT routing is reference to N and away from other noisy signals. R N_K_J 00 R N_K_J 00 0MIL TP 00_XR 0MIL TP N_0.U_0V_K 0MIL TP0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TLRF PU_TT PU_TT PU_TT PU_TT PU_TT PU_TT U0 [0]# F []# []# []# F []# []# []# []# K []# J J H F K H N K P R L M L M P P P T R L []# [0]# []# []# []# []# []# J TN[0]# H TP[0]# H INV[0]# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# T [0]# N []# L TN[]# M TP[]# N INV[]# TLRF TT TT TT F TT F TT TT L[0] L[] L[] T RP T RP 0 MI T RP T RP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# []# []# [0]# []# []# []# OMP[0] OMP[] OMP[] OMP[] Y V V V T U U Y W Y W W TN[]# Y TP[]# INV[]# U 0 F F TN[]# TP[]# F INV[]# 0 PRTP# PLP# PWR# R U Y PWROO LP# PI# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# OMP0 OMP OMP OMP R0._F 00 R._F 00 R._F 00 R._F 00 H_PRTP#,, H_PLP# PU OKT_P FOX_PZ-M-0 Layout Note: omp0, connect with Zo=. ohm, make trace length shorter then 0.". omp, connect with Zo= ohm, make trace length shorter then 0.". H_#[..0] H_TN# H_TP# H_INV# H_#[..0] H_TN# H_TP# H_INV# Layout: onnect test point with no stub TP 0MIL H_PWR# H_PWR H_PULP# PI# IMVP (ILRZ-T) cpu PI# <-> ILRZ-T PI# ILRZ-T: VIHmin=0.V VILmax=0.V (ref. IMVP- NO:0) FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision Merom (HOT U) / ize ocument Number Rev M ate: Tuesday, March, 00 heet of
5 U_.V_M_ 00 U_.V_M_ 00 VHOR VHOR VHOR VHOR VHOR VHOR VHOR VHOR VHOR VHOR N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ U_.V_M_ 00 U_.V_M_ 00 0 N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ N_U_.V_M_ 00 N_0.U_V_M_ 00 U_.V_M_ 00 0 U_.V_M_ 00 U_.V_M_ 00 0 U_.V_M_ 00 0 N_U_.V_M_ 00 N_0.U_V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 N_0.U_V_M_ U_.V_M_ 00 U_.V_M_ U_.V_M_ 00 U_.V_M_ 00 N_0.U_V_M_ U_.V_M_ 00 U_.V_M_ U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 U_.V_M_ 00 N_0.U_V_M_ F F F0 F F F F F F U0 V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[0] VP[] VP[] VP[] VP[] VP[] VP[] PU OKT_P FOX_PZ-M F F0 F F F F F F0 V J K M J K M N N R R T T V W V[0] V[0] VI[0] VI[] VI[] VI[] VI[] VI[] VI[] VN VN F F F F VHOR H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI R 0_J 00 R0 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 R 0_J 00 VN VN ame Length PU_V---->0m PU_VP----->. PU_V------> P + 0U_V_ FL0Y 0.U_V_M_ 0.U_V_M_ U_.V_Y 00_YV Layout Note: Route VN & VN traces at. Ohms with 0 mil spacing. Place PU and P within inch of PU. width= mil spacing= mil TP0 tpc0t_0 TP tpc0t_0 TP tpc0t_0 TP tpc0t_0 TP tpc0t_0 TP tpc0t_0 TP tpc0t_0 0.0U_V_M_ 00 H_VI0 H_VI H_VI H_VI H_VI H_VI H_VI 0.U_V_M_ 00 +_VRUN VI0 VHOR VI VI VI VI R VI VI 00_F 00 R 00_F 00 0.U_V_M_ 00 0 mil LYOUT NOT: Place 0.0uF near PIN VN VN 00 mil 0.U_V_M_ 00 0.U_V_M_ 00 PU & P avoid to route with stub +_0VRUN U0 V[00] V[00] V[00] V[00] V[00] V[00] V[00] F V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[0] F V[00] F V[0] F V[0] V[0] V[0] V[0] V[0] H V[0] H V[0] H V[0] H V[00] J V[0] J V[0] J V[0] J V[0] K V[0] K V[0] K V[0] K V[0] L V[0] L V[00] L V[0] L V[0] M V[0] M V[0] M V[0] M V[0] N V[0] N V[0] N V[0] N V[00] P V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] PU OKT_P FOX_PZ-M-0 P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F 000P_0V_K_ P_0V_K_ P_0V_K_ P_0V_K_ P_0V_K_ 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision Merom (POWR/ROUN) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
6 VOUT_LK +_VRUN H0KF-T0 R 0_J 00 L 0R-00MHZ_00 R N_0_J 00 R0 N J 00 Q 00 N_00P_0V_K_N N_ If LP0, populate R,R0,,Q and depopulate R. Ig LP0, populate R and depopulate R,R0,,Q. H0KF-T0 L 0R-00MHZ_00 H0KF-T0 L 0R-00MHZ_00 H0KF-T0 L 0R-00MHZ_00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR VP0 VP0 VP0 VP0 +V_LK_F +V_LK_ +V_LK_ +V_LK_ +V_LK_ +V_LK_ +VRUN +V_LK_ 0.0U_V_K_ 00 +V_LK_ +V_LK_F H0KF-T0 L 0R-00MHZ_00 0.0U_V_K_ U_V_K_ 00 R 00 _F U_V_K_ 00 R 00 _F U_V_K_ 00 R 00 _F U_V_K_ 00 R 00 _F R 00 _F R 00 _F 0U_.V_M 00_XR 0.0U_V_K_ 00 +V_LK_ 0.0U_V_K_ U_V_K_ 00 U_V_K_ 00 +V_LK_ +V_LK_ U_V_K_ 00 0 U_V_K_ 00 Length as short as possible. LK_ LK_U PLK_ ual mode of PI clock (pin,,,) PLK_FWH should link to PLK_JI +VRUN on-board device., LK_KPI +VRUN LK_U N_0P_0V N 00 LK_KPI N_0P_0V N 00 PLK_ N_0P_0V N 00 PLK_FWH N_0P_0V N 00 LK_IHPI N_0P_0V N 0 00 LK_IH N_0P_0V N 00 PLK_JI N_0P_0V N 00 PU_L0 PU_L LK_IHPI,,, M_LK_U,,, M_T_U LK_PI_IH# LK_PI_IH Y ITTI_L MHZ_0P_0PPM VP0 VP0 VP0 0 VP0 P_0V_J P_0V_J 00_NPO 00_NPO R _J 00 R _J 00 R.K_J 00 R 0_J 00 U_XTLIN U_XTLOUT LP0_LK R_PU_L R 0K_J 00 VOUT_LK R0 _J 00R_LK_IHPI R _J 00R_PLK_ R0 _J 00 R _J 00R_PLK_JI R 0K_J 00 R _J 00R_LK_KPI R0 NV_0K_J 00 R _0K_J 00 RP 00_PR R_LK_PI_IH# R_LK_PI_IH R_RFLK_OR_M R_RFLK#_OR_M_ U V_IO VPU_IO 0 VPLL_IO VR_IO VR_IO VR_IO 0 X X PI PI/TM PI/_elect N N NR NR NR N NPU NPI NRF 0 FL/U_MHZ FL/TT_MO N PI_F/ITP_N LK T R/R#_ RT/R#_ ILPRLFT null VPU VR VRF VPI V VPLL RT//MHZ_nonss R//MHZ_ M bus ddress : 000x(HX:) (IHM) For clock generator PI_TOP# PU_TOP# PUT_F PU_F PUT0 PU0 RT/PUT_ITP R/PU_ITP RT/R#_F RT R RP 00_PR R_LK_MH_LK 0R_LK_MH_LK# RP 00_PR R_LK_PU_LK R_LK_PU_LK# RP N_ 00_PR R_LK_PI_ROON# R_LK_PI_ROON ROON_T#_L R _F 00 ROON_T# RP 00_PR 0 R_LK_MH_PLL R_LK_MH_PLL# MH_LK_RQ#_R R0 MH_LK_RQ# R/R# F 00 RP0 00_PR R_LK_LN RT 0 R_LK_LN# R LK_PI_LN R0 LK_PI_LN# PI_LN_LKRQ# _F 00 R/R#_ RP 00_PR R_LK_PI_MINI RT LK_PI_MINI 0 R_LK_PI_MINI# R LK_PI_MINI# 0 MINI_R_T#_L R MINI_R_T# PI/R# F 00 RP 00_PR R_LK_PI_XP# R0 LK_PI_XPR# R_LK_PI_XP RT0 LK_PI_XPR XPR_T#_LR XPR_T# RT/R#_H _F 00 RP 00_PR R_LK_PI_T RT/TT LK_PI_T R_LK_PI_T# R/T LK_PI_T# R _F TLKRQ#_R 00 TLKRQ# PI0/R#_ RT0/OTT_ R0/OT_ OT_OR_R0 OT#_OR_R0# K_PWR/P# R_LK_IH FL/RF0/TT_L R _F 00 PU_L R 0K_J 00 PM_TPPI# TP_PU# LK_MH_LK LK_MH_LK# LK_PU_LK LK_PU_LK# LK_PI_ROON# LK_PI_ROON LK_MH_PLL LK_MH_PLL# LK_PWR LK_IH RP,RP close to LK N. +VRUN +VRUN XPR_T# elete(for docking) ROON_T# R0 0K_J 00 +VRUN +VRUN +VRUN MINI_R_T# MH_LK_RQ# TLKRQ# R 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 heck LKRQ with internal pull-up resistor or not. efault stuff Pull-up Resistor. XPR_T# ROON_T# MINI_R_T# 0 MH_LK_RQ# TLKRQ# close to clk gen (For MI) F Frequency Table: PU_L0 R FL FL FL PU R[:0] PI R PU_L PU_L R R R R 0_J 00 N_0_J 00 0_J 00 N_0_J 00 0_J 00 N_0_J 00 MH_L0 MH_L MH_L OT_OR_R0 OT#_OR_R0# RP _ 00_PR RFLK RFLK# LK_PI_P LK_PI_P# RP0 NV_ 00_PR R_RFLK_OR_M R_RFLK#_OR_M_ RP0 00_PR _ R0 NV J 00 R0 NV J 00 FOXONN RFLK RFLK# R_NV_XTLIN 0 R_XTLIN 0 HON HI Precision Ind. o., Ltd. P - R& ivision LOK N ize ocument Number Rev M0--0. ate: Wednesday, March, 00 heet of
7 +_0VRUN +_0VRUN +_0VRUN R _F 00 R 00_F 00 R._F 00 R._F 00 R._F 00 W/ = 0/0mil H_WIN 0.U_V_M_ 00 W/ = 0/0mil H_ROMP H_OMP H_OMP# +_0VRUN R K_F 00 H_#[..0] H_#[..0] H_PURT# H_PULP# Place ap. near MH within 00 mils. H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_OMP H_OMP# H_PURT# H_PULP# H_VRF M H H F N H M0 N N H P K M W0 Y V M J N N W W N Y Y P W N Y J H J H J H J J J J H H U H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP W H_OMP W H_OMP# H_PURT# H_PULP# H_VRF H_VRF restline MH-QP0 0 mil HOT H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_T#0 H_T# H_NR# H_PRI# H_RQ# H_FR# H_Y# HPLL_LK HPLL_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# J M F L K L J K P R H0 L M N J N H 0 F 0 M M H K 0 K L M K H L K J0 H_RQ#0 M H_RQ# H_RQ# H_RQ# H H_RQ# H_R#0 H_R# H_R# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] R K_F 00 0.U_0V_K 00_XR R 0_J 00 H_VRF FOXONN restline (HOT) / HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
8 ,, R_LRT#, PRLPVR N_0P_0V_J_N 00 N_0K_F R +_VU R N_0K_F VU U R 00 N_LMIMX RIMM_VRF R 0_J 00 0.U_V_M_ 00 MR_VRF MH_RV_0 TP 0MIL MH_RV_ TP 0MIL MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ TP 0MIL MH_RV_ TP 0MIL MH_RV_ MH_RV_ MH_RV_0 MH_RV_ M, M M, M MH_RV_ TP 0MIL MH_RV_ TP 0MIL MH_RV_ TP0 0MIL M_O_RXIN- M_O_RXIN+ MH_RV_ MH_RV_0 MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_RV_ MH_L0 MH_L MH_L MH_F_ MH_F_ MH_F_ TP 0MIL MH_F_ MH_F_ TP 0MIL MH_F_ TP 0MIL MH_F_0 MH_F_ MH_F_ (PI Low = Reverse Lane MH_F_ MH_F_ raphics High = Normal MH_F_ Lane) operation MH_F_ For layout convenience TP 0MIL MH_F_ +VRUN TP 0MIL TP0 0MIL R0 0K_J 00 TP 0MIL PM_XTT#0 R0 0K_J 00 PM_XTT# PM_MUY# R 0_J 00,, H_PRTP# PM_XTT#0 PM_XTT#0 PM_XTT#0 PM_XTT# PM_XTT#, IMVP_PWR R0 00_F 00PLTRT#_R,,,,,,,0,,,, PLT_RT# R0 0_J 00THRMTRIP#_R PM_THRMTRIP# PRLPVR N_0.U_V_Y_Y 00 N_0_J 00 N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ J0 K F H0 K J F J H W0 K0 restline MH-QP0 0.U_V_M_ 00 H0 N0 U MH_RV_ P MH_RV_ RV P MH_RV_ RV M_K0 V M_LK_R0 R MH_RV_ RV M_K M_LK_R TP 0MIL N MH_RV_ RV M_K M_LK_R R +_VU MH_RV_ RV M_K V M_LK_R R MH_RV_ RV M W0 MH_RV_ RV M_K#0 M_LK_R#0 TP 0MIL N R MH_RV_ RV M_K# M_LK_R# TP 0MIL J W MH_RV_0 RV M_K# M_LK_R# TP 0MIL R W K_F MH_RV_ RV0 M_K# M_LK_R# M MH_RV_ RV 00 L M_ROMP_VOH MH_RV_ RV M_K0 M_K0, TP 0MIL M Y MH_RV_ RV M_K M_K, TP 0MIL 0 RV M_K M_K, M_K R 0.0U_V_K_.U_0V_Y M_K, 00 00_YV RV0 RV RV RV RV RV RV RV RV RV RV0 RV _M _M RV RV RV LV_T# LV_T RV RV0 RV RV RV RV RV P F0 N F N F F F F F N F F J0 F 0 F R F0 L F J F F 0 F K F M0 F M F L F N F L F0 F[:] internal pull-up F[0:] internal pull-down PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# THRMTRIP# PRLPVR J N K N K0 N L0 N L N L N L N K N J N N0 N N 0 N 0 N N K N RV R MUXIN LK F MI RPHI VI PM M N MI M_#0 M_# M_# M_# M_OT0 M_OT M_OT M_OT M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF0 M_VRF PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF 0 K H J J L K K L R W H H K K N J N N M J N N J J M0 M J J M M M K0 T N M0 VO_TRL_LK H VO_TRL_T K LKRQ# IH_YN# 0 TT TT R M_ROMP# M_ROMP M_ROMP_VOH M_ROMP_VOL MR_VRF MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MH_LVRF R NV_0_J 00 R0 NV_0_J 00 MH_LK_RQ# MH_TT_ MH_TT_ M_OT0, M_OT, M_OT, M_OT, R0 0_F 00 +_VU R0 0_F 00 R 0K_J 00 M_#0, M_#, M_#, M_#, RFLK RFLK# RFLK RFLK# LK_MH_PLL LK_MH_PLL# FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision R restline (MI) / 0_J 00 ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of.0k_f 00 R K_F 00 MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] FT_VI_0 FT_VI_ FT_VI_ FT_VI_ FT_VR_N, L_LK0 L_T0 MPWROK L_RT#0 MH_LK_RQ# MH_IH_YN# R NV_0_J 00 R NV_0_J 00 R NV_0_J 00 R NV_0_J 00 M_ROMP_VOL RFLK# RFLK RFLK# RFLK R N_.K_J 00 RFLK +_VRUN RFLK# R0 N_.K_J 00 +_VRUN 0 0.U_0V_K 00_XR PR K_F 00 R _F U_V_K_ 00.U_0V_Y 00_YV
9 +VRUN +_0VRUN R0 NV_0_J 00 R _0K_J 00 R NV_0_J 00 R0 _0K_J 00 R _.K_J 00 R NV_0_J 00 R NV_0_J 00 R _.K_J 00 M_O_RXIN0- M_O_RXIN- M_O_RXIN- M_O_LKIN- M_O_LKIN+ M_O_RXIN0+ M_O_RXIN+ M_O_RXIN+ M_ M_ VRUN 0 M_LK R NV_0_J 00 0 M_T 0 M_HYN 0 M_LU M_RN M_R M_VYN N_RJ M_INV_N M_LV_N R.K_F 00 L_TRL_LK L_TRL_T L LK L T LV_I LV_V MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP M_ M_ M_ +VRUN TV_IRTN TV_IRTN TV_IRTN R _.K_J 00 R _.K_J 00 R _0._F 00 R _.K_F00 R NV_0_J 00 R _0._F 00 MIL TP MIL TP TV_ONL0 TV_ONL M_LU M_RN M_R 00 R NV_0_J R _0_F 00 R _0_F 00 R _0_F 00 R NV_0_J 00 M_HYN_R RT_IRF M_VYN_R R NV_0_J 00 M_ R0 NV_0_J 00 M_ R NV_0_J 00 M_ U J0 L_KLT_TRL H L_KLT_N L_TRL_LK 0 L_TRL_T L LK L T K0 L_V_N L LV_I L LV_V N LV_VRFH N0 LV_VRFL LV_LK# LV_LK F 0 0 F K F J L M P R NV_0_J 00 LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T LV_T#0 LV_T# LV_T# LV_T0 LV_T LV_T TV_ TV_ TV_ TV_RTN TV_RTN TV_RTN TV_ONL0 TV_ONL H RT_LU RT_LU# K RT_RN J RT_RN# F RT_R RT_R# K RT LK RT T F RT_HYN RT_TVO_IRF RT_VYN restline MH-QP0 LV PI-XPR RPHI TV V P_OMPI P_OMPO N M P_OMP P_RXN0 P_RX#0 J P_RXN P_RX# L P_RXN P_RX# N P_RXN P_RX# T P_RXN P_RX# T0 P_RXN P_RX# U0 P_RXN P_RX# Y P_RXN P_RX# Y0 P_RXN P_RX# P_RXN P_RX# W P_RXN0 P_RX#0 P_RXN P_RX# 0 P_RXN P_RX# P_RXN P_RX# H P_RXN P_RX# P_RXN P_RX# J0 P_RXP0 P_RX0 L0 P_RXP P_RX M P_RXP P_RX U P_RXP P_RX T P_RXP P_RX T P_RXP P_RX W P_RXP P_RX W P_RXP P_RX 0 P_RXP P_RX Y P_RXP P_RX P_RXP0 P_RX0 P_RXP P_RX H P_RXP P_RX P_RXP P_RX H P_RXP P_RX P_RXP P_RX P_TXN0 P_TX#0 N P_TXN P_TX# U P_TXN P_TX# U P_TXN P_TX# N P_TXN P_TX# R0 P_TXN P_TX# T P_TXN P_TX# Y W P_TXN P_TX# W P_TXN P_TX# P_TXN P_TX# P_TXN0 P_TX#0 P_TXN P_TX# P_TXN P_TX# H P_TXN P_TX# P_TXN P_TX# H P_TXN P_TX# P_TX0 P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX0 P_TX P_TX P_TX P_TX P_TX M T T N0 R U W Y Y 0 0 H P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP R._F 00 P_RXN[..0] P_RXP[..0] P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN P_TXN0 P_TXN P_TXN P_TXN P_TXN P_TXN P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP P_TXP0 P_TXP P_TXP P_TXP P_TXP P_TXP 00 NV_0.U_V_M_ 00 P_RXN_0 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_ 0 NV_0.U_V_M_ 00 P_RXN_0 NV_0.U_V_M_ 00 P_RXN_ NV_0.U_V_M_ 00 P_RXN_ NV_0.U_V_M_ 00 P_RXN_ NV_0.U_V_M_ 00 P_RXN_ NV_0.U_V_M_ 00 P_RXN_ NV_0.U_V_M_ 00 P_RXP_0 NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ 0 NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_0 NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ 0 NV_0.U_V_M_ 00 P_RXP_ NV_0.U_V_M_ 00 P_RXP_ P_RXN_[..0] P_RXP_[..0] R NV_0_J 00 M_HYN_R R NV_0_J 00 M_VYN_R R NV_0_J 00 R _0_F 00 M_LU R NV_0_J 00 R _0_F 00 M_RN R NV_0_J 00 R _0_F 00 M_R Place resistor close to MH TV_IRTN TV_IRTN TV_IRTN FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision restline (RPHI) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
10 M0--0. restline (RII) / 0 Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN M Q M Q M Q M Q M Q M Q M Q M Q0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q#0 M M0 M M M M M M M M M M M M M M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M M M M M M M M 0 M M 0 M M M M M 0 M M M M M M M M M M 0 M M M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q# M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M M0 M M M M M M M M M M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q _RVN# _RVN# R YTM MMORY U restline MH-QP0 P R 0 Y F0 F J0 J J L W0 K K K K J L J J K J0 W L K K K N J0 L K L K K0 J J F H N0 K J R T V0 Y Y U T V 0 0 Y R0 K L H J F W T0 0 K K J L V U0 0 L K K K F V W F Y V Y _Q0 _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M0 _M _M _M _M _M _M _M _M _M _M _M _R# _RVN# _W# R YTM MMORY U restline MH-QP0 R W J 0 H W 0 F H 0 F0 R0 W0 T W W Y Y V T V T W V U T R 0 0 Y 0 W Y R T T Y R R R N M N0 T T N M N W F K F L T W W Y T H P N T H P J 0 0 J K H L K J J L Y0 _Q0 _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q _Q0 _Q _Q _Q _Q _Q _Q _0 _# _M0 _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _M _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M0 _M _M _M _M _M _M _M _M _M _M _M _R# _RVN# _W# M Q[..0] M Q#[..0] M W#, M R#, M #, M, M, M 0, M 0, M, M, M #, M R#, M W#, M M[..0] M [..0], M [..0], M Q[..0] M Q[..0] M Q#[..0] M Q[..0] M M[..0]
11 +_VRUNL _0UH_00 L0-00K +_VRUN V.M_MH_PLL P _0U_.V_ + RTP0M P _0U_.V_ RTP0M R 0_J 00 +VRUN +_VRUN L 0R-00MHZ_00 H0KF-T0 00 U_.V_M_ L _0UH_00 L0-00K L 0R-00MHZ_00 H0KF-T0 L LMPN _0R-00MHZ_00 NOT: Ps used in +.V_TV should be within 0 mils of edge of MH. 0m 0m + 00 _0.U_V_M_ R 00 0._F 00 _0U_.V_Y_Y +_0VRUN +V._PLL +._RT R L N_0_J +VRUN L FILTR 00 _0R-00MHZ_00 NFMR R LMPN NV_0_J 00 _0.U_V_M_ +V._PLL +V. +_0VRUN V_TV_TV R L N_0_J +V_TV FILTR 00 R _0_J NFMR NV_0_J 00 R +V._TXLV 00 R _0.U_V_M_ NV_0_J _000P_0V_K_ R 00 NV_0_J 00 +V.M_HPLL +VRUN 0m 0m +V_TV +V.M_MPLL 0.0U_V_M 0U_0V_M 00_XR 00_XR 00 _0.U_V_M_ 00 U_.V_M_ L LMPN _0R-00MHZ_00 QTV_F 0 00_XR 0.U_0V_K 00_XR 0.U_0V_K 00 _0.U_V_M_ 00 0 _0.U_V_M_ 00 0 _0.U_V_M_ U_V_M_ 00 0 _0.U_V_M_ 00 NFMR L FILTR +V._TV 0m R NV_0_J 00 +V._TV 0m +V._TV 0m R NV_0_J 00 +V._TV NFMR L _FILTR 00 NFMR L FILTR NFMR L FILTR NFMR L FILTR R NV_0_J 00 0m +V._Q m R NV_0_J 00 +_VRUN R NV_0_J 00 +V._PPLL +V._PPLL_R 00_XR 0U_.V_M 0m 00u 0m m 0m +VRUN _0_J NV_0_J 00 +VRUN_ R R 00 _0.U_0V_K 00_XR UH +V_RT J V_YN +_VRUN + +_VRUN 00 0 U_.V_M_ P 00U_.V_ FX0J0R R NV_0_J U_.V_Y_Y 00 U_.V_M_ +V._PLL +V._PLL +V.M_HPLL +V._TV V.M_MH_PLL +V._Q 0.U_0V_K 00_XR +_VU R _0_J U_.V_Y_Y +V.M_MPLL +V._TV +V._TV +V._TV +V._PPLL 00 U_.V_M_ 0.U_0V_K 00_XR L LMPN 0R-00MHZ_00 R _F 00 0m m 0.U_0V_K 00_XR 00 U_.V_Y_Y 0.U_0V_K 00_XR R _0_J U_.V_K 00_XR 0m 00m 0m +V._LV 0 00 _U_.V_Y_Y 00_XR _0U_.V_M +V._PPLL 0 H L M K0 K U W V U U U T T R R N N U NOT: +V. and +V.M should be +V. for Fountaingrove (alero Interposer). V_RT_ V_RT_ V_PLL V_PLL V_HPLL V_MPLL V_LV M V_RT L V_TV restline MH-QP U_V_M_ 00 V V_P_ V_P_PLL V_M V_M V_M V_M V_M T V_M T V_M T V_M V_M_K V_M_K V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_Q V_HPLL V_P_PLL J V_LV H V_LV R NV_0_J 00 V V_LV V_P_ V_M0 V_M V_M_NTF V_M_NTF RT PLL K M P LV POWR TV TV/RT LV X XF M K MI P VTT HV VTTLF VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT V_M_K V_M_K V_M_K V_M_K V_RXR_MI V_RXR_MI VTTLF VTTLF VTTLF T T T T T T R R R +VRUN U U U U U U U U U U T T T0 V_X T V_X U V_X U V_X T V_X T V_X T0 V_X_NTF V_XF V_XF V_XF V_MI V_TX_LV V_HV V_HV V_P V_P V_P V_P V_P R J0 K K J J 0 0 W0 W V V0 H0 H F H 00m +V._HV VTTLF_P VTTLF_P VTTLF_P 00 0.U_.V_Y_Y +_0VRUN 0.U_0V_K 00_XR 0m 00m U_.V_Y_Y 00 0m 0 0U_.V_M 00_XR 00m 00m 00m 0m 0m U_.V_Y_Y +V._HV _00V-0-LF R _0_J 00.U_.V_K 00_XR _000P_0V_K_ 00 0.U_.V_Y_Y 00 R 0_J 00.U_.V_K 00_XR 0 U_0V_Y 0_YV +_VRUN el R +_VRUN +V._TXLV +_VU L0 _0.UH_00 FI0F-RK P R + _0U_.V_ TP0MI NV_0_J 00 0U_.V_M 00_XR U_.V_Y_Y 00 0.U_0V_K 00_XR.U_0V_Y_Y 00 0.U_0V_K 00_XR P0 + 0U_.V_ TP0MI FOXONN +_VRUN ate: Tuesday, March, 00 heet of 0.U_.V_Y_Y U_.V_M_ +V._M_K +V_MI L0.0UH_00 WF0-0NM-L0 P 0U_.V_M + 0U_.V_ 00_XR TP0MI 0.U_0V_K 00_XR 0.U_0V_K 00_XR +_0VRUN +_VU L 0.UH_00 FI0F-RK R _F 00 +_0VRUN +_0VRUN HON HI Precision Ind. o., Ltd. P - R& ivision 0.U_0V_K 00_XR restline (POWR,V) / ize ocument Number Rev M U_.V_M 00_XR
12 Place on the dge. avity apacitors avity apacitors Note: ll VM pins shorted internally. avity apacitors Place where LV and R taps. 0 mils from the dge. 0 mils from the dge. Place on the dge.. 0m.. M0--0. restline (V OR) / Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN +_VU +_VU +_0VRUN +_0VRUN +_0VRUN +_0VRUN +VFX_OR +VFX_OR +VFX_OR +_0VRUN _U_.V_M_ 00 0.U_0V_K 00_XR _U_.V_Y_Y 00 _0.U_0V_K 00_XR + P _0U_V_ FL0Y 0.U_0V_Y_Y U_0V_Y_Y 00 0.U_0V_Y_Y 00 0 U_.V_M_ 00 U_.V_M_ 00 PJ OPN 0.U_0V_K 00_XR 0 0.U_.V_Y_Y 00 N_0.U_V_Y_Y 00 0.U_0V_Y_Y U_V_T P FX0R U_.V_M_ 00 0 U_.V_M_ 00 R NV_0_J 00 + P 0U_.V_ RTP0M _0U_.V_M 00_XR U_.V_M_ 00 0.U_0V_K 00_XR 00 0.U_0V_Y_Y 00 _0.U_0V_K 00_XR 0.U_0V_K 00_XR POWR V OR V M V FX V FX NTF V M LF U restline MH-QP0 K J J H H H F T F J W Y U F H H H J J U K K K K U U U0 U U U V V V V0 T V V V Y Y Y Y Y0 Y Y T Y Y Y Y T F F H H H H T J J J K K L L L L0 L T L M M M M M P P P T P P0 P U U L V W T T U R0 T W W Y F F H0 H H H P P R0 R R R R R0 H J0 N W W T H M0 U0 V V V Y V V V V V V0 V V V V V_M0 V_M0 V_M0 V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_M V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_M V_M V_M V_X_NTF V V_M V_X V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X V_X V_X V_X V_X V_X V_X V_X V_X0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V V_X V_X V_X V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_X V_X V V_X_NTF V_M V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF 0.U_0V_K 00_XR _0.U_.V_Y_Y 00 0.U_0V_K 00_XR 0 0.U_0V_Y_Y 00 R 0_J 00 U_.V_M_ 00 POWR V NTF V NTF V V XM V XM NTF UF restline MH-QP0 K P U F F H H H H J K K K L L P R R T0 T T U U U U U V V V T T U U V V F K M P R R R Y K K J J L L L M M M M P P R Y Y Y Y L L J F J K L L L M M M M P P P R R T T V V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF V_XM V_XM V_XM V_XM V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF0 V_XM_NTF V_XM_NTF V_NTF V_NTF V_NTF V_NTF V_ V_ V_ V_ V_ V_ V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_XM V_XM_NTF V_XM_NTF V_XM_NTF V_NTF V_XM_NTF V_XM_NTF V_NTF V_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM_NTF V_XM V_XM V_NTF 0.U_0V_K 00_XR
13 M0--0. restline (V) / Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN V UJ restline MH-QP0 0 0 F F F F0 F0 H H H H J J J J J J J J K K K L L L0 L L L L L M M M M M M0 M N N N N N N N N N N P P P P P0 R T T T U U U0 W W W W W W Y Y Y V V Y Y Y Y0 Y P T T T R F F T V H0 V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V0 V V V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V UI restline MH-QP F0 F F F 0 H H0 H H H J J J J J J J J J K0 K K K K K L M M M M M M N N N N N N P P P0 R R R R R R T0 T T T W W W W W W Y0 Y Y Y Y Y Y Y F F F H H0 H H H J J J J J J K K K K U U U U U U U V V W W K K K L L K0 K L L L L V V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V V V0 V V V V V V V V V0 V V V V V V V V V V V V V V V0 V V V
14 0.U_V_M_ µf and. µf placed close to VRF pins "Intel check list suggest a 0uF",,,,, M_T_U,,, M_LK_U +VRUN.U_0V_Y_Y 00 M_K0 0, M 0, M 0 0, M W# 0, M #, M_# M_OT R_VRF M Q M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q M Q0 M Q M Q0 M Q# M Q M Q M Q M Q M Q M M M Q0 M Q M M M M M M M 0 M Q M Q M Q# M Q M Q M Q M Q M Q0 M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q 0.U_0V_Y_Y 00 0.U_V_Y 00_YV +_VU VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V K0 V N _ V V V0 0/P 0 W# V # # V OT V Q Q V Q# Q V Q Q V Q0 Q V M V Q Q V0 Q Q V NTT V0 Q# Q V Q0 Q 0 0 V Q Q V M V Q Q V L V(P) IMM_0 MFIX MFIX P-00/P-00 R RM O-IMM (00P) NPTH NPTH 0 0 N V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V V0 Q0 Q V N M V Q Q V Q Q V Q# Q V0 Q0 Q V K V V V 0 V R# 0# V OT0 V N V Q Q V M V Q Q V Q Q V Q# Q V Q Q V Q Q V K K# V M V Q Q V Q0 Q V Q# Q V Q Q V _VU M M M M M M 0.V per IMM=.0 M Q0 M Q M M0 M Q M Q M Q M Q M M M Q M Q M Q M Q R_XTT#0 M M M Q M Q M Q M Q M Q# M Q M Q M Q M M M Q M Q M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q0 M Q M Q M Q0 M Q# M Q M Q M Q 0_IM0 _IM0 R N_0_J 00 M, R 0K_J 00 R R O-IMM_00P 0K_J 00 FOX_0-NRN-F Mus ddress: 0(W)/(R) M_LK_R0 M_LK_R#0 M_K, M 0, M R# 0, M_#0, M_OT0, M_LK_R M_LK_R# PM_XTT#0 Place IMM_0 near MH Place these aps near o-imm0..u_0v_y_y 00 Place these aps near o-imm0. R_VRF (0 mil).u_0v_y_y 00 0.U_V_Y_Y 00 M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0, R_VRF 0.U_V_M_ 00.U_0V_Y_Y 00 RIMM_VRF 0 0.U_V_Y_Y 00 R 0_J 00 0.U_V_Y_Y 00 +_VU.U_0V_Y_Y 00 +_VU.U_0V_Y_Y 00 0.U_V_Y_Y 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision R(II)O-IMM_0 ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
15 Mus ddress: (W)/(R) IMM_ IMM_ is placed farther from the MH than IMM_0 0. µf and. µf placed close to VRF pins Place these aps near o-imm. Place these aps near o-imm..v per IMM=.0 M R(II)O-IMM_ Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN M Q#0 M Q M Q# M Q M Q M Q M Q# M Q M M Q# M 0 M M Q M Q M M Q M Q M Q M M Q M M Q M Q M Q _IM M M Q M Q M Q M Q M M M0 M Q# M 0 M M M Q M Q M Q M M Q# M M M M M Q M M M M M 0_IM M Q# M M Q M Q# M Q M M M M M Q0 M M R_XTT# M M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q R_VRF +_VU +_VU +_VU +_VU +VRUN +VRUN.U_0V_Y_Y 00.U_0V_Y_Y 00 0.U_0V_Y_Y 00 0.U_V_Y_Y 00 P-00/P-00 R RM O-IMM (00P) N R O-IMM_00P FOX_0-NN-F VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V Q# Q V Q Q V Q Q V M N V Q Q V K0 V N _ V V V0 0/P 0 W# V # # V OT V Q Q V Q# Q V Q Q V Q0 Q V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V V0 Q0 Q V N M V Q Q V Q Q V Q# Q V0 Q0 Q V K V V V 0 V R# 0# V OT0 V N V Q Q V M V Q Q V Q Q V V M V Q Q V0 Q Q V NTT V0 Q# Q V Q0 Q Q Q V M V Q Q V L V(P) Q# Q V Q Q V Q Q V K K# V M V Q Q V Q0 Q V Q# Q V Q Q V 0 V NPTH NPTH MFIX MFIX 0.U_V_Y 00_YV 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_0V_Y_Y 00 R 0K_J 00 R 0K_J 00.U_0V_Y_Y 00 0.U_V_M_ 00 R N_0_J 00.U_0V_Y_Y 00.U_0V_Y_Y 00 0.U_V_Y_Y 00 M Q[0..] 0 M M[0..] 0 M Q[0..] 0 M Q#[0..] 0 M 0, M_#, M_OT, M_K, M W# 0, M 0 0, M_#, M # 0, M_K, M 0, M_OT, M R# 0, M_LK_U,,, M_T_U,,, M_LK_R# M_LK_R M_LK_R# M_LK_R PM_XTT# M, M [0..] 0,
16 +0_VU,, M M R0 00 _J R0 00 _J, M_OT M M M RP 00_PR RP 00_PR M M RP 00_PR +0_VU M 0 M RP 00_PR 0, M 0 0, M # 0, M W# M 0 M M RP 00_PR RP 00_PR RP 00_PR +0_VU 0, M [0..] M M RP 00_PR 0, M [0..] 0, M R# 0, M M M RP0 00_PR RP 00_PR +0_VU +0_VU M M RP 00_PR 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 Layout note: Place cap close to every R-pack terminated to +0_VU 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0, M R# 0, M M M RP 00_PR RP 00_PR +0_VU +0_VU, M_OT0 0, M M M RP 00_PR RP 00_PR 0 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 M M M M RP 00_PR RP 00_PR Layout note: Place cap close to every R-pack terminated to +0_VU +0_VU 0, M 0 0, M W# 0, M # M 0 M 0 M RP 00_PR RP0 00_PR RP 00_PR +0_VU +0_VU +0_VU,,,, M_K0 M_K M_K M_K R R R R 00 _J 00 _J 00 _J 00 _J,,,, M_#0 M_# M_# M_# R R R R0 00 _J 00 _J 00 _J 00 _J, M_OT, M_OT 0, M M R R R R 00 _J 00 _J 00 _J 00 _J FOXONN R(II)Termination HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M ate: Tuesday, March, 00 heet of
17 +VRUN R0 N_0_J 00 R0 +VRUN,,,,,,,0,,,, TXP[0..] TXN[0..] P_RXP_[0..] P_RXN_[0..] PLT_RT# NV_0K_J 00 TXP0 TXP TXP TXP TXP TXP TXP TXP TXP TXP TXP0 TXP TXP TXP TXP TXP TXN0 TXN TXN TXN TXN TXN TXN TXN TXN TXN TXN0 TXN TXN TXN TXN TXN P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_0 P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXP_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_0 P_RXN_ P_RXN_ P_RXN_ P_RXN_ P_RXN_ U NV_H0W LK_PI_P LK_PI_P# 00MHz R0 NV J 00 LK_PI_P LK_PI_P# TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN TXP0 TXN0 TXP TXN TXP TXN TXP TXN TXP TXN TXP TXN H H J J K H H H K J J H 0 H0 H K J J H H K J J H H K J J H U PX_RT# PX_RFLK PX_RFLK# PX_TX0 PX_TX0# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX0 PX_TX0# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# PX_TX PX_TX# P_RXP_0 K P_RXN_0 PX_RX0 K P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K0 P_RXP_ PX_RX# L0 P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_0 PX_RX# L P_RXN_0 PX_RX0 L P_RXP_ PX_RX0# M P_RXN_ PX_RX M P_RXP_ PX_RX# K P_RXN_ PX_RX K P_RXP_ PX_RX# L P_RXN_ PX_RX L P_RXP_ PX_RX# M P_RXN_ PX_RX M P_RXP_ PX_RX# L P_RXN_ PX_RX L PX_RX# PI XPR NM-T--/H MULTI-U I/O INTRF MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ P N N N M M P N N M L L R R P P R P M L L L F Y Y Y MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO R NV_K_F 00 MIO_HYN MIO_VYN TP MIL MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ MIO_HYN MIO_VYN MIO_ MIO_TL MIO_LKOUT MIO_LKOUT# MIO_LKIN MIO_VRF MIOL_PU_N MIOL_P_VQ MIO0 MIO TP MIL TP MIL TP MIL MIO TP0 MIL MIO MIO TP0 MIL TP MIL MIO0 MIO MIO MIO MIO MIO MIO MIO MIO TP MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL elete TP TP MIL TP MIL TP MIL +VRUN R N_0K_J 00 MIO_HYN MIO_TL R NV_0K_J 00 FOXONN V(PI-) HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
18 M KU HH H Vender Qimonda amsung Qimonda amsung Qimonda amsung Hynix Vendor PN HYHF- KJQ- HYHF- KJQ- HYHFL KJQ-HYRFP- H.H PN -HYH-00 -KJ-00 -HYH-00 -KJ-00 -HYH-000 -KJ-00-HYR-00 onfiguration NM-T with pcs (Mx) R NM-T with pcs (Mx) R NM-T with pcs (Mx) R lotion tuff U,U,U,U tuff U,U; No stuff U,U tuff U,U; No stuff U,U F: TV Mode trap no use, remove. (MIO, MIO0, MIO) +VRUN P_RXP[0..] P_RXP0 TXP0 NV_0.U_V_M_ 00 TXP[0..] P_RXN[0..] P_RXN0 TXN0 NV_0.U_V_M_ 00 TXN[0..] trap for R-ball 000 Mx (-bit) Qimonda 00 Mx (-bit) amsung_-die RM_F0 RM_F MIO0 R0 NVH_K_J 00 R0 NVQ/_K_J 00 MIO R0 NVQ_K_J 00 R0 NVH/_K_J 00 P_RXP TXP NV_0.U_V_M_ 00 P_RXN TXN NV_0.U_V_M_ Mx (-bits) Qimonda 0 Mx (-bits) amsung_-die RM_F MIO R0 NVM_K_J 00 R0 NVM K_J 00 P_RXP P_RXP TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN P_RXN TXN 0 NV_0.U_V_M_ 00 TXN NV_0.U_V_M_ 00 0 Mx (-bits) Qimonda 0 Mx (-bits) Hynix Mx (-bits) amsung_-die RM_F MIO R0 NVbit_K_J 00 R0 NVbit_K_J 00 P_RXP P_RXP TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN P_RXN TXN NV_0.U_V_M_ 00 TXN NV_0.U_V_M_ 00 UVNOR 0 (U YTM IO) (U XTRNL ROM) UVNOR MIO R NV_K_J 00 MIO P_RXP P_RXP P_RXP P_RXP P_RXP0 TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP 0 NV_0.U_V_M_ 00 TXP 0 NV_0.U_V_M_ 00 TXP0 0 NV_0.U_V_M_ 00 P_RXN P_RXN P_RXN P_RXN P_RXN0 TXN NV_0.U_V_M_ 00 TXN 00 NV_0.U_V_M_ 00 TXN 0 NV_0.U_V_M_ 00 TXN 0 NV_0.U_V_M_ 00 TXN0 0 NV_0.U_V_M_ 00 MIO0 is used to set the PI xpress PLL termination enable. FULT "0" IO_PF[:0] -> 000 for Mobile PX_PLL_N_TRM IO_PF0 IO_PF IO_PF IO_PF MIO0 R NV_K_J 00 MIO R N_K_J 00 MIO R NV_K_J 00 MIO R NV_K_J 00 MIO_HYN R NV_K_J 00 MIO0 R NV_K_J 00 R N_K_J 00 R0 N_K_J 00 R0 N_K_J 00 P_RXP P_RXP P_RXP P_RXP P_RXP TXP 0 NV_0.U_V_M_ 00 TXP 0 NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 TXP NV_0.U_V_M_ 00 P_RXN P_RXN P_RXN P_RXN P_RXN TXN 0 NV_0.U_V_M_ 00 TXN 0 NV_0.U_V_M_ 00 TXN NV_0.U_V_M_ 00 TXN NV_0.U_V_M_ 00 TXN NV_0.U_V_M_ 00 NM-T PI_VI[:0]= "000" -> NM- PI_VI[:0]= "00" -> NM- PI_VI[:0]= "0000" -> PI_VI 0 PI_VI PI_VI PI_VI PI_VI MIO R NV_K_J 00 MIO R N_K_J 00 MIO R N_K_J 00 MIO R NV_K_J 00 MIO_TL R NV_K_J 00 R N_K_J 00 R NV_K_J 00 R NV_K_J 00 R N_K_J 00 R N_K_J 00 RYTL MIO R NV_K_J 00 MIO MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO MIO0 MIO MIO MIO MIO MIO MIO MIO MIO 0 rystal MHz (efault) Reserved MIO_TL MIO_HYN MIO_TL MIO_HYN FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision V(TRP) ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
19 NX: lave I/MU compatible interface. M0--0. V(R)# Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN FQM0 FQM FQM FQM FQM FQM FQM FQM F_ F_R# F_ F_ F_# F_W# F_0# F_ F_0 F_0 F_ F_ F_ F_ F_ F_ F_RFLK F_RFLK# FWQ FWQ0 FWQ FWQ FWQ FWQ FWQ FWQ FRQ FRQ FRQ0 FRQ FRQ FRQ FRQ FRQ F F0 F F F F F F F F F F0 F F F F F F F F F F F F F F F F F F F0 F F0 F F F F F F F F F F F F F F F0 F F0 F F F F F F F F F F F F F F0 F_ F_ F_ F_0 F_R# F_ F_ F_ F_ F_ F_ F_0# F_ F_ F_R# F_0# FQM F F0 F F F F F_ F F F FQM F F F F F F_LK F_LK0# FWQ F_0 F F F0 FRQ F_RT F F0 F F F F_LK0 F_ FWQ F_K F_ F F F F F_K FRQ F_0 FQM0 F F F F_LK# FWQ F_ F_0 F_ F_ FQM F F F F F_RT FRQ F_W# FWQ F_ F_ F F FRQ F_ F F F F F FRQ FWQ FWQ F_ F_# FQM F F F F FRQ FWQ0 F_LK0# F F FRQ0 FWQ F_ F_ F_ FQM F F0 F F0 F_ F F F F F F0 FRQ F_R# FQM FQM F F0 F F F_ F_ F F F F F_0# F_ F_LK F_LK0 F_ F_ F_LK# I_L I_ +VRUN +VRUN TPMIL TPMIL R(-ROUP) U NM-T--/H W0 T V N M N L K K J J P0 N N0 N L L0 J0 L H0 K0 H F0 H 0 0 H H J F F 0 Y 0 M0 F0 J J0 J K M L0 0 0 F H F M M0 0 F K0 0 0 Y V T0 W R R0 P U V0 U R P U P U0 Y W W T V T T U W P R Y L K L F H0 M K L F H F_M F_M F_M F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F FQM0 FQM FQM FQM FQM FQM FQM FQM F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_LK0 F_LK0# F_LK F_LK# F_RFLK F_RFLK# FQ_WP0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_RN0 FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN R NV_.K_J 00 R NV_.K_J 00 TPMIL R(-ROUP) U NM-T--/H F F0 F F F F F 0 0 F F F 0 F F 0 F0 F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F F F F F F F F0 F F F FQM0 FQM FQM FQM FQM FQM FQM FQM F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_M F_M F_M F_M0 F_M F_M F_M F_M F_M F_M F_LK0 F_LK0# F_LK F_LK# FQ_WP0 FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_WP FQ_RN0 FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN FQ_RN F_RFLK F_RFLK# TPMIL F[0:] FWQ[..0] F[0:] FQM[..0] F_0# F_[..] F_[0..] F_W# F_LK F_LK0 F_LK# F_LK0# F_[..] F_[0..] FQM[..0] FRQ[..0] FRQ[..0] F_ F_K F_RT F_0 F_# F_R# F_ F_ F_ F_R# F_0# F_RT F_K F_# F_LK0# F_0 F_LK# F_LK0 FWQ[..0] F_LK F_W# I_ I_L
20 +VRUN R0 NV_.K_J 00 NV_I_L NV_I_ R0 NV_.K_J 00 R NV_.K_J 00 R NV_.K_J 00 NV_I_L NV_I_ 0 NV_I_L 0 NV_I_ HP HP_L HP_ NV_I_L NV_I_ NV_I_L NV_I_ NV_I_L NV_I_ H H J K J UF IH_L IH_ I_L I_ I_L I_ I_L I_ I THRMN THRMP UFRT# TRO J K F T NV_THRMN NV_THRMP UFRT# TRO TP MIL TP MIL NV_THRMN NV_THRMP NV_PIO NV_THRMP 00 N_00_J R +VRUN R0 NV_.K_J 00 +VRUN NV_JT_TI R NV_0K_J 00 NV_JT_TM R NV_0K_J 00 NV_JT_TRT# R NV_0K_J 00 NV_JT_TK R NV_0K_J 00 +VRUN MIL TP0 MIL TP0 MIL TP MIL TP MIL TP MIL TP MIL TP0 MIL TP0 ROM_# ROM_O ROM_I ROM_LK IFP_VPRO IFP_VPRO PX_TTLK_OUT PX_TTLK_OUT# TP_F_U TP_F_U TTMO R0 NV_0K_J 00 MIL TP0 NV_JT_TK NV_JT_TM NV_JT_TI NV_JT_TO W M K M M F H J K K L NV_JT_TRT# L ROM# ROM_O ROM_I ROM_LK IFP_VPRO IFP_VPRO ROM PX_TTLK_OUT PX_TTLK_OUT# F_U F_U TTMO JT_TK JT_TM JT_TI JT_TO JT_TRT_N NM-T--/H PIO TT INL NRL INL RYTL WPRY_ MMTRPL0 MMTRPL MMTRPL MMTRPL M H H N_P_0V_J_N NV_XTLOUT WPRY MMTRPL0 MMTRPL MMTRPL MMTRPL XTLIN XTLOUTUFF NV_XTLIN Y TP MIL TP0 MIL TP MIL TP MIL PIO0 K TPI_INT_N PIO H NV_RJ PIO K PIO NV_INV_N PIO NV_PIO PIO J R0 NV_0_J 00 NV_PIO PIO TP MIL K NV_PIO TP MIL PIO NV_PIO NV_PIO PIO NV_PIO PIO H NV_PIO0 PIO0 F NV_RT_TL R0 N_0_J 00 PIO NV_PIO PIO 00 R00 N_0_J XTLIN XTLOUTUFF XTLIN XTLOUT T T U U 00 TP MIL N_MHZ_0P_0PPM ITTI_L N_P_0V_J_N 00 NV_HMI_T_ TP MIL NV_RJ NV_LV_N# NV_INV_N V_PIO R0 NV_0_J 00 NV_PIO NV_PIO0, HMI_ TP MIL PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO I/O I I R0 NV_0_J 00 R_NV_XTLIN NM: XTLIN use.v level +VRUN O O O O O O O O O O I R_XTLIN Inter pull low Yes Yes Yes No Yes Yes Yes Yes No No No No(Low) -- PIO TL HMI Hot Plug etect 0 (HP0) Hot Plug etect (HP) Panel rightness (PWM) ctive High Panel Power nable ctive Low Panel acklight On/Off ctive High NVV VI0 NVV VI FV VI0 THRM ctive Low LRT ctive Low TM LINK LT no function yet /TT# HP_L HP_ R NV_0K_J 00 HP ROM R0 NV_0K_J 00 U L V N N N N N PROM_OI-P_K NV_0.U_V_M_ 00 R N_0K_J 00 _0 R N_0K_J 00 XTLOUTUFF XTLIN R R N_0K_J 00 R N J 00 R0 N_0K_J 00 N J 00 R N_0K_J 00 N_U_0V_Y_Y 00 R place near PU R place near spectrum chip N_000P_0V_M_ 00 U0 XTLOUTUFF_R X/ILK X _0 N V VMOUT 0 P# RFLK LK RFLK TP N_MK-0 Tis chip can use MK or P PR PTRUM TTIN FOR MK 0 PR IRTION 0 OWN M OWN OWN 0 = connect to N M= unconnected = connect directly to V MIL pread Percentage(%) FOXONN PR PTRUM TTIN FOR P R PR pread PIN IRTION Percentage(%) 0 OWN -. OWN -. nvidia support own -.% HON HI Precision Ind. o., Ltd. P - R& ivision V(MULTIU) ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet 0 of
21 NV_R R NV_0_F 00 NV_RN R NV_0_F 00 NV_LU R NV_0_F 00 NV RT R0 NV F 00 H U _RT _RT R NV RT R NV F 00 0 F F F F F 0 H J0 J J J J0 J J J J J K K K L L L L L L L L M M M M0 M M M UH N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 NM-T--/H N N N N N N N N N N N0 N N N N N N N N N N00 N0 N0 N0 N0 N0 N0 N0 N0 N_N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N N N N N N N N N0 N N F F F F F F F F H H J J J J K0 K K K L L M M M M N N N N P P P P R R R R R R R0 R T T T T T U U U U U V V V V V V V0 V W W W W Y Y Y Y N L0 N N M0 LO TO PU N_N Only suport one channel LV 0 NV_R 0 NV_RN 0 NV_LU 0 NV_HYN 0 NV_VYN MIL TP MIL TP MIL TP MIL TP MIL TP NV_O_RXIN- NV_O_RXIN+ N_N NV_O_LKIN- NV_O_LKIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_RXIN- NV_O_RXIN+ NV_O_RXIN- NV_O_RXIN+ NV_O_RXIN- NV_O_RXIN+ -R -RN -LU -HYN -VYN V-RT R HYN VYN V-LK NV_O_RXIN- NV_O_RXIN+ MIL TP MIL TP MIL TP00 V-T NV_R NV_HYN NV_VYN NV_R NV_HYN NV_VYN IFP_TX# IFP_TX IFP_RT I L H NV_RN J _RN NV_LU H _LU 0m F0 K0 TP_NV RT F _RT F NV_RN _RN NV_LU _LU 0m _IUMP J K J H H H K J H J L K M M L M K K L K L _R _IUMP _HYN _VYN _R _HYN _VYN IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT NM-T--/H -R -RN -LU -VIO VIO LV TM Y _R R NV_R _RN T NV_RN _LU IFP_TX# IFP_TX IFP_TX0# IFP_TX0 IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_TX# IFP_TX IFP_RT T M M F F H NV_LU V 00m _IUMP NV_HMI_TX- NV_HMI_TX+ NV_TM_- NV_TM_+ NV_TM_0- NV_TM_0+ NV_TM_- NV_TM_+ H VI_TM_LKIN- VI_TM_LKIN+ J VI_TM_- K VI_TM_+ L L J J H VI_TM_- VI_TM_+ NV_O_LKIN- NV_O_LKIN+ NV_O_RXIN0- NV_O_RXIN0+ NV_O_RXIN- NV_O_RXIN+ MIL TP0 NV_VN_RXIN- MIL TP0 NV_VN_RXIN+ MIL TP0 NV_VN_LKIN- MIL TP NV_VN_LKIN+ MIL TP0 NV_VN_RXIN- MIL TP0 NV_VN_RXIN+ MIL TP0 NV_VN_RXIN0- MIL TP0 NV_VN_RXIN0+ VI_TM_- VI_TM_+ IFP_RT Not support VI NV_R NV_RN NV_HMI_TX- NV_HMI_TX+ NV_TM_0- NV_TM_0+ NV_TM_- NV_TM_+ NV_TM_- NV_TM_+ TP TP TP TP TP TP00 TP0 TP0 MIL MIL MIL MIL MIL MIL MIL MIL TP0 MIL NV_R LO TO PU NV_RN R NV_0_F 00 NV_LU R NV_0_F 00 R NV_0_F 00 FOXONN V(LV/V ) ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of HON HI Precision Ind. o., Ltd. P - R& ivision
22 +_VRUN +_VRUN +_VRUN F F F F F F F F0 F F F0 F F F F F F F F F F F F0 F F F0 F F F F F F F F M M V V K K T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V V V V V V V V V0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 V V R R R VQ VQ VQ0 VQ VQ R N N N N J J VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 U RFU J H0 0 RFU 0 /P 0 M M M M0 J L K M K L K0 H K M K H K N N0 0 U_RFU F_ F_0 FQM FQM FQM0 FQM FRQ RQ P FRQ RQ P0 FRQ0 RQ 0 FRQ RQ0 F_R# R# H F_# # F H F_W# W# F F_0# # J F_LK0 K J0 F_LK0# K# H F_K K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF P P V V H FWQ FWQ FWQ0 FWQ F_RT VRM_VRF_ TP MIL F_ F_0 F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 R NV_0K_J 00 F_[..0] +_VRUN F F F F0 F F F F F F0 F F F F F F F0 F F F F F F F F F F F F F F F T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F V V R R R R N N N N J J U FQM FQM FQM FQM FWQ FWQ FWQ FWQ MF F_RT U Mirror function on U_RFU V RFU J TP MIL F_ V H0 F_R# F F_0 V F F_ V 0 M V M V V V V V F_R# F_# F_W# F_0# F_LK0 F_LK0# F_K F_RT K K V V0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU 0 /P 0 M M M M0 J L K M K L K0 H K M K H K N N0 0 P P V V H F_ F_ F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ FRQ RQ P FRQ RQ P0 FRQ RQ 0 FRQ RQ0 R# H F F_0# # H F_K W# F F_# # J F_LK K J0 F_LK# K# H F_W# K H VRM_VRF_ VRF0 WQ WQ WQ WQ0 MF N RT VRF VRM_VRF_ R NV_0K_F 00 F_ F_ F_ F_ F_[..0] F_0# F_K F_# F_LK F_LK# F_W# F_RT F_0 F_ +_VRUN F_[..] F_ U_ZQ R0 NV_0_F 00 ZQ V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T NV_RM_P-TF-_M HYHF- U_ZQ ZQ R00 NV_0_F 00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 L L V V0 J J VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 L L P P P P T T T T NV_RM_P-TF-_M HYHF- F[0:] FQM[..0] FRQ[..0] FWQ[..0] VRM_VRF is 0%FVQ for R.V 0, NV_PIO0 R0 (0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm Q N_NV_N00PT R N_NV_.0K_F 00 +_VRUN 00 R 0, NV_PIO0 R0 NV_.K_F 00 NV_0K_F 00_XR 0 VRM_VRF_ NV_0.0U_V_K 00 N_U_0V_K F: Remove termination resistor for,,, Remove M/M selection strap. Q0 N_NV_N00PT R N_NV_.0K_F 00 +_VRUN 00 R R NV_.K_F 00 NV_0K_F 00_XR 00 R0 NV_0K_J 00 F_RT VRM_VRF_ NV_0.0U_V_K 00 N_U_0V_K / F uggest: all to termination resistor trace length < ps R F_LK0# F_LK0 NV F 00 R Q N_NV_N00PT F_LK# F_LK NV F 00 +_VRUN 0, NV_PIO0 0, NV_PIO0 R NV_.K_F R 00 VRM_VRF_ N_NV_.0K_F R NV_0K_F 00_XR 0 NV_0.0U_V_K 00 0 N_U_0V_K Q N_NV_N00PT FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision VRM(R)# / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of R N_NV_.0K_F 00 +_VRUN 00 R R NV_.K_F 00 NV_0K_F 00_XR VRM_VRF_ NV_0.0U_V_K 00 N_U_0V_K
23 VRM_VRF is 0%FVQ for R.V U Mirror function on R(0 ohm-0 ohm) 0 ohm --> Output impedence 0 ohm F: Remove termination resistor for,,, Remove M/M selection strap. / F uggest: all to termination resistor trace length < ps M0--0. VRM(R)# / Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN VRM_VRF_ VRM_VRF_ VRM_VRF_ F_RT U_ZQ F_RT F_K VRM_VRF_ U_ZQ F_ F_0 F_ F_ F_0 F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_0# F_W# F_LK0 F_# F_R# F_LK0# F_ F_ F_ F_ F_ F_0 F_ FMF F_# F_W# F_0# F_K F_ F_ F_ F_ F_LK F_LK# F_0 F_ F_ F_ F_ F_ F_0 F_ F_RT VRM_VRF_ VRM_VRF_ VRM_VRF_ VRM_VRF_ F F0 F F F F F F F F F F F F F F F0 F F F F0 F F F F F F F F FRQ FWQ FWQ FRQ FQM FQM FQM FQM0 FRQ0 FRQ FWQ0 FWQ F_LK0# F_LK# F_LK F_LK0 FRQ FRQ FRQ FRQ FWQ FWQ FWQ FWQ F0 F FQM FQM FQM FQM F F F F F F F F F F F F F F F F F0 F F F F F F F F F F F F0 F F F F0 U_RFU U_RFU +_VRUN +_VRUN +_VRUN +_VRUN +_VRUN +_VRUN +_VRUN +_VRUN +_VRUN R N_NVbit_.0K_F 00 N_U_0V_K 00 U NVbit_RM_P-TF-_M HYHF- T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F 0 L L V V0 J J L L P P P P T T T T V V M M F F N N N N J J J J L K M K L K0 H K M K H K N N0 0 P P0 0 H F H F J J0 H H P P V V H V V R R R R K K H0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 V V V V V V V V VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 R# # W# # K K# K VRF0 WQ WQ WQ WQ0 MF N RT ZQ VRF VQ VQ VQ0 VQ VQ VQ V V0 U NVbit_RM_P-TF-_M HYHF- T T R R M N L M T0 T R0 R M0 N L0 M 0 F F0 0 0 F F 0 L L V V0 J J L L P P P P T T T T V V M M F F N N N N J J J J L K M K L K0 H K M K H K N N0 0 P P0 0 H F H F J J0 H H P P V V H V V R R R R K K H0 Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 V V V V V V V V VQ VQ VQ VQ VQ VQ VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 VQ0 RFU 0 RFU 0 /P 0 M M M M0 RQ RQ RQ RQ0 R# # W# # K K# K VRF0 WQ WQ WQ WQ0 MF N RT ZQ VRF VQ VQ VQ0 VQ VQ VQ V V0 N_U_0V_K 00 0 NVbit_0.0U_V_K 00_XR R NVbit_0K_F 00 R NVbit_.K_F 00 Q N_NVbit_N00PT R NVbit_0K_J 00 R0 NVbit_0K_F 00 R N_NVbit_.0K_F 00 Q N_NVbit_N00PT R00 NVbit F 00 R NVbit_.K_F 00 R NVbit_0K_F 00 R N_NVbit_.0K_F 00 N_U_0V_K 00 R NVbit_0_F 00 Q N_NVbit_N00PT R NVbit_0_F 00 TP MIL R NVbit_.K_F 00 0 NVbit_0.0U_V_K 00_XR R00 NVbit_0K_F 00 TP MIL R NVbit_0K_J 00 R00 NVbit F 00 N_U_0V_K 00 0 NVbit_0.0U_V_K 00_XR R NVbit_0K_F 00 R N_NVbit_.0K_F 00 R NVbit_.K_F 00 Q N_NVbit_N00PT 0 NVbit_0.0U_V_K 00_XR F_K F_RT FWQ[..0] FQM[..0] FRQ[..0] F[0:] F_RT F_0 F_ F_[..0] F_W# F_0# F_# F_R# F_LK0# F_LK0 F_[..] F_ F_0 F_[..0] F_# F_W# F_0# F_K F_LK# F_LK F_ F_ F_R# NV_PIO0 0, NV_PIO0 0, NV_PIO0 0, NV_PIO0 0,
24 +VRUN +VRUN +VRUN +VRUN L0 L R NV_0_J 00 NV_0U_0V_M 00_XR NV_0R-00MHZ_00 M00 NV_0R-00MHZ_00 M00 R NV_0_J 00 m 00m NV_0.U_V_M_ 00 0m 00m NV_0.U_V_M_ 00 0 NV_.U_0V_Y_Y 00 NV_000P_0V_M_ 00 NV_.U_0V_Y_Y 00 NV V N_0.0U_V_K_ 00 MIO_V MIO_V N_0.0U_V_K_ 00 MIL TP0 NV V NV VRF NV V NV VRF NV V NV VRF 0m M M R T U 0 H0 V R H T U MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ MIO_VQ _V _VRF _V _VRF _V _VRF PLLV POWR IFP_PLLV IFP_PLLN IFP_IOV IFP_IOV IFP_IOV IFP_IOV IFP_PLLV F F IFP_IOV 0 IFP_PLLV IFP_IOV -- LV I/O power IFP_IOV -- LV I/O power IFP_IOV IFP_IOV -- TM I/O power IFP_IOV -- TM I/O power IFP_PLLV NV_U_0V_Y_Y 00 NV_000P_0V_M_ 00 NV_000P_0V_M_ 00 0m+0m L0 m NV_0R-00MHZ_00 M00 0 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 L0 m NV_0R-00MHZ_00 M00 NV_0.U_V_M_ 00 +_VRUN +_VRUN IFP_PLLV and IFP_PLLV XM:.V NX:.V Filter will change by NVII reference circuit +_VRUN NV V 0m PLLV and VI_PLLV XM:.V NX:.V Filter will change by NVII reference circuit PX_V 0m NV_PLLV NV VRF NV_0.0U_V_K_ 00 NV VRF NV_0.0U_V_K_ 00 IFP_IOV 0m+0m +VLW R NV_0K_J 00 RUN_IFP +VRUN NV_0R-00MHZ_00 M00 NV_.U_0V_Y_Y 00 R NV_0K_J 00 L0 U0 PLLN IFP_PLLN 0 T0 VI_PLLV NM-T--/H L0 NV_0R-00MHZ_00 M00 NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 0 NV_000P_0V_M_ 00 NV_0.U_V_M_ 00 NV_.U_0V_Y_Y 00 Q NV_I0-T-,,,, RUN_ON Q NV_TU FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision V(POWR) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
25 PX_V PX_V L +_VRUN L 0 NV_.U_0V_Y_Y 00 NV_0R-00MHZ_00 M00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 0m(Frame uffer nalog Power) NV_.U_0V_Y_Y 00 NV_0.U_V_M_ 00 0m(Frame uffer nalog Power) 0 NV_000P_0V_M_ 00 F_PLLV NV_0.U_V_M_ 00 F_PLLV FL_P_VQ FL_PU_N FL_TRM_N H H J0 J J J K K K K K K L M T U 0 K H J UI FVTT0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT FVTT0 FVTT FVTT FVTT FVTT FVTT FVTT FVTT F_PLLV F_PLLN F_PLLV F_PLLN FL_P_VQ FL_PU_N FL_TRM_N POWR FV0 FV FV FV FV FV FV FV FV FV FV0 FV FV FV FV FV FV FV FV FV F_VRF FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ FVQ0 FVQ FVQ FVQ 0 K F J M R V H H H H H H L L M M R R V V FVQ 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 Reserve for NM. F_VRF hecking with nvidia +_VRUN R0 N_.K_F 00 NM-T xx m (Frame uffer core power for I/O) 0 NV_0.U_V_M_ 00 N_0.U_V_M_ 00 R N_0K_F 00 NV_000P_0V_M_ 00 +_VRUN NV_0R-00MHZ_00 M00 P + NV_0U_.V_T U0JR NV_.U_0V_Y_Y 00 NV_000P_0V_M_ 00 NV_0.U_V_Y_Y 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NV_.U_0V_Y_Y 00 NV_0.U_V_Y_Y 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 NM-T--/H FL_P_VQ R00 NV_._F 00 +_VRUN R/ FL_PU_N FL_TRM_N R NV_._F 00 R NV_0._F 00 FL_P_VQ FL_PU_N FL_TRM_N. ohm. ohm 0. ohm FOXONN V(POWR) / HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
26 PX_V 0m NV_.U_0V_Y_Y 00 NV_U_V_K_ 00 0 NV_0.U_V_M_ 00 N_U_V_K_ 00 N_0.U_V_M_ 00 NV_0U_.V_M 00_XR PX_V PX_V NV_V L0 00m(nalog Power) 0m(Power rail) NV_0.U_V_M_ 00 (econdary internal core power) NV_000P_0V_M_ 00 PX_PLL_V NIVII F suggest to use 000p capacitor PX_PLL_V +VRUN 0m(.V Power rail PIO,I,PU IITL LOI) NVV_N.(Internal logic core power) NV_V F: N_ for NP power on issue. N_0.0U_V_K_ 00 N_N NM-T :.V(T) NV_0R-00MHZ_00 P M00 NV_.U_0V_Y_Y NV_0.U_V_M_ NV_000P_0V_M_ V NV_0.U_V_M_ NV_0.U_V_M_ NV_0.U_V_M_ L NV_0R-00MHZ_00 M00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 W NV_0U_.V_Y_Y NV_0.U_V_M_ NV_0.U_V_M_ NV_000P_0V_M_ V0 W V Y NV_000P_0V_M_ NV_000P_0V_M_ NV_000P_0V_M_ V V_LP V Y Y V NV_0.U_V_M_ 00 F P0 T0 T U0 U W0 U PX_V PX_IOV0 F m(frame uffer nalog Power) NV_V PX_IOV L0 F PX_IOV 0m (I/O Power) F T NV_PLLV PX_IOV NV_PLLV PX_IOV NV_0R-00MHZ_00 PX_IOV Place close to L0 M00 NV_U_V_K_ 00 NV_U_V_K_ 00 F F F F PX_IOVQ0 PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ PX_IOVQ0 PX_PLLV PX_PLLV PX_PLLN V_LP V_LP V_LP V_LP V_LP POWR V0 V V V V V V V_NR V K K N N N N N N0 P P P P R R T T T T U U U U U V V W W W Y Y Y0 NV_0.U_V_M_ 00 V_0 P V_ NV_0U_.V_M NV_0U_.V_M NV_0U_.V_M + NV_0U_.V_ NV_U_0V_Y_Y NV_000P_0V_M_ NV_0.U_V_Y V_ V_ 00_XR 00_XR 00_XR RTP0M _YV V_ V_ H V_ J V_ K 0 V_ L0 NV_PIO NV_0.U_V_Y NV_0.U_V_Y V_ N U TP MIL NV_0.U_V_Y L NFN 00_YV 00_YV V_0 N V TP MIL 00_YV L NFN V_ N V TP MIL M0 F_M TP MIL V_ N 0 NFN N TP MIL NFN TP MIL N W NFN H_PLLV is new power rail for NM TP_NFN N V TP0 MIL NFN0 TP MIL Nx Nx +VRUN 0 TP_NFN N N0 Y H NFN TP MIL 0.V wing.v wing N_T-LF PIF_PU N N W L J NFN TP MIL MIL TP NFN PIF N W NFN PX_V 0nF 0nF MIL TP NFN N N W TP MIL M NFN MIL TP NFN N N V TP MIL NV_0R-00MHZ_00 M Y NFN TP0 MIL FM0KF-T0 R. ohm No tuff MIL TP F_M N N Y0 F NFN TP MIL TP_NFN N N TP_F_PLLV NV_.U_0V_Y_Y R MIL TP NFN N N TP MIL NV_0.U_V_M_ U H_PLLV 00 NFN0 N N 00 MIL TP F_VRF TP MIL V N_.K_F MIL TP NFN N0 N U F TRP TP0 MIL R N_00K_J00 00 MIL TP _YN N N0 U TTMMLK TP MIL N N NM-T--/H PIF_IN NV_0.0U_V_M 00_XR NX update HON HI Precision Ind. o., Ltd. The trace impedance -F_M/ F_M: dditional memory address bit to FOXONN P - R& ivision R R0 of PIF_IN should support dual rank bank memory configuration. V(POWR) / be ohm +/- ohm N_._F N_.K_F -_YN: omposite sync for RT support ize ocument Number Rev NV_PIO: dditional PIO M0--0. ate: Tuesday, March, 00 heet of NV_0U_.V_M 00_XR NV_U_V_K_ 00 NV_000P_0V_M_ 00 V0 V V V V V V V V V0 V V V V V V V V V V V V NV_0.U_V_Y_Y 00 NV_.U_0V_Y_Y 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 N_000P_0V_K_ 00
27 +_VRUN Place around the VRM U NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_000P_0V_M_ 00 +_VRUN +_VRUN Place around the VRM U NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 +_VRUN NVbit_0.U_V_M_ 00 0 NVbit_0U_.V_M 00_XR NVbit_0.U_V_M_ 00 NVbit_000P_0V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_000P_0V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_000P_0V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 0 NVbit_0U_.V_M 00_XR NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 0 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_0.U_V_M_ 00 NVbit_000P_0V_M_ 00 NVbit_000P_0V_M_ 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision VRM(YP) / ize ocument Number Rev M ate: Tuesday, March, 00 heet of
28 +_VRUN Place around the VRM U NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 +_VRUN. +_VRUN Place around the VRM U NV_0U_.V_M 00_XR NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 0 NV_0U_.V_M 00_XR 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 0 NV_0.U_V_M_ 00 0 NV_000P_0V_M_ 00 +_VRUN NV_0.U_V_M_ 00 NV_000P_0V_M_ NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_0.U_V_M_ 00 NV_000P_0V_M_ 00 0 NV_000P_0V_M_ 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision VRM(YP) / ize ocument Number Rev M ate: Tuesday, March, 00 heet of
29 NV_RN M_ R NV_0_J 00 R _0_J 00 TV Y_OUT R 0_F 00 0 P_0V_K_N 00 -VIO These compoent close to -Video connector within 00 mil R NV_0_J 00 TV OUT R 0_F 00 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 Y_OUT _OUT N _V_T# Y N N -VIO_P FOX_MH-FN-F _OUT Y_OUT +VRUN _V_T# +VRUN VR MLV00M0_VR +VRUN R NV_.K_J 00 Q emi-pnp NV_HMI_T_ emi-pnp( IN) +VRUN N L 0R-00MHZ_00 MMZ00T 0P_0V_J_N 00 0P_0V_K_ 00 NV_R M_ R0 _0_J 00 P_0V_K_N 00 L 0P_0V_K_ 00 PN0YR R NV_HMI_T_ Q NV_TU NV_.K_J 00 NV_TU NV_HMI_T_ 0 U0 N_MVHFT XT_V_N, R 0_J 00 R0 R0 0 V_RT_T# (RT) V_RT_T# _V_T# 0K_J 00 0K_J 00 U MVHFT FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision TVIN and OUT/emi-PnP# ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
30 +VRUN _HIFT_+VRUN NV_R M_R NV_RN M_RN NV_LU M_LU NV_VYN M_VYN NV_HYN M_HYN R NV_0_J 00 R _0_J 00 R NV_0_J 00 R _0_J 00 R NV_0_J 00 R _0_J 00 R NV_0_J 00 R _0_J 00 R0 NV_0_J 00 R0 _0_J 00 V_R V_RN V_LU VVYN HYN_IN 0 NV_I_L M_LK 0 NV_I_ M_T 0 0.U_V_Y 00_YV R NV_0_J 00 R _0_J 00 0.U_V_Y 00_YV R NV_0_J 00 R _0_J 00 +VRUN +VRUN R.K_J 00 R.K_J 00 +VRUN R0 00 0_J 0 0.U_V_Y 00_YV HYN_IN VVYN 00 M_LK J_R J_LU J_RN M_T U V_VIO V_ VIO_ V_YN VIO_ VIO_ YP 0 _IN _OUT _IN YN_IN YN_IN M00-0QR _OUT YN_OUT YN_OUT N 0.U_V_M_ U_V_M_ M_RT_LK_R M_RT_T_R PR_V_HYN VYN 0 0.U_V_Y 00_YV _HIFT_+VRUN +VRUN _HIFT_+VRUN V_LU V_RN V_R R 0_F 00 J_LU J_RN J_R M_RT_LK V_RT_T# TP_V_I VYN RT_+VRUN HYN M_RT_T TP_V_I0 RT ONNTOR PR_V_HYN VYN HYN VYN R 0_J 00 M_RT_LK M_RT_LK_R For MI R 0_J 00 M_RT_T M_RT_T_R _HIFT_+VRUN R 0_F 00 R 0_F 00 0P_0V_J_N 00 0P_0V_J_N 00 P_0V_J_N 00 R.K_J 00 0P_0V_J_N 00 V_RT_T# L L L 0R-00MHZ_00 M00 0R-00MHZ_00 M00 0R-00MHZ_00 M00 0P_0V_J_N 00 F V-._0 M0P0TF 0 0 PTH PTH N -U_P FOX_Z-M-F R _J 00 R _J 00 P_0V_J_N 00 R.K_J 00 V_RT_T# 0P_0V_J_N 00, N_XT_V_N# emi-pnp( out) Q0 TU TPT +VRUN FOXONN RT HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet 0 of
31 LV roup,roup should be close roup roup 00_PR 00_PR O_LKIN- NV_O_LKIN- M_O_LKIN- O_LKIN+ NV_O_LKIN+ M_O_LKIN+ NV_0 RP _0 RP 00_PR 00_PR O_RXIN0- NV_O_RXIN0- M_O_RXIN0- O_RXIN0+ NV_O_RXIN0+ M_O_RXIN0+ NV_0 RP _0 RP 00_PR 00_PR NV_O_RXIN- O_RXIN- M_O_RXIN- O_RXIN+ NV_O_RXIN+ M_O_RXIN+ NV_0 RP0 _0 RP 00_PR 00_PR O_RXIN- NV_O_RXIN- M_O_RXIN- O_RXIN+ NV_O_RXIN+ M_O_RXIN+ NV_0 RP _0 RP 00_PR 00_PR O_RXIN- NV_O_RXIN- M_O_RXIN- O_RXIN+ NV_O_RXIN+ M_O_RXIN+ NV_0 RP _0 RP 0 N_0.U_0V_K_ 00 INV_N_ NV_RJ N_RJ Place 0 and close to N. +VRUN U_V_Y 00_YV 00 NV_0_J _0_J 00 R R N_0_J 00 R TOUT 0.U_0V_K_ 00 RJPWM_LPF 0 +VRUN TOUT 0.U_0V_K_ 00 INV_NL INV_RJ U0 INVRTR ONN. H0W LV O_LKIN+ O_LKIN- O_RXIN+ O_RXIN- O_RXIN+ O_RXIN- O_RXIN+ O_RXIN- O_RXIN0+ O_RXIN0- restline () stuff R.no stuff R. restline () stuff R.no stuff R. U +VRUN H0W LV ONNTOR INV_NL R 0K_J 00 VT use 0pin VT modify to 0pin U INV_NL_ +VRUN +VRUN (.V tolerant) H0W M_LV_N PNL I +VRUN R 0K_J 00 MFIX MFIX FOX_H0F HR_P N 0.U_V_M 00_XR FOX_0-0-F FP_0P 0 0 N NPTH NPTH MFIX MFIX MFIX MFIX INV_N_ W H0-_W-LI LI0 LI LI LI,, LIIN# 0 NV_INV_N M_LV_N 0 NV_LV_N# R NV_K_J 00 U V N N NV_HW R _0_J 00.U_.V_K 00_XR R _0_J 00 LV R _00K_J U 00 R Vender amsung ( lamp) PT ( lamp) UO ( lamp) UO ( lamp) IN 00 OUT IN evice Name LTNX-L0 LW0N W0 QTL0 R0 N IN N IN IHR LV KU R N_0_J THRML P Panel I [..0] RU_V0. HH/H/M 0K ohm Q R IN N J LOW 00K ohm N_M0T N_.K_J LI is for InstantOn switch 00 nable: 0 0 R isable: 0.U_V_Y_Y.U_0V_Y_Y 00 00_J Q R NV_LV_N# 00 NV_0.U_V_Y_Y N_K_J R 00 N_0K_J 00 N_MMT0 IHR HON HI Precision Ind. o., Ltd. The R will consume about FOXONN P - R& ivision 0.0 Watt (.x./00 = LV 0.0W). We changed resistor ize ocument Number Rev to 00 size (/ Watt) M0--0. ate: Tuesday, March, 00 heet of R0 00K_J 00 M_INV_N +VRUN Type ize WX."W WX."W WX."W WX."W
32 +VRUN PI_FRM# PI_TOP# PI_RR# PI_TRY# PI_PRR# PI_LOK# PI_RQ# PI_VL# +VRUN +VRUN 0_0PR INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# RP.K RP 0_0PR.K RP.K 0_0PR PI_IRY# PI Pullups +VRUN PI_RQ#0 INT_PIRQH# INT_PIRQ# INT_PIRQ# +VRUN +VRUN INT_PIRQF# PI_[..0] INT_PIRQ# INT_PIRQ# INT_PIRQ# U PI_0 0 PI_ 0 PI_ PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 0 PI_ PI_ F PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# F 0 PI Interrupt I/F PIRQ# PIRQ# PIRQ# PIRQ# IHM-QN RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IRY# PR PIRT# VL# PRR# PLOK# RR# TOP# TRY# FRM# F 0 F F0 F F PI_RQ#0 PI_NT#0 PI_RQ# R.K_J 00 +VRUN PI_NT# 0MIL TP PI_RQ# +VRUN PI_NT#R.K_J 00 0MIL TP0 PI_RQ# R00 PI_NT# 0MIL TP0 PI_/#0 PI_/# PI_/# PI_/# PI_IRY# PI_PR PI_RT# PI_VL# PI_PRR# PI_LOK# PI_RR# PI_TOP# PI_TRY# PI_FRM# PLT_RT# PLTRT# 0 LK_IHPI PILK PI_PM# PM# PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO INT_PIRQ# INT_PIRQF# INT_PIRQ# INT_PIRQH# PI_/#0 PI_/# PI_/# PI_/# PI_IRY# PI_PR PI_RT#, PI_VL# PI_PRR# PI_RR# PI_TOP# PI_TRY# PI_FRM# N_K_J 00 PLT_RT#,,,,,,,0,,,, LK_IHPI PI_PM# 0MIL TP PI_RQ#0 PI_NT#0 For oot IO election. trap for oot-io LP(efault) PI NT0# Hi Hi PI_# Hi LOW PI LOW Hi elete signal For ocking onnector LN_RXN LN_RXP LN_TXN LN_TXP ROON_RXN ROON_RXP ROON_TXN ROON_TXP XPR_RXN XPR_RXP XPR_TXN XPR_TXP 0 MINI_RXN 0 MINI_RXP 0 MINI_TXN 0 MINI_TXP For oot IO election. N_0.U_V_M_ 00ROON_TXN_ 0 N_0.U_V_M_ 00ROON_TXP_ 0.U_V_M_ 00XPR_TXN_ 0.U_V_M_ 00XPR_TXP_ 0.U_V_M_ 00LN_TXN_ 0.U_V_M_ 00LN_TXP_ R N_K_J 00 0.U_V_M_ 00 0.U_V_M_ 00 TP0 0MIL TP 0MIL TP 0MIL TP 0MIL, U_O#0 U_O# U_O# U_O# U_O# MINI_TXN_ MINI_TXP_ TP 0MIL TP0 0MIL TP 0MIL TP 0MIL TP_PRN TP_PRP TP_PTN TP_PTP TP 0MIL TP 0MIL TP_PI_R TP 0MIL TP 0MIL U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# P P N N M M L L K K J J H H F F F H U PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP PRN PRP PTN PTP IHM-QN PI-xpress PRN/LN_RXN PRP/LN_RXP PTN/LN_TXN PTP/LN_TXP PI_LK PI_0# PI_# PI_MOI PI_MIO J O0# O#/PIO0 O#/PIO O#/PIO F O#/PIO O#/PIO O#/PIO0 J O#/PIO O# O# PI irect Media Interface U MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN MI_LKP MI_ZOMP MI_IROMP V V U U Y Y W W T T Y Y UP0N UP0P UPN H UPP H UPN H UPP H UPN J UPP J UPN K UPP K UPN K UPP K UPN L UPP L UPN M UPP M UPN M UPP M UPN N UPP N URI# URI F F MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_OMP U_PN0 U_PP0 U_PN U_PP U_PN U_PP 0MIL TP 0MIL TP0 U_PN U_PP U_PN U_PP 0MIL TP 0MIL TP U_PN U_PP U_PN U_PP 0MIL TP 0MIL TP R URI._F 00 MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH R._F 00 U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP Place within 00 mils of IH +_V_PI +VLW MLINK0 MLINK0 U_O# U_O# U_O# 0 RP 0K 0_0PR U_O# U_O# U_O# U_O# Place within 00 mils of IH and don't routing next to high speed signals FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH-M( PI/MI/U/PI ) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
33 HR_P FOX_H0 IH_ITLK RTRT# VccRT heck resistor value N0 0 +V R _J 00 R0 _J 00 Min : ms R0 0_F 00 R 0_F 00 00V-0-LF +_V_PI R0._F 00 T_L# VRT R M_J 00 U_.V_Y 00_YV R 0K_J 00 Within 00 mils of the IHM,and avoid routing next to clock pins. +VRUN H_M_ITLK R0 0K_J 00 T_RXN0 T_RXP0 T_TXN0 T_TXP0 H_O_ITLK.KHZ_.P_0PPM QM00000 The traces inside this block should be wider. No digital signals routed under XTL 00 P_0V_K_N LK_KX Y LN_OMP mils J INTVRMN LN00_LP OPN_JUMP_OPN TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL TP 0MIL IH_ITLK IH_YN IH_RT# H_O_TIN0 H_O_TIN0 H_M_TIN H_M_TIN TP_H_IN TP 0MIL TP_H_IN TP0 0MIL 00P_V_K_00 00P_V_K_ P_V_K_00 00P_V_K_00 IH_TO H_OK_N# TP 0MIL _OUT T_RXN0_ T_RXP0_ T_TXN0_ T_TXP0_ TP 0MIL TP 0MIL TP 0MIL TP00 0MIL R 0M_J 00 P_0V_K_N 00 LK_KX LK_KX_R R 0_J 00 RTRT# M_INTRUR# U_.V_M_ 00 LK_PI_T# LK_PI_T TP 0MIL R0._F 00 Within 00 mils of the IHM,and avoid routing next to clock pins. F F 0 0 H J J J H H 0 F0 F F H H J J U RTX RTX RTRT# INTRUR# F INTVRMN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_OK#/PIO LN_OMPI LN_OMPO H_IT_LK H_YN H_RT# H_IN0 H_IN H_IN H_IN H_OUT TL# T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP F TRXN F TRXP TTXN TTXP T_LKN T_LKP TRI# TRI IHM-QN IH-M Internal VR nable trap (Internal VR for Vccus_0, Vccus_, VccL_) INTVRMN H_OK_N#/PIO H_OK_RT#/PIO IH LN / LN RT I PU LP T Low= Internal VR isabled High= Internal VR nabled(efault) FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRM# LRQ0# LRQ#/PIO 0T 0M# PRTP# PLP# FRR# PUPWR/PIO INN# INIT# INTR RIN# NMI MI# TPLK# THRMTRIP# F F F F F 0 H INTVRMN LP_0 LP_ LP_ LP_ LP_FRM# LP_RQ#0 0MIL TP H_0T H_0M# H_PWR H_INN# H_INIT# H_INTR H_RIN# H_NMI H_MI# H_TPLK# PM_THRMTRIP_R TP 0MIL TP I_P[0..] I_P0 0 V I_P U I_P V I_P T I_P V T I_P I_P T I_P T I_P R I_P T I_P0 0 V I_P V I_P U I_P V I_P U I_P 0 # # IOR# IOW# K# IIRQ IORY RQ Y Y W W Y Y Y W I_P0 I_P I_P I_P# I_P# VRT R0 K_F 00 R0 N_0_J 00 LP_0,, LP_,, LP_,, LP_,, +VRUN IH-M LN00_LP trap (Internal VR for VccLN_0 and VccL_0) LN00_LP LP_FRM#,, LP_RQ#0 H_0M# H_RIN# Low= Internal VR isabled High= Internal VR nabled(efault) +_0VRUN R _J 00 H_PWR H_INN# H_INIT# H_INTR I_P0 I_P I_P +_0VRUN H_0T R0 N J 00 +_0VRUN +VRUN +VRUN R N J 00 +VRUN LN00_LP R N_0_J 00 R N_0_J 00 VRT 0K_J 00 R R0 K_F 00 R N_0_J 00 H_RIN# H_0T _OUT I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ H_NMI H_MI# 0MIL TP H_TPLK# R _J 00 I_P[0..] Q0 Q0 N00 N00 H_PRTP#,, H_PLP# H_FRR# R 0K_J 00 _RIN#, _0T, _OUT R 0K_J 00 R0 IH_TO R _J 00 R _J 00 H_M_TOUT H_O_TO IH_RT# R0 _J 00 R _J 00 H_M_RT# H_M_YN H_O_RT# H_O_YN R0 _J 00 IH_YN R _J 00 N_K_J 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH-M( LP,I,T ) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
34 +VLW, +VLW U_O#0 U_O# U_O# PM_RI# M_PWRN R 0K_J 00 PM_RMRT# R 0K_J 00 IMVP_PWR R 0K_J 00 TP_PIO0 R 0K_J 00 _RT# R 0K_J 00 PM_YRT# R 0K_J 00 M_LRT# R 0K_J 00 TLOW# R.K_J 00 PI_WK# R K_J 00 XTMI# R 0K_J 00 WK_I# R0 0K_J 00 +VRUN U_O#0 U_O# U_O# R 0K_J 00 N_0U_.V_M 00_XR _THRM# R0.K_J 00 RUNTIM_I# R0.K_J 00 INT_RIRQ R.K_J 00 PM_LKRUN# R.K_J 00 PI R.K_J 00 PI R.K_J 00 I_LP_PI# R 0K_J 00 M_LK_U R.K_J 00 M_T_U R0.K_J 00 0 RP0 0K 0_0PR INV_N_ PI_XPR_WK# MLINK Q0 0, PI_WK# +VU N_N00 R 0_J 00,,, M_LK_U,,, M_T_U 0 M_LINK_LRT# MLINK0,,, INT_RIRQ PM_U_TT# PM_MUY# PM_TPPI# TP_PU#,,, PM_LKRUN# tuff for No-reboot Low=efault High=No-reboot M_LK_U M_T_U M_LINK_LRT# MLINK0 MLINK PM_RI# PM_TPPI# TP_PU# PM_LKRUN# INT_RIRQ _THRM# VRMPWR J H_PKR U IHM-QN +VRUN R N_K_J 00 PM_U_TT# F PM_YRT# U_TT#/LPP# Y_RT# PM_MUY# M_LRT# MUY#/PIO0 MLRT#/PIO 0 0 Port I/F: TP 0MIL TP_PIO J R0 H: LP bus TH/PIO I_LP_PI# J N_0_J L: PI bus TH/PIO, RUNTIM_I# H 00 TH/PIO, XTMI# R 0_J 00 PIO,,,, OVT_# TP 0MIL TP_PIO PIO TP 0MIL TP_PIO TH0/PIO H TP 0MIL TP_PIO0 PIO TP0 0MIL TP_PIO PIO0 0 +VRUN INV_N_ LOK/PIO H M_PWRN QRT_TT0/PIO QRT_TT/PIO TLKRQ# TLKRQ#/PIO LI F LO/PIO LI J TP 0MIL TP_PIO TOUT0/PIO 0 TOUT/PIO R0 0K_J H_PKR H_PKR 00 PKR MH_IH_YN# J R 0K_J MH_YN# 00 J TP F H F J0 J R N_K_F 00 MLK MT LINKLRT# MLINK0 MLINK RI# TP_PI#/PIO TP_PU#/PIO LKRUN#/PIO WK# RIRQ THRM# VRMPWR TP M Y PIO PIO MI T PIO locks LN_RT# R 0K_J 00 R N_0_J 00 IMVP_PWR chematic check list suggestion J PI J0 F PI LI LK_IH LK_U 0/: Intel F suggest follow design guide, connect LN_RT# to Vss if no integrated lan. ULK U_LK 0MIL TP LP_# R LP_# 00_J 00 PM_LP_#,, F LP_# R LP_# 00_J 00 PM_LP_#, LP_# R 0_J 00 LP_# PM_LP_#, 0MIL _TT#/PIO H TP R 00_J Review R and R resistor value PWROK IMVP_PWR_ 00 IMVP_PWR, PRLPVR/PIO J 0 R 0_J 00 PRLPVR, TLOW# TLOW# PWRTN# PWRTN#, R LN_RT# H0 LN_RT# N_00K_J R 00_J 00 RMRT# PM_RMRT#_ 00 PM_RMRT#, K_PWR LK_PWR_IH LK_PWR R 0_J 00 LK_PWR LPWROK MPWROK LP_M# J TP_LP_M# 0MIL TP L_LK0 F L_LK0 L_LK L_LK L_LK 0 L_T0 F L_T0 F L_T L_T L_T 0 L_VRF0_IH L_VRF_IH 0MIL TP 0MIL TP WK_I#, _RT# +VRUN MPWROK IMVP_PWR R 0_J 00 onnect LPWR to existing PWROK inputs on IHM L_VRF ~=0.0V 0 LK_U R N_0_J 00 +VRUN +VLW +VU R R N_.K_F.K_F M_LK_U M_T_U +VRUN 0.U_V_Y 00_YV PM_RMRT#_ 0 M VT uto power on solution PT IMVP_PWR_ LW_PWR,, M PVT 00V-0-LF RT timer stop solution.-> PWR_OK glich +VRUN R K_J 00 U R N_.K_F 00 Power MT ontroller Link T0P/PIO TP/PIO TP/PIO TP/PIO LK LK L_VRF0 L_VRF L_RT# R N_0_J00 H J R N_0_J 00 TP_PIO LPIO0/PIO J J TP_PIO0 LPIO/PIO0 LPIO/PIO F WOL_N/PIO LK_IH LK_U R N_00K_J 00 U_PWR_0M,,,,, PLT_RT#,,,,,,,0,,,, L_RT#0 LI0 R 0K_J 00 R 0K_J 00 LI 0.U_V_M_ 00 N_0P_0V_J_N 00 R _F 00 U V L V WP 0 PROM_OP-_x HTL0 LW_PWR,, V N N_0.U_V_M_ 0 00 R N F 00 _LK_N# VRMPWR_R VRMPWR_R VRMPWR N HW R0,, IMVP_OK R 0_J 00 VRMPWR R N_0_J 00 00K_J 00 VRMPWR_R LK_PWR R N_0_J 00 FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision IH-M( PIO) / ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
35 +VLW R0 0_J 00 +VRUN +VLW 00V-0-LF 0.U_V_Y_Y 00 +_VRUN +VRUN R 0_J 00 R N_0_J 00 R 00_J 00 +VRUN +_VRUN R 0_J 00 +V._PLL_IH_R VRT. for all V_ +_VRUN 0.U_0V_K 00_XR 0.U_V_Y_Y 00 00V-0-LF R _F 00 +_V_PI L 0R-00M_0 HKF-T0.U_V_K 00_XR P0 TP0ML 0U_.V_ 0 0U_0V_M 0.U_V_Y_Y 00 L 0UH_00 L0-00K 0.U_V_Y_Y V._PLL_IH VLN_ L VLNPLL UH_00 FI0F-R0K 0 0uF_0%_.V_XR +VRUN U_0V_Y 0_YV 0.U_V_Y_Y 00 VRF VRF_U +_V_PI 00_XR 0 U_0V_Y_Y 00 R 0_J 00 0 U_0V_Y 0_YV u m m 0 U_0V_Y_Y 00 U_0V_Y_Y 00 m 0.U_V_Z 00_YV m 0m 0m m.u_v_z 00_YV 0.U_V_Y_Y 00 TP 0MIL 0m +V._LN_IH m UF VRT IHM-QN T J F H J 0 F L L M M W F F 0 VRF[] VRF[] VRF_U V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] F V [] F V [] V [] H V [] H V [] J V [] J V [] K V [] K V [0] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [0] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V [0] U V [] V V [] V V [] V V [] W V [] Y V [] VTPLL V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] V [] V [] V [] V [] V [] H V [] V [] V [] VUPLL V [0] V [] V [] V [] V [] V [] VLN_0[] VLN_0[] VLN_[] VLN_[] VLNPLL VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_ OR VP RX TX VP_OR I PI VPU U OR VPU LN POWR V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] F L L L L L L M M P P T T V_0[] U V_0[] U V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] R F V_[0] V_[0] V_[0] V_[0] F V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VH VUH VU_0[] VU_0[] VU_[] VU_[] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VL_0 VL_ VL_[] VL_[] U V W W W Y 0 F J F0 J 0 H P P N P P P P P R R R R F0 VU_0 VU_ VccL_0 VccL_ 0.UF 0% VMIPLL_IH 0.0U_V_K 00_XR m 0.UF 0% 0.UF 0% 0.UF 0%. m 0m m m for all V_ m m m for all VU_ 0.UF 0% 0 0.UF 0%.U_V_K 00_XR 0.UF 0% 0.UF 0% 0MIL TP 0 0.UF 0% N_U_0V_Y_Y 00 +VRUN 0.UF 0% FOXONN L VMIPLL_IH_R UH_00 FI0F-R0K 0 0uF_0%_.V_XR 0.UF 0% N_0.UF 0% N_0.UF 0% 0.UF 0% TP 0MIL IH-M( POWR) / 00 N_0.0U_V_K_ 0MIL TP N_0.UF 0% N_0.UF 0%.U_0V_Y 00_YV +VLW U_0V_Y 0_YV 0 0.UF 0% 0.UF 0% P 0U_V_M.x. R _F 00 In non Intel MT systems, these rails should be powered at a minimun in 0-state since PI functionality is power from these wells. HON HI Precision Ind. o., Ltd. P - R& ivision ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of +_0VRUN +_VRUN +_VRUN +_0VRUN +VRUN +VLW +VRUN
36 M0--0. IH-M( N) / Tuesday, March, 00 ize ocument Number Rev ate: heet of HON HI Precision Ind. o., Ltd. P - R& ivision FOXONN U IHM-QN 0 F F F F F H0 H H H H F H H H H H H J 0 F F F F 0 H H H H H J J J J J J K K K K K L L L L L L L M M M M M M M M M M N N N N N N N N N N N N N N P P P P P P P P P R R R R R R R R R R T T T T T T T U U U U U U U U U U U V V V V W W W Y Y Y H H J J J J U K W V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[0] V_NTF[] V_NTF[] V[] V[0] V[] V[] V[] V[0] V[]
37 0.U_V_M_ 00 +VRUN 0.U_V_M_ 00 T_TXP0 T_TXN0 T_RXN0 T_RXP0. P + N_U_0V_0 0TPM 0U_0V_M 00_XR R0 0_J N TX TX# RX# RX V_._ V_._ V_. P V_.0 P V_.0_ V_.0_ P_RRV_ V P V V N_M N_M N_M N_M_P_ N_M_P_ N_M_P_ N_M_P_0 N_M_P_ PTH PTH NPTH NPTH RIL T RPTL_P FOX_LH-L T H ONN +VRUN +VRUN I_P[0..] I_P[0..] R R R R. +VRUN O must Master I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW#,,,,,,,0,,,, H: lave L: Master R 0_J 00 PLT_RT# L I_P# I_P0 I_P INT_IRQ I_PIORY I_PIOW#.K_J 00 R _J 00.K_J 00 O_RT# VR N_.K_J 00 I_P0 I_P I_P I_P I_P I_P I_P I_P N_.K_J 00 PTH_ PTH_ N N_ N_ 0 L N_ N_ N_ N_ N_ +V_ +V_ +V_ +V_ 0 P# +V_ FX# FX# 0 PI# 0 INTRQ IO# IORY MK# IOW# N_ N_ IOR# 0 MRQ RT# UIO_N N_ UIO_L UIO_R TO _0P FOX_QTH00-R-F 00 0U_0V_M 00_XR I_P# I_P IO# I_PK# I_PIOR# I_PRQ I_P I_P I_P I_P I_P I_P0 I_P I_P 0 000P_0V_M_ 00 I_P# I_P PI I_PK# I_PIOR# I_PRQ 0 0.U_V_Y_Y 00 R 0K_J 00 / Follow doi san suggest O: Master/H:lave MLV00M0_VR For. -ROM ONN FOXONN HON HI Precision Ind. o., Ltd. P - R& ivision T H/-ROM ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
38 RP 0K 00_PR +V R 00K_J 00 LIIN# TT_PR# +VLW IN RP 0K 00_PR, PWRW# +V +VLW PWRW# 00 0.U_V_Y 00_YV R0 N_.K_J 00 U +V_L R 0_J 00+V_R V R 0_J 00 INT_RIRQ LP_FRM# LP_0 LP_ LP_ LP_ LK_KPI PM_LKRUN# U_PWR_0M PLT_RT# _RIN# _0T RUNTIM_I# RT# KI0 KI KI KI KI KI KI KI KO0 KO0 KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO0 KO0 KO KO KO KO KO KO KO KO, KO KO KO KO TP00 0MIL N N N N N N N RIRQ LFRM# L0 L L L LLK LKRUN#/PIO0 PIO0 LRT#/PIO KRT#/PIO0 0/PIO0 I# RT# KI0/PIK0 KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK KI/PIK KO0/POK0 KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK KO0/POK0 KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK KO/POK 00 TP 0MIL, XT_V_N XT_V_N TT_PR_#, PM_THRM# 0,, LIIN# LIIN# 0, T_WLN_W# TT_PR_# Q TT_PR_# N00W--F 0MIL TP LK_M 0 T_M PLK LK_KM PT T_KM PLK +VRUN LK_TP PT, LK_TP T_TP PLK, T_TP INT_MI_T_R# PT, INT_MI_T# R00 0_J 00 Q0 0/PI0, T_PR# N_N00 /PI TP 0MIL R0 0_J 00 0 /PI,, LW_PWR /PI TP 0MIL R00 R0 /PI TP 0MIL N_0_J N_0_J TP0 /PI 0MIL /PI TP 0MIL 0 R 0_J 00 IMVP_PWR_ /PI N_XT_V_N# PIO0 0, N_XT_V_N# PIO0,, R_LRT# TOUT/PIOF TP 0MIL,, IMVP_OK R 0_J 00 RUN_ON, RUN_ON R0 K_J 00 TP 0MIL 0, T_00, LK_00,,,, OVT_# R 0_J 00 R0 K_J 00 TP0 0MIL,, PM_LP_# PM_LP_#, PM_LP_# PM_LP_#, PM_LP_# PM_LP_# 0, PM_RMRT# PM_RMRT# R_PWR PIO, R_PWR 0 PIO, RUN_ON +VLW PIO TP 0MIL RUN_PWR PIO, RUN_PWR U_ON PIO,, U_ON NH# PIO, NH# IN_ PIO IN_ RUN_ON PIO,,,, RUN_ON IN_ PWRTN# PIO, PWRTN# PIO N00W--F Q +VU,,, INT_RIRQ,, LP_FRM#,, LP_0,, LP_,, LP_ RP,, LP_ 0K, LK_KPI 00_PR,,, PM_LKRUN#,,,,, U_PWR_0M LK_M LK_KM LK_TP,,,,,,,0,,,, PLT_RT# T_M T_KM T_TP, _RIN#, _0T, RUNTIM_I# PM_LP_# R 00K_J 00, RT# PM_LP_# R 00K_J 00 PM_LP_# R 00K_J 00 RUN_ON R 00K_J 00 U_ON R 00K_J 00, LW_ON R0 00K_J 00, RUN_ON R 00K_J 00, XIO_F R 00K_J 00, IMVP_OK R0 00K_J 00, RUN_ON R0 00K_J 00,,, IMVP_PWR 0 IMVP_PWR_ LK_M_R T_M_R NLO_V KXLKO KXLKI 0 00 LW_ON_R R00.K_J 00 KI0 KI KI KI KI KI KI KI PWU0 PWU PWU PWU PWU PWU PWU/TIN PWU/TIN/FNF PIO0 PIO0/FNPWM/TT_TP PIO0/FNF/PLL_TP PIO0 PIO0 PIO0 PIO0 PIO PIO PIO PIO K0F V V V V V V V XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIO#/PIO XIOF#/PIOF NLO_V YTM_I0 YTM_I YTM_I YTM_I YTM_I YTM_I XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F LW_ON_RR K_J 00 M_THRM_LK M_THRM_LK, M_THRM_T M_THRM_T, LK_M_R LK_M T_M_R R 00_J 00 T_M R 00_J 00 XTMI# XTMI#, WK_I# WK_I#, FN_PWM FN_PWM, 0MIL TP _OFF, 0MIL TP0 IMVP_VR_ON IMVP_VR_ON, 0MIL TP FN_TH 00 onsider short F after test. 00_RT#, UPN_L UPN_L, POWR_L POWR_L, TTRY HRIN L# TTRY HRIN L#, PK_MUT_N_R R0 0_J 00 PK_MUT_N, WLN_N 0, T_ON, HW_POP_MUT_, PWRLIMIT#, 0 R 0_J 00 OVT_FX# RX RX, TX TX, 0MIL TP KXLKO N_0M_J 00 Y.KHZ_.P_0PPM QM P_0V_J_N P_0V_J_N V N 0 0 0/PIO 0 R# WR# IO# MM# L L PWM0/POW0 PWM/POW PWM/POW/FNPWM PWM/POW PWM/POW PWM/POW PWM/POW PWM/POW/FNPWM FNF/TOUT/PIO PLOK#/PIO FNLOK#/PIO ROLLLOK#/PIO0F NUMLOK#/PIO0 0/PO0 /PO /PO /PO /PO /PO /PO /PO IT0/PIO00 IT/PIO0 RX/PIO TX/PIO #/PIO0 XLKO XIO_F0 XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F XIO_F FR# FWR# IO# MM# KXLKI XLKI FR# FWR# 0MIL TP MM# 000P_0V_K P_L#, 0MIL TP ROLL_LOK_L#, NUM_LOK_L#, R 0_J 00 R U_.V_Y 00_YV 0MIL TP 0MIL TP YTM_I0 YTM_I YTM_I YTM_I YTM_I YTM_I XIO_F[..0] 00_XR L 0.U_V_Y 00_YV LW_ON,,, XIO_F[..0] FN_TH, 0R-00MHZ_00 MMZ00T 0U_.V_Y_Y 00 FOR MI 0.U_V_Y 00_YV Reserve for NM's internal thermal sensor. M0 & M0 PIO ifferent Table K NN ystem I table check with software define I +V_L LK_M R.K_J 00 T_M R.K_J 00 +V R N_0_J 00 M_THRM_T M_THRM_LK R N_0_J 00 +V R0 K_J 00 R0 K_J 00 XIO_F XIO_F +VLW R 00K_J 00YTM_I0 R _00K_J 00YTM_I R 00K_J 00YTM_I R 00K_J 00YTM_I R 00K_J 00YTM_I R0 00K_J 00YTM_I I I I I I0 L 0 H FOXONN R0 0_J 00 0.U_V_Y 00_YV I_ I_L N MFIX MFIX 0 0 R N_K_J KI0 KI KI KO0 KO KO KI KO KO KO KO KO KO KI KO KI KI KO0 KI KO KO KO KO KO +V FP_P P-TWO_00-0 R N_00K_J 00 R0 NV_00K_J 00 R N_00K_J 00 R N_00K_J 00 R N_00K_J 00 R N_00K_J 00 HON HI Precision Ind. o., Ltd. P - R& ivision +K ize ocument Number Rev M0--0. ate: Tuesday, March, 00 heet of
Schematics Page Index (Title / Revision / Change Date)
Page 0 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page chematics Page Index lock iagram LOK N (K0) MROM(HOT U) / MROM(HOT U) / MROM(Power/nd) / restline (HOT) / restline (MI) / restline (RPHI) / restline (RII)
- - SA - - SA. Project Code & Schematics Subject: MS31/51 Main Board. Rev. Page Charger (MAX1909)
Page 0 0 0 0 0 0 0 0 0 0 0 0 chematics Page Index ( / Revision / hange ate) of chematics Page chematics Page Index lock iagram Yonah(HOT U) / Yonah(HOT U) / Yonah(Power/nd) / LITO (HOT) / LITO (MI) / LIT
Schematics Page Index (Title / Revision / Change Date) Rev.
Page 0 0 0 0 0 0 0 0 0 0 0 0 0 of chematics Page Index page LOK IRM LOK EN (LL) Penryn(HOT U) / Penryn(HOT U) / Penryn(HOT U) / antiga (HOT) / antiga (MI) / antiga (RPHI) / antiga (RII) / antiga (POWER,V)
Page. 49 VRAM(BYPASS) 50 SDVO TO LVDS 51 LVDS-Inverter
Page 0 0 0 0 0 0 0 0 09 0 9 0 9 0 9 of chematics Page Index Page lock iagram(ystem) LOK N PU HOT / PU THRML / PU POWR / aglelake HOT/PI- / aglelake V/MI / aglelake RII H / aglelake RII H / aglelake POWR
Spears Intel UMA Block Diagram
pears Intel UM lock iagram 00/0/ PU / IL LK N ILPR Intel PU Merom M F:MHz/00MHz,, Project code :.W00.00 P P/N : 0 Revision : - INPUT OUTPUT TOUT _OR YTM / TP R RT RT INPUT OUTPUT Host U /MHz LV L TOUT
Intel CPU. Penryn SV 3,4,5. FSB 800/1066MHz. Cantiga-PM. nvidia INTEGRATED GRAHPICS LVDS, CRT I/F. PCIE x 16 6,7,8,9,10,11 C-LINK INTEL ICH9-M
/MM M/M Pro/x RJ ONN RJ ONN LIN OUT MI IN INTRNL MI VIT lock iagram lock enerator ILPR RII /00 lot 0 RII /00 Realtek RT lot Realtek RTL0-R 0/00 MOM MOM X0-Z H UIO O X0-Z RII /00 hannel R II /00 hannel
2 HBU Intel UMA Block Diagram. Intel CPU. Penryn SV 3,4,5. FSB 800/1066MHz RGB CRT. Cantiga-GM/GL AGTL+ CPU I/F
/MM M/M Pro/x RJ ONN RJ ONN LIN OUT MI IN INTRNL MI HU- Intel UM lock iagram lock enerator ILPR RII /00 lot 0 RII /00 Realtek RT lot Realtek RTL0T 0/00 MOM MOM X0-Z H UIO O X0-Z RII /00 hannel R II /00
Thermal Sensor LM26 5. Keyboard Light 12.1'' XGA LCD 19 LVDS CRT SELECTION RGB CRT USB 2.0 CH3 RICOH R5C847 IEEE1394 CONN. Cardbus + SD Card +
March ' Thermal ensor MX0 LM I us / M us us witch I HP OUT MI ONN for ali Int. MI for K- MI IN Mus UNUFFR R OIMM Normal ocket 00-PIN R OIMM UNUFFR R OIMM Reverse ocket T H OP MP MX99 9 H UIO O 9JP,, M
FOXCONN. Schematics Page Index (Title / Revision / Change Date) Title of Schematics Page. Project Code & Schematics Subject: PCB P/N:
Page 0 0 0 0 0 0 0 0 09 0 9 0 9 0 9 0 chematics Page Index ( / Revision / hange ate) of chematics Page Page chematics Page Index LOK IRM N (MI,PE,FI) N (LK,MI,JT) N (R) N (POWER) N (RPHI POWER) 9 N (N)
COMPONENTS LIST BASE COMPONENTS
ITLIN TEHNOLOGY grifo PPENIX : R SSEMLY The GP F can be ordered in two different mode: completely mounted, tested and ready to use or in assembly kit. In this final condition the user can directly use
Surface Mount Multilayer Chip Capacitors for Commodity Solutions
Surface Mount Multilayer Chip Capacitors for Commodity Solutions Below tables are test procedures and requirements unless specified in detail datasheet. 1) Visual and mechanical 2) Capacitance 3) Q/DF
MIL-DTL Micro-D Connector R04J Series Straight to PCB Type
MIL-TL-353 Micro- onnector R4J Series Straight to P Type Specication MIL-TL-353 Micro- onnector nvironment temperature: ~ Vibration: Hz~Hz, 6m/s Random vibration: Power spectrum density.4g Hz root mean
Electrical Specifications at T AMB =25 C DC VOLTS (V) MAXIMUM POWER (dbm) DYNAMIC RANGE IP3 (dbm) (db) Output (1 db Comp.) at 2 f U. Typ.
Surface Mount Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz Features 3V & 5V operation micro-miniature size.1"x.1" no external biasing circuit required internal DC blocking at RF input &
Multilayer Ceramic Chip Capacitors
FEATURES X7R, X6S, X5R AND Y5V DIELECTRICS HIGH CAPACITANCE DENSITY ULTRA LOW ESR & ESL EXCELLENT MECHANICAL STRENGTH NICKEL BARRIER TERMINATIONS RoHS COMPLIANT SAC SOLDER COMPATIBLE* PART NUMBER SYSTEM
Multilayer Ceramic Chip Capacitors
FEATURES X7R, X6S, X5R AND Y5V DIELECTRICS HIGH CAPACITANCE DENSITY ULTRA LOW ESR & ESL EXCELLENT MECHANICAL STRENGTH NICKEL BARRIER TERMINATIONS RoHS COMPLIANT SAC SOLDER COMPATIBLE* Temperature Coefficient
NEC Silicon RFIC Amplifiers Low Power, Wideband & SiGe/SiGeC
NEC Silicon RFIC Amplifiers Low Power, Wideband & SiGe/SiGeC Low Power Amplifiers ELECTRICAL CHARACTERISTICS (TA = 25 C) Range VCC ICC NF Gain RLIN RLOUT PdB ISOL @ 3dB (V) (ma) (dbm) Part down Package
Applications. 100GΩ or 1000MΩ μf whichever is less. Rated Voltage Rated Voltage Rated Voltage
Features Rated Voltage: 100 VAC, 4000VDC Chip Size:,,,,, 2220, 2225 Electrical Dielectric Code EIA IEC COG 1BCG Applications Modems LAN / WAN Interface Industrial Controls Power Supply Back-Lighting Inverter
DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE
SPECIFICATION ORDER NO. LDD-00L LDD-0L LDD-00L LDD-00L LDD-700L CURRENT RANGE 00mA 0mA 00mA VOLTAGE RANGE Note. ~ VDC for LDD-00~700L/LW ; ~ 8VDC for LDD-00~700LS CURRENT ACCURACY (Typ.) ±% at VDC input
RF series Ultra High Q & Low ESR capacitor series
RF series Ultra High Q & Low ESR capacitor series FAITHFUL LINK Features Application» High Q and low ESR performance at high frequency» Telecommunication products & equipments:» Ultra low capacitance to
RSDW08 & RDDW08 series
/,, MODEL SELECTION TABLE INPUT ORDER NO. INPUT VOLTAGE (RANGE) NO LOAD INPUT CURRENT FULL LOAD VOLTAGE CURRENT EFFICIENCY (Typ.) CAPACITOR LOAD (MAX.) RSDW08F-03 344mA 3.3V 2000mA 80% 2000μF RSDW08F-05
Garda-5 Block Diagram
arda- lock iagram LK N. I YTM / Yonah (RTMT-00/YR00) TPRR P TKUP INPUT OUTPUT, R x RJ MOM M ard /MHz Mobile PU TL+ PT /MHz TI R0M U,,,, 0 LV R RT N FIR Project code:.q0.00 P P/N :.Q0.XXX RVIION : 00- (Hannstar,
DC-DC Constant Current Step-Down LED driver LDD-300L LDD-350L LDD-500L LDD-600L LDD-700L CURRENT RANGE
SPECIFICATION ORDER NO. LDD-00L LDD-0L LDD-00L LDD-00L LDD-700L CURRENT RANGE 00mA 0mA 00mA 00mA VOLTAGE RANGE Note. ~ VDC for LDD-00~700L/LW ; ~ 8VDC for LDD-00~700LS CURRENT ACCURACY (Typ.) ±% at VDC
Monolithic Crystal Filters (M.C.F.)
Monolithic Crystal Filters (M.C.F.) MCF (MONOLITHIC CRYSTAL FILTER) features high quality quartz resonators such as sharp cutoff characteristics, low loss, good inter-modulation and high stability over
ULX Wireless System USER GUIDE SUPPLEMENT RENSEIGNEMENT SUPPLÉMENTAIRES INFORMACION ADICIONAL. M1 ( MHz)
ULX Wireless System USER GUIDE SUPPLEMENT RENSEIGNEMENT SUPPLÉMENTAIRES INFORMACION ADICIONAL M1 (662 698 MHz) 2003, Shure Incorporated 27B8733A (Rev. 4) Printed in U.S.A. SPECIFICATIONS ULX1 Transmitter
Precision Metal Film Fixed Resistor Axial Leaded
Features EIA standard colour-coding Non-Flame type available Low noise and voltage coefficient Low temperature coefficient range Wide precision range in small package Too low or too high ohmic value can
Page of schematic page Rev. ate 0 0 0 0 0 0 0 0 0 0 0 0 Index lock iagram hange ist IR PROOR /(MI&HOT&PI) PROOR /(R) PROOR /(POWR) PROOR /() PH / (MI&VIO) PH / (T/P/zalia) PH / (PI/PI/K/U) PH / (PIO) PH
DISPLAY SUPPLY: FILTER STANDBY
ircuit iagrams and PW Layouts. ircuit iagrams and PW Layouts J.0 P. 0 isplay Supply P: ilter Standby MNS NPUT -Vac 00 P-V- V_OT 0 0 0 0 0 0 0 0 SPLY SUPPLY: LT STNY 0 M0 V 0 T,/0V MSU -VOLTS NOML... STNY
+3V3 Supply. +3V0 Flash + VCCPGMy +2V5 FPGA VCC + FPGA I/O +1V1 FPGA Core. Overview. abaxor engineering GmbH
6 7 8 Supply +V0 Flash + PGMy +V FPG + FPG I/O +V FPG ore Overview 6 7 8 6 7 8 I0NK_ IO H IO P IO L IO J VRFN0 N IO/IFFIO_TX_L9N/IFFOUT_L9N IO/IFFIO_RX_L0N/IFFOUT_L0N/QL J IO/IFFIO_TX_L9P/IFFOUT_L9P/QL
First International Computer,Inc Portable Computer Group HW Department
irst International omputer,inc Portable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : LM0W. PI & IRQ & M escription : Version : 0. Initial ate : eb, 00.
SMC SERIES Subminiature Coaxial Connectors
SERIES Subminiature Coaxial Connectors FEATURES Subminiature coaxial connectors with 50 Ω impedance for applications up to 10 GHz. (screw on mechanism)fulfills the subminiature coaxial connector requirement
B37631 K K 0 60
Multilayer Ceramic acitors High; X5R and X7R Chip Ordering code system B37631 K 7 5 K 6 Packaging 6 ^ cardboard tape, 18-mm reel 62 ^ blister tape, 18-mm reel Internal coding acitance tolerance K ^ ± %
SMC SERIES Subminiature Coaxial Connectors
SERIES Subminiature Coaxial Connectors FEATURES Subminiature coaxial connectors with 50 Ω impedance for applications up to 10 GHz. (screw on mechanism)fulfills the subminiature coaxial connector requirement
EΘΝΙΚΟ ΚΑΙ ΚΑΠΟΔΙΣΤΡΙΑΚΟ ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΘΗΝΩΝ ΕΙΔΙΚΟΣ ΛΟΓΑΡΙΑΣΜΟΣ ΚΟΝΔΥΛΙΩΝ ΕΡΕΥΝΑΣ ΓΡΑΜΜΑΤΕΙΑ ΕΠΙΤΡΟΠΗΣ ΕΡΕΥΝΩΝ ΑΝΑΡΤΗΤΕΑ ΣΤΟ ΚΗΜΔΗΣ & ΣΤΗ ΔΙΑΥΓΕΙΑ
EΘΝΙΚΟ ΚΑΙ ΚΑΠΟΔΙΣΤΡΙΑΚΟ ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΘΗΝΩΝ ΕΙΔΙΚΟΣ ΛΟΓΑΡΙΑΣΜΟΣ ΚΟΝΔΥΛΙΩΝ ΕΡΕΥΝΑΣ ΓΡΑΜΜΑΤΕΙΑ ΕΠΙΤΡΟΠΗΣ ΕΡΕΥΝΩΝ ΑΝΑΡΤΗΤΕΑ ΣΤΟ ΚΗΜΔΗΣ & ΣΤΗ ΔΙΑΥΓΕΙΑ Πρόσκληση εκδήλωσης ενδιαφέροντος 45005/2015 στο πλαίσιο
BM1385. Bitcoin Hash ASIC Datasheet. Bitmain Technologies Limited
BM1385 Bitcoin Hash ASIC Datasheet Bitmain Technologies Limited Page 1 of 14 Contents Contents... 1 Revision History... 2 1 Overview... 3 1.1 Features... 3 1.2 Applications... 3 2 Pin Description... 4
SUBJECT: RD01MUS2B & RD07MUS2B TETRA 2stage amplifier RF characteristics data.
APPLICATION NOTE Silicon RF Power Semiconductors Document NO. AN-UHF-129 Date : 2nd Sep. 11 Prepared : H.Hiraoka,Y.Tanaka Confirmed : S.Kametani (Taking charge of Silicon RF by MIYOSHI Electronics) SUBJECT:
First International Computer,Inc Protable Computer Group HW Department
irst International omputer,inc Protable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : LMR. PI & IRQ & M escription : Version : 0. Initial ate : March,
RT-178 / ARC-27 All schematics
RT / ARC All schematics J I K P0 L A B M C P N D O E H G F P0 RT /ARC F L P0 A C D G J M P S B E K R H N SQ OFF GUARD REC MOD I k I B E i DRVR I g FINAL I g I ant SQ OFF MAIN REC SENS PHONE METER MIC SENS
First International Computer,Inc Protable Computer Group HW Department
First International omputer,inc Protable omputer roup HW epartment oard name : Mother oard chematic. chematic Page escription : Project : P(M). PI & IRQ & M escription : Version : 0. Initial ate : ugust
GAUGE BLOCKS. Grade 0 Tolerance for the variation in length. Limit deviation of length. ± 0.25μm. 0.14μm ±0.80μm. ± 1.90μm. ± 0.40μm. ± 1.
GAUGE BLOCKS Accuracy according to ISO650 Nominal length (mm) Limit deviation of length Grade 0 Tolerance for the variation in length Grade Grade Grade Grade 2 Limit deviations of Tolerance for the Limit
WinMate Communication Inc. 9F, No Hsing Teh Road, San-Chung, Taipei, Taiwan, R.O.C TEL: FAX:
www.winmate.com.tw WinMate Communication Inc. 9F, No. 111-6 Hsing Teh Road, San-Chung, Taipei, Taiwan, R.O.C TEL:886-2-6635-5758 FAX:886-2-6635-5859 MTBF Test Report Product Model Product cription Issue
1.575 GHz GPS Ceramic Chip Antenna Ground cleared under antenna, clearance area 4.00 x 4.25 mm / 6.25 mm. Pulse Part Number: W3011 / W3011A
W0 Datasheet version. ceramic antenna. (09/08).575 GHz Ceramic Chip Antenna Ground cleared under antenna, clearance area x 4.5 mm / 6.5 mm. Pulse Part Number: W0 / W0A Features - Omni directional radiation
MMCX SERIES Microminiature Coaxial Connectors
SERIES Microminiature Coaxial Connectors FEATURES connectors are smaller than MCX connectors and are used from DC up to 6 GHz in applications where a tiny size is crucial. INTERFACE MATING DIMENSIONS PLUG:
65W PWM Output LED Driver. IDLV-65 series. File Name:IDLV-65-SPEC
~ A File Name:IDLV65SPEC 07050 SPECIFICATION MODEL OUTPUT OTHERS NOTE DC VOLTAGE RATED CURRENT RATED POWER DIMMING RANGE VOLTAGE TOLERANCE PWM FREQUENCY (Typ.) SETUP TIME Note. AUXILIARY DC OUTPUT Note.
ichip CO2128 with EBI Flash and Siemens HC25 GSM Modem
Reference Design ichip CO with EBI Flash and Siemens HC GSM Modem Revision History Version Date Description.0 May 00 Initial version.0 September 00 Changed from Mb Flash to Mb Flash Introduction This Reference
Quick Installation Guide
A Installation 1 F H B E C D G 2 www.trust.com/17528/faq Quick Installation Guide C C D Freewave Wireless Audio Set 17528/ 17529 D Installation Configuration Windows XP 4 5 8 Windows 7/ Vista 6 7 9 10
Visual Systems Division Technical Bulletin MultiSync MT820/MT1020 Installation Data Desk Top and Ceiling Mount
Visual Systems ivision ontents Notes and Formulas Page 1 Projection istances and Screen Sizes eiling Mount (Lens Wide) Page 2 eiling Mount (Lens Telephoto) Page 3 esktop Setup (Lens Wide) Page 4 esktop
Metal thin film chip resistor networks
Metal thin film chip resistor networks AEC-Q200 Compliant Features Relative resistance and relative TCR definable among multiple resistors within package. Relative resistance : ±%, relative TCR: ±1ppm/
MOSFETs. MOSFETs. High Voltage MOSFET (THD Type) Max. Ratings R DS(ON) ( ) Q g (nc) Outline (Unit: mm) Type No.
MOFETs High age MOFET (TH Type) Ratings R (ON) ( ) Q g (nc) BV I P (W) V I V KMB050N60P 60 50 1 0.018 0.022 10 25 32 10 KMB075N75P 75 75 190 0.013 0.017 10 37.5 85 10 KHB95NP 0 9.5 72 0.29 0.36 10 4.75
First International Computer,Inc Protable Computer Group HW Department
irst International omputer,inc Protable omputer roup W epartment oard name : Mother oard chematic. chematic Page escription : Project : P. PI & IRQ & M escription : Version : 0. Initial ate : January,
(#5 5::%%%$ " (#5 5::%%%$" %
!" "#! " # $ "! "#" "" ""! % %! % " &"#!! "' (%)* (% (%! "' + "',! "' $% " %! "'% " %!"! #!" " $ #!" #$ #! #!#!" -%$!"#!".! "!"#!"! "!" " " "!!" "! %!"!#/ "%! %! #! )0+! *.." )0)!- % 67&* 6**&7*0.8 67&*67&*90&0.8
Siemens AG Rated current 1FK7 Compact synchronous motor Natural cooling. I rated 7.0 (15.4) 11.5 (25.4) (2.9) 3.3 (4.4)
Synchronous motors Siemens 2009 FK7 Compact motors Nural cooling Selection and ordering da Red speed Shaft height n red S P red ΔT=00 K rpm kw (P) Red power Stic torque M 0 ΔT=00 K Red torque ) M red ΔT=00
Thin Film Chip Resistors
FEATURES PRECISE TOLERANCE AND TEMPERATURE COEFFICIENT EIA STANDARD CASE SIZES (0201 ~ 2512) LOW NOISE, THIN FILM (NiCr) CONSTRUCTION REFLOW SOLDERABLE (Pb FREE TERMINATION FINISH) Type Size EIA PowerRating
FP series Anti-Bend (Soft termination) capacitor series
FP series Anti-Bend (Soft termination) capacitor series Features Applications» High performance to withstanding 5mm of substrate» For general digital circuit bending test guarantee» For power supply bypass
First International Computer,Inc Protable Computer Group HW Department
First International omputer,inc Protable omputer roup HW epartment oard name : Mother oard chematic. chematic Page escription : Project : T. PI & IRQ & M escription : Version : 0. Initial ate : eptember,
Series AM2DZ 2 Watt DC-DC Converter
s Single output FEATURES: RoHS Compliant Operating temperature -40 o C to + 85 o C Low ripple and noise Pin compatible with multiple manufacturers High efficiency up to 82% Input / Output Isolation 1000,3000,
SMD Transient Voltage Suppressors
SMD Transient Suppressors Feature Full range from 0 to 22 series. form 4 to 60V RMS ; 5.5 to 85Vdc High surge current ability Bidirectional clamping, high energy Fast response time
2.4mm Series Connectors
2.4mm Series Connectors Table of Contents 2.4mm Series Connectors(DC~50GHz)... 1 2.4mm Replaceable Connectors... 2 2.4mm Receptacle (Round Contact) Connectors... 7 2.4mm Receptacle (Exposed Teflon) Connectors...
Multilayer Chip Inductor
Features -Monolithic structure for high reliability -High self-resonant frequency -Excellent solderability and high heat resistance Construction Applications -RF circuit in telecommunication and other
SMD Power chokes- SPD Series SPD series chokes For High Current Use
SMD Power chokes- SPD Series SPD series chokes For High Current Use Features 1.Shielded construction. 2.High current rating up to DC Amp 3.High frequency range up to 5.MHz 4.Ultra low buzz noise, due to
Series Overview *SOP (Small Outline Packages, Gullwing Leads) SMT Devices. Series IC51 (Clamshell) SOP, TSOP Type I & II
SMT evices Series Overview *SOP *SOP variations e.g. TSSOP... Series I51 (lamshell) SOP, TSOP Type I & II Insulation Resistance: 1,000MΩ min. at 500V ielectric Withstanding Voltage: 700V for 1 minute ontact
M p f(p, q) = (p + q) O(1)
l k M = E, I S = {S,..., S t } E S i = p i {,..., t} S S q S Y E q X S X Y = X Y I X S X Y = X Y I S q S q q p+q p q S q p i O q S pq p i O S 2 p q q p+q p q p+q p fp, q AM S O fp, q p + q p p+q p AM
... 5 A.. RS-232C ( ) RS-232C ( ) RS-232C-LK & RS-232C-MK RS-232C-JK & RS-232C-KK
RS-3C WIWM050 014.1.9 P1 :8... 1... 014.0.1 1 A... 014.0. 1... RS-3C()...01.08.03 A.. RS-3C()...01.08.03 3... RS-3C()... 003.11.5 4... RS-3C ()... 00.10.01 5... RS-3C().008.07.16 5 A.. RS-3C().0 1.08.
SPBW06 & DPBW06 series
/,, MODEL SELECTION TABLE INPUT ORDER NO. INPUT VOLTAGE (RANGE) NO LOAD INPUT CURRENT FULL LOAD VOLTAGE CURRENT EFFICIENCY (TYP.) CAPACITOR LOAD (MAX.) SPBW06F-03 310mA 3.3V 0 ~ 1500mA 81% 4700μF SPBW06F-05
Unshielded Power Inductor / PI Series
.Features: 1. Excellent solderability and high heat resistance. 2. Excellent terminal strength construction. 3. Packed in embossed carrier tape and can be used by automatic mounting machine..applications:
Summary of Specifications
Snap Mount Large High CV High Ripple 85 C Temperature The series capacitors are the standard 85 C, large capacitance, snap-in capacitors from United Chemi-Con. The load life for the series is 2,000 hours
Aluminum Electrolytic Capacitors
Aluminum Electrolytic Capacitors Snap-In, Mini., 105 C, High Ripple APS TS-NH ECE-S (G) Series: TS-NH Features Long life: 105 C 2,000 hours; high ripple current handling ability Wide CV value range (47
Dynamic types, Lambda calculus machines Section and Practice Problems Apr 21 22, 2016
Harvard School of Engineering and Applied Sciences CS 152: Programming Languages Dynamic types, Lambda calculus machines Apr 21 22, 2016 1 Dynamic types and contracts (a) To make sure you understand the
Instruction Execution Times
1 C Execution Times InThisAppendix... Introduction DL330 Execution Times DL330P Execution Times DL340 Execution Times C-2 Execution Times Introduction Data Registers This appendix contains several tables
2.92mm Series Connector
2.92mm Series Connector Table of Contents 2.92mm Series Connector(DC~40GHz)... 1 2.92mm Replaceable Connectors... 2 2.92mm Receptacle (Round Contact) Connectors... 7 2.92mm Receptacle (Exposed Teflon)
Product Selection Tables. 2005 SMD Resistors. Yageo brand
eo.com Product Selection Tables 2005 SMD Resistors Yageo brand Table of Contents www.yageo.com Table of contents Resistor chips, General purpose / Yageo brand 2 General purpose, 0201-0805 2 General purpose,
1951 {0, 1} N = N \ {0} n m M n, m N F x i = (x i 1,..., xi m) x j = (x 1 j,..., xn j ) i j M M i j x i j m n M M M M T f : F m F f(m) f M (f(x 1 1,..., x1 m),..., f(x n 1,..., xn m)) T R F M R M R x
Buck Solution_20W LED Driver for T8 LD7835_T8_20W_R00_TEST. Key Features
Subject LD7835 T8 Demo Board Manual Model Name LD7835_20W_R00_TEST (60V/300mA) Key Features Buck Topology Current Ripple Reduction (CRR) Current Accuracy < 5% Single Stage PFC > 0.9 @ Normal Line Efficiency
7. Schematic Diagram. 7-1 Overall Block Diagram FRONT MAIN MAIN CD SMPS (MAX-A54U)...
7. Schematic Diagram 7- Overall Block Diagram... 7-7- FRONT... 7-7- MAIN-... 7-7- MAIN-... 7-5 7-5 CD... 7-7- SM (MAX-A5U)... 7-7 7-7 SM (MAX-A55U)... 7- Samsung Electronics This Document can not be used
FEATURE EXPANSION BOARD TYPE 2018 B658 PARTS LOCATION AND LIST
FEATURE EXPANSION BOARD TYPE 2018 B658 PARTS LOCATION AND LIST This section instructs you as to the numbers and names of parts on this machine. 1.RA2K Expansion Unit 1 (B658) Rev. 08/04/2004 B658 2 Parts
jqa=mêççìåíë=^âíáéåöéëéääëåü~ñí= =p~~êäêωåâéå= =déêã~åó
L09 cloj=klk=tsvjmosopa jqa=mêççìåíë=^âíáéåöéëéääëåü~ñí= =p~~êäêωåâéå= =déêã~åó 4 16 27 38 49 60 71 82 93 P Éå Ñê ÇÉ áí dbq=ql=hklt=vlro=^mmif^k`b mo pbkq^qflk=ab=slqob=^mm^obfi ibokbk=pfb=feo=dboûq=hbkkbk
Chilisin Electronics Singapore Pte Ltd
hilisin Electronics ingapore Pte Ltd High urrent hip Beads, PBY eries Feature: Our MD High urrent hips Beads is specially designed to with tand large urrents while providing a means of EMI/RFI attenuation
High Voltage Ceramic Capacitor (Radial Disc Type)
High Voltage Ceramic Capacitor (Radial Disc Type) 1. Material Characteristics Series No TEMP. CHAR. Working Temperature ( ) Insulation Resistance ( MΩ) 1 UJ -25~+85 100000 2 SL -25~+85 100000 Disspation
CSR series. Thick Film Chip Resistor Current Sensing Type FEATURE PART NUMBERING SYSTEM ELECTRICAL CHARACTERISTICS
FEATURE Operating Temperature: -55 ~ +155 C 3 Watts power rating in 1 Watt size, 1225 package High purity alumina substrate for high power dissipation Long side terminations with higher power rating PART
f RF f LO f RF ±f LO Ιδανικός μείκτης RF Είσοδος f RF f RF ± f LO IF Έξοδος f LO LO Είσοδος f RF f LO (ω RF t) (ω LO t) = 1 2 [(ω RF + ω LO )t + (ω RF ω LO )t] RF LO IF f RF ± f LO 0 180 +1 RF IF 1 LO
SPEEDO AQUABEAT. Specially Designed for Aquatic Athletes and Active People
SPEEDO AQUABEAT TM Specially Designed for Aquatic Athletes and Active People 1 2 Decrease Volume Increase Volume Reset EarphonesUSBJack Power Off / Rewind Power On / Fast Forward Goggle clip LED Status
Smaller. 6.3 to 100 After 1 minute's application of rated voltage at 20 C, leakage current is. not more than 0.03CV or 4 (µa), whichever is greater.
Low Impedance, For Switching Power Supplies Low impedance and high reliability withstanding 5000 hours load life at +05 C (3000 / 2000 hours for smaller case sizes as specified below). Capacitance ranges
Mock Exam 7. 1 Hong Kong Educational Publishing Company. Section A 1. Reference: HKDSE Math M Q2 (a) (1 + kx) n 1M + 1A = (1) =
Mock Eam 7 Mock Eam 7 Section A. Reference: HKDSE Math M 0 Q (a) ( + k) n nn ( )( k) + nk ( ) + + nn ( ) k + nk + + + A nk... () nn ( ) k... () From (), k...() n Substituting () into (), nn ( ) n 76n 76n
Answers to practice exercises
Answers to practice exercises Chapter Exercise (Page 5). 9 kg 2. 479 mm. 66 4. 565 5. 225 6. 26 7. 07,70 8. 4 9. 487 0. 70872. $5, Exercise 2 (Page 6). (a) 468 (b) 868 2. (a) 827 (b) 458. (a) 86 kg (b)
Ανταλλακτικά για Laptop Lenovo
Ανταλλακτικά για Laptop Lenovo Ημερομηνία έκδοσης καταλόγου: 6/11/2011 Κωδικός Προϊόντος Είδος Ανταλλακτικού Μάρκα Μοντέλο F000000884 Inverter Lenovo 3000 C200 F000000885 Inverter Lenovo 3000 N100 (0689-
The Simply Typed Lambda Calculus
Type Inference Instead of writing type annotations, can we use an algorithm to infer what the type annotations should be? That depends on the type system. For simple type systems the answer is yes, and
ο ο 3 α. 3"* > ω > d καΐ 'Ενορία όλις ή Χώρί ^ 3 < KN < ^ < 13 > ο_ Μ ^~~ > > > > > Ο to X Η > ο_ ο Ο,2 Σχέδι Γλεγμα Ο Σ Ο Ζ < o w *< Χ χ Χ Χ < < < Ο
18 ρ * -sf. NO 1 D... 1: - ( ΰ ΐ - ι- *- 2 - UN _ ί=. r t ' \0 y «. _,2. "* co Ι». =; F S " 5 D 0 g H ', ( co* 5. «ΰ ' δ". o θ * * "ΰ 2 Ι o * "- 1 W co o -o1= to»g ι. *ΰ * Ε fc ΰ Ι.. L j to. Ι Q_ " 'T
1. Ηλεκτρικό μαύρο κουτί: Αισθητήρας μετατόπισης με βάση τη χωρητικότητα
IPHO_42_2011_EXP1.DO Experimental ompetition: 14 July 2011 Problem 1 Page 1 of 5 1. Ηλεκτρικό μαύρο κουτί: Αισθητήρας μετατόπισης με βάση τη χωρητικότητα Για ένα πυκνωτή χωρητικότητας ο οποίος είναι μέρος
EE101: Resonance in RLC circuits
EE11: Resonance in RLC circuits M. B. Patil mbatil@ee.iitb.ac.in www.ee.iitb.ac.in/~sequel Deartment of Electrical Engineering Indian Institute of Technology Bombay I V R V L V C I = I m = R + jωl + 1/jωC
0.635mm Pitch Board to Board Docking Connector. Lead-Free Compliance
.635mm Pitch Board to Board Docking Connector Lead-Free Compliance MINIDOCK SERIES MINIDOCK SERIES Features Specifications Application.635mm Pitch Connector protected by Diecasted Zinc Alloy Metal Shell
5V/9V/12V Output QC2.0+USB Auto Detect+USB-PD Type-C Application Report ACT4529
FEATURES 5V/9V/12V Output QC2.0+USB Auto Detect+USB-PD Type-C Application Report ACT4529 Wide input voltage range from 6V to 32V Transparent input voltage surge up to 40V QC2.0 decoding, 5V/9V/12V output
k k ΚΕΦΑΛΑΙΟ 1 G = (V, E) V E V V V G E G e = {v, u} E v u e v u G G V (G) E(G) n(g) = V (G) m(g) = E(G) G S V (G) S G N G (S) = {u V (G)\S v S : {v, u} E(G)} G v S v V (G) N G (v) = N G ({v}) x V (G)
BMA SERIES Subminiature Blind Mate Connectors
SERIES Subminiature Blind Mate Connectors FEATURES The blindmate connectors are designed for blindmate applications up to Ghz. They have a slide-on, non-locking interface which ensures frequent matings
High Power Amp BMT321. Application Note
RF MMIC Innovator www.berex.com [Classification] Application Note [Date] 2015.11 [Revision No.] Rev.A [Measuring Instruments] - NA_Agilent E5071B - SA_Agilent N9020A - SG_Agilent 4438C - SG_Agilent N5182A
J J l 2 J T l 1 J T J T l 2 l 1 J J l 1 c 0 J J J J J l 2 l 2 J J J T J T l 1 J J T J T J T J {e n } n N {e n } n N x X {λ n } n N R x = λ n e n {e n } n N {e n : n N} e n 0 n N k 1, k 2,..., k n N λ
Unshielded Power Inductors
Unshielded Power Inductors /080/0804/0810/106/106 Series Inductance with current and temperature: Inductance is measured with P-484 LR Meter or equivalent. Inductance drops 10% typical at Isat level with
k A = [k, k]( )[a 1, a 2 ] = [ka 1,ka 2 ] 4For the division of two intervals of confidence in R +
Chapter 3. Fuzzy Arithmetic 3- Fuzzy arithmetic: ~Addition(+) and subtraction (-): Let A = [a and B = [b, b in R If x [a and y [b, b than x+y [a +b +b Symbolically,we write A(+)B = [a (+)[b, b = [a +b
FEATURES APPLICATION PRODUCT T IDENTIFICATION PRODUCT T DIMENSION MAG.LAYERS
FEATURES RoHS compliant. Super low resistance, ultra high current rating. High performance (I sat) realized by metal dust core. Frequency Range: up to 1MHz. APPLICATION PDA, notebook, desktop, and server
LAr ROD boards. TM - TBM - CarteP3. Pierre Matricon LAL - Orsay
LAr ROD boards TM - TBM - CarteP3 Pierre Matricon LAL - Orsay October 2002 matricon@in2p3.fr Connections between the ROD boards TBM Crate Busy Trigger Timing Control CarteP3 Configuration TM to ROS 8 FEBs
Congruence Classes of Invertible Matrices of Order 3 over F 2
International Journal of Algebra, Vol. 8, 24, no. 5, 239-246 HIKARI Ltd, www.m-hikari.com http://dx.doi.org/.2988/ija.24.422 Congruence Classes of Invertible Matrices of Order 3 over F 2 Ligong An and
ichip CO2128 with EBI Flash and Siemens MC39i GSM Modem
Reference Design 0 ichip CO with EBI Flash and Siemens MCi GSM Modem Revision History Version Date Description.0 May 00 Initial version.0 September 00 Changed from Mb Flash to Mb Flash Introduction This