Contents i SYLLABUS osmania university UNIT - I BASIC VERILOG HDL Introduction to HDLs, Basic Concepts of Verilog, Data Types, System Tasks and Complier Directives. Gate Level Modeling : Gate Types and Gate Delays, Dataflow Modeling : Continuous Assignment and Delays, Design of Stimulus Block. UNIT - II BEHAVIOURAL MODELING Structured Procedures, Procedural Assignments, Timing Control, Conditional Statements, Sequential and Parallel Blocks, Generate Blocks. Switch Level Modeling, Tasks, Functions, Procedural Continuous Assignments, Design of Mealy and Moore State Models using Verilog, Logic Synthesis, Synthesis Design Flow, Gate Level Netlist. UNIT - III INTRODUCTION Introduction to MOS Technology, Basic MOS Transistor Action : Enhancement and Depletion Modes, Basic Electrical Properties of MOS, Threshold Voltage and Body Effect, Design of MOS Inverter with Different Loads, Basic Logic Gates with CMOS : Inverter, NAND, NOR, AOI, and OAI Gates, Transmission Gate Logic Circuits, BiCMOS Inverter. UNIT - IV MOS AND BICMOS CIRCUIT DESIGN PROCESSES MOS Layers, Stick Diagrams, Lambda Based Design Rules and Layout Diagrams, Basic Circuit Concepts : Sheet Resistance, Area Capacitance and Delay Calculation.
ii Contents UNIT - V COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS Combinational Logic : Manchester, Carry Select and Carry Skip Adders, Crossbar and Barrel Shifters, Multiplexer. Sequential Logic : Design of Dynamic Register Element, 3T, 1T Dynamic RAM Cell, 6T Static RAM Cell, D Flip Flop using Transmission Gates, NOR and NAND based ROM Memory Design.
Contents iii vlsi design FOR b.e. (o.u) iv year i semester (ELECTRONICS AND COMMUNICATION ENGINEERING) CONTENTS UNIT - I [BASIC VERILOG HDL]... 1.1-1.70 1.1 OVERVIEW OF DIGITAL AL DESIGN WITH VERILOG HDL... 1.2 1.1.1 Evolution of Computer-Aided Digital Design... 1.2 1.1.2 Emergence of HDLs... 1.3 1.1.3 Typical Design Flow (VLSI Design Flow)... 1.3 1.1.4 Importance of HDLs... 1.4 1.1.5 Popularity of Verilog HDL... 1.4 1.1.6 Trends in HDLs... 1.5 1.1.7 Major Capabilities of Verilog... 1.6 1.1.8 Design Methodologies... 1.6 1.1.8.1 4-Bit Ripple Carry Counter (Example For Design Hierarchy)... 1.7 1.2 BASIC CONCEPTS OF VERILOG... 1.8 1.2.1 Laxical Conventions... 1.8 1.2.1.1 White Space... 1.9 1.2.1.2 Comments... 1.10 1.2.1.3 Operators... 1.11 1.2.1.4 Number Specification... 1.11
iv Contents 1.2.1.5 Strings... 1.14 1.2.1.6 Identifiers and Keywords... 1.15 1.2.1.7 Escaped Identifiers... 1.15 1.3 DATA A TYPES... 1.16 1.3.1 Value System... 1.16 1.3.2 Data Declaration... 1.17 1.3.3 Reg Declaration... 1.18 1.3.4 Net Declaration... 1.18 1.3.5 Syntax... 1.23 1.3.6 Port Types... 1.23 1.3.7 Delays on Nets... 1.25 1.3.8 Integer and Time... 1.25 1.3.9 Hierarchical Names... 1.27 1.3.10 Arrays... 1.27 1.3.11 Strings... 1.28 1.4 SYSTEM TASKS AND COMPLIER DIRECTIVES... 1.29 1.4.1 System Tasks... 1.29 1.4.2 Compiler Directives... 1.32 1.5 GATE TE-LEVEL MODELING... 1.34 1.5.1 Gate Types... 1.34 1.5.1.1 And/Or Gates... 1.34 1.5.1.2 BUF/NOT T Gates... 1.38 1.5.1.3 Array of Instances... 1.42 1.5.1.4 Examples... 1.42 1.5.2 Gate Delays... 1.49 1.5.2.1 Rise, Fall and Turnurn-off Delays... 1.49 1.5.2.2 Min/Typ/Max Values alues... 1.50 1.5.2.3 Delay Example... 1.51
Contents v 1.6 DATAFL AFLOW MODELING... 1.53 1.6.1 Continuous Assignments... 1.54 1.6.1.1 Implicit Continuous Assignment... 1.55 1.6.1.2 Implicit Net Declaration... 1.56 1.6.2 Delays... 1.56 1.6.2.1 Regular Assignment Delay... 1.56 1.6.2.2 Implicit Continuous Assignment Delay... 1.57 1.6.2.3 Net Declaration Delay... 1.57 1.7 COMPONENTS OF A SIMULATION... 1.58 1.7.1 Example... 1.59 1.7.1.1 Design Block... 1.59 1.7.1.2 Stimulus Block... 1.61 Short Questions and Answers... 1.63-1.68 Expected University Questions with Answers... 1.69-1.70 UNIT - II [BEHAVIOURAL MODELING]... 2.1-2.92 2.1 BEHAVIOURAL MODELING... 2.2 2.2 STRUCTURED PROCEDURES... 2.3 2.2.1 Initial Statement... 2.3 2.2.2 Always Statement... 2.6 2.2.3 In One Module... 2.8 2.3 PROCEDURAL ASSIGNMENTS... 2.9 2.3.1 Blocking Assignment... 2.11 2.3.2 Nonblocking Assignment... 2.12 2.4 TIMING CONTROLS... 2.13 2.4.1 Delay-Based Timing Control... 2.13 2.4.2 Event-Based Timing Control... 2.16 2.4.3 Level-Sensitive Timing Control... 2.18 2.5 CONDITIONAL STATEMENTS TEMENTS... 2.19
vi Contents 2.6 SEQUENTIAL AND PARALLEL BLOCKS OCKS... 2.21 2.6.1 Sequential Blocks... 2.21 2.6.2 Parallel Blocks... 2.23 2.7 GENERATE BLOCKS OCKS... 2.25 2.7.1 Generate Loop... 2.26 2.7.2 Generate Conditional... 2.27 2.7.3 Generate Case... 2.29 2.8 SWITCH LEVEL MODELING... 2.30 2.8.1 Switch-Modeling Elements... 2.30 2.8.1.1 MOS Switches... 2.30 2.8.1.2 CMOS Switches... 2.32 2.8.1.3 Bidirectional Switches... 2.33 2.8.1.4 Power and Ground... 2.34 2.8.1.5 Resistive Switches... 2.35 2.8.1.6 Delay Specification on Switches... 2.36 2.8.2 Examples... 2.37 2.8.2.1 CMOS NOR Gate... 2.37 2.8.2.2 2-to-1 Multiplexer... 2.39 2.8.2.3 Simple CMOS Latch... 2.40 2.9 TASKS... 2.42 2.9.1 Task Declaration and Invocation... 2.42 2.9.2 Task Examples... 2.43 2.9.3 Automatic (Re-Entrant) Tasks... 2.46 2.10 FUNCTIONS... 2.47 2.10.1 Function Declaration and Invocation... 2.47 2.10.2 Function Examples... 2.48 2.10.3 Automatic (Recursive) Functions... 2.50
Contents vii 2.10.4 Constant Functions... 2.51 2.10.5 Signed Functions... 2.52 2.10.6 Differences Between Tasks and Functions... 2.52 2.11 PROCEDURAL CONTINUOUS ASSIGNMENTS... 2.53 2.11.1 Assign and Deassign... 2.53 2.11.2 Force and Release... 2.55 2.12 DESIGN OF MEALY AND MOORE STATE TE MODELS USING VERILOG OG... 2.57 2.12.1 Defining Terms in State Machines... 2.57 2.12.2 Mealy Circuit... 2.57 2.12.3 Design of a Mealy Circuit... 2.58 2.12.4 Moore Circuit... 2.67 2.12.5 Design of a Moore Sequential Network... 2.68 2.12.6 Comparison Between Moore and Mealy Models... 2.69 2.13 LOGIC SYNTHESIS... 2.70 2.13.1 What is Logic Synthesis... 2.70 2.13.2 Impact of Logic Synthesis... 2.71 2.13.3 Verilog HDL Synthesis... 2.72 2.13.3.1 Verilog Constructs... 2.73 2.13.3.2 Verilog Operators... 2.73 2.13.3.3 Interpretation of a Few ew Verilog Constructs... 2.75 2.14 SYNTHESIS DESIGN FLOW... 2.78 2.14.1 RTL to Gates... 2.78 2.14.2 An Example of RTL-to-Gates... 2.80 2.15 GATE LEVEL NETLIST... 2.84 2.15.1 Functional Verification... 2.84 Short Questions and Answers... 2.86-2.90 Expected University Questions with Answers... 2.91-2.92
viii Contents UNIT - III [INTRODUCTION INTRODUCTION]... 3.1-3.68 3.1 INTRODUCTION TO IC TECHNOLOG OGY... 3.2 3.1.1 Classification of ICs... 3.2 3.1.2 Evolution of IC Technology... 3.3 3.1.3 Advantages of ICs... 3.3 3.1.4 Moore s Law... 3.4 3.1.5 IC Manufacturing Process... 3.5 3.1.6 IC Design Challenges... 3.6 3.1.6.1 System Design Cycle... 3.6 3.1.6.2 Transistor Modeling... 3.7 3.1.6.3 Integration of Technologies... 3.7 3.1.7 Microelectornics Field... 3.7 3.1.8 IC Fabrication Steps... 3.10 3.2 MOS TECHNOLOGY... 3.11 3.2.1 Basic MOS Transistors ransistors... 3.12 3.2.1.1 Enhancement Mode Transistor Action... 3.14 3.2.1.2 Depletion Mode Transistor Action... 3.15 3.3 BASIC ELECTRICAL PROPERTIES OF MOS... 3.16 3.3.1 I DS DS Relationships... 3.16 3.3.1.1 The Non-Saturated Region... 3.17 3.3.1.2 The Saturated Region... 3.20 3.3.1.3 I DS DS Graph for Depletion Mode... 3.21 3.3.1.4 I DS DS Graph for Enhancement Mode... 3.22 3.4 THRESHOLD VOL OLTAGE AND BODY EFFECT... 3.23 3.4.1 Threshold Voltage oltage... 3.23 3.4.2 Body Effect... 3.24 3.5 MOS TRANSISTOR TRANSCONDUCTANCE ANCE (g m ) AND OUTPUT CONDUCTANCE ( ds )... 3.26 3.6 FIGURE OF MERIT (ω O )... 3.29
Contents ix 3.7 DESIGN OF MOS INVERTER WITH DIFFERENT LOADS... 3.30 3.7.1 nmos Inverter with Resistive Load... 3.30 3.7.2 nmos Inverter with Depletion Mode NMOS as a Load... 3.30 3.7.3 Z P.U /Z P.D Ratio for an nmos Inverter Driven by Another nmos Inverter... 3.32 3.7.4 Z P.U /Z P.D Ratio for an nmos Inverter Driven Through One (or) More Pass Transistors... 3.34 3.8 VARIOUS PULL-UPS... 3.37 3.8.1 nmos Enhancement Mode Transistor Pull-Up ull-up... 3.37 3.8.2 Complementary Transistor Pull-Up... 3.38 3.9 CMOS INVERTER ANALYSIS AND DESIGN... 3.39 3.10 CMOS LOGIC CIRCUIT... 3.43 3.11 BASIC LOGIC GATES WITH CMOS... 3.45 3.11.1 CMOS Inverter (Not Gate)... 3.45 3.11.2 CMOS NAND Gate... 3.46 3.11.3 CMOS NOR Gate... 3.47 3.11.4 Complex Gates in CMOS Logic... 3.49 3.11.4.1 AOI Logic Function... 3.49 3.11.4.2 OAI Logic Function... 3.51 3.12 SWITCH LOGIC... 3.52 3.12.1 Pass ass Tra ransistors nsistors... 3.53 3.12.2 Transmission Gates... 3.55 3.13 BICMOS INVERTER... 3.58 Short Questions and Answers... 3.61-3.66 Expected University Questions with Answers... 3.67-3.68 UNIT - IV [MOS AND BICMOS CIRCUIT DESIGN PROCESSES]... 4.1-4.86 4.1 INTRODUCTION TO VLSI CIRCUIT DESIGN... 4.2 4.2 FLOW... 4.2 4.2.1 Y-Chart... 4.2 4.2.2 Simplified View of VLSI Design Flow... 4.4 4.2.3 Top op-down and Bottom-Up Approach... 4.7 4.2.4 Semi-Custom and Full-Custom Design... 4.7 4.3 MOS LAYERS... 4.8
x Contents 4.4 STICK DIAGRAMS... 4.8 4.4.1 nmos Design Style... 4.12 4.4.1.1 Guidelines to Draw Stick Diagram of nmos Logic... 4.13 4.4.1.2 Stick Diagrams for nmos Logic Gates... 4.13 4.4.2 PMOS Design Style... 4.19 4.4.2.1 Guidelines to Draw Stick Diagrams of PMOS Logic... 4.19 4.4.2.2 Stick Diagrams for PMOS Logic Gates... 4.20 4.4.3 CMOS Design Style... 4.25 4.4.3.1 Guidelines to Draw Stick Diagram of CMOS Logic... 4.26 4.4.3.2 Stick Diagrams for Basic Logic Gates Using CMOS Design Style... 4.28 4.5 DESIGN RULES... 4.32 4.5.1 Lambda-based Design Rules... 4.32 4.5.1.1 Lambda-based Design Rules for Conducting Paths... 4.33 4.5.1.2 Lambda-based Design Rules for Transistors... 4.34 4.5.1.3 Lamda-based Design Rules for Contact Cuts... 4.34 4.5.2 Double Metal MOS Process Rules... 4.37 4.5.3 CMOS Lambda-based Design Rules... 4.38 4.5.4 2μm m CMOS Design Rules... 4.38 4.6 LAYOUT DIAGRAMS GRAMS... 4.40 4.7 BASIC CIRCUIT CONCEPTS... 4.42 4.7.1 Sheet Resistance... 4.42 4.7.2 Sheet Resistance Concept Applied to MOS Transistors and Inverters... 4.43 4.7.2.1 Sheet Resistance in MOS Transistors... 4.43 4.7.2.2 Inverter Resistance Calculation... 4.55 4.7.2.2.1 nmos Inverter... 4.55 4.7.2.2.2 CMOS Inverter... 4.56
Contents xi 4.7.3 Area Capacitance... 4.57 4.7.4 Standard Unit of Capacitance C g... 4.58 4.7.5 Some Area Capacitane Calculations... 4.58 4.8 DRIVING LARGE CAPACITIVE CITIVE LOADS... 4.62 4.8.1 Cascaded Inverters as Drivers... 4.62 4.8.2 Super Buffers... 4.64 4.8.3 BiCMOS Drivers... 4.65 4.9 WIRING CAPACIT CITANCE... 4.67 4.9.1 Fringing Fields... 4.67 4.9.2 Inter Layer Capacitances... 4.68 4.9.3 Peripheral Capacitance... 4.68 4.10 TIME DELAY Y UNIT (τ)... 4.68 4.10.1 Inverter Delays... 4.70 4.10.1.1 Estimation of CMOS Inverter Delay... 4.71 4.10.2 Propagation Delays... 4.73 4.10.2.1 Cascaded Pass ass Transistors... 4.74 4.10.2.2 Design of Long Polysilicon Wires ires... 4.76 4.10.3 Effects of Fan-in and Fan-out On Propagation Delay... 4.77 4.11 Choice of Layers... 4.77 Short Questions and Answers... 4.79-4.84 Expected University Questions with Answers... 4.85-4.86 UNIT - V [COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS]... 5.1-5.48 5.1 COMBINATIONAL LOGIC CIRCUITS... 5.2 5.2 ADDERS... 5.2 5.2.1 Single Bit Addition... 5.3 5.2.2 Carry Propagate Addition (CPA)... 5.7 5.2.2.1 Carry Ripple Adder (CRA)... 5.7 5.2.2.2 Carry Look Ahead Adder (CLA)... 5.9 5.2.2.3 Manchester Carry Chain Adder... 5.10 5.2.2.4 Carry Skip Adder... 5.12 5.2.2.5 Carry Select Adder... 5.13
xii Contents 5.3 SHIFTERS... 5.14 5.3.1 Crossbar Switch... 5.14 5.3.2 Barrel Shifter... 5.16 5.4 MULTIPLEXERS (DATA A SELECTORS)... 5.17 5.5 SEQUENTIAL LOGIC CIRCUITS... 5.20 5.6 DESIGN OF DYNAMIC REGISTER ELEMENT... 5.20 5.7 DYNAMIC SHIFT REGISTER... 5.21 5.8 DRAM (DYNAMIC RANDOM ACCESS MEMORY)... 5.23 5.8.1 One-Transistor DRAM... 5.23 5.8.2 Three-Transistor ransistor DRAM... 5.23 5.8.3 Four Transistor DRAM... 5.24 5.9 SRAM (STATIC TIC RANDOM ACCESS MEMORY) Y)... 5.25 5.9.1 6-Transistor SRAM... 5.25 5.10 D-FLIPFL -FLIPFLOP OP USING TRANSMISSION GATES TES... 5.25 5.11 READ ONLY MEMORY... 5.28 5.11.1 ROM Cell Organization... 5.28 5.11.2 Mask Programmed (ROM) Memory Circuits... 5.30 5.11.2.1 NOR-based ROM... 5.30 5.11.2.2 NAND-based ROM... 5.31 5.11.3 Flash Memory... 5.33 5.12 SERIAL ACCESS MEMORIES... 5.33 5.12.1 Shift Registers... 5.34 5.12.2 Queues (FIFO,, LIFO)... 5.36 5.13 CONTENT-ADDRESSABLE MEMORY... 5.36 Short Questions and Answers... 5.42-5.46 Expected University Questions with Answers... 5.47-5.48