PD553L-E RF POWER TRANSISTOR The LdmoST Plastic FAMILY General features Excellent thermal stability Common source configuration P OUT =3W mith 17dB gain@5mhz/12.5v New leadless plastic package Esd protection Supplied in tape & reel of 3K units In compliance with 22/95/EC european directive PowerFLAT (5x5) Description The PD553L-E is a common source N- Channel, enhancement-mode lateral Field-Effect RF power transistor. It is designed for high gain, broadband commercial and industrial application. It operates at 12V in common source mode at frequencies of up to 1GHz. PD55L-E boasts the excellent gain, linearity and reliability of STH1LV latest LD-MOS technology mounted in the innovative leadless SMD plastic package, PowerFLAT. PD55L-E s superior linearity performances makes it an ideal solution for car mobile radio. PIN configuration TOP VIEW Order codes Sales Type Marking Package Packaging PD553L-E 553 PowerFLAT (5x5) TAPE & REEL February 26 Rev1 1/19 www.st.com 19
Contents: PD553L-E Contents: 1 Electrical data.............................................. 3 1.1 Maximum Ratings............................................ 3 1.2 Thermal data............................................... 3 2 Electrical specification....................................... 4 2.1 Typical performances....................................... 6 2.2 Typical performance (broadband)............................... 8 3 Test circuit schematic........................................ 9 3.1 Test Circuit................................................ 1 3.2 Test circuit photomaster...................................... 1 4 Package mechanical data.................................... 14 5 Revision history........................................... 18 2/19 Rev1
PD553L-E Electrical data 1 Electrical data 1.1 Maximum Ratings Table 1. Absolute maximum ratings (T CASE =25 C) Symbol Parameter Value Unit V (BR)DSS Drain-Source Voltage 4 V V GS Gate-Source Volatge -.5 to+15 V I D Drain Current 2.5 A P DISS Power Dissipation (@T C = 7 C) 14 W T stg Storage Temperature 65 to +15 C T j Operating Junction Temperature 15 C 1.2 Thermal data Table 2. Thermal data Symbol Parameter Value Unit R th(j-c) Junction-Case Thermal Resistance 5.7 C/W Rev1 3/19
Electrical specification PD553L-E 2 Electrical specification (T CASE =25 C) Table 3. Static Symbol Test Condictions Min. Typ. Max. Unit I DSS V GS =V, V DS =28V 1 µa I GSS V GS =2V, V DS =V 1 µa V GS(Q) V DS =1V, I D =5mA 2. 5. V V DS(ON) V GS =1V, I D =.5A.36 V g fs V DS =1V, I D =1A 1. mho C iss 34 pf C oss V GS =V, V DS =12.5V, f=1mhz 23 pf C rss 1.8 pf Table 4. Dynamic Symbol Test Condictions Min. Typ. Max. Unit P 1dB V DD =12.5V, I DQ =5mA, f=5mhz 3 W G P V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz 17 19 db ηd V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz 5 52 % Load mismatch Table 5. V DD =12.5V, I DQ =5mA, P OUT =3W, f=5mhz 2:1 VSWR Switching on/off (inductive load) Test Condictions Class Human Body Model 2 Machine Model M3 Table 6. Switching energy (inductive load) Test Methodology Rating J-STD-2B MSL 3 4/19 Rev1
PD553L-E Electrical specification Figure 1. Typical Input/Drain load Impedances D Z DL Typical Input Impedance Typical Drain Load Impedance G Zin S Table 7. Impedance Data FREQ. MHz Z IN (Ω) Z DL (Ω) 48 1.79 - j 4.96 1.68 + j 7.45 5 1.88 - j 5.93 1.28 + j 8.92 52 2.1 - j 7.3 9.86 + j 1.18 Rev1 5/19
Electrical specification PD553L-E 2.1 Typical performances Figure 2. Capacitance Vs supply Voltage Figure 3. Output Power Vs Input Power 1 f = 1 M Hz 6 5 Idq = 7 ma 1 4 Idq = 5 ma C (pf) Coss Ciss Pout (W) 3 1 2 Crss 1 2 4 6 8 1 12 14 16 Vds (V) 1 Vds = 12.5 V f = 5 MHz 25 5 75 1 125 Pin (mw) Figure 4. Power Gain Vs Output Power Figure 5. Efficiency Vs Output Power 24 7 22 2 Idq = 5 ma Idq = 7mA 6 5 Idq = 5 ma Gp (db) 18 16 Idq = 3 ma Idq = 2 ma Nd (%) 4 3 Idq = 7 ma 14 2 12 1 Vds = 12.5 V f = 5 MHz..5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. Pout (W) 1 Vds = 12.5 V f = 5 MHz..5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. Pout (W) Figure 6. Input Return Loss Vs Output Power Figure 7. Output Power Vs Bias Current 7 RL (db) -5-1 -15 Idq = 5 ma Pout (W) 6 5 4 3-2 Idq = 7 ma 2-25 -3 Vds = 12.5 V f = 5 MHz..5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. Pout (W) 1 Pin = 2 dbm f = 5 MHz Vdd = 12.5 V 5 1 15 2 25 3 35 4 45 5 Idq (ma) 6/19 Rev1
PD553L-E Electrical specification Figure 8. Efficiency Vs Bias Current Figure 9. Output Power Vs Supply Voltage 8 7 6 8 7 6 Nd (%) 5 4 3 2 1 Pin = 2 dbm f = 5 MHz Vdd = 12.5 V 5 1 15 2 25 3 35 4 45 5 Idq (ma) Pout (W) 5 4 3 2 1 Idq = 5 ma Pin = 2 dbm f = 5 MHz 5 6 7 8 9 1 11 12 13 14 15 Vds (V) Figure 1. Output Power Vs Gate-Source Voltage 7 6 5 Pout (W) 4 3 2 1 Pin = 2 dbm Vdd = 12.5 V f = 5 MHz..5 1. 1.5 2. 2.5 3. 3.5 4. Vgs (V) Rev1 7/19
Electrical specification PD553L-E 2.2 Typical performance (broadband) Figure 11. Power Gain Vs Frequency Figure 12. Efficiency Vs Frequency 2 6 18 16 14 5 4 Gp (db) 12 1 8 6 Nd (%) 3 2 4 2 Vds = 12.5 V Idq = 5 m A Pout = 3 W 47 48 49 5 51 52 53 54 f (MHz) 1 Vds = 12.5 V Idq = 5 m A Pout = 3 W 47 48 49 5 51 52 53 54 f (MHz ) Figure 13. Return Loss Vs Frequency -5-1 RL (db) -15-2 -25-3 Vds = 12.5 V Id q = 5 m A Pout = 3 W 47 48 49 5 51 52 53 54 f (MHz) 8/19 Rev1
PD553L-E Test circuit schematic 3 Test circuit schematic VGG 2 1 + C8 C7 C6 R1 B1 R3 C13 B2 C14 C15 C16 VDD 1 2 L C5 R4 RF in N1 C1 Z1 Z2 C2 C3 Z3 Z7 Z8 Z9 Z1 Z4 Z6 Q Z5 C4 C9 C1 C11 C12 RF out N2 Z1 Z2.79 X.8.551 X.8 Z3.217 X.8 Z4.59 X.8 Z5.452 X.223 Z6.26 X.223 Z7.118 X.8 Z8.315 X.8 Z9.866 X.8 Z1.512 X.8 Table 8. Test Circuit Component List Component Description B1, B2 FERRIDE BEAD C1, C12 3Pf, 1B ATC CHIP CAPACITOR C2, C3 15pF, 1B ATC CHIP CAPACITOR C4, C9 -:- 2 pf VARIABLE CAPACITOR JOHANSON C5, C13 12pF 1B ACT CHIP CAPACITOR C6, C14.1mF 1B ACT CAPACITOR C7, C15 12pF 1B ACT CAPACITOR C8, C16 1µF, 35V, SMD ELECTROLYTIC CAPACITOR C1 C11 R1.5 -:- 5pF VARIABLE CAPACITOR JOHANSON.8 -:- 1pF VARIABLE CAPACITOR JOHANSON 33KΩ CHIP RESISTOR 1W R2, R3 15Ω MELF RESISTOR 1W R4 1KΩ CHIP RESISTOR 1W N1, N2 TYPE N FLANGE MOUNT BOARD ROGER ULTRA LAM 2 THK.3 ε r = 2.55 2OZ ED Cu BOTH SIDES Rev1 9/19
Test circuit schematic PD553L-E 3.1 Test Circuit 3.2 Test circuit photomaster 4 inches 6.4 inches 1/19 Rev1
PD553L-E Test circuit schematic Table 9. (V DS =12.5V, I DS =.15A) S-Parameter (PD553L) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) 5.88-11 2.14 112.39 22.672-19 1.772-141 11.77 93.42 5.633-138 15.771-152 7.86 82.41-5.642-147 2.779-157 5.8 73.4-11.665-151 25.794-161 4.5 66.38-17.694-154 3.89-163 3.62 6.35-22.721-155 35.824-165 2.98 54.33-26.75-157 4.839-166 2.5 49.31-3.774-159 45.853-168 2.13 44.28-32.796-16 5.865-169 1.83 4.25-34.818-161 55.874-171 1.59 36.23-36.837-163 6.885-172 1.39 33.21-36.852-164 65.894-173 1.23 29.18-37.867-165 7.91-174 1.1 26.16-37.88-166 75.96-175.97 23.15-36.89-167 8.911-176.88 2.12-32.92-169 85.916-177.79 18.11-28.99-169 9.918-178.72 15.1-22.918-171 95.922-179.65 13.8-13.922-171 1.925 18.59 11.7-7.928-172 15.925 179.54 9.7 8.934-173 11.928 178.5 7.6 21.938-174 115.927 177.46 5.7 38.941-175 12.928 176.43 4.8 51.944-176 125.929 175.4 2.1 56.947-176 13.927 175.37 1.11 61.953-177 135.927 174.34-1.11 65.951-178 14.925 173.32-2.12 68.952-178 145.922 172.3-4.14 72.954-179 15.922 172.28-5.16 73.957-18 Rev1 11/19
Test circuit schematic PD553L-E Table 1. (V DS =12.5V, I DS =.8A) S-Parameter (PD553L) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) 5.841-124 22.2 17.29 21.651-13 1.8-15 12.84 92.31 6.654-153 15.8-159 8.59 83.31-2.666-159 2.83-163 6.38 76.3-8.684-161 25.812-166 5. 7.28-11.72-163 3.822-168 4.7 64.27-15.721-163 35.83-169 3.39 59.25-17.74-164 4.837-17 2.87 55.24-2.76-165 45.848-172 2.47 5.22-23.777-166 5.857-172 2.15 46.2-23.795-166 55.866-174 1.89 42.18-25.813-167 6.874-174 1.67 39.17-23.825-168 65.882-175 1.49 35.15-24.839-168 7.887-176 1.33 32.13-22.853-169 75.893-177 1.19 29.12-16.863-17 8.898-178 1.8 26.11-15.875-171 85.93-179.98 23.1-11.885-172 9.94-18.89 21.9-1.893-173 95.99 179.82 19.8 7.91-173 1.911 179.75 16.8 16.94-174 15.914 178.69 14.8 27.911-175 11.916 177.64 12.8 35.916-175 115.917 176.59 1.9 43.919-176 12.917 176.55 8.1 48.923-177 125.918 175.51 6.1 57.929-177 13.917 174.47 5.12 62.929-178 135.917 173.44 3.13 63.934-179 14.914 173.42 1.13 67.936-179 145.912 172.39.15 71.938-18 15.911 171.36-2.16 72.941 179 12/19 Rev1
PD553L-E Test circuit schematic Table 11. S-Parameter (PD553L) (V DS =12.5V, I DS =1.5A) FREQ IS 11 I S 11 Φ IS 21 I S 21 Φ IS 12 I S 12 Φ IS 22 I S 22 Φ (MHz) 5.837-114 18.43 111.3 24.588-132 1.799-143 1.49 93.33 6.632-152 15.81-154 6.99 82.32-3.656-158 2.89-159 5.15 74.31-9.68-16 25.823-163 4. 67.29-14.71-162 3.835-165 3.22 61.28-18.726-163 35.845-167 2.66 56.25-2.75-164 4.855-169 2.23 52.24-24.768-165 45.866-17 1.91 47.22-26.789-166 5.876-171 1.65 43.2-24.812-167 55.882-173 1.44 39.18-25.828-167 6.892-174 1.26 36.16-25.836-168 65.898-175 1.12 33.15-25.844-169 7.93-176 1. 29.13-2.857-17 75.97-177.9 27.11-17.868-171 8.99-178.81 24.1-1.883-171 85.912-179.73 21.9-6.889-172 9.915-18.67 19.9 1.894-173 95.917 179.61 17.8 17.95-174 1.917 178.56 15.8 24.97-174 15.918 178.51 13.8 32.98-175 11.92 177.47 11.9 4.912-176 115.92 176.44 9.1 48.919-177 12.92 175.41 7.1 57.922-177 125.919 174.38 6.12 59.926-178 13.919 174.35 4.13 61.931-179 135.918 173.33 3.14 63.928-179 14.917 172.31 1.15 68.929-18 145.914 172.29.16 7.933 18 15.912 171.27-1.18 71.935 179 Rev1 13/19
Package mechanical data PD553L-E 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 14/19 Rev1
PD553L-E Package mechanical data Table 12. PowerFLAT Mechanical Data Dim. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A.9 1..35.39 A1.2.5.1.2 A3.24.9 AA.15.25.35.6.1.14 b.43.51.58.17.2.23 c.64.71.79.25.28.31 D 5..197 d.3.11 E 5..197 E2 2.49 2.57 2.64.98.11.14 e 1.27.5 f 3.37.132 g.74.3 h.21.8 Figure 14. PowerFLAT Package Dimensions Rev1 15/19
Package mechanical data PD553L-E Table 13. PowerFLAT Tape & Reel Dimensions DIM. mm. MIN. TYP MAX. Ao 5.15 5.25 5.35 Bo 5.15 5.25 5.35 Ko 1. 1.1 1.2 Figure 15. PowerFLAT Tape & Reel 16/19 Rev1
PD553L-E Package mechanical data Table 14. Recommended FOOTPRINT Rev1 17/19
Revision history PD553L-E 5 Revision history Table 15. Document revision history Date Revision Changes 14-Feb-26 1 First Issue 18/19 Rev1
PD553L-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 26 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Rev1 19/19