intel <MCH Processor> intel <PCH>

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1 For UM For Pure is. For special setting For Optimus & UM special setting For Pure is.special setting For udio version setting For udio version For G setting PIV@ For UM Power PEV@ For Pure is. Power R III SO-IMM 0 SO-IMM P, H (ST) P O (ST) P ual hannel 0/ MHz ST0 ST R SYSTEM MEMORY FI interface ST Gen FI FI intel <MH Processor>.GT/s ST Gen Sandyridge 0. rpg (.mm X.mm) intel <PH> MI MI PI-E X P~P PIE X MI interface GT/s igfx Interfaces GT/s INT_RT INT_LVS INT_HMI Fan river (PWM Type) P LS (SM/US) nvii GPU NP Fermi Package G- Optimus (Muxless) X'TL.0MHz P~P GPU ORE PWR RT0 P GPU IO PWR UPQ P ischarger/+v_m P +.V UPQ +0.V ISL P PU igpu_ore RT0 P P RT R-SW LVS Switchable HMI R-SW HRGER ISL PH +.0V UPQ P P P RT LVS HMI P /V SYS PWR P RT0 PU ORE PWR ISL P~P PU +.0V_VTT P UPQ R PWR RT0 P P0 0 P P P US NNs US0,, luetooth US US ardreader RTS US P P P P udio OE RTL LV P0 US.0 zalia US H SPI ual SPI ROM M x (asic ME+raidwood) P ougarpoint 0. mg (mm X mm) RT P PI-E P~P LP WPE/FLSH PEI.0 P X'TL.KHz PI-Express Gen GT/s X'TL MHz US PIE US PIE Realtek RTLE-GR Transformer RJ P P Neward P X'TL MHz P Mini ard WiFi US PIE P US Mini ard G US PIE P US SIM ard onn P HP Jack MI Jack SPK MI P0 P0 P0 P SPI ROM P Touch Pad P Keyboard P Light Sensor P P utton on mechanical key Quanta omputer Inc. PROJET : FH Size ocument Number Rev lock iagram ate: Monday, September, 00 Sheet of

2 0 NP-GE Power Up Sequence MS-UM Power-ON Sequence IN MINON GPU_VRON +VPU/+VPU NSWON# +V_GPU(V) S_ON RSMRST# E_PWRTN# T T +.0V_GPU(PEX_V) tnvv SLP_S#,SLP_S#,SLP_S# +VGPU_ORE(NVV) +.V_GPU(IFP_IOV) tnv-ifp_iov tnv-fvq SUSON MINON MINON +.VSUS/+VSUS/+VSUS T T +.V/+.V/+V/+V +.V_GPU(FVQ) +.0V_PH/+.0V_VTT/+0.V_R_VTT NP-GE Power up Sequence tnvv>0 tnv-ifp_iov>0 tnv-fvq>0 HWPG VRON PU SVI US T0 +V_ORE +V_GFX +V_SW WPROK eep S/S off-on Sequence IMVP_PWRG E_PWROK T T SUSWRN# SYS_PWROK T SUS_K# SLP_SUS# RSMRST# S_ON +V_S/+V_S eep S/S Sequence T: S_ON TO RSMRST# = 0ms (spec:mini 0ms) T RMPWROK UNOREPWRGOO SUS_STT# PLTRST# System Power Sequence T: S_ON TO RSMRST# = 0ms (spec:mini 0ms) T: RSMRST# TO E_PWRTN# = 0ms (spec:mini 00ms) T: MINON TO VRON = 0ms (spec:mini ms) T: VRON TO E_PWROK = 0ms (HWPG NEE TO E HIGH at that time) T: MINON to MINON =00us T: E_PWROK to UNOREPWRGOO =ms(min) T: SUS_STT# to PLTRST# =0us(Min) T: SYS_PWROK to SUS_STT# =ms(min) T: +V_ORE to IMVP_PWRG =ms(max) T0: VRON to accept SVI command. =ms(max) T T Quanta omputer Inc. PROJET : FH Size ocument Number Rev Frontpage Monday, September, 00 ate: Sheet of

3 0 +V_S +V_S +V_GPU +V_GPU +V_GPU.K SM_ME0_LK.K G NMOS S.K IS_SL.K NP-GE SM_ME0_T +V_S +V_S +V_S +VPU +VPU G NMOS S IS_S intel <PH> ougarpoint 0. SM_ME_LK SM_ME_T.K.K S S G NMOS G NMOS.K.K MLK MT E ITE mg (mm X mm) +V_S.K SM_PH_LK +V_S.K +V_S G NMOS S +V.K SM_RUN_LK +V.K Slave RESS :0H R IMM-0-ST (.H) VREF Q0 M Solution Slave RESS :H R IMM--ST (.H) VREF Q M Solution SM_PH_T G NMOS S SM_RUN_T Quanta omputer Inc. PROJET : FH Size ocument Number Rev SMus ddress Monday, September, 00 ate: Sheet of

4 0 Sandy ridge Processor (MI,PEG,FI) U MI_TXN0 MI_RX#[0] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXP0 MI_RX[0] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_RXN0 G MI_TX#[0] MI_RXN E MI_TX#[] MI_RXN F MI_TX#[] MI_RXN MI_TX#[] MI_RXP0 G MI_TX[0] MI_RXP MI_TX[] MI_RXP F0 MI_TX[] MI_RXP MI_TX[] FI_TXN0 FI0_TX#[0] FI_TXN H FI0_TX#[] FI_TXN E FI0_TX#[] FI_TXN F FI0_TX#[] FI_TXN FI_TX#[0] FI_TXN 0 FI_TX#[] FI_TXN FI_TX#[] FI_TXN E FI_TX#[] FI_TXP0 FI0_TX[0] FI_TXP G FI0_TX[] FI_TXP E0 FI0_TX[] FI_TXP G FI0_TX[] FI_TXP 0 FI_TX[0] FI_TXP FI_TX[] FI_TXP FI_TX[] FI_TXP F FI_TX[] FI_FSYN0 FI_FSYN0 J FI_FSYN FI0_FSYN FI_FSYN J FI_FSYN FI_INT FI_INT H0 FI_INT FI_LSYN0 FI_LSYN0 J FI_LSYN FI0_LSYN FI_LSYN H FI_LSYN ep_omp ep_ompio INT_eP_HP_Q ep_iompo ep_hp ep_ux ep_ux# ep_tx[0] F ep_tx[] ep_tx[] G ep_tx[] ep_tx#[0] E ep_tx#[] ep_tx#[] F ep_tx#[] PU-P-rPG MI Intel(R) FI ep PI EXPRESS* - GRPHIS J PEG_OMP PEG_IOMPI PEG_IOMPO J PEG_ROMPO H PEG_RXN[0..] PEG_RXN0 PEG_RX#[0] K PEG_RXN PEG_RX#[] M L PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] J PEG_RXN PEG_RX#[] J H PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] H G PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] G0 F PEG_RXN PEG_RX#[] PEG_RXN0 PEG_RX#[0] E E PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] PEG_RXN PEG_RX#[] PEG_RXP[0..] J PEG_RXP0 PEG_RX[0] PEG_RXP PEG_RX[] L PEG_RXP PEG_RX[] K PEG_RXP PEG_RX[] H H PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] G PEG_RXP PEG_RX[] G F PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] F0 E PEG_RXP PEG_RX[] PEG_RXP0 PEG_RX[0] E F PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] E PEG_RXP PEG_RX[] PEG_RXP PEG_RX[] PEG_TXN0_ PEG_TXN0 PEG_TX#[0] M 0 EV@0.U/0V_ M PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] PEG_TXN_ PEG_TXN PEG_TX#[] M 0 EV@0.U/0V_ L PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] PEG_TXN_ 0 EV@0.U/0V_ PEG_TXN PEG_TX#[] L K PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] PEG_TXN_ PEG_TXN PEG_TX#[] K 0 EV@0.U/0V_ PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] J0 J PEG_TXN_ 00 EV@0.U/0V_ PEG_TXN PEG_TX#[] PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] H PEG_TXN0_ PEG_TXN0 PEG_TX#[0] G EV@0.U/0V_ PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] E PEG_TXN_ PEG_TXN PEG_TX#[] F EV@0.U/0V_ PEG_TXN_ EV@0.U/0V_ PEG_TXN PEG_TX#[] PEG_TXN_ PEG_TXN PEG_TX#[] F EV@0.U/0V_ PEG_TXN_ PEG_TXN PEG_TX#[] E EV@0.U/0V_ PEG_TXP0_ PEG_TXP0 PEG_TX[0] M 0 EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] M 0 EV@0.U/0V_ PEG_TXP_ 0 EV@0.U/0V_ PEG_TXP PEG_TX[] M0 PEG_TXP_ EV@0.U/0V_ PEG_TXP PEG_TX[] L PEG_TXP_ PEG_TXP PEG_TX[] L 0 EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] K0 EV@0.U/0V_ PEG_TXP_ 0 EV@0.U/0V_ PEG_TXP PEG_TX[] K PEG_TXP_ EV@0.U/0V_ PEG_TXP PEG_TX[] J PEG_TXP_ EV@0.U/0V_ PEG_TXP PEG_TX[] J PEG_TXP_ PEG_TXP PEG_TX[] H EV@0.U/0V_ PEG_TXP0_ EV@0.U/0V_ PEG_TXP0 PEG_TX[0] G PEG_TXP_ PEG_TXP PEG_TX[] E 0 EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] F EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] E EV@0.U/0V_ PEG_TXP_ PEG_TXP PEG_TX[] EV@0.U/0V_ 0.uF coupling aps for PIE GEN// +.0V_VTT PEG_TXN[0..] PEG_TXP[0..],, H_SN_IV# E_PEI H_PROHOT# PM_THRMTRIP# +.0V_VTT H_PROHOT# PM_SYN H_PWRGOO SN_IV# N. at SN ES # 0.v R R LVG0GW GNOUT IN N U V R PU_PLTRST# +V_S R *.K/F_ R R /J_ TP TP SKTO# TP_TERR# H_PROHOT#_R PM_SYN_R H_PWRGOO_R PM_RM_PWRG_Q_R PU_PLTRST#_R PLTRST# 0,,,,, /J_ 0/J_ *0.U/0V_ 0/J_ 0K/J_ 0 0.U/0V_, R /J_ SYS_PWROK PM_RM_PWRG Sandy ridge Processor (LK,MIS,JTG) N L N L N M P V R R *0/F_ U PRO_SELET# SKTO# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# PU-P-rPG R 0/J_ PM_RM_PWRG_R R *K/F_ MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM +V_S U TSH0 0.U/0V_ LK LK# PLL_REF_LK PLL_REF_LK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R K P P R R P0 R P L T R R0 T0 P R T R LK_PU_LKP_R LK_PU_LKN_R LK_PLL_SSLKP_R LK_PLL_SSLKN_R SM_ROMP_0 SM_ROMP_ SM_ROMP_ XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO XP_RST# XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM PM_RM_PWRG_Q R */J_ R R R R0 R +.V_PU R 00/F_ R TP TP TP TP TP TP TP TP TP0 TP TP 0/F_./F_ 00/F_ *SPE@K/J_ *SPE@K/J_ TP TP0 TP TP R 0X R SPI@0X PU_RMRST# XP_RST# 0/F_ +.0V_VTT PM_RM_PWRG_Q_R LK_PU_LKP 0 LK_PU_LKN 0 LK_PLL_SSLKP 0 LK_PLL_SSLKN 0 EV UM Terminate PLL_REF_SSLK to GN and PLL_REF_SSLK# to VP on Processor if motherboard only supports external graphics. G.0 : SM_ROMP[] value to. (S0F)from due to component selection issue R.0 change R0 to./f Q *N00K, IMVP_PWRG Q MINON_ON_G, FV0N R K_ PM_THRMTRIP# Q MMT0 SYS_SHN# FI isabling (iscrete Only) FI_INT +.0V_VTT P & PEG ompensation +.0V_VTT ep Hot-plug Processor pull-up(pu) R R R0 *EV@0/J_ *EV@0/J_ *EV@0/J_ FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN Note: Place PU resistor within inches of PU H_PROHOT# R0 +.0V_VTT /J_ R *EV@K/F_ R *EV@K/F_ FI_FSYN can gang all these signals together and tie them with only one K resistor to GN (G V0. h..). R./F_ ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms R./F_ PEG_OMP PEG_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PEG_IOMPO signals should be routed within 00 mils typical impedance =. mohms HP disable INT_eP_HP_Q +.0V_VTT R 0K/J_ XP_TO XP_TMS XP_TI_R XP_PREQ# XP_TLK XP_TRST# R R R0 R R R /J_ /J_ /J_ */J_ /J_ /J_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev Sandy ridge / Monday, September, 00 ate: Sheet of

5 Sandy ridge Processor (R) 0 U U M Q[:0] M S#0 M S# M S# M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q F0 F G0 G F F G G K K K J J J J K M N0 N N M0 M N M G G K K H H J J J K J K H H L L P N L M M L P N J H L K L K J H E0 F0 V E F S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] S_S#[0] S_S#[] RSV_TP[] RSV_TP[] S_OT[0] S_OT[] RSV_TP[] RSV_TP[0] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] V V0 W W0 K L G H H G G H G J M L M R M F K N L M R M 0 W W W V V W W V W V W F V V M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] M Q[:0] M S#0 M S# M S# M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 G F F G G F F G J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] S_S#[0] S_S#[] RSV_TP[] RSV_TP[] S_OT[0] S_OT[] RSV_TP[] RSV_TP[0] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] E R E R0 T T0 E E E E F K N N P K P G J M N P K P T R T T T T R T R R T 0 R R M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] PU-P-rPG PU-P-rPG +.V_SUS, R_RMRST# 0/ dd K ohm #PGU 0. 0 R00 K/F_ R K/F_ R0 *0/J_ PU_RMRST# 0 RMRST_NTRL_PH R 0/J_ Q N00K 0.0U/0V_ R.K/F_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev Sandy ridge / ate: Monday, September, 00 Sheet of

6 + 0u/V_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ U/.VS_ + 0 0u/V_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ U/.VS_ SN: uf_ x Socket TOP cavity uf_ x0 Socket OT cavity uf_ x Socket TOP edge 0uF_ x / change 0U FP to u/V_ U/.VS_ U/.VS_ 0 U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ 0 *U/.VS_ Sandy ridge Processor (POWER) +V_ORE G G G G G G0 G G G G F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P UF uf_ x Socket TOP cavity uf_ x Socket OT cavity uf_ x Socket TOP cavity (no stuff) uf_ x Socket OT cavity (no stuff) 0uF_ x V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 POWER ORE SUPPLY SENSE LINES SVI PEG N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSSIO_SENSE H H0 G0 0 Y0 U0 P0 L0 J J J J H H H G G G F F F F E E E J J J0 J J J 0 0 SPI@ For Optimus & UM SPE@ For Pure is. SP@ For special setting +.0V_VTT_0 H_PU_SVILRT# H_PU_SVILK H_PU_SVIT R R R0 R0 + *0U/V_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ *U/.VS_ *U/.VS_ SN:. 0/J_ 0/J_ 0/J_ 0/J_ R U/.VS_ 0 U/.VS_ U/.VS_ *U/.VS_ U/.VS_ R +.0V_VTT + 0u/V_ U/.VS_ +.0V_VTT *0_short R U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ 00/J_ 00/J_ VP_SENSE VSSP_SENSE +SMR_VREF PU VPL SN W: 0uF x +V_ORE VSENSE VSSSENSE R 0uF/mohm x uf x *0.U/0V_ *0/J_ *0.U/0V_ +V_GFX +.V +VR_REF_PU PU VGT SN W: 0uF/mohm x uf x VR_SVI_LK VR_SVI_T VR_SVI_LERT# *0.U/0V_ +VR_REF_PU SPI@0U/V_ SPI@U/.V_ SPI@U/.V_ SPI@U/.V_ *SPI@0U/.V_ + 0 SPI@U/.V_ SPI@0U/.V_ uf () R SPI@0U/.V_ *SPI@U/.V_ 0 0U/.V_ SPI@0U/V_ + 00 SPI@U/.V_ SPI@U/.V_ SPI@0U/.V_ *SPI@U/.V_ *SPE@0/J_ 0 U/.V_ H_PU_SVILK H_PU_SVIT +.0V_VTT Sandy ridge Processor (GRPHI POWER) *SPI@0U/V_ + 0 SPI@0U/.V_ SPI@U/.V_ SPI@U/.V_ *SPI@U/.V_ 0 U/.V_ + *0U/V_ Layout note: need routing together and LERT need between LK and T R T T T T0 T T R R R R0 R R P P P P0 P P N N N N0 N N M M M M0 M M L L L L0 L L K K K K0 K K J J J J0 J J H H H H0 H H 0/J_ UG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VPLL VPLL VPLL PU-P-rPG Place PU resistor close to PU R 0/F_ Place PU resistor close to PU R +.0V_VTT POWER GRPHIS.V RIL 0/J_ +.0V_VTT +.0V_VTT SENSE LINES S RIL R -.V RILS VREF MIS SVI LK lose to VR R./F_ VR_SVI_LK SVI T lose to VR R 0/F_ VXG_SENSE VSSXG_SENSE SM_VREF VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VS VS VS VS VS VS VS VS VS_SENSE F_ VS_VI VR_SVI_T SVI LERT K K L F F F Y Y Y U U U P P P M M L J J J H H H H_F_ R0 TP 0/J_ 0/J_ 0 mil +VR_REF_PU VS_SEL 0 +.V_SUS, MIN +VR_REF_PU Note: +VR_REF_PU should have 0 mil trace width R R TP 0U/.V_ 0U/.V_ 0U/.V_ R0 0/J_ R R 0U/.V_ 0 0U/.V_ 0U/.V_ 0K/J_ VS_SENSE 0 MINON_ON_G 00/J_ 00/J_. +V_GFX V_XG_SENSE VSS_XG_SENSE PU MH SN W: 0uF/mohm x 0uF x 0U/.V_ + *0U/V_ 0U/.V_ JP *SHORT P Q O *0P/0V_ 0U/.V_ VS +.V_PU 0 +.V_PU uf () + *0U/V_ 0 U/.V_ PU S SN W: 0uF/mohm x 0uF x R 0/J_ 0 U/.V_ Q MN0K- PU-P-rPG,, MIN MIN Q N00K R 00K/J_ R0 /J_ H_PU_SVILRT# R /J_ R 0/J_ VR_SVI_LERT# Quanta omputer Inc. PROJET : FH Size ocument Number Rev Sandy ridge / Monday, September, 00 ate: Sheet of

7 UH T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T0 VSS0 T VSS T VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS0 R VSS R VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS0 P0 VSS P VSS P VSS P VSS N0 VSS N VSS N VSS N VSS N VSS N VSS0 N VSS N0 VSS N VSS N VSS M VSS M VSS M VSS M VSS M VSS M VSS0 M0 VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L VSS L0 VSS L VSS L VSS L VSS K VSS K0 VSS0 K VSS K VSS K VSS K VSS K VSS K VSS K0 VSS K VSS K VSS J VSS0 Sandy ridge Processor (GN) VSS UI VSS J VSS J VSS J T VSS VSS J T VSS VSS J0 T VSS VSS J T VSS VSS J T VSS VSS J T0 VSS VSS J T VSS VSS0 J T VSS VSS H T VSS VSS H T VSS0 VSS H P VSS VSS H0 P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H N VSS VSS00 H N VSS VSS0 H N VSS VSS0 H N VSS0 VSS0 H N VSS VSS0 G N0 VSS VSS0 G N VSS VSS0 G N VSS VSS0 F N VSS VSS0 F N VSS VSS0 F M VSS VSS0 F L VSS VSS E L0 VSS VSS E L VSS0 VSS E L VSS VSS E L VSS VSS E L VSS VSS E0 L VSS VSS E L VSS VSS E L VSS VSS E L VSS VSS0 E L VSS VSS E K VSS VSS K VSS00 VSS K VSS0 VSS K VSS0 VSS J VSS0 VSS J VSS0 VSS H VSS0 VSS H0 VSS0 VSS H VSS0 VSS0 H VSS0 VSS H VSS0 VSS H VSS0 VSS H VSS VSS 0 H VSS VSS H0 VSS VSS H VSS VSS H VSS VSS H VSS VSS Y H VSS VSS0 Y H VSS VSS Y H VSS VSS Y H VSS0 VSS Y H VSS VSS Y H VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS0 W0 G0 VSS VSS W G VSS VSS W G VSS0 VSS W F VSS VSS W F VSS VSS U F VSS VSS U VSS U VSS U VSS U VSS0 U VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS F F E0 E E E E E E E0 E E E E E E E E E SMR_VREF_Q0_M SMR_VREF_Q_M TP TP TP Voltage selection for VIO: this pin must be pulled high on the motherboard FG0 FG FG FG FG FG FG FG Sandy ridge Processor (RESERVE, FG) / Remove XP R *K/J_ 0/0 dd for Pre-ES TP On R H_SN_IV#_PWRTRL = low,.0v H_SN_IV#_PWRTRL = high/n,.0v R *K/J_ UE K FG[0] K FG[] L FG[] L FG[] K FG[] L FG[] L0 FG[] M FG[] M FG[] M0 FG[] M FG[0] M FG[] N FG[] N FG[] N FG[] M FG[] K FG[] N FG[] J VXG_VL_SENSE H VSSXG_VL_SENSE J V_VL_SENSE H VSS_VL_SENSE J F RSV F RSV F RSV0 RSV G RSV G RSV E RSV RSV 0 RSV RSV 0 RSV RSV 0 RSV0 RSV 0 RSV RSV J RSV RSV RSV J0 RSV RSV VIO_SEL RSV PU-P-rPG RESERVE RSV L RSV G RSV0 E RSV K RSV W RSV T RSV M RSV J RSV T RSV J RSV H RSV0 G RSV R RSV T RSV T RSV P RSV R RSV RSV RSV RSV RSV0 RSV J RSV K V_IE_SENSE RSV T RSV T RSV R KEY H RSV N RSV M For rpg socket, RSV pin should be left N 0 PU-P-rPG PU-P-rPG Processor Strapping FG (PEG Static Lane Reversal) FG PEG Static x Lane FG (P Presence Strap) FG (PEG efer Training) The FG signals have a default value of '' if not terminated on the board. Normal Operation Normal Operation PEG train immediately following xxreset de assertion 0 isable; No physical P attached to ep Lane Reversed Lane Reversed Enable; n ext P device is connected to ep PEG wait for IOS training FG FG FG R R R K/F_ *K/F_ *K/F_ FG FG R R *K/F_ *K/F_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled Quanta omputer Inc. PROJET : FH Size ocument Number Rev Sandy ridge / ate: Monday, September, 00 Sheet of

8 ougar Point (MI,FI,PM) U0 ougar Point (LVS,I) U0 0 XP_RST#, E_PWROK PM_RM_PWRG RSMRST# E_PWRTN# +.0V_PH SUS_PWR_K XP_RST# SYS_PWROK E_PWROK PM_RM_PWRG RSMRST# SUS_PWR_K _PRESENT PM_TLOW# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R R R R0 R0 R0 R0 R00 0/J_ T./F_ 0/F_ *0/J_ 0/J_ *0/J_ 0/J_ 0/J_ MI_OMP SUSK#_R SYS_PWROK_R E_PWROK_R PWROK_R E_PWRTN#_R E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H K P L L0 K E0 H0 E0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_RESET# SYS_PWROK PWROK PWROK RMPWROK RSMRST# MI System Power Management +V +V_S +V_S +V_S FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SWVRMEN PWROK WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SUSWRN#/SUSPWRNK/GPIO0 +V_S SLP_S# PWRTN# SLP_# PRESENT / GPIO SW SLP_SUS# TLOW# / GPIO+V_S PMSYNH J Y E H J G0 G G F G E G J0 H W V 0 V 0 E N G N 0 H F G0 G P SLP_SUS# SWVREN R PIE_WKE# LKRUN# T T 0/J_ T T T0 FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN RSMRST# PWROK PIE_WKE#, LKRUN# SUS_STT# PH_SUSLK SLP_S#, SLP_S#, PM_SYN INT_RT_HSYN INT_RT_VSYN INT_LVS_LON INT_LVS_VEN INT_LVS_RIGHT INT_EILK INT_EIT INT_TXLLKOUTN INT_TXLLKOUTP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP R place close to PH R R R0 0/F_ 0/F_ 0/F_ INT_RT_LU +V INT_RT_GRE INT_RT_RE INT_RT_LU INT_RT_GRE INT_RT_RE R R INT_LK INT_T /F_ /F_ R R R SYN RS ohm for irect onnect 0ohm for ock Support 0ohm for Switchable Graphics evice own Topology 0ohm for Switchable Graphics ock Support INT_EILK INT_EIT T.K/J_.K/J_.K/F_ INT_TXLLKOUTN INT_TXLLKOUTP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP INT_RT_LU INT_RT_GRE INT_RT_RE INT_RT_HSYN_R INT_RT_VSYN_R _IREF R K/F_ J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN ougarpoint_rp0 LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V INT_HMI_TXN V0 INT_HMI_TXP V INT_HMI_TXN V INT_HMI_TXP U INT_HMI_TXN0 U INT_HMI_TXP0 V INT_HMI_TXN V INT_HMI_TXP P P P P T Y Y Y Y M M T T H F E F E J G INT_HMI_SL INT_HMI_S INT_HMI_HP_Q INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN INT_HMI_TXP INT_HMI_TXN0 INT_HMI_TXP0 INT_HMI_TXN INT_HMI_TXP R 0/J_ +V INT. HMI PM_RI# 0 RI# +V_S SLP_LN# / GPIO K SLP_LN# R *M/F_ ougarpoint_rp0 INT_HMI_HP_Q INT_HMI_HP R0 *00K/J_ Q *N00K R *0K/J_ PH Pull-high/low(LG) +V +V_S System PWR_OK(LG) +V_S +V_RT PWROK FOR SW (eep Sx Well ) +VPU +VPU LKRUN# XP_RST# RSMRST# SYS_PWROK R PM_RI# R 0K/J_ PM_TLOW# R.K/J_ R R R.K/J_ *K/J_ 0K/J_ 0K/J_ PIE_WKE# SLP_LN# SUS_PWR_K _PRESENT PM_RM_PWRG R0 R R R0 R R G 0. PU 00ohm to +V_S 0K/J_ 0K/J_ *0K/J_ 0K/J_ 0K/J_ 00/F_ G.0 without R Power Gating dno't PU to +V_S, SYS_PWROK U0 SYS_PWROK TSH0 *0.U/0V_ IMVP_PWRG, E_PWROK R 00K/J_ SWVREN EEP S/S well On ie SW VR Enable High = Enable (efault) Low = isable R 0K/J_ R *0K/J_ PR *0K/J_ +V_SW +VPU PR *0/J_ +V_S P *R00V-0 PQ *TEU PR *0.K/J_ R *0/J_ PWROK P0 *0.U/.V_ PQ *N00K add cap to timing tune Quanta omputer Inc. PROJET : FH Size ocument Number Rev ougar Point / Monday, September, 00 ate: Sheet of

9 RT ircuitry(rt) 0mils +V_SW R *0/J_ +V_RT R 0/J_ +VPU R0 0K/J_ +V_RT_ 0MIL T U/.V_ 0mils R K/J_ R 0K/J_ 0MIL U/.V_ U/.V_ ON -T-0-K0 bat-_-_ RESET JUMP (Near ROOM OOR) RT_RST# SRT_RST# G L L L_L *P -0 RT_RST# SRT_RST# PH(LG) GPIO +V 0 Z_SYN_R Flash escriptor Security Override Low = Enabled High = isabled (Internal 0K/F pull high to +V) Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. hange SIZE / +V_RT dd MOSFET to separate OE SYN signal R p/0v_ p/0v_ 0K/J_ N00K Q Y.KHz 0 0 R SPKR Z_SIN0 / Remove XP TP R 0M/J_ M/J_ TP RT_RST# SRT_RST# PH_INVRMEN Z_ITLK_R Z_SYN_Q SPKR Z_RST#_R Z_SOUT_R RT_X RT_X PH_JTG_TK_R PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R ougar Point (H,JTG,ST) G SM_INTRUER# K N L T0 K E G N J H K H U0 RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# RT IH JTG ST LP ST G +V FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP H_SIN0 STRXN STRXP H_SIN STTXN STTXP H_SIN STRXN H_SIN STRXP STTXN STTXP H_SO STRXN STRXP H_OK_EN# / GPIO +V STTXN STTXP H_OK_RST# / GPIO +V_S STRXN STRXP STTXN JTG_TK STTXP JTG_TMS JTG_TI JTG_TO SERIRQ STIOMPO STIOMPI STROMPO STOMPI E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 PH_RQ#0 PH_RQ# SERIRQ ST_TXN0_ ST_TXP0_ ST_TXN_ ST_TXP_ ST_OMP ST_OMP TP TP0 0 R R L0, L, L, L, SERIRQ LFRME#, GPIO SERIRQ ST_RXN0 ST_RXP0 0.0U/V_ ST_TXN0 0.0U/V_ ST_TXP0 ST_RXN ST_RXP 0.0U/V_ ST_TXN 0.0U/V_ ST_TXP./F_ +.0V_PH./F_ R R ST H ST O +V.K/J_ *0K/J_ 0 *SHORT_ P PH_SPI_LK T SPI_LK STRIS H ST_RIS R 0/F_ PH_SPI_S0# Y SPI_S0# R 0K +V H us(lg) +VPU R *0K/J_ PH_SPI_S# PH_SPI_SI PH_SPI_SO T SPI_S# V SPI_MOSI U SPI_MISO ougarpoint_rp0 SPI +V +V STLE# ST0GP / GPIO STGP / GPIO P V P GPIO S_IT0 ST_T# 0 Z_ITLK R0 /J_ Z_ITLK_R 0 Z_SYN R0 /J_ Z_SYN_R 0 Z_RST# R /J_ Z_RST#_R 0 Z_SOUT R /J_ Z_SOUT_R PH JTG ebug (LG) +V_S Modify for test. R R 0/F_ 0/F_ PH Strap Table Pin Name Strap description Sampled onfiguration efault weak pull-up on GNT0/# No reboot mode setting 0 = efault (weak pull-down 0K) [Need external pull-down for LP IOS] SPKR PWROK +V R0 *K/J_ SPKR internal P = Setting to No-Reboot mode GNT# / GPIO Top-lock Swap Override internal PU PWROK 0 = "top-block swap" mode = efault (weak pull-up 0K) R *K/J_ PI_GNT# 0 GNT[:0]# functionality is not available on Mobile. Used as GPIO only. R /J_ R 00/F_ PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TK_R R 00/F_ INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up GNT# / GPIO GPIO oot IOS Selection [bit-] internal PU oot IOS Selection 0 [bit-0] internal PU PWROK PWROK GNT# 0 GNT0# 0 oot Location SPI LP * +V_RT +V R R R R R 0K/J_ K/J_ K/J_ *K/J_ *K/J_ PH_INVRMEN S_IT0 S_IT 0 efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO R 0_ R 0_ R 0_ +V R0 PH SPI ROM(LG) +V U PH_SPI_LK_R E# V PH_SPI_SI_R SK PH_SPI_SO_R SI R.K_ SO HOL# WP# VSS *P/0V_ SPI Flash Socket 0.U/0V_.K_ H_SO F_TVS GPIO H_SYN GPIO Flash escriptor Security internal P MI/FI Termination voltage internal P On-die PLL Voltage Regulator internal PU On-ie PLL VR Voltage Select internal P Intel ME rypto Transport Layer Security (TLS) cipher suite internal P RSMRST PWROK RSMRST# RSMRST RSMRST 0 = efault (weak pull-up 0K) = Override 0 = Set to Vss = Set to Vcc (weak pull-up 0K) 0 = isable = Enable (efault) 0 = Support by.v (weak pull-down) = Support by.v 0 = Intel ME TLS with no confidentiality = Intel ME TLS with confidentiality +V_S +V +V_S R R ME_WR# R R R0 R *K/J_ Z_SOUT_R R 0_.K/J_ K/J_ *K/J_ K/J_ +.V Z_SYN_Q F_TVS H_SN_IV# Need check schematic K_ PLL_OVR_EN PH_GPIO R change to K ohm follow G.0 and chklist.0 It needs to be connected to PRO_SELET with a K±% pull-up resistor to PH VPNN rail and a.k±% series resistor. New dd in PT ES Rev.0 at 0, Needs to be pulled High for Huron River platform. Vender EON Winbond Socket Size M M P/N KEFN0Q00 (ENF-00HIP) KEP0N00 (WQVSSIG) G Quanta omputer Inc. PROJET : FH Size ocument Number Rev ougar Point / Monday, September, 00 ate: Sheet of

10 ougar Point-M (PI,US,NVRM) ougar Point-M (PI-E,SMUS,LK) U0 0 LK_PI_LP LK_PI_E S_IT PI_GNT# LK_PI_F TP R R R PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_EISEL# GPU_SELET# GPIO MP_PWR_TRL# GPIO0 EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH PI_PME# PI_PLTRST# /J_ /J_ /J_ GPIO LK_PI_F_R LK_PI_LP_R LK_PI_E_R *0P/0V_ G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 U0E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 RSV PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 +V REQ# / GPIO +V REQ# / GPIO +V GNT# / GPIO +V GNT# / GPIO +V GNT# / GPIO +V PIRQE# / GPIO +V PIRQF# / GPIO +V PIRQG# / GPIO +V PIRQH# / GPIO +V PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI ougarpoint_rp0 *0P/0V_ PI US RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS +V_S O0# / GPIO +V_S O# / GPIO0 +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO0 +V_S O# / GPIO Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L NV_LE USP0- USP0+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ US_IS US_O0# US_O# US_O# US_O# US_O# US_O# US_O# US_O# TP TP R TP USP0- USP0+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+./F_ US_O0# US NN (harge) US NN US NN WLN WWN ard Reader New ard luetooth on LVS EHI EHI PIE_RXN PIE_RXP WLN PIE_TXN PIE_TXP PIE_RXN PIE_RXP WWN PIE_TXN PIE_TXP PIE_RXN PIE_RXP New ard PIE_TXN PIE_TXP PIE_RXN_LN PIE_RXP_LN GLN PIE_TXN_LN PIE_TXP_LN LK_PIE_WLNN LK_PIE_WLNP WLN PIE_LKREQ_WLN# LK_PIE_WWNN LK_PIE_WWNP WWN PIE_LKREQ_WWN# LK_PIE_NEWN LK_PIE_NEWP New ard PIE_LKREQ_NEW# LK_PIE_LNN LK_PIE_LNP LN PIE_LKREQ_LN# G PERN J +V_S 0 0.U/0V_ PIE_TXN_ PERP SMLERT# / GPIO V 0.U/0V_ PIE_TXP_ PETN U PETP SMLK E PERN SMT F 0.U/0V_ PIE_TXN_ PERP 0.U/0V_ PIE_TXP_ PETN Y PETP +V_S SML0LERT# / GPIO0 TP G PERN TP J PERP SML0LK TP V PETN TP0 U PETP SML0T F PERN E 0.U/0V_ PIE_TXN_ PERP Y +V_S 0.U/0V_ PIE_TXP_ PETN SMLLERT# / PHHOT# / GPIO PETP +V_S SMLLK / GPIO G PERN TP H PERP +V_S SMLT / GPIO TP Y PETN TP PETP J PERN G 0.U/0V_ PIE_TXN_LN_ PERP U 0 0.U/0V_ PIE_TXP_LN_ PETN L_LK V PETP G0 PERN L_T J0 PERP TP Y0 PETN TP 0 PETP L_RST# E PERN PERP TP W PETN TP Y PETP +V_S LK_PIE_WLNN PEG LKRQ# / GPIO Y0 LK_PIE_WLNP LKOUT_PIE0N Y LKOUT_PIE0P PIE_LKREQ_WLN# LKOUT_PEG N J PIELKRQ0# / GPIO +V_S LKOUT_PEG P LK_PIE_WWNN LK_PIE_WWNP LKOUT_PIEN LKOUT_MI_N LKOUT_PIEP LKOUT_MI_P PIE_LKREQ_WWN# M PIELKRQ# / GPIO +V LKOUT_P_N LKOUT_P_P TP LKOUT_PIEN TP LKOUT_PIEP PIE_LKREQ_US# LKIN_MI_N V0 PIELKRQ# / GPIO0 +V LKIN_MI_P LK_PIE_NEWN Y LK_PIE_NEWP LKOUT_PIEN LKIN_GN_N Y LKOUT_PIEP LKIN_GN_P PIE_LKREQ_NEW# PIELKRQ# / GPIO +V_S LKIN_OT_N LKIN_OT_P TP Y LKOUT_PIEN TP Y LKOUT_PIEP PIE_LKREQ_REV# LKIN_ST_N L PIELKRQ# / GPIO +V_S LKIN_ST_P LK_PIE_LNN V LK_PIE_LNP LKOUT_PIEN REFLKIN V LKOUT_PIEP PIE_LKREQ_LN# L PIELKRQ# / GPIO +V_S LKIN_PILOOPK TP LKOUT_PEG N XTL_IN TP 0 LKOUT_PEG P XTL_OUT GPIO E PEG LKRQ# / GPIO+V_S XLK_ROMP V0 LKOUT_PIEN V LKOUT_PIEP LK_PIE_REQ# T PIELKRQ# / GPIO +V_S V LKOUT_PIEN +V LKOUTFLEX0 / GPIO V LKOUT_PIEP +V GPIO LKOUTFLEX / GPIO K PIELKRQ# / GPIO +V_S +V LKOUTFLEX / GPIO TP K LKOUT_ITPXP_N TP K LKOUT_ITPXP_P +V LKOUTFLEX / GPIO ougarpoint_rp0 PI-E* LOKS SMUS ontroller Link FLEX LOKS E SMLERT# H SM_PH_LK SM_PH_T RMRST_NTRL_PH RMRST_NTRL_PH SM_ME0_LK G SM_ME0_T SMLLERT#_R R E SM_ME_LK M SM_ME_T M T P0 M0 PIE_LKREQ_PEG# LK_PIE_VGN LK_PIE_VGP V U M M *0_ SMLLERT#, For E L_LK L_T L_RST# PIE_LKREQ_PEG# LK_PIE_VGN LK_PIE_VGP LK_PU_LKN LK_PU_LKP LK_PLL_SSLKN LK_PLL_SSLKP F LK_UF_PIE_GPLLN E LK_UF_PIE_GPLLP J0 LK_UF_LKN G0 LK_UF_LKP LK_PI_F G LK_UF_REFLKN E LK_UF_REFLKP *0P/0V_ K LK_UF_REFSSLKN K LK_UF_REFSSLKP K LK_PH_M H LK_PI_F P/0V_ V XTL_IN V XTL_OUT Y XLK_ROMP R K LK_FLEX0 F LK_FLEX H LK_FLEX K *0P/0V_ Y R0 MHz M/J_ P/0V_ 0./F_ +.0V_PH R */J_ LK_M_VG R /J_ LK_M_R R /J_ LK_M_LN *0P/0V_ *0P/0V_ +V LK_REQ/Strap Pin(LG) SMus/Pull-up(LG) PLTRST#(LG) +V_S PI_PLTRST# U TSH0FU 0.U/0V_ PLTRST# R 00K/J_ PLTRST#,,,,, PI/USO# Pull-up(LG) +V_S R 0 US_O# US_O# US_O# US_O# 0KX US_O# US_O0# US_O# US_O# MP_PWR_TRL# GPIO0 GPIO PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPIO MP_PWR_TRL# +V MP Switch ontrol MP_PWR_TRL# R 0 0KX R R R R R.K/J_.K/J_.K/J_.K/J_ *0K/J_ EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH GPU_EISEL# GPU_SELET# Low = MP ON High = MP OFF (efault) R *K/J_ +V_S R 0K/J_ PIE_LKREQ_WLN# R 0K/J_ PIE_LKREQ_NEW# R 0K/J_ PIE_LKREQ_REV# R 0K/J_ PIE_LKREQ_LN# R 0K/J_ LK_PIE_REQ# R0 0K/J_ GPIO R0 0K/J_ GPIO +V R 0K/J_ PIE_LKREQ_WWN# R 0K/J_ PIE_LKREQ_US# +V_S R 0K/J_ PIE_LKREQ_PEG# R0 *0K/J_ LK_UF_LKN R 0K/J_ LK_UF_LKP R 0K/J_ LK_UF_PIE_GPLLN R0 0K/J_ LK_UF_PIE_GPLLP R0 0K/J_ LK_UF_REFLKN R 0K/J_ LK_UF_REFLKP R 0K/J_ LK_UF_REFSSLKN R 0K/J_ LK_UF_REFSSLKP R 0K/J_ LK_PH_M R 0K/J_ *0P/0V_ LOK TERMINTION for FIM heck Q N00K N00K Q SM_ME_LK MLK SM_PH_T SM_RUN_T,,.K/J_ R +V_S +V R.K/J_ SM_ME_T +V_S R R R0 R0 R R0 R K/J_ RMRST_NTRL_PH 0K/J_ SMLLERT#_R 0K/J_ SMLERT#.K/J_ SM_PH_LK.K/J_ SM_PH_T.K/J_ SM_ME0_LK.K/J_ SM_ME0_T Quanta omputer Inc. PROJET : FH Size ocument Number Rev ougar Point /.K/J_ R0 R.K/J_ MT SM_PH_LK SM_RUN_LK,, Q Q N00K N00K Monday, September, 00 ate: Sheet of 0

11 SGPIO ougar Point (GPIO,VSS_NTF,RSV) U0F +V S_GPIO S_GPIO R0 K/J_ T MUSY# / GPIO0 +V +V TH / GPIO 0 OR_I R0 *K/J_ E_EXT_SMI# E_EXT_SMI# TH / GPIO +V +V TH / GPIO R.K/F_ OR_I H TH / GPIO +V +V TH / GPIO0 R.K/F_ E_EXT_SI# E_EXT_SI# E TH / GPIO +V +V TH / GPIO 0 R0.K/F_ TP TP I_EN# LN_ISLE# 0 GPIO +V_S LN_PHY_PWR_TRL / GPIO +V_S PH_GPIO G GPIO +V_S 0GTE P PEI U R GPU_HOL_RST# U STGP / GPIO +V GPIO RIN# P Intel ME rypto Transport Layer, GFXPG GFXPG 0 TH0 / GPIO +V PROPWRG Y Security (TLS) cipher suite internal P IOS_RE T +V PH_THRMTRIP# SLOK / GPIO THRMTRIP# Y0 R +V_S R K/F_ 0 = Intel ME TLS with no confidentiality IOS_WP# E GPIO / MEM_LE+V_S INIT_V# T = Intel ME TLS with confidentiality GPIO E GPIO SW F_TVS Y PLL_OVR_EN P GPIO +V_S STP_PI# TS_VSS H K STP_PI# / GPIO +V TS_VSS K GPUORE_ON,, dgpu_vron K GPIO +V GPU_PWR_ON dgpu_pwr_en dgpu_pwr_en MI_OVRVLTG TS_VSS H0 R EV@0_ V STGP / GPIO +V dgpu_prsnt# FI_OVRVLTG TS_VSS K0 R0 EV@0_ M STGP / GPIO +V MFG_MOE N SLO / GPIO +V N_ P OR_I0 M STOUT0 / GPIO +V TEST_SET_UP V STOUT / GPIO +V VSS_NTF_ G 0, SMLLERT# R 0_ RIT_TEMP_REP# V STGP / GPIO +V VSS_NTF_ G SV_ET GPIO +V_S VSS_NTF_ H GPIO PU/MIS +V E_0GTE *0_ E_RIN# 0/J_ Muxed with STP_PI# If not used,.-k to 0-k pull-up to +V.S. E_0GTE E_PEI, E_RIN# H_PWRGOO PM_THRMTRIP# F_TVS LN_ISLE# R PLL_OVR_EN R I_EN# R E_EXT_SMI# E_EXT_SI# STP_PI# E_0GTE E_RIN# GFXPG RIT_TEMP_REP# dgpu_pwr_en GPIO GPIO Pull-up/Pull-down(LG) R R R0 R R R R R0 R 0K/J_ 0K/J_ *0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ *0K/J_ 0K/J_ 0K/J_ 0K/J_ Un-multiplexed. an be configured as wake input to allow wakes from eep Sleep. If not used then use.-k to 0-k pull-down to GN. +V_S +V VSS_NTF_ H VSS_NTF_ VSS_NTF_ J VSS_NTF_ VSS_NTF_0 J VSS_NTF_ VSS_NTF_ J VSS_NTF_ VSS_NTF_ NTF VSS_NTF_ VSS_NTF_ J J VSS_NTF_ VSS_NTF_ J E VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E SV_SET_UP High = Strong (efault) +V +V_S R *0K/J_ SV_ET R 00K/J_ E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ ougarpoint_rp0 VSS_NTF_0 VSS_NTF_ VSS_NTF_ E F F TEST_SET_UP R0 R 0K/J_ *K/J_ [I0:] 0:0 0: :0 : Fuction UM Optimus (Hynix) oard I reserve P Optimus (Samsung) Rev. +V ST[:]GP/GPIO[:] internal Pull-down 0K STGP/GPIO (FI_OVRVLTG) & STGP/GPIO (MI_OVRVLTG) Sampled at Rising edge of PWROK. Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts) NOTE: This signal should NOT be pulled high when strap is sampled MFG-TEST R0 R0 R *SP@0K/J_ OR_I0 SP@0K/J_ OR_I SP@0K/J_ OR_I EV R R R SP@0K/J_ *SP@0K/J_ *SP@0K/J_ UM R0 FI TERMINTION VOLTGE OVERRIE *00K/J_FI_OVRVLTG R00 *K/J_ MI_OVRVLTG R *00K/F_ IOS_RE LOW - Tx, Rx terminated to same voltage +V +V +V MI TERMINTION VOLTGE OVERRIE Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) R R IOS REOVERY 0K/J_ *K/J_ High = isable (efault) Low = Enable MFG_MOE R R +V 0K/J_ *K/J_ Stuff +V R0 SPE@0K/J_ Ra Ra GPU_PRSNT# Quanta omputer Inc. PROJET : FH Size ocument Number Rev ougar Point / ate: Monday, September, 00 Sheet of Rb R0 *SPI@00K/J_ Rb

12 PH(LG) +.0V_PH R +.0V_PH R0 +.0V_PH L0 +.0V_PH R +.0V_PH_V VccORE =. (0mils) 0.00/F_0 U/.V_ U/.V_ U/.V_ 0U/.V_ +.0V_PH_VPLL_EXP 0/J_ +.0V_VPLL_EXP *uh/m_ *0U/.V_ +.0V_VIO VccIO =. (0mils) 0.00/F_0 0 U/.V_ U/.V_ U/.V_ U/.V_ 0U/.V_ +V +V_V_EXP R 0/J_ 0.U/0V_ +VFI_VRM +VFI_VRM +.0V_PH R *0/J_ +.0V_VPLL_FI R 0/J_ +.0V_VPLL_FI +.0V_VTT +VFI_VRM F F G G G G G G J J J J J N J N N N N N P P P P T N N H P G P U0 OUGR POINT (POWER) U0G VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] ougarpoint_rp0 POWER V ORE VIO FI RT LVS FT / SPI MI HVMOS V VSS VLVS VSSLVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] VVRM[] VMI[] VLKMI VFTERM[] VFTERM[] VFTERM[] VFTERM[] VSPI U U K K M M P P V V T T0 G G J J V +VFI_VRM +V Vcc =m(mils) L +VLVS +V VccLVS=m(mils) R SPI@0/J_ +V_TX_LVS VccTX_LVS=0m(0mils) L +V_V_GIO U/.V_ R *0/J_ 0.U/0V_ +VP_NN SPI@0.0U/V_ 00 SPI@0.0U/V_ R +V_VME_SPI +V +VFI_VRM +.V_V_MI_I *0U/.V_ R 0.U/0V_ R U/.V_ 0.0U/V_ 0/J_ 0/J_ 0/J_ +.V +V 0.U/0V_ L *0uH/00m_ 0U/.V_ R R SPI@U/.V_ +.V_V_MI +V_MI_I VSPI = 0m(mils) 0ohm/ +.0V_VTT +.0V_PH +V VMI = m(0mils) R U/.V_ *SPE@0/J_ VLKMI = 0m(mils) R R *SPE@0/J_ SPI@0.uH_ 0/J_ */F_ 0/J_ VPNN = 0 m(mils) +.V +.0V_PH L +.0V_PH +.0V_PH +.0V_PH +V_S +V_SW +VPLL_PY_PH VME(+.0V) =??(??mils) R0 R R R R0 *0uH/00m_ +.0V_PH +.0V_PH *0U/.V_ VSW_= m +.0V_VEPW VccSW =.0 (0mils) 0.00/F_0 0/J_ 0/J_ 0/J_ *0/J_ R R0 U/.V_ U/.V_ U/.V_ U/.V_ 0/J_ *0/J_ U/.V_ U/.V_ R 0.U/0V_ R U/.V_ U/.V_ *0/J_ 0/J_ 0.U/0V_ +VFI_VRM m(0mils) m(mils) *0.U/0V_ *U/.V_ +VLK +VPSW PH_VSW +V_SUS_LKF +VPLL_PY +VSUS +VRTEXT +VFI_VRM +.0V_V PL +.0V_V PL +VIFFLK +VIFFLKN VIFFLKN= m(0mils) VSS= m(0mils) +V.0V_SSV ougar Point-M (POWER) T V T H L L W W W W W W W N Y F F F F G G U0J VLK VSW_ PSUSYP V_[] VPLLMI VIO[] PSUS[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] PRT VVRM[] VPLL VPLL VIO[] VIFFLKN[] VIFFLKN[] VIFFLKN[] VSS POWER lock and Miscellaneous ST PI/GPIO/LP US VIO[] VIO[0] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VIO[] VREF_SUS PSUS[] VSUS_[] VREF VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLST VVRM[] VIO[] VIO[] VIO[] N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F +V_VPUS +V_VUG +VUPLL +V_PH_VREFSUS +V_USSUS +V_VPSUS +V_PH_VREF +V_VPSUS +V_VPORE +V 0.U/0V_ +V.0S_ST +V.LN_VPLL VVRM= K m(mils) F +VFI_VRM R U/.V_ +.0V_VUSORE R *U/.V_ L 0/J_ *0U/.V_ 0/J_ R U/.V_ R 0.U/0V_ R0 0.U/0V_ +.0V_PH 0 0.U/0V_ U/.V_ +V R +.0V_PH R0 +.0V_PH VSUS_ = m(mils) +V_S VREFSUS=m VREF= m VSUS_ = m(mils) U/0V_ VPORE = m(0mils) 0.U/0V_ 0.U/0V_ U/0V_ 0/J_ 0/J_ 0/J_ R R R *0uH/00m_ 0/F_ R00V-0 0/F_ R00V-0 0/J_ 0/J_ 0/J_??m(??mils) +.0V_PH +V_S +V_S +V +V +V_S +V +.0V_PH +.V +.0V_PH R R 0/J_ +VFI_VRM *0/J_ VVRM:.V (estop) 0/0 del for Pre-ES.V (Mobile) +.0V_VTT m(mils) R VRT<m(mils) +V_RT 0/J_ *U/.V_.U/.V_ 0.U/0V_ +VSST +V.0M_VSUS +VTT_VPPU 0.U/0V_ 0.U/0V_ V PSST T PSUS[] V PSUS[] J V_PRO_IO PU MIS VSW[] T VSW[] V VSW[] T +.0V_VEPW VME =.0(0mils) +V U/.V_ 0.U/0V_ 0.U/0V_ VRT ougarpoint_rp0 RT H VSUSH P +V._._H_IO R *U/.V_ 0.U/0V_ 0/J_ +V_S VSUSH= 0m(mils) *0.U/0V_ *0.U/0V_ *0.U/0V_ *0.U/0V_ +.0V_PH L 0uH/00m +.0V_V PL +V + 0 0U/.V_ 0 U/.V_ R0 R *0/J_ /F_ L 0uH/00m_ +V_SUS_LKF L 0uH/00m +.0V_V PL 0U/.V_ U/0V_ + 0U/.V_ U/.V_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev ougar Point / ate: Monday, September, 00 Sheet of

13 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, September, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, September, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : ougar Point / Monday, September, 00 FH IEX PEK-M (GN) PH(LG) U0I ougarpoint_rp0 U0I ougarpoint_rp0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J U0H ougarpoint_rp0 U0H ougarpoint_rp0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L

14 M 0 M M M M M M 0 M M M M M M M M M SM_RUN_LK SM_RUN_T M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q IMM0_S0 IMM0_S R_RMRST# +SMR_VREF_IMM +SMR_VREF_Q0 SMR_VREF_Q0_M SMR_VREF_Q0_M +SMR_VREF_IMM SMR_VREF_Q0_M +SMR_VREF_IMM R_RMRST# M [:0] M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# M WE# M QSP[:0] M QSN[:0] M OT0 M OT M Q[:0] SM_RUN_LK 0,, SM_RUN_T 0,, R_RMRST#, SMR_VREF_Q0_M +.V_SUS +V +0.V_R_VTT +V +SMR_VREF +.V_SUS +SMR_VREF +.V_SUS +SMR_VREF_IMM +V +.V_SUS +0.V_R_VTT +SMR_VREF_Q0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Monday, September, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Monday, September, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Monday, September, 00 FH. R_ST(R) VREF Q0 M Solution Place these aps near So-imm0. 0/ Remove 0ohm to GN Note: ll VREF traces should have 0 mil trace width + *0U/V_ + *0U/V_ 0 u/.v_ 0 u/.v_ R0 *0/J_ R0 *0/J_ R *0/J_ R *0/J_ U/0V_ U/0V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R0 0/J_ R0 0/J_ 0 0.u/0V_ 0 0.u/0V_ U/.V_ U/.V_ 0 U/.V_ 0 U/.V_ R *0K/J_ R *0K/J_ 0 0U/.V_ 0 0U/.V_ 0.u/0V_ 0.u/0V_ 0U/.V_ 0U/.V_ 0 U/0V_ 0 U/0V_ P00 R SRM SO-IMM (0P) JIM R-IMM0_H=._RVS_LTS P00 R SRM SO-IMM (0P) JIM R-IMM0_H=._RVS_LTS 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0 U/0V_ 0 U/0V_ R0 K/F_ R0 K/F_ *0U/.V_ *0U/.V_ R0 *0/J_ R0 *0/J_ R 0K/J_ R 0K/J_ P00 R SRM SO-IMM (0P) JIM R-IMM0_H=._RVS_LTS P00 R SRM SO-IMM (0P) JIM R-IMM0_H=._RVS_LTS V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 0 0P/0V_ 0 0P/0V_ 0.U/.V_ 0.U/.V_ 0U/.V_ 0U/.V_ *0U/.V_ *0U/.V_ R K/F_ R K/F_ 0.u/0V_ 0.u/0V_.U/.V_.U/.V_ R0 0K/J_ R0 0K/J_ 0 U/.V_ 0 U/.V_ 0.U/.V_ 0.U/.V_ 0U/.V_ 0U/.V_ 0 0.u/0V_ 0 0.u/0V_ R0 0K/J_ R0 0K/J_ 0U/.V_ 0U/.V_ R0 0K/J_ R0 0K/J_ U/0V_ U/0V_ 0 0U/.V_ 0 0U/.V_

15 R_RVS(R) +V R R M [:0] M 0 M Q M 0 Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 M Q M Q M Q M Q M Q M Q M Q M 0 Q 0 M Q M 0/P Q0 M Q0 M Q M Q M /# Q M Q M Q 0 M Q M Q M Q Q M Q0 Q M Q M S#0 0 0 Q M Q M S# 0 Q M Q M S# Q M Q M S#0 0 S0# Q0 M Q M S# S# Q M Q M LKP0 0 0 K0 Q M Q M LKN0 0 K0# Q M Q M LKP 0 K Q M Q M LKN 0 K# Q M Q M KE0 KE0 Q M Q M KE KE Q M Q M S# S# Q M Q M RS# 0 RS# Q M Q M WE# 0K/J_ IMM_S0 WE# Q0 0 M Q0 0K/J_ IMM_S S0 Q 0 M Q 0,, SM_RUN_LK SM_RUN_LK S Q 0 M Q 0,, SM_RUN_T SM_RUN_T SL Q 00 M Q S Q SMR_VREF_Q_M M Q Q M OT0 0 M Q OT0 Q M OT 0 M Q OT Q M Q Q 0 M Q M0 Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q 0 M Q M Q M Q M QSP[:0] M Q 0 M Q M QSP0 Q M Q M QSP QS0 Q M Q M QSP QS Q M Q M QSP QS Q0 M Q M QSP QS Q M Q M QSP QS Q M Q M QSP QS Q M Q M QSP QS Q M Q0 M QSN0 QS Q 0 M Q M QSN QS#0 Q M Q0 M QSN QS# Q M Q M QSN QS# Q M Q M QSN QS# Q 0 M Q M QSN QS# Q0 M Q M QSN QS# Q M Q M QSN QS# Q M Q M QSN[:0] QS# Q 0/ Remove 0ohm to GN JIM P00 R SRM SO-IMM (0P) M Q[:0] SMR_VREF_Q_M R SMR_VREF_Q_M R +V, R_RMRST# 0/J_ *0/J_ Note: ll VREF traces should have 0 mil trace width. R +V +SMR_VREF_Q +SMR_VREF_IMM +.V_SUS *0K/J_ JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS 0 VTT VTT 0 GN 0 GN 0 R-IMM_H=._RVS_MLX +0.V_R_VTT R-IMM_H=._RVS_MLX +.V_SUS Place these aps near So-imm. 0U/.V_ 0U/.V_ 0U/.V_ U/0V_ U/0V_ +SMR_VREF_IMM +SMR_VREF_Q 0U/.V_ 0U/.V_ 0U/.V_ 0.u/0V_ 0.U/.V_ 0.u/0V_ 0.U/.V_ 0U/.V_ 0U/.V_ *0U/.V_ U/0V_ U/0V_ +V +0.V_R_VTT.U/.V_ 0.u/0V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ 0U/.V_ *0U/.V_ VREF Q M Solution +.V_SUS ST H ST H FOX R K/F_ LTK GMK00000 GMK0000 +SMR_VREF R *0/J_ SMR_VREF_Q_M R K/F_ SUY MLX GMK0000 GMK00000 Standard H type:r--00-0p- Quanta omputer Inc. PROJET : FH Size ocument Number Rev RIII SO-IMM- ate: Monday, September, 00 Sheet of

16 PEX_IOV+PEX_IOVQ+PEX_PLLV >. 000m U +.0V_GPU fcbga-nvidia-np-ge OMMON *EV@0.U/0V_ K PLE NER LLS EV@0.U/0V_ PEX_IOV_ PEX_RX0 K EV@0.U/0V_ PEX_IOV_ PEX_RX0* K EV@U/.V_ PEX_IOV_ PEX_RX K EV@U/.V_ PEX_IOV_ PEX_RX* K PLE NER G EV@.U/.V_ PEX_IOV_ PEX_RX EV@0U/.V_ PEX_RX* EV@U/.V_ PEX_RX PEX_RX* PEX_RX PEX_RX* +.0V_GPU G PEX_IOVQ_ PEX_RX G *EV@0.U/0V_ PEX_IOVQ_ PEX_RX* G PLE NER LLS EV@0.U/0V_ PEX_IOVQ_ PEX_RX G EV@0.U/0V_ PEX_IOVQ_ PEX_RX* G EV@U/.V_ PEX_IOVQ_ PEX_RX G EV@U/.V_ PEX_IOVQ_ PEX_RX* G PLE NER G EV@.U/.V_ PEX_IOVQ_ PEX_RX G EV@0U/.V_ PEX_IOVQ_ PEX_RX* G EV@U/.V_ PEX_IOVQ_ PEX_RX G PEX_IOVQ_0 PEX_RX* G PEX_IOVQ_ PEX_RX0 G PEX_IOVQ_ PEX_RX0* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_ PEX_RX* J PEX_IOVQ_ PEX_RX J PEX_IOVQ_0 PEX_RX* K PEX_IOVQ_ PEX_RX K0 PEX_IOVQ_ PEX_RX* K PEX_IOVQ_ K PEX_IOVQ_ 0m L PEX_IOVQ_ PEX_TX0 +V_GPU PEX_TX0* PLE NER G EV@.U/.V_ PI EXPRESS PEX_TX EV@U/.V_ PEX_TX* J0 EV@0.U/0V_ V_ PEX_TX J PLE NER LLS EV@0.U/0V_ V_ PEX_TX* J EV@0.U/0V_ V_ PEX_TX J V_ PEX_TX* J V_ PEX_TX PEX_TX* 0 V_SENSE PEX_TX VGPU_V_SENSE N_/ V_SENSE PEX_TX* P N_/ V_SENSE PEX_TX VGPU_VSS_SENSE PEX_TX* PEX_TX 0m 0-ohm / ESR=0. +.0V_GPU L EV@LMGSN GN_SENSE PEX_TX* E N_0/ GN_SENSE PEX_TX R EV@.U/.V/XR_ N_/ GN_SENSE PEX_TX* PLE NER G EV@U/.V/XR_ PEX_TX PEX_TX* *EV@U/.V_ +PEX_PLLV PEX_TX0 G *EV@U/.V_ PEX_PLLV PEX_TX0* PEX_TX EV@0.U/0V/XR_ PEX_TX* PEX_TX PLE NER LLS PEX_TX* PEX_TX 0m +V_GPU L EV@0_ +PEX_SV_V PEX_TX* G +.0V_GPU L0 *EV@0_ PEX_L_P_VQ/ PEX_SV_V PEX_TX F N_/ PEX_SV_V PEX_TX* EV@0.U/0V_ PEX_TX PLE NER LLS EV@.U/.V_ PEX_TX* G0 PEX_L_PU_GN/ N PEX_REFLK N_ PEX_REFLK* N_ N_ F N_ PEX_TSTLK_OUT G N_ PEX_TSTLK_OUT* J N_ K N_ L R EV@0K_ N_ PEX_RST* E N_ H N_ PEX_LKREQ* M R0 EV@0.K/F_ N_ P N_ PEX_TERMP U N_ V N_ TESTMOE P N N P R R0 P0 N0 N P R R P N N P R R P N N P R R P N N P R R R P L M M M L K L0 M0 M M L K L M M M L K L M M M L K K L M M0 M M N P R R J J M PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP0_ PEG_RXN0_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP_ PEG_RXN_ PEG_RXP0_ PEG_RXN0_ PEX_TSTLK R PEX_TSTLK# VG_RST# R PEX_LKREQ# R0 G P PEX_TERMP TESTMOE EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ EV@0.U/0V_ LK_PIE_VGP 0 LK_PIE_VGN 0 R R0 *EV@00/J_ R EV@0K/J_ EV@.K/F_ EV@0K/J_?? EV@0/J_ +V_GPU PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP0 PEG_TXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 R0 EV@00K/J_ GPU_RST#,0,,,, PLTRST# GPU_HOL_RST# GPU_RST# GPU RST# GPU all PWROK +.V_GPU R *EV@000P/0V/XR_@N GFXPG PEX_LKREQ# EV@0K_ R R EV@00K/J_ +V *EV@0K/F_ EV@0.U/0V_ +V_GPU GPU_RST# +V +V_GPU U EV@TSH0FU R EV@0K_ Q EV@PTTT R EV@0K/J_ R EV@0K_ Q EV@TEU GFXPG Q EV@MMT0 R Q EV@TEU GFXPG, *EV@0K/J_ +V PIE_LKREQ_PEG# 0 Ffor NP-GE, they can be unstuffed by default Quanta omputer Inc. PROJET : FH Size ocument Number Rev NP-GE (PIE I/F) / ate: Monday, September, 00 Sheet of