Tablet SYSTEM BLOCK DIAGRAM

Transcript

1 VER : OM P/N escription Tablet SYSTEM LOK IGRM Memory own Max. G P M* R III /00 MHZ IM FI Ivy ridge G 0 W P,,,, MI ep US- ep onn. TOUH PNEL P MI(x) mst - H P0 ST FI MI Gyroscope P ST LG0 e-compass/ G sensor P ST LSM0LH US Port US.0 * P Sensor Hub ST P STMF0RYTR US.0 US- US- US.0 Panther Point isplay PI-E x HMI PIE- HMI onn. P WLN+T Light sensor P LM MOP onn. FRONT P onn. RER P US-0 US- US.0 PH G P,,, 0,, PI-E x X'TL.KHz US-0 FOXONN TH.00 P0 POGO ONN P US- X'TL MHz P zalia TTERY RT IH LP SPI SPI ROM P M+M MI UIO OE RELTEK L-V P LP E NUVOTON WPE P TPM INFINEON SL P atery harger V/V P P +.0V +.V/+V P P +VGFX_XG PU core P P OM Option Table Reference escription EV@ Optimize SKU SN@ For Sandy bridge. Speaker MI/HP JK WXVSSG SPI FLSH P Fan river P +VGPU_IO P ischarger P Thermal Protection P IV@ For Ivy bridge. IV@ For UM. * do not stuff Quanta omputer Inc. PROJET : EE Size ocument Number Rev lock iagram Wednesday, September, 0 ate: Sheet of

2 () () () () () () MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_iompo mil ep_ompio mil EP_UX# EP_UX EP_TX0# EP_TX# EP_TX0 EP_TX EP_OMP INT_EP_HP# Ivy ridge Processor (MI,PEG,FI) U M P MI_RX#[0] P MI_RX#[] P0 MI_RX#[] MI_RX#[] N P MI_RX[0] P MI_RX[] P MI_RX[] MI_RX[] K M MI_TX#[0] N MI_TX#[] R MI_TX#[] MI_TX#[] K M MI_TX[0] P MI_TX[] T MI_TX[] MI_TX[] U W FI0_TX#[0] W FI0_TX#[] FI0_TX#[] W FI0_TX#[] V FI_TX#[0] Y FI_TX#[] FI_TX#[] FI_TX#[] U W0 FI0_TX[0] W FI0_TX[] FI0_TX[] W FI0_TX[] T FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN U FI_INT 0 G FI0_LSYN FI_LSYN F ep_ompio G ep_iompo ep_hp G F ep_ux# ep_ux ep_tx#[0] E ep_tx#[] E ep_tx#[] ep_tx#[] ep_tx[0] E0 ep_tx[] E ep_tx[] ep_tx[] MI Intel(R) FI P PI EXPRESS -- GRPHIS G PEG_IOMPI PEG_IOMPO G PEG_ROMPO G H PEG_RX#[0] J PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] 0 PEG_RX#[] G PEG_RX#[0] PEG_RX#[] PEG_RX#[] H PEG_RX#[] E PEG_RX#[] K PEG_RX#[] K PEG_RX[0] K PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] F PEG_RX[0] PEG_RX[] PEG_RX[] H PEG_RX[] F PEG_RX[] K PEG_RX[] G PEG_TX#[0] PEG_TX#[] PEG_TX#[] F PEG_TX#[] H PEG_TX#[] PEG_TX#[] K PEG_TX#[] F PEG_TX#[] F PEG_TX#[] PEG_TX#[] J PEG_TX#[0] H PEG_TX#[] M0 PEG_TX#[] F0 PEG_TX#[] PEG_TX#[] J PEG_TX#[] PEG_OMP PEG_IOMPO mil PEG_IOMPI, PEG_ROMPO mil, +V Thermal Sensor () () 0.u/0V_ THERML+ THERML- THM_TRIT# +V +V R 0K_ U V + - TRIT# NTW THM_LERT# PEG_IOMPI and ROMPO signals should be shorted and routed with - max length = 00 mils - typical impedance = mohms PEG_IOMPO signals should be routed with - max length = 00 mils - typical impedance =. mohms SLK ST LERT# THM_LERT# THM_LK () THM_T () THM_TRIT# 0.uF coupling aps for PIE GEN// P_OMPIO and IOMPO signals should be shorted near balls and routed with - typical impedance < mohms P & PEG ompensation G.0 : The recommended cap value is changed to 0nF for compatibility with PIe Gen on future platforms. For Gen only designs, it is acceptable to continue to use the 00nF capacitor. ep Hot-plug (isable) +.0V_VTT LERT# Pull Up Value K ohm.k ohm 0.K ohm lert temperature point degree 0 degree 00 degree +.0V_VTT K ohm.k ohm 0 degree 0 degree EP_OMP INT_EP_HP# F PEG_TX[0] PEG_TX[] PEG_TX[] E PEG_TX[] G PEG_TX[] PEG_TX[] K PEG_TX[] G PEG_TX[] E PEG_TX[] PEG_TX[] K PEG_TX[0] G PEG_TX[] K0 PEG_TX[] G0 PEG_TX[] PEG_TX[] K PEG_TX[] 0u/.V_ R0 0K_ SN_G_P0 R K_ R./F_ PEG_OMP R +.0V_VTT./F_ Note: Place PU resistor within inches of PU HP PU/P resistor values based on R and different to G Q N00 EP_HP R 00K_ EP_HP () Quanta omputer Inc. PROJET : EE Size ocument Number Rev Ivy ridge / ate: Wednesday, September, 0 Sheet of

3 oot S S RSM (,,) (0) H_PROHOT# PM_THRMTRIP# (0) () Over 0 degree will drive low () H_SN_IV# PM_SYN H_PWRGOO Isolate Space:0mils +.0V_VTT R /F_ PU_PLTRST# E_PEI R _ H_PROHOT#_R 0 *P/0V_N R TP PM_RM_PWRG_R TP0 TP 0.U/0V_ 0K_ R _ Ivy ridge Processor (LK,MIS,JTG) TP_TERR# PU_PLTRST#_R R F E U PRO_SELET# PRO_ETET# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM LK J H LK# PLL_REF_LK G G PLL_REF_LK# LK_ITP N N LK_ITP# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] T0 N PRY# N PREQ# TK L TMS L J TRST# M0 TI TO L LK_PIE_XPP_R LK_PIE_XPN_R Isolate Space:0mils Impedance ohm XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI XP_TO TP F SM_ROMP_0 R E SM_ROMP_ R G SM_ROMP_ R0 TP TP TP TP0 TP TP TP TP0 R R0 K XP_RST#_R R 0_ R# G PM#[0] E PM#[] E PM#[] G PM#[] G PM#[] H0 PM#[] J PM#[] J PM#[] TP LK_PU_LKP () LK_PU_LKN () *0_ *0_ PU_RMRST# (,) 0/F_./F_ 00/F_ TP XP_TLK () XP_TMS () XP_TO () +.V_PU RM_PWRG SYS_PWROK SM_RMPWROK LK_PLL_SSLKP () LK_PLL_SSLKN () LK_PIE_XPP () LK_PIE_XPN () NOTE: ll R_OMP signals should be routed such that :- - max length = 00 mils - trace width = mils and - M trace impedance < mohms (worst case resistance) XP_RST# TP0 TP Option for Prochot# function ohm for unused, ohm for used 00 ns after +.V_PU reaches 0% If motherboard only supports external graphics or if it supports Processor Graphics but without ep: onnect PLL_REF_SSLK on Processor to through K +/- % resistor. onnect PLL_REF_SSLK# on Processor to VP through K +/ - % resistor H_PROHOT# XP_TMS XP_TI XP_TO XP_PREQ# R0 _ R _ R _ R _ R0 *_ +.0V_VTT *0/F_ TP0 XP_TLK XP_TRST# R _ R _ SN_G_P0 When MP, JTG PU/P resistor can be removed? (Yes Intel, TI, TO, TMS, TRST#, TK,PREQ#, PRY#) +V Thermal Trip <PU> +.0V_VTT +V_S R *K_ s leakage circuit R *0K_ If PM_RM_PWEG connector,the R0 must stuff. +V_S 0.u/0V_ +.V_PU (,) PI_PLTRST# U N V IN OUT LVG0GW_N 0 0.U/0V_ PU_PLTRST# (,) IMVP_PWRG PM_THRMTRIP# R0 K_ Q N00 Q MMT0 SYS_SHN# (,,) +.V_PU PM_RM_PWRG SYS_PWROK *N00W Q R 0_ R U HG0 *0_ PM_RM_PWRG_Q R 00/F_ (,) R R *_ MINON_ON_G 0/F_ Q PM_RM_PWRG_R *N00 R0 IN L H PU_PLTRST#_R OUT ate: Wednesday, September, 0 Sheet of L High-Z Quanta omputer Inc. PROJET : EE Size ocument Number Rev Ivy ridge / *.K/F_

4 Sandy ridge Processor (R) U U () M Q[:0] () () () () () () M S#0 M S# M S# M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q G J P L J0 J L L R P U V R P T U Y V R Y R U R W R T Y V Y U V P0 P V T P P N N G G N N G K F E T S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] U V Y T0 U0 0 Y0 L R V T V Y T K J R0 Y U W V T K G E T U T Y V E 0 0 W Y U M LK M LK# M KE M S# M OT M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M TP TP TP M LK0 () M LK0# () M KE0 () M S#0 () M OT0 () M QSN[:0] () M QSP[:0] () M [:0] () L L N R K K N R U T V U R Y E F F 0 E F E E E E G G F 0 F F E E F E Y0 E G W W U N N U U N R K L G G M0 L F H0 G T V F0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y R F E E T G L V G G T0 K M V E E R K F E U0 0 V0 G0 E0 E T V T U SN_G_P0 SN_G_P0 M LK M LK# R /F_ +0.V_R_VTT u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ 0u/.V_ +0.V_R_VTT s leakage circuit S circuit:- RM_RST# to memory should be high during S () 000 hange to E for new IOS 0. +V_S 00 move R to near Q and del net RMRST_NTRL_PH, and E_RMRST_NTRL and R. Q N00 () R_RMRST# R K/F_ PU_RMRST# (,) E_RMRST_NTRL () EEPS_E R 0_ +.V_SUS R K/F_ R K_ R *0_ 0 0.0u/0V_ R.K/F_ M 0 M M M M M M M M M M 0 M M M M M R _ R _ R _ R _ R _ R0 _ R _ R _ R _ R _ R _ R _ R _ R _ R _ R _ M WE# M S# M RS# M S#0 M S# M KE0 M OT0 M S#0 M S# R _ R _ R _ R _ R _ R0 _ R _ R _ R _ +0.V_R_VTT Quanta omputer Inc. PROJET : EE Size ocument Number Rev Ivy ridge / Wednesday, September, 0 ate: Sheet of

5 + + +.u/0v_.u/0v_.u/0v_.u/0v_ 0.u/0V_ PU ore Power IVY W:T 0.u/0V_.u/0V_ 0.u/0V_.u/0V_.u/0V_ IVY SPE.mΩ/Loadlineesign total :.uf x total : uf x tatal : 0u x(power side*) ose down IVY SPE.mΩ/Loadlineesign total :.uf x total : 0uF x tatal : 0u x(power side*) 000 remove for debug I. 000 remove for debug I..u/0V_.u/0V_.u/0V_ 0.u/0V_ 00.u/0V_ 0u/.V_ 0u/.V_ 0u/.V_.u/0V_ 0.u/0V_.u/0V_.u/0V_.u/0V_ 0u/.V_.u/0V_.u/0V_.u/0V_ 0u/.V_.u/0V_.u/0V_ 0u/.V_ 0u/.V_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_ u/.V_ 0.u/0V_ 0u/V_ 0u/.V_ 0 0u/.V_.u/0V_.u/0V_.u/0V_ 0.u/0V_ Sandy ridge Processor (POWER) +V_ORE 0 + 0u/V_ E E E E E E F F F F F F F F G H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N UF V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] SN_G_P0 ORE SUPPLY POWER PEG N R SENSE LINES SVI QUIET RILS VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO0 VIO VIO_SEL VPQE[] VPQE[] VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO F G G0 G J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 G G G G0 G J J W W M N F G N N +.0V_VTT VIO_SEL H_PU_SVILRT# H_PU_SVILK H_PU_SVIT PU VIO IVY W:. ose down SN : Spec 0uF/mohm x 0uF/mohm x 0uF x 0 uf x / hange form to 0u/.V_ 0u/.V_ 0 R 0_ R 0_ 0u/.V_ 0uF x 0 uf x u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ IVY SPE uf_ x Socket TOP cavity uf_ x Socket OT cavity uf_ x Socket TOP cavity (no stuff) uf_ x Socket OT cavity (no stuff) 0uF_ x +V_ORE +.0V_VTT + 0u/V_ 0u/.V_ +.0V_VTT Voltage selection for VIO: this pin must be pulled high on the motherboard +.0V_VTT u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ R 00_ R 00_ 0u/.V_ 0u/.V_ TP U/.V_ 0 0 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0 On R H_SN_IV#_PWRTRL = low,.0v H_SN_IV#_PWRTRL = high/n,.0v V_SENSE () VSS_SENSE () VP_SENSE () VSSP_SENSE () PU VXG IVY W:T Spec.mΩ/Loadlineesign total : uf x total : 0uF x total : uf x tatal : 0u x (power side*) PU VPL IVY W:. Spec Real 0uF/mohm x 0uF x uf x uf x IVY SPE 0uF x, 0uF_ x, uf_ x Socket OT edge. ose down.mω/loadlineesign total : uf x total : 0uF x tatal : 0u x (power side*) IVY SPE 0uF x, 0uF_ x Socket OT edge, 0uF_ x Socket OT cavity. PU VS IVY W: Spec 0uF/mohm x 0uF x uf x Real 0uF x 0u/.V_ 0u/.V_ u/.v_ VXG_SENSE/VSSXG_SENSE R=00, Trace impedance.~., <mils. () () 0 0u/.V_ 0u/.V_ 0u/.V_ 0 u/.v_ u/.v_ +V_GFX V_XG_SENSE VSS_XG_SENSE +.V_PU 0u/.V_ u/.v_ 0u/.V_ 0u/.V_ u/.v_ 0 0u/.V_ u/.v_ u/.v_ 0 0u/.V_ 0u/.V_ u/.v_ u/.v_ S STUFF NO_STUFF enable - u/.v_ 0 PU_VPLL 0 u/.v_ u/.v_ 0u/.V_ 0 disable - R/R 0u/.V_ 0u/.V_ u/.v_ 0 u/.v_ / hange form to +SMR_VREF +VR_REF_PU +.V_PU Sandy ridge Processor (GRPHI POWER) 0u/.V_ 0 0u/.V_ u/.v_ TP R 00_ R 00_ 0u/.V_ u/.v_ 0u/.V_ 0 u/.v_ TP +V_GFX + *0u/V_ + 0u/V_ u/.v_ +VS R/R 0 0 E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y F G L L N N0 N P P0 R R R U V V V V W0 UG VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG_SENSE VSSXG_SENSE VPLL[] VPLL[] VPLL[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[] VS[0] VS[] VS[] VS[] VS[] VS[] VS[] SN_G_P0 000 Intel PG change. GRPHIS +.V_SUS POWER SENSE LINES.V RIL S RIL SENSE LINES R -.V RILS QUIET RILS SM_VREF VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ_SENSE VSS_SENSE_VQ Q MVQ VS_SENSE VS_VI[0] VS_VI[] Note: +VR_REF_PU should have 0 mil trace width +.V_PU +VR_REF_PU R *00/F_ U0 +VS VS_SENSE SN_IV# N. at SN ES # 0.v R for SN ridge 000 Intel PG change to.v +.V_PU Y J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 G M N R0 R R0 R 000 Intel PG change 0u/.V_ 0u/.V_ 0 u/.v_ u/.v_ U/.V_ *_ *_ *0K_ *0K_ 0 0u/.V_ *0u/.V_ u/.v_ u/.v_ *n/0v_ R 0_ 0u/.V_ *0u/.V_ u/.v_ 0 u/.v_ +.V_PU 0u/.V_ u/.v_ +.V_PU VI[0] 0 PU VQ IVY W: Spec 0uF/mohm x For SN ridge VI[] 0 0uF x uf x 0 0 0u/.V_ 0u/.V_ u/.v_ u/.v_ u/.v_ 000 Intel PG change / hange form to 000 Intel PG change 00 for Intel fw issue, if solve need un-stuff. VS_VI0 VS_VI -K pull-down resistor should be placed on the VS VI lines. This will ensure the VI is 00 prior to VIO stability.. VI[] 0 +VS 0.V 0.V For IV ridge +VS 0.V Layout note: need routing together and LERT need between LK and T SVI LK H_PU_SVILK R 0_ VR_SVI_LK () Place PU resistor close to PU SVI T +.0V_VTT R 0/F_ H_PU_SVIT R 0_ VR_SVI_T () Place PU resistor close to PU +.0V_VTT R /F_ H_PU_SVILRT# R _ VR_SVI_LERT#_R R 0_ SVI LERT VR_SVI_LERT# () (,) MIN MIN R *0_ S circuit:.v input to IV is gated & IV Read Vref 0.V is gated Q N00 R 00K_ R *K/F_ R *K/F_ change to K/F_ (,) MINON_ON_G MIN MINON_G R 0_ 0P/0V_ Q MN0K- 0 0.V 0 0.V 0.V Quanta omputer Inc. PROJET : EE Size ocument Number Rev Ivy ridge / ate: Wednesday, September, 0 Sheet of

6 Sandy ridge Processor () Sandy ridge Processor (RESERVE, FG) UH UI UE E S_IMM_VREFQ G S_IMM_VREFQ E E F F F F F F0 F F F F F F F G0 G G G G G G H H J J J0 J J J0 J J J J J J K K L0 L L L L L L L L0 L L L M M0 M M M0 M VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] M M M M M M N N N N N N N0 N N N0 N P0 P P P R R R R R R R T T T T T T T U U U U U U V V V V V0 V V W W W W Y Y Y0 Y Y Y Y Y Y Y Y 0 E G R *0_ G G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] VSS[0] VSS[] 0 VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] 0 VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[] E0 VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F0 VSS[] F VSS[] G VSS[0] G VSS[] G VSS[] G VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L0 VSS[] L VSS[0] L VSS[] L0 VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] VSS[0] SN_G_P0 VSS NTF Processor Strapping FG (PI-E Static x Lane Reversal) FG (PI-E Static x Lane Reversal) M VSS[] M VSS[] M VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] N0 VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R0 VSS[] R VSS[] R VSS[] T VSS[0] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] V0 VSS[0] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[00] Y VSS[0] VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ G VSS_NTF_ G VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ Normal Operation Normal Operation TP TP FG FG FG FG FG FG FG TP TP TP TP TP TP TP The FG signals have a default value of '' if not terminated on the board. 0 Lane Reversed Lane Reversed 0 FG[0] FG[] FG[] FG[] FG[] FG[] H FG[] FG[] H FG[] K FG[] K FG[0] F FG[] G FG[] L FG[] F FG[] FG[] L FG[] FG[] H K V_VL_SENSE VSS_VL_SENSE SN_G_P0 FG FG RESERVE H K VXG_VL_SENSE VSSXG_VL_SENSE F V_IE_SENSE H K RSV RSV V RSV T RSV RSV0 RSV Y RSV RSV Y RSV U RSV U RSV RSV RSV RSV RSV0 G RSV E RSV G RSV E RSV F RSV E RSV RSV R0 R _TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_ E _TEST_E E _TEST_E G _TEST_G G _TEST_G G _TEST_G G _TEST_G G _TEST_G E _TEST_E G _TEST_G E _TEST_E _TEST_ *K/F_ *K/F_ E RSV G RSV N RSV0 L RSV L RSV L RSV M RSV M RSV U RSV W RSV P RSV T RSV K RSV0 H RSV G RSV M RSV M RSV RSV SMR_VREF_Q0_M () for M solution need R/R, W/O M then N FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG 00 stuff for revers FG FG FG N0 R0 R0 R0 R0 processor signal balls F and G for Ivy ridge -core and balls E and G for Ivy ridge -core K/F_ K/F_ R R *K/F_ *K/F_ *K_ *K_ SN_G_P0 FG (P Presence Strap) FG (PEG efer Training) isable; No physical P attached to ep Enable; n ext P device is connected to ep PEG train immediately following xxreset de assertion PEG wait for IOS training Quanta omputer Inc. PROJET : EE Size ocument Number Rev Ivy ridge / ate: Wednesday, September, 0 Sheet of

7 PT/PPT (LVS,I) 0 () (0,) () () () () () 00 add SUSWEN to SUSK connector. SUSK# SUSWRN#_R SYS_PWROK R 0_ PWROK_ER0 0_ PM_RM_PWRG PH_RSMRST# NSWON# () () () () () () () () () () () () () () () () XP_RST# IO_PIERST# PRESENT +.0V_VTT R MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP *0_ R R R 0_ R R0 TP PRESENT *U/0V_ R0./F_ 0/F_ *0_ XP_RST# R 0_ *0_ *0_ MI_OMP SUSK#_R SYS_PWROK_R E_PWROK_R PWROK_R PM_RM_PWRG PH_RSMRST# SUSWRN#_R PT/PPT (MI,FI,PM) U E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H K P L L0 K E0 H0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_RESET# SYS_PWROK PWROK PWROK RMPWROK RSMRST# MI System Power Management +V +V_S +V_S +V_S SUSWRN#/SUSPWRNK/GPIO0 +V_S SLP_S# PWRTN# PRESENT / GPIO SW FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SWVRMEN PWROK WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SLP_# SLP_SUS# J Y E H J G0 G G F G E G J0 H W V 0 V 0 E N G N 0 H F G0 G PWROK_R Need notice IOS if MI or FI reverse. PIE_WKE#_LN LKRUN# PH_SUSLK SLP_# SLP_SUS# SWVREN () R 0_ TP TP TP0 TP FI_TXN0 () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXN () FI_TXP0 () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () FI_TXP () 00 FI reverse 0 FI change to normal FI_INT () FI_FSYN0 () FI_FSYN () FI_LSYN0 () FI_LSYN () LKRUN# (,) SUS# () SUS# () () () () PWROK need to be shorted to RSMRST# when eep S/S state is not support PWROK () SLP_SUS# (,) INT_LVS_LON INT_LVS_IGON INT_LVS_RIGHT UM VG/LVS disable 000 change PWROK from PH_Rsmrst# to E control. _IREF R0 K/F_ % or % J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN Panther Point_RP0 LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y M M T T H F E F E J G INT_HMITXN_ INT_HMITXP_ INT_HMITXN_ INT_HMITXP_ INT_HMITX0N_ INT_HMITX0P_ INT_HMILK-_ INT_HMILK+_ isplayport isplayport HMI_LK_SW () HMI_T_SW () HMI_HP () INT_HMITXN_ () INT_HMITXP_ () INT_HMITXN_ () INT_HMITXP_ () INT_HMITX0N_ () INT_HMITX0P_ () INT_HMILK-_ () INT_HMILK+_ () INT. HMI PM_TLOW# E0 TLOW# / GPIO +V_S PMSYNH P PM_SYN () PM_RI# 0 RI# +V_S SLP_LN# / GPIO K SLP_LN# Panther Point_RP0 PH Pull-high/low(LG) +V +V_S System PWR_OK(LG) +V_S IMVP_PWRG PU +V PWROK_E P so N gate output dont need P again +V_S () FWS 00 FWS for 00msce timing. R 0_ LKRUN# R XP_RST# R R0 PH_RSMRST# R0 SYS_PWROK R0.K_ PM_RI# R 0K_.K/F_ PM_TLOW# R0.K_ *K_ PIE_WKE#_LN R 0K_ 0K_ SLP_LN# R *0K_ SUSWRN#_R R 0K_ *0K_ PRESENT R *0K_ PM_RM_PWRG R 00/F_ wo S leakage, un-stuff R0 () to PH Pin, XP and EE debug SYS_PWROK SYS_PWROK U TSH0FU R 0.u/0V_ PWROK_E *0_ R 00K_ PWROK_E () U IMVP_PWRG_R *TSH0 *0.U/0V_ IMVP_PWRG (,) GFX_PWRG (,) R 0_ 0 add 0ohm to passed IMVP_PERG include GFX_PWRG to SYS_PWROK for PH check (,) +0.V_ON R *0_ PWROK_R R0 0K_ Quanta omputer Inc. PROJET : EE Size ocument Number Rev Panther Point / Wednesday, September, 0 ate: Sheet of

8 RT ircuitry(rt) +V_RT PH(LG) p/0v_ PT/PPT (H,JTG,ST) 0 H us(lg) () 0mils PH JTG ebug (LG) PH ual SPI (LG) () () () () +V_PH_ME +VPU VRT_ R _ () () () () PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO PH_SPI_S# PH_SPI_LK PH_SPI_SI PH_SPI_SO PH_SPI_LK_E PH_SPI_SI_E PH_SPI_SO_E +V_PH_ME +V_S SPI_S0#_UR_ME R 0_ R *p/0v_ 0MIL PH_Z_OE_ITLK PH_Z_OE_SYN PH_Z_OE_RST# PH_Z_OE_SOUT R0 0/F_ R 00/F_ +V_S R _ R0 _ R0 _ R R 0/F_ R 00/F_.K_ 0 T XP_TMS XP_TO PH_JTG_TO XP_TLK 0mils For EMI solution. 0 *p/0v_ Z_ITLK_R Z_SYN_OE Z_RST#_R Z_SOUT_R WQVSSIG / KEP0N >M KEGN0Q00 (realtek) WQVSSIG / KEFP0N0----->M KEGN0Q00 (realtek) R0 _ R _ R _ *p/0v_.k_ R 0/F_ R 00/F_ R 0_ U E# SK SI SO WP# R ROM-M_ME U E# SK SI SO WP# R u/.v_ V HOL# ROM-M_E VSS R0 0K_ 0K_ R _ R0 _ R _ R _ V HOL# VSS R0 R0 *0_ R 0_ 0 u/.v_ u/.v_ +V_PH_ME.K_.K_ J RT_RST# *SHORT_ P J SRT_RST# *SHORT_ P +V_PH_ME 0.u/0V_ +V_PH_ME 0.u/0V_ PH_SPI_S0# PH_SPI_S# dd MOSFET to separate OE SYN signal PH Strap Table Pin Name Strap description Sampled onfiguration 0 = efault (weak pull-down 0K) SPKR No reboot mode setting PWROK = Setting to No-Reboot mode GNT# / GPIO GNT# / GPIO GPIO F_TVS Top-lock Swap Override oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] MI/FI Termination voltage PWROK INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up GPIO On-die PLL Voltage Regulator PWROK PWROK H_SO Flash escriptor Security RSMRST PWROK RSMRST# 0 = "top-block swap" mode = efault (weak pull-up 0K) GNT# 0 = overridden GNT0# 0 +V H_OK_EN# / GPIO +V H_OK_RST# / GPIO +V_S oot Location SPI LP 0 = effect (default)(weak pull-down 0K) 0 = Set to Vss (weak pull-down 0K) = Set to Vcc 0 = isable = Enable (weak pull-up 0K) * +V +V efault weak pull-up on GNT0/# S_IT () [Need external pull-down for LP IOS] S_IT0 for future PU, Sandy ridge N F_TVS needs to be pulled up to VccFTERM power rail through. kohm ±% - R change to 0 or not?? H_SYN On-ie PLL VR Voltage Select RSMRST 0 = Support by.v (weak pull-down) Z_SYN_R +V_S R K_ Needs to be pulled High for Huron River platform. = Support by.v chklist. GPIO SWVREN +V Z_SYN_OE R.0 R 0_ R0 M_ () Intel ME rypto Transport Layer Security (TLS) cipher suite internal P EEP S/S well On ie SW VR Enable p/0v_ Q N00 () RSMRST SW SPKR PH_Z_OE_SIN0 () +V_RT () () +V_PH_ME Y.KHZ R TP TP XP_TLK XP_TMS XP_TO R0 R 0M_ M_ TP *K_ RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK_R Z_SYN_R SPKR Z_RST#_R Z_SOUT_R PH_GPIO PH_GPIO XP_TLK XP_TMS XP_TO PH_JTG_TO 0 = isable (efault) = Enable TP PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO High = Enable (efault) Low = isable G K N L T0 K E G N J H K H T Y T V U U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO JTG_TK JTG_TMS JTG_TI JTG_TO SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO Panther Point_RP0 RT IH JTG SPI () +V +V_RT ME_WR# +V_S +V_RT ST LP ST G FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPI STLE# ST0GP / GPIO STGP / GPIO R0 R R R R SERIRQ STIOMPO STROMPO STOMPI STRIS R R R R.K_ K_ R E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 H P V P *K_ 0K_ *K_ *K_ 0K_ *K_ *K_ PH_RQ#0 PH_RQ# UM ST port, disable. ST_OMP ST_OMP ST_RIS PU 0k to +V, becaue no sata LE. ST_T# PH_O_EN S_IT0 0 add R PU 0K to +V for PH_O_EN not use. SPKR R 0_ PI_GNT# () PH_INVRMEN Z_SOUT_R -test change to +.V_SUS +.V_SUS K_ R R0 R TP TP.K_ R00 R0 R 0K_ F_TVS (0) H_SN_IV# () PLL_OVR_EN (0) PH_GPIO (0) *0K_ R SWVREN TP0./F_ LP_L0 (,0,) LP_L (,0,) LP_L (,0,) LP_L (,0,) LP_LFRME# (,0,) SERIRQ (,) TP./F_ 0/F_ 0K_ ST_RXN0 (0) ST_RXP0 (0) ST_TXN0 (0) ST_TXP0 (0) mst G recommended that coupling capacitors should be close to the connector (<00 mils) for optimal signal quality. +V +V +.0V_VTT +V Used as GPIO only. at chklist. ST0GP/GPIO STGP/GPIO STGP/GPIO If these pins are unused use.k to 0k pull-up to +Vcc_ or.k to 0k pull-down to ground ME_WR default E setting folating SPI_S0#_UR_ME R K_ +V_PH_ME NV_LE Intel nti-theft H protection Only for Interposer PWROK 0 = isable (Internal pull-down 0kohm) +.V_SUS R *K_ -test change to +.V_SUS NV_LE () Quanta omputer Inc. PROJET : EE Size ocument Number Rev Panther Point / Wednesday, September, 0 ate: Sheet of

9 TX cap place at connector side, cap to connector < 00mils () () () () (0) () () (,) PLK_TPM LK_PI_F LK_LP_EUG LK_PI_E () (0) () R _ TP L TP TP *MM000GE/00m/0ohm R0 _ TP0 R _ TP L S_IT OR_I PI_GNT# PI_PLTRST# R _ R _ R _ R _ TP TP *MM000GE/00m/0ohm R _ TP TP TP TP PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_EISEL# GPU_SELET# REQ# OR_I MP_PWR_TRL# GPU_PWR_EN GPU_HOL_RST# EXTTS_SNI_RV_PH PI_PLTRST# PI_PME# PLK_TPM_R LK_PI_F_ LK_LP_EUG_ LK_PI PT/PPT (PI,US,NVRM) G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 UE TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 RSV US.0 US0_RXN US0_RXN US0_RXN US0_RXN US0_RXP US0_RXP US0_RXP US0_RXP US0_TXN US0_TXN US0_TXN US0_TXN US0_TXP US0_TXP US0_TXP US0_TXP PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 +V REQ# / GPIO +V REQ# / GPIO +V GNT# / GPIO +V GNT# / GPIO +V GNT# / GPIO +V PI PIRQE# / GPIO +V PIRQF# / GPIO +V PIRQG# / GPIO +V PIRQH# / GPIO +V PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI Panther Point_RP0 US RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS +V_S O0# / GPIO +V_S O# / GPIO0 +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO +V_S O# / GPIO0 +V_S O# / GPIO Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L US_IS US_O0# US_O# US_O# RM_I0 US_O# RM_I RM_I RM_I NV_LE () USP0- () USP0+ () USP- () USP+ () USP- USP+ port& can be used on debug mode port& may not be available on all PH sku (HM support port only) (UM US port,,, disable) R USP- () USP+ () USP- () USP+ () USP0- (0) USP0+ (0) USP- () USP+ ()./F_ R 0_ R 0_ US_O0# () amera M US<debug> Touch Panel Sensor Hub amera debug reserve T POGO ONN USP-_ () USP+_ () EHI EHI Wireless XHI for USP0- (0) (0) (0) (0) Wireless () () USP- USP+ USP- USP+ US0_RX- US0_RX+ US0_TX- US0_TX+ PIE port for commeral model S can't weak up. G PIE_RX- J PIE_RX+ 0.u/0V_ PIE_TXN_ V PIE_TX- 0.u/0V_ PIE_TXP_ U PIE_TX+ E F Y G J V U F E Y G H Y UM ~ PIE port disable J G U V G0 J0 Y0 0 E W Y Y0 (0) LK_PIE_WLN# Y (0) LK_PIE_WLN (0) PIE_LKREQ0# PIE_LKREQ0# J TP PIE_LKREQ# M PIE_LKREQ# V0 Y Y PIE_LKREQ# Y Y PIE_LKREQ# L V V PIE_LKREQ# L 0 LK_PIE_LN_REQ# E V0 TP0 V LK_PIE_REQ# T V TP V LK_PIE_REQ# K K LK_PIE_XPN K LK_PIE_XPP PT/PPT (PI-E,SMUS,LK) U PERN PERP +V_S SMLERT# / GPIO PETN PETP SMLK PERN SMT PERP PETN PETP +V_S SML0LERT# / GPIO0 PERN PERP SML0LK PETN PETP SML0T PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P +V_S PIELKRQ0# / GPIO LKOUT_PIEN LKOUT_PIEP +V PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP +V PIELKRQ# / GPIO0 LKOUT_PIEN LKOUT_PIEP +V_S PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP +V_S PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP +V_S PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P +V_S +V_S SMLLERT# / PHHOT# / GPIO +V_S SMLLK / GPIO +V_S SMLT / GPIO PI-E* LOKS SMUS ontroller Link L_LK L_T L_RST# PEG LKRQ# / GPIO +V_S LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN N LKIN P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT PEG LKRQ# / GPIO XLK_ROMP LKOUT_PIEN LKOUT_PIEP +V_S PIELKRQ# / GPIO LKOUT_PIEN +V LKOUTFLEX0 / GPIO LKOUT_PIEP +V_S +V LKOUTFLEX / GPIO PIELKRQ# / GPIO +V LKOUTFLEX / GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P +V LKOUTFLEX / GPIO FLEX LOKS 0 E SMLERT# H SM_PH_LK SM_PH_T RMRST_NTRL_PH SM_ME0_LK G SM_ME0_T SMLLERT#_R TP E SM_ME_LK M SM_ME_T M L_LK TP T L_T TP P0 L_RST# TP G LK_UF_REFLKN E LK_UF_REFLKP K LK_UF_REFSSLKN K LK_UF_REFSSLKP K LK_PH_M H LK_PI_F V XTL_IN V XTL_OUT Y XLK_ROMP R 0./F_ K SKU_I F SEN_WKE H K TP For E M0 PIE_LKREQ_PEG#_R TP LK_PIE_VGN TP LK_PIE_VGP TP V U LK_PU_LKN () LK_PU_LKP () M M LK_PLL_SSLKN () LK_PLL_SSLKP () F LK_UF_PIE_GPLLN E LK_UF_PIE_GPLLP J0 LK_UF_LKN G0 LK_UF_LKP XTL_IN XTL_OUT R0 M_ +.0V_VTT SEN_WKE OR_I (0) Y MHz 0p/0V_ 0p/0V_ Panther Point_RP0 PLTRST#(LG) +V PI/USO# Pull-up(LG) +V_S +V LK_REQ/Strap Pin(LG) PI_PLTRST# 0.u/0V_ PLTRST# U0 TSH0FU R *0_ R 00K_ PLTRST# (,0,) MP Switch ontrol MP_PWR_TRL# MP_PWR_TRL# US_O0# US_O# US_O# US_O# R R R R 0K_ 0K_ 0K_ 0K_ Low = MP ON High = MP OFF (efault) R *K_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# MP_PWR_TRL# EXTTS_SNI_RV_PH REQ# GPU_PWR_EN +V R0 0 0KX R R R R.K_.K_.K_.K_ GPU_HOL_RST# GPU_EISEL# dgpu_selet# +V_S R0 R R R R0 R R0 +V R R0 +V_S 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ PIE_LKREQ# PIE_LKREQ# PIE_LKREQ0# PIE_LKREQ# LK_PIE_LN_REQ# LK_PIE_REQ# LK_PIE_REQ# PIE_LKREQ# PIE_LKREQ# () () SMus(E) N_MLK N_MT +V_S R.K_ Q R0.K_ SM_ME_LK SM_ME_T R 0K_ PIE_LKREQ_PEG#_R RIII Memory down strap +V_S Optimize SKU SKU_I (GPIO) SKU_I0 (GPIO) VG H/W Signal Setup Menu N00W R *K/F_ RM_I0 R 0K_ R K/F_ RM_I R *0K_ R K/F_ RM_I R *0K_ R K/F_ RM_I R *0K_ RM RM_I0 RM_I RM_I RM_I Hynix sku Elpida sku, Elpida sku +V +V R R0 R R *0K_ 0K_ *0K_ 0K_ SKU_I UM Only dgpu Only Switchable (Mux) Optimize (Muxless) SKU_I0 (0) UM GPU UM+GPU UM Hidden Hidden dgpu/sg UM/SG dgpu_pw_trl# 0 = GPU power is control by PH GPIO (iscrete, SG or Optimize) = GPU power is control by H/W (pure iscrete SKU) UM boot GPU boot UM boot UM boot LK_UF_LKN R 0K_ LK_UF_LKP R 0K_ LK_UF_PIE_GPLLN R 0K_ LK_UF_PIE_GPLLP R 0K_ LK_UF_REFLKN R 0K_ LK_UF_REFLKP R 0K_ LK_UF_REFSSLKN R 0K_ LK_UF_REFSSLKP R 0K_ LK_PH_M R 0K_ LOK TERMINTION for FIM +V_S R R R R00 R R0 R K_ 0K_.K_.K_.K_.K_ 0K_ RMRST_NTRL_PH SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SMLLERT#_R Quanta omputer Inc. PROJET : EE Size ocument Number Rev Panther Point / Wednesday, September, 0 ate: Sheet of

10 () () () () () TP () () SIO_EXT_SMI# SIO_EXT_SI# LINT PH_GPIO SKU_I0 TP WK_GPIO PLL_OVR_EN SEN_PWR_EN S_GPIO SIO_EXT_SMI# OR_I SIO_EXT_SI# STGP : strap for reserved at chklist. STGP : strap for reserved at chklist. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled. SMI GPU_PWROK G_SENSOR_I PH_GPIO WK_GPIO PLL_OVR_EN STP_PI# MI_OVRVLTG FI_OVRVLTG MFG_MOE OR_I0 TEST_SET_UP RIT_TEMP_REP# SV_ET R0 00_ R 0_ R 0_ PT/PPT (GPIO,VSS_NTF,RSV) LINT_R UF T MUSY# / GPIO0 +V +V TH / GPIO 0 FU_EN# H E TH / GPIO TH / GPIO TH / GPIO +V +V +V +V +V +V TH / GPIO TH / GPIO0 TH / GPIO 0 R0 L_SELET OR_I.K/F_ 0 GPIO +V_S R *0_ LN_PHY_PWR_TRL / GPIO +V_S G GPIO +V_S 0GTE P SIO_0GTE U STGP / GPIO +V 0 T E TH0 / GPIO +V SLOK / GPIO +V GPIO / MEM_LE +V_S E P GPIO GPIO SW +V_S K STP_PI# / GPIO +V K GPIO +V V M N STGP / GPIO +V STGP / GPIO +V SLO / GPIO +V M V V STOUT0 / GPIO STOUT / GPIO STGP / GPIO +V +V +V GPIO +V_S E E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ Panther Point_RP0 GPIO NTF PU/MIS PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ U P Y Y0 T Y H K H0 K0 P G G H H J J J J J J E E F F E_PEI_R SIO_RIN# PH_THRMTRIP# +V FU_EN# LVS = Pull HIGH ep = Pull LOW SEN_RST# TP R 0_ TP SGPIO SIO_0GTE () SIO_RIN# () H_PWRGOO () PM_THRMTRIP# () F_TVS () SMI US.0 I TL LOW = US.0 I SV_SET_UP High = Strong (efault) TEST_SET_UP S_GPIO R R R R0 R0 0 GPIO Pull-up/Pull-down(LG) GPIO : If not used then use.-kω to 0-kΩ pull-down to. 0K_ K_ *K_ 0K_ *K_ +V +V_S +V MI TERMINTION VOLTGE OVERRIE R0 +V_S R R R R R R () () PH_GPIO PLL_OVR_EN SIO_EXT_SMI# SIO_EXT_SI# STP_PI# SIO_0GTE SIO_RIN# RIT_TEMP_REP# WK_GPIO 00 un-stuff R for SW GPU_PWROK R *0K_ Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) MI_OVRVLTG high VR=+.V_SUS for RL Low VR =+.V_SUS(default) 0K_ SV_ET assign to VI for VR control 0K_ 0K_ 0K_ *0K_ *0K_ OR_I OR_I OR_I0 OR_I OR_I OR_I OR_I R0 R R R R R R R R R R R R R R R R0 *0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ 0K_ *0K_ *0K_ *0K_ *0K_ *0K_ 0K_ 0K_ oard_i Hight=Symatic, LOW=ELN. oard_i Hight=non-TPM, LOW=TPM +V_S +V *00K/F_ *00K_ +V +VPU +V +V +V +V LINT R K_ R 00K_ FI TERMINTION VOLTGE OVERRIE FI_OVRVLTG R *K_ LOW - Tx, Rx terminated to same voltage G_SENSOR_I R 0K_ R *K_ High = isable (efault) G_SENSOR_I Low = Enable MFG-TEST MFG_MOE R R 0K_ *K_ +V Quanta omputer Inc. PROJET : EE Size ocument Number Rev Panther Point / ate: Wednesday, September, 0 Sheet 0 of

11 PH(LG) +.0V_VTT R near PH ball for VP sense +.0V_VTT L +.0V_VTT +.0V_VPLL_EXP *uh/m_ +.0V_VTT VccORE =. (0mils) VccIO =. (0mils) +VFI_VRM VccMI needs to be powered by the same.0 V voltage source as the PU VIO, and the trace needs to be at least 0 mils width with full VSS/ V reference plane. +V +VFI_VRM 0 u/.v_ *0u/.V_ u/.v_ +.0V_VTT u/.v_ u/.v_ u/.v_ R u/.v_ u/.v_ 0u/.V_ 0.u/0V_ *0_ 0.u/.V_ +VFI_VRM +.0V_VPLL_FI +.0V_VTT VMI[] witdth >= 0mils. F F G G G G G G J J J J J N J N N N N N P P P P T N N H P G P U0 PT/PPT (POWER) lock and Miscellaneous ST PI/GPIO/LP US VSUS_ = m(mils) +V +V Vcc =m(mils) L 0ohm/ PT/PPT (POWER) UG POWER 0.u/0V_ UJ POWER VORE[] V U 0.0u/V_ 0u/.V_ 0u/.V_ +.0V_VTT VORE[] +.0V_VTT R0 *0_ +VLK N VORE[] VLK VIO[] VORE[] VSS U VSW_= m P VORE[] +VPU T VIO[0] VORE[] VSW_ P u/.v_ +V_S VORE[] VIO[] VORE[] PH_VSW V T VORE[] VLVS K 0.u/0V_ PSUSYP VIO[] VORE[0] T VORE[] VSSLVS K When is sku and ep, LVS power can short to +V_SUS_LKF T VIO[] 0 VORE[] +.0V_VTT +VPLL_PY_PH *0.u/0V_ V_[] 0.u/0V_ VORE[] M T VORE[] VTX_LVS[] L *0uH/00m_ H VSUS_[] VORE[] M VPLLMI T VORE[] VTX_LVS[] 0 +.0V_VTT L VSUS_[] VORE[] P VIO[] V VTX_LVS[] *0u/.V_ VSUS_[] P +VSUS L V VTX_LVS[] PSUS[] VSUS_[0] 0.u/0V_ VIO[] P VSUS_[] VME(+.0V) =??(??mils) +V *u/.v_ VPLLEXP VSW[] T +.0V_VTT +.0V_VTT V VIO[] VREFSUS=m V_[] VSW[] VIO[] VccSW =.0 (0mils) VMI = m(0mils) +.0V_VTT +V_PH_VREFSUS VSW[] VREF_SUS M R 0/F_ +V_S VIO[] V 0.u/0V_ R00V-0 V_[] +V_S 00 0 VSW[] N +V_USSUS u/.v_ u/.v_ u/.v_ PSUS[] 0.u/0V_ VIO[] VSW[] N +V_S VSUS_[] VIO[] VSW[] *u/.v_ T +VFI_VRM +VFI_VRM u/.v_ VREF= m VIO[] VVRM[] VSW[] +.V V_MI witdth >= 0mils. 0 P +V_PH_VREF R 0/F_ VIO[0] VSW[] VREF +V T0 0u/.V_ 0u/.V_ R00V-0 VIO[] VMI[] VSW[] +V N0 +.0V_VTT VSUS_[] u/.v_ VIO[] VSW[0] N VLKMI = 0m(mils) VSUS_[] VIO[] VLKMI VSW[] P0 +V_S +V_S VSUS_[] VIO[] VSW[] P VSUS_ = m(mils) u/.v_ *0u/.V_ VSUS_[] VSW[] u/0v_ VIO[] W G VSW[] V_[] -test change to +.V_SUS VIO[] VFTERM[] +.V_SUS VPNN = 0 m(mils) W W VSW[] V_[] +V G R 0_ W T +V VPORE = m(0mils) V_[] VFTERM[] VSW[] V_[] W 0.u/0V_ J 0 VSW[] VFTERM[] 0.u/0V_ W 0.u/0V_ VSW[] VVRM[] J +.0V_VTT W J VFTERM[] VSW[] V_[] +V W VccFIPLL VSW[0] F +V_VME_SPI VIO[] VSPI = 0m(mils) 0.u/0V_ 0.u/0V_ +VRTEXT N VIO[] V u/.v_ PRT H VSPI VIO[] +.0V_VTT +VFI_VRM +VFI_VRM Y H VMI[] 0 VVRM[] VIO[] u/.v_ u/0v_ Panther Point_RP0 F 0 m(0mils) +.0V_V PL VIO[]??m(??mils) u/.v_ VPLL +V.LN_VPLL +.0V_VTT m(mils) +.0V_V PL F VPLLST K L *0uH/00m_ VVRM= m(mils) VPLL F +VFI_VRM *0u/.V_ F VVRM[] F VIO[] F VIFFLKN[] VIFFLKN[] VIO[] +.0V_VTT u/.v_ VIFFLKN= m(0mils) G +.0V_VTT VIFFLKN[] +V VIO[] VSS= m(0mils) +V_VME_SPI R *0_ G u/.v_ R *0_ +V_S VSS VIO[] V ORE VIO FI RT LVS FT / SPI MI HVMOS +.V +.0V_VTT R 0_ R0 *0_ VVRM:.V (estop).v (Mobile) R 0_ Reserve +V_S to VSPI for E co-layout VRT<m(mils) +.0V_VTT +V_RT *u/.v_ m(mils).u/.v_ 0.u/0V_ +VSST +V.0M_VSUS 0.u/0V_ 0.u/0V_ V PSST T V PSUS[] PSUS[] J V_PRO_IO PU MIS T VSW[] V VSW[] T VSW[] +.0V_VTT VME =.0(0mils) R *0_ +VPU u/.v_ 0.u/0V_ 0.u/0V_ VRT Panther Point_RP0 RT H VSUSH P *u/.v_ R 0_ 0.u/0V_ +V_S VSUSH= 0m(mils) R 0_ R 0_ +V_S +V_S +V_S +V_S +V R *0_ +.0V_VTT L0 0uH/00m_ +.0V_V PL 0 *0.u/0V_ R *O 00K_ Q *0.u/0V_ R *O 00K_ Q R /F_ L 0uH/00m_ +V_SUS_LKF + 0u/.V_ u/.v_.u/.v_ u/0v_ L 0uH/00m_ +.0V_V PL (,) SLP_SUS# + 0u/.V_ u/.v_ Q N00W 0 change mose footprint to dual type. 00 SW ricuit 000 modify cuirucit. Quanta omputer Inc. PROJET : EE Size ocument Number Rev Panther Point / ate: Wednesday, September, 0 Sheet of

12 IEX PEK-M () PH(LG) Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Wednesday, September, 0 EE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Wednesday, September, 0 EE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Wednesday, September, 0 EE UH Panther Point_RP0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L UI Panther Point_RP0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J

13 SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Place these aps near Memory own <R> Should be 0 Ohms +-% Should be 0 Ohms +-% Should be 0 Ohms +-% Should be 0 Ohms +-% YTE0_0- YTE_- YTE_- YTE_- YTE_- YTE_0- YTE_- YTE_- Shielding Holder / hange MEM down to channel from M S# M S#0 M S# M S# M RS# M WE# M LK0# M LK0 M KE0 M S#0 M OT0 R_RMRST# M ZQ M ZQ SMR_VREF_Q0 +SMR_VREF_IMM +SMR_VREF_IMM SMR_VREF_Q0 M ZQ +SMR_VREF_IMM SMR_VREF_Q0 R_RMRST# +SMR_VREF_IMM SMR_VREF_Q0 R_RMRST# M ZQ M QSP M QSN M QSP M QSN M QSP M QSN M QSP M QSN M QSN0 M QSP0 M QSP M QSN M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M QSN M QSP M QSP M QSN M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q +SMR_VREF_IMM SMR_VREF_Q0 SMR_VREF_Q0_M M LK0 M LK0# SMR_VREF_Q0 +SMR_VREF_IMM M M M 0 M M M M M M M M M M M M M 0 M M M 0 M M M M M M M M M M M M M 0 M M M 0 M M M M M M M M M M M M M 0 M M M 0 M M M M M M M M M M M M M 0 M S# M S#0 M S# M S# M RS# M WE# M LK0# M LK0 M KE0 M S#0 M OT0 M S# M S#0 M S# M S# M RS# M WE# M LK0# M LK0 M KE0 M S#0 M OT0 M S#0 () M S# () M S# () M LK0 () M LK0# () M KE0 () M OT0 () M S#0 () M S# () M RS# () M WE# () R_RMRST# () SMR_VREF_Q0_M () EEPS_E () M Q[:0] () M QSP[:0] () M QSN[:0] () M [:0] () +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +SMR_VREF +SMR_VREF_IMM +.V_SUS +SMR_VREF +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +SMR_VREF_IMM SMR_VREF_Q +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS +.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Wednesday, September, 0 EE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Wednesday, September, 0 EE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Wednesday, September, 0 EE 0 0.u/0V_ S_LIP SUL-M 0u/.V_ u/.v_ u/.v_ 0 u/.v_ u/.v_ R K/F_ 0u/.V_ u/.v_ 0 u/.v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0u/.V_ u/.v_ R0 0/F_ 0 u/.v_ 0 u/.v_ 0.P/0V_ 0u/.V_ u/.v_ 00-LL SRM R U0 RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ 0u/.V_ R0 K/F_ u/.v_ u/.v_ 0.u/0V_ 0u/.V_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ u/.v_ u/.v_ 0 u/.v_ 0 u/.v_ 0u/.V_ S_LIP SUL-M 0.u/0V_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ u/.v_ R *0_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ u/.v_ 0 0.u/0V_ 0u/.V_ u/.v_ 0.u/0V_ u/.v_ 0 u/.v_ u/.v_ u/.v_ 0u/.V_ R 0/F_ u/.v_ u/.v_ 0u/.V_ 00 u/.v_ R0 0/F_ u/.v_ 0 0u/.V_ R 0/F_ u/.v_ 0.u/0V_ u/.v_ + *0u/.V_ u/.v_ S_LIP SUL-M 0u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ u/.v_ 0.u/0V_ 0u/.V_ 0.u/0V_ u/.v_ R00 K/F_ S_LIP SUL-M u/.v_ u/.v_ 0.u/0V_ u/.v_ u/.v_ u/.v_ Q0 *N00 u/.v_ u/.v_ 0.u/0V_ u/.v_ 0u/.V_ R 0/F_ u/.v_ 0u/.V_ 0 u/.v_ u/.v_ u/.v_ u/.v_ S_LIP SUL-M 0u/.V_ S_LIP SUL-M R K/F_ 0 u/.v_ u/.v_ u/.v_ 0.u/0V_ R *0_ 0u/.V_ u/.v_ u/.v_ u/.v_ 0u/.V_ 0u/.V_ u/.v_ 0u/.V_ u/.v_ u/.v_ u/.v_ S_LIP SUL-M R *0_ S_LIP SUL-M u/.v_ u/.v_ u/.v_ u/.v_ R 0/F_ u/.v_

14 odec(o) HPR HPL MI-VREFO-L MI-VREFO-R T T HEPHONE/Mic combo MI-J# 0 placed close to codec O MI-VREFO INT_MI-VREFO placed close to codec 0u/.V_ O Q SK0 K/F_ R +V +V +V 0u/.V_ O Place next to pin 0u/.V_ 0 0u/.V_ R0 0_ 0.u/0V_ R 0_ 0 0.u/0V_ 0.u/0V_ +VPV 0u/.V_ Place next to pin +VPV 0u/.V_ NLOG Spilt by 0.u/0V_ Spilt by P 0 Spilt by 0.u/0V_ L_SPK+ L_SPK- R_SPK- R_SPK+ EP# O 0 U.u/0V_.u/0V_ VSS V PV SPK-L+ PVSS PVSS SPK-L- SPK-R- SPK-R+ PV P (Vista Premium Version) V N GPIO0/MI-T SPIFO/EP SPIFO P PVEE GPIO/MI-LK HP-OUT-R P# HP-OUT-L ST-OUT MI-VREFO-L IT-LK MI-VREFO-R 0 VSS MI-VREFO ST-IN LO-P V-IO VREF SYN Place next to pin OE_VREF O VSS RESET# V MONO-OUT PEEP 0.u/0V_ LINE-R LINE-L MI-R MI-L JREF Sense- MI-R MI-L LINE-R LINE-L Sense 0 0 *0u/.V_ NLOG LINE-R LINE-L MI_R MI_L OE_JREF SENSE MI_R MI_L LINE-R LINE-L SENSE 0 0.u/0V_ T 00 0.u/0V_ +V Place next to pin O Placement near udio odec R0 T T T R R00 T T 0K/F_ 0K/F_.K/F_ MI-J# HP_J# 0u/.V_ O MI_R MI_L.u/0V_.u/0V_ HPR R HPL R MI-VREFO R MI_MI.K/J_ K/J_ R R0 K/F_ O /F_ HPR- /F_ HPL- O 0 0u/.V_ OMO_MI OMO_MI () HPR- () HP_J# HPL- () HP_J# () / Remove phone jack to Place next to pin 0 LX IGITL PEEP dont coupling any signals if possible / separate PEEP to igital from Realtek suggestion +V R 0_ 0.u/0V_ +Z_V 0u/.V_ PEEP 0.Vrms u/0v_ 0 EEP_ 00p/0V_ R0 R0.K_ K_ EEP_ T / add PEEP_E () SPKR () If either H device io power use +.V, all device IO power change to +.V MI(O) Place next to pin MI_T_L MI_LK_L PH_Z_OE_RST# PH_Z_OE_RST# () PH_Z_OE_SYN () P# 0V : Power down lass SPK amplifer.v : Power up lass SPK amplifer Z_SIN R _ *p/0v_ PH_Z_OE_SIN0 () PH_Z_OE_ITLK () PH_Z_OE_SOUT () +Z_V 0.u/0V_ 0u/.V_ Place next to pin MI_LK_L MI_T_L *0p/0V_ lose to codec R R *0p/0V_ 00,0. 00,0. MI_LK MI_T M LK T S MI V +V -test change footprint, and P/N R 0_ R 0_ R 0_ R0 0_ R 0_ R 0_ *000p/0V_ *000p/0V_ RF suggest to add R,R,, Reserve for MI.(not use) O Power (O) Mute(O) Internal Speaker Speaker connector st PN: FH0MR ONN SM HEER P R MR(P.,H.) nd PN: FH0MR0 ONN SM HEER P R MR(P.,H.) rd PN: FH0MR0 ONN SM HEER P R MR(P.,H.) +V IGITL L U IN NLOG /ohm_ OUT +V +V R *0K_ 0mil for each signal R_SPK+ R 0_ R_SPK- R 0_ L_SPK- R 0_ L_SPK+ R0 0_ R_SPK+_ R_SPK-_ L_SPK-_ L_SPK+_ N R+ R- L- L+ SHN SET R *.K/F_ P# S PH_Z_OE_RST# *p/0v_ *p/0v_ *p/0v_ *p/0v_ SPEKER-ONN *0.u/0V_ *0U/0V_ *G-0TUF R *0_ R *0K/F_ *0U/0V_ *0.u/0V_ *S S R *0_ EP# MP_MUTE# () O 0, close U pin and L O Quanta omputer Inc. PROJET : EE Size ocument Number Rev L/HP/MI/SPK Wednesday, September, 0 ate: Sheet of

15 LE river-i Penal SPE: Iout:~m Vout:~.V LE string SP ---> sharp panel L Power VL =(M/R0+)*. +V R0 0_ L 0uH_. FLS0--F.V -->.K SF (UO).V -->K S0F0 (LG).K SF0 (sharp) VL U/.V_ U IN OUT LV.u/V_ 000p/0V_.U/V_ Q0 *O0.u/0V_0 R0.K_ R M_ *0.u/0V_ INT_LVS_IGON IN ON/OFF 0.u/0V_ 0.0u/V_.u/0V_ MOE F F R T0- R00 0 *00K/F_ *S *0.u/0V_ / add isolation circuit P P P SW N FULT P OV RFPWM/MOE IF IF U TPS 0 IF IF IF F F / dd F for UO panel_evis 00K_ INT_LVS_RIGHT R 0_ LVS_RIGHT R 0K_ LVS_RIGHT_R 0 PWM P P P P VIO EN FSLT ISET FPO IF P P P acklight ontrol +V 0 *0K_ R 00 Reserve if Host need to know any fault trigger on backlight driver +V R 0K_ R 0K_ u/.v_ VIO R *0_ R R 0.K_ 0K/F_ I=./R*0 0.K-->.m S0F0 (UO).K -->.m SF (LG) 0K-->m S0F00 (ch EP) L# L_ON R FLT K K K F SW 00KHz 00KHz MHz R Select is from 0Hz~0KHz,K~.0K. MOE R.0K_ 0 R *0.0u/V XR 00 Reserve Phase shift PWM mode cirucit, if R high impedance, bypassing capacitor is for improves noise sensitivit and not exceed pf..k_ L_ON 00 Un-stuff 0 for L flacking issue, FE suggestion. INT_LVS_LON R 00K_ Q N00W Q TEU E_FPK# () +V L ONNETOR R R *00K_ EP_UX_ *00K_ EP_UX#_ R R *00K_ *00K_ FRONT ONNETOR +V +V-current budget 0. () () () () () () () EP_TX# EP_TX EP_TX0# EP_TX0 EP_UX EP_UX# EP_HP VL 0.u/0V_ N 0.U/0V_ EP_TX#_ R0 0_ 0.U/0V_ EP_TX_ L 0 0.U/0V_ EP_TX0#_ USP0-_R () USP0-0.U/0V_ EP_TX0_ USP0+_R () USP0+ 0.U/0V_ EP_UX_ *MM000GE/00m/0ohm 0.U/0V_ EP_UX#_ 0 R0 0_ 0 LV R 0_ EP_HP 0 0 F F F F R 0_ 0 0 LVS 000p/0V_ TP N _N -test remove -ch circuit Quanta omputer Inc. PROJET : EE Size ocument Number Rev EP/LE RIVER/ Wednesday, September, 0 ate: Sheet of

16 HMI from PH INT_HMITX0N_ INT_HMITX0P_ INT_HMITXN_ INT_HMITXP_ INT_HMITXN_ INT_HMITXP_ INT_HMILK-_ INT_HMILK+_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ INT_HMITX0N INT_HMITX0P INT_HMITXN INT_HMITXP INT_HMITXN INT_HMITXP INT_HMILK- INT_HMILK+ R 0_ R0 0_ R 0_ R 0_ R0 0_ R 0_ R 0_ R 0_ +V Q N00 HMI-detect I +V MOS close to connector +V +V +V () HMI_HP_E# +V +V HMI_M_HP HMI_HP HMI_LK_SW HMI_LK_SW HMI_LK_M follow R.0 change to.k +V Q N00W +V R.K_ +V Q R.K_ R0V-0 SN0 HMI_T_SW HMI_T_SW R *00K/F_ R 0K_ R0.K_ Q0 SN0 R.K_ R *0K_ R 0K_ R0V-0 HMI_T_M follow R.0 change to.k R R R R0 EMI +V HMI_M_HP Q IN OUT PS- R 0K_ 0P/0V_ INT_HMITXP INT_HMITXN INT_HMITXP INT_HMITXN INT_HMITX0P INT_HMITX0N INT_HMILK+ HMI_LK_M HMI_T_M HMI_V TP HMI-Type connector INT_HMITXP 00/F_ INT_HMITXN INT_HMITXP 00/F_ INT_HMITXN INT_HMITX0P 00/F_ INT_HMITX0N INT_HMILK+ 00/F_ INT_HMILK- INT_HMILK- N H UTILITY TMS_+ SHIEL[] TMS_- TMS_+ SHIEL[] TMS_- 0 TMS_0+ SHIEL[] TMS_0- TMS_LK+ SHIEL[] 0 TMS_LK- OSS[] E OSS[] _ OSS[] SL OSS[] S +V HMI_Type 00 change to 0k. Quanta omputer Inc. PROJET : EE Size ocument Number Rev HMI (PS0) ate: Wednesday, September, 0 Sheet of

17 Sensor HU () LS_INT_R +VPU +V_SEN_TT +V +V_S R 0_ R *0_ INTEL STUFF INTEL UN-STUFF +VPU R M_ 0 0.u/0V_ u/.v_ () SEN_WKE () () INTEL STUFF _RY_R R 0_ GYRO_INT_R R 0_ intel stuff M Hz INTEL UN-STUFF R0 *0 INT_R R 0_ LS_INT_R R 0_ GYRO_INT_R R 0 INT_R USP- USP+ +V_SEN_PWR 0 P/0V_ (0) R R0 R R R R R0 0_ P/0V_ SEN_RST# Y MHZ *0K_ *0K_ *0K_ *0K_ *0K_ *0K_ R0 INTEL STUFF 0.u/0V_.K/F_ +V_SEN_PWR ST stuff 0K ohm S00F INTEL UN-STUFF R *.K/F_ R 0_ INTEL UN-STUFF R0 *00K_ TP MHz,MIN: G000 'N: G000 MHz,MIN: G 'N: R R0 R R R R +V_SEN_PWR R *0_ R 0_ INTEL UN-STUFF TP TP STM_P0 STM_P STM_P STM_P STM_P STM_P STM_P TP TP *0K_ *0K_ *0K_ P P P SEN_M_IN SEN_M_OUT SEN_RST# 0 0.u/0V_ *0K_ *0K_ *0K_ +V_SEN_PWR +V_SEN_PWR ST (,0,0),(,,0) F E P0 H P G P H P E P G P G P E P P P P0 P P P P P G F P0 G P P P0 P P nrst OOT0 F G VREF+ V E VSS TP TP TP STMF0RYTR-WLSP P P GYRO_INT R P P INTEL STUFF U H P0 F P H P P P P P P P P G P F P P F E P0 F P P H P H P E P E P E P P P0 P P P P P VT H V V V G V H VSS VSS VSS F VSS R R R R _INT _INT GYRO_INT GYRO_INT P SEN_SLK SEN_ST _RY LS_INT +V_SEN_TT 0K_ 0K_ 0K_ 0K_ 0K_ R 0_ 0.u/0V_ +V_SEN_PWR R.K_ INTEL STUFF INTEL STUFF R 0_ 0 Y.KHZ LS_INT () p/0v_ p/0v_ INTEL STUFF 0.u/0V_ +V_SEN_PWR R.K_ 0.u/0V_ SEN_SLK () SEN_ST () FU_EN# (0) +V_SEN_PWR 0.u/0V_ (0) G-sensor/E-compass R INTEL STUFF INTEL UN-STUFF _RY R0 *0 INT R *0 INT R *0_ Gyroscope GYRO_INT GYRO_INT SEN_PWR_EN 00K_ R *M_ 0.u/0V_.u/0V_ 0.u/0V_ SEN_SLK SEN_ST WR ddress : 0x R ddress : 0x UN-STUFF R0 *0_ GYRO_INT_R R *0_ GYRO_INT_R INTEL UN-STUFF SEN_SLK SEN_ST _RY_R _INT_R _INT_R EL_ EL_SETP EL_SETN U SL S INT RY 0.0u/V_ Q O0 LG0 R0 U SL S RY INT INT SETP SETN LSM0LH 00K_ RSV -test change footprint PLLFILT 0 RSV RSV INTEL STUFF INTEL UN-STUFF R *0_ INTEL STUFF +V_SEN_PWR INTEL UN-STUFF +V_SEN_PWR WR ddress : 0x R ddress : 0x E-compass WR ddress : 0x R ddress : 0x G-sensor 0, close to pin ate: Wednesday, September, 0 Sheet of +V, close to pin V_IO V R 0_ VIO V RSV S S0 Reserved_ Reserved_ 0 Reserved_ Reserved_ Reserved_ 0 Q O R 0_ R 00K_ 0.u/V_ 0u/.V_ TP R 0 0.u/V_ 0 0.u/V_ 0u/.V_ +V_SEN_PWR Quanta omputer Inc. PROJET : EE Size ocument Number Rev Sensor (Hub/Gyr/G+E) *0_ R 0_ 0.u/V_

18 TPM -test change to L00K0 SL STUFF +V R TPM@0_ +V R TPM@0_ R +V_S *TPM@0_ TPM@0.u/0V_ SL UN-STUFF TPM@0.u/0V_ TPM@0u/.V_ +V SL UN-STUFF (,0,) PLTRST# (,0,) (,0,) (,0,) (,0,) () (,0,) TPM@0_ (,) (,) SERIRQ LKRUN# +V_S LP_L0 LP_L LP_L LP_L PLK_TPM LP_LFRME# R SL UN-STUFF TPM@0.u/0V_ R R R 0 PLK_TPM LPFRME# PLTRST#_TPM TPM@0_ *TPM@0_ TPM@.K U V V LPP# SL UN-STUFF L0 TPM_ L TEST/ R *TPM@0_ L R *TPM@0_ R TPM@0_ PLTRST#_TPM L TEST SL UN-STUFF SL STUFF TPM TPM_XTLO SL TT. XTLO TPM_XTLI LLK XTLI LFRME# LRESET# GPIO GPIO SERIRQ N LKRUN# N +V TPM_XTLO N PP N 0 R TPM@0_ TPM@SLTT_TSSOP SL STUFF VS R *TPM@.K 0 +V Y *TPM@.KHZ R TPM@.K_ R *TPM@.K_ *TPM@P/0V_ R *TPM@.K TPM_XTLI *TPM@P/0V_ SL UN-STUFF Thermal Remote Sensor THERML+ () Resiger ase ddress Q MMT0 =0 = (default) E / F E / F 00p/0V_ THERML- () Quanta omputer Inc. PROJET : EE Size ocument Number Rev RTS0-GR (ard Reader) ate: Wednesday, September, 0 Sheet of

19 + udio/ ONN (RER ) LS_INT_R +V-current budget 0. +V 0.u/0V_ 000p/0V_ US.0 +V_S FFFR00-00m-v0-p-ldh Win switch/ onn LS_INT () HPR- () HP_J# () USP+ R *0_ LS_INT_R SEN_ST INTEL UN-STUFF +V +VPU () VOL_UP () NSWON# () PWRLE# () VOL_N () SUSLE# +V SEN_SLK +V_SEN_PWR () USP- () OMO_MI () HPL- N 0 0 -test remove +V_S to / -test change footprint & P/N FUNTION/ O -test add +V Reserve for ebug () USP- () USP+ () USP- () USP+ () US0_RX- () US0_RX+ () US0_TX- () US0_TX+ U/.V_ () USON# R *0_ USP-_R R0 *0_ USP+_R R 0_ L *MM000GE/00m/0ohm R 0_ 0.U/0V_ US0_TX-_ 0 0.U/0V_ US0_TX+_ US.0 OMMON MOE HOK X00000.P/0V_ () US_O0# *MM000GE/00m/0ohm L U IN OUT IN OUT OUT EN# O# PL0XI R _ R _ R _ R _ USPWR 0u/.V_ *MM000GE/00m/0ohm.P/0V_.P/0V_ L USP-_R USP+_R US0_RX-_R US0_RX+_R US0_TX-_R US0_TX+_R 000p/0V_.P/0V_ N US.0 ONN VUS - + SSRX- SSRX+ SSTX- SSTX V R *0_ POGO_PRSNT# R 00K_ () () +V () USP-_ USP+_ R 0_ POGO_EN# R 0_ +V_POGO Q +V O () USP- () USP+ () POGO_PRSNT# () HOME_KEY# *MM000GE/00m/0ohm (0) LINT USP- R USP+ R L () VRT_ R 0_ +V_S +V N US0_RX-_R US0_RX+_R US0_TX-_R US0_TX+_R U 0 _/ *Rlamp0P 0 US0_RX-_R US0_RX+_R US0_TX-_R US0_TX+_R USP-_R USP+_R U *Rlamp0N USPWR USP-_R USP+_R POGO_ RESET SW PU FN -test change footprint SWITH_. SW SYS_SHN# SYS_SHN# (,,) +V +V +V +V 0.u/0V_ *V/V/00P_ R0 K_ R 0K_ R 0K_ R 0_ () PUFN# Q MMT0 () FNSIG FN_PWM_N 0mil N FN Rotate Switch SW SWITH_. ROTTE () 0.u/0V_ *V/V/00P_ ES 'nd Y00G0000 Quanta omputer Inc. PROJET : EE Size ocument Number Rev US.0/TPM/Fan Wednesday, September, 0 ate: Sheet of

20 Mini ard (MP) () () LK_PIE_WLN# LK_PIE_WLN () () () () PIE_RX- PIE_RX+ PIE_TX+ PIE_TX- 0/ swap Tx /Rx 0 U N L L L0 NT Location L PETN0 L PETP0 L PERP0 L PERN0 L REFLK+ L L L L TH.00 H H WL/T LG OMO R(TH.00) PH000 H REFLK- US_- US_+ T_LE WIFI_LE WIFI_ISLE N.VUX.v N N N N LKREQ_L H G G0 G G G G G G G G F F0 F F F F F F F F WLN_OFF () WLN_LE# TP RF_EN RF_EN () (Low ctive) +V_WLN R *0_ R 0_ LKREQ_L +VPU USP0- () USP0+ () R () IO_LNPWR# +V_WLN +V *00K_ Q O R +V_WLN 0_ *0u/.V_ 0 0.U/0V_ 0.U/0V_ 0.U/0V_ +V_S +V_S 0.U/0V_ 0 NT Location R 0K/J_ LKREQ_L MINI_WKE# PERST_L 0 N E WKE_L E E E E E E E E0 E T_ISLE +V_WLN N00W Q (,,) PLTRST# *0_ R0 R 0_ (Low ctive) T_POWERON# () PIE_LKREQ0# () (,) IO_PIERST# 0_ R0 WKE_SR_ () () PIERST# *0_ R MINI_WKE# R 0K/J_ +V_WLN mst +V_ST ebug PLTRST# () LK_LP_EUG () ST_TXP0 0 () ST_TXN0 () ST_RXN0 () ST_RXP0 R *0_ R *0_ 0.0u/V_ ST_TXP0_ 0.0u/V_ ST_TXN0_ 0.0u/V_ ST_RXN0_ 0.0u/V_ ST_RXP0_ N MINI-SS Reserved Reserved Reserved Reserved +.Vaux +.Vaux PETp0 PETn0 PERp0 PERn0 UIM_ UIM_ REFLK+ REFLK- LKREQ# Reserved Reserved WKE# +.V 0 +.V LE_WPN# LE_WLN# LE_WWN# 0 US_+ US_- SM_T SM_LK 0 +.V +.Vaux PERST# 0 W_ISLE# UIM_VPP UIM_RESET UIM_LK UIM_T 0 UIM_PWR +.V +.V -test change footprint _LFRME#_R _L_R _L_R _L_R _L0_R +V 00 move debuge port to cn ebug R 0_ LP_LFRME# (,,) R 0_ LP_L (,,) R 0_ LP_L (,,) R 0_ LP_L (,,) R 0_ LP_L0 (,,) lose N R 0_ +V_ST 0u/.V_ 0.U/0V_ 0.U/0V_ rating = G Quanta omputer Inc. PROJET : EE Size ocument Number Rev Mini-ard/WL Wednesday, September, 0 ate: Sheet of 0

21 SREW HOLE HOLE H-cdp HOLE *H-P HOLE *H-P HOLE *H-P EE RETURN-PTH PITORS +V *0.u/0V_ +.V_SUS *0.u/V_ 0 +V *00p/0V_ +.V_SUS *0.u/0V_ +.V_SUS *0.u/V_ +V *0.u/0V_ +V HOLE *H-P HOLE *H-P HOLE *H-P HOLE *H-P *0.u/0V_ 0 +V *0.u/0V_ +.0V_VTT +.0V_VTT *0.u/V_ +V_ORE 0.U/0V_ *0P/0V_ +V 00 for EMI suggestion. 00 dd for EMI suggestion to. HOLE0 *H-P HOLE *H-P HOLE *H-P *0.u/V_ +VPU +.0V_VTT 0 del 0/0// and change path cap power well. *0.u/0V_ *0.u/V_ 0 *0.u/0V_ 0 *0P/0V_ 0.u/V_ *00p/0V_ HOLE *H-dn HOLE *h-oxdxn *0.u/V_ *0.u/V_ 0.u/V_ *0.u/V_ TT Enable short pad HOLE *O-EE- TT_EN# () *00p/0V_ *00p/0V_ *00p/0V_ *00p/0V_ HOLE *H-N HOLE *O-EE- TT_EN# P *spad-rex Quanta omputer Inc. PROJET : EE Size ocument Number Rev Hole \ RETURN-PTH ate: Wednesday, September, 0 Sheet of

22 E(K) L PY00T-0Y-N//ohm_ 0mil +VPU 0.u/0V_ 0u/.V_ +V 00 for EMI suggestion. +VPU +VPU LK_PI_E R *_ *0p/0V_ R._ pin +V_GFX pin +V_ for TI pin +V for TI pin +.V_GPU for TI pin GPU_RST# +VPU_E.u/.V_ (,,0) (,,0) (,,0) (,,0) (,,0) () (0) (0) () (0) (,) (0) (,,0) (,) HRGER PH THERML Reserve for writing ME ROM (0) () () (0) 0.0(0mils) VTT - the power supply for the PEI signal PEI - the PEI.0 data bus, bidirectional signal. G0. and chklist 0. apply one series ohm near E side pin GFX_PWRG pin dgpu_vron pin +VGPU_ORE pin +.V_GPU pin dgpu_pwrok 0.u/0V_ LP_LFRME# LP_L0 LP_L LP_L LP_L LK_PI_E +.0V_VTT E_PEI LKRUN# SIO_0GTE SIO_RIN# SIO_EXT_SI# E_FPK# MP_MUTE# PLTRST# RF_EN SERIRQ SIO_EXT_SMI# *0.u/V_ () MLK () MT () N_MLK () N_MT () THM_LK () THM_T () ME_WR# T_POWERON# LI# 0.u/0V_ R 0_ R _ TP TP TP0 TP TP TP TP TP *0.u/V_ E +.0V_VTT_E E_PEI_R 0.u/0V_ MLK MT N_MLK N_MT THM_LK THM_T 0 U LFRME L0 L L L LLK GPIO/LKRUN GPIO/LRQ LREST GPIO/SMI GPIO/PSLK 0 GPIO/PST GPIO/PSLK GPIOPST VTT PEI V V V V V ESI/GPIO KSIN0 KSIN KSIN KSIN KSIN KSIN KSIN KSIN KSOUT0/JENK KSOUT/TK 0 KSOUT/TMS KSOUT/TI KSOUT/JEN0 KSOUT/TO KSOUT/RY KSOUT KSOUT 0 KSOUT/SP_VIS KSOUT0/P0_LK KSOUT/P0_T KSOUT/GPIO NPEL0X L LP KSOUT/GPIO KSOUT/GPIO KSOUT/GPIO/XOR_OUT GPIO0/KSOUT GPIO/KSOUT 0 GPIO/SL GPIO/S GPIO/SL GPIO/S 0 GPIO/SL GPIO/S GPIO/G0 KRST/GPIO GPIO0/LPP GPIO/PWUREQ SERIRQ GPIO00/KLKIN V 0 K SM PS/ PY00T-0Y-N//ohm_ E / / IR FIU VORF_uR V GPIO0/T GPIO0 GPIO0 GPIO0 0 GPIO0 GPIO0/IOX_OUT/RTS GPIO0 GPIO 0 GPIO0 GPIO/TS 0 GPIO GPIO/SL/TK 0 GPIO/S/TMS GPIO/TI GPIO GPO/SL GPIO0/PSLK/TO GPIO GPIO/PST/RY GPIO/S GPIO0 GPIO GPIO GPIO/SPI_SK GPO/SHM GPIO GPIO 0 GPO/IOX_LSH/TEST GPO/IOX_SLK/XORTR 0 GPIO GPIO/T GPIO0/T/IOX_IN_IO GPIO/T TIMER GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/_PWM GPIO/E_PWM GPIO0/F_PWM/RI GPIO/G_PWM GPIO/H_PWM/SOUT GPIO/IRRXM/SIN_R GPIO/SIN/IRRXL GPIO/IRRXM/TRST GPO/SOUT_R/TRIST GPIO/LKOUT/IOX_IN_IO 0 0 VORF R00V-0 F_SI/F_SIO F_SO/F_SIO0 F_S0 F_SK 0 GPIO0/0 GPIO/ GPIO/ GPIO/ GPIO/0 GPI/ GPI/ u/.v_ V_POR VREF u/.V_ E IMNT_R HWPG PWROK_E_uR RSMRST#_uR o not use it LI# PROHOT_E V_POR# -test remove SM_RMRST# PH_SPI_SO_R PH_SPI_SI_R PH_SPI_LK_R VREF_uR 0.u/0V_ L STUFF IMNT IMNT E_RMRST_NTRL TP TP TP0 TP TP 0.u/0V_ 0u/.V_ R 0_ TP 0.0u/V_ R 0_ R 0_ R _ R _ R TP TP R _ R 0_ 0 add ohm series resistor and for E FE suggestion contact to SPI M ROM. K/F_ +VPU +VPU TEMP_MT () POGO_PRSNT# () () IMNT () E_RMRST_NTRL () WLN_OFF (0) WK_GPIO (0) 000 dd K backlight EN function. IN () SUSK# NSWON# () SLP_SUS# (,) 00 hange SUSWRN# to IO_PIRST#. IO_PIERST# (,0) WKE_SR_ (0) S_ () 00 ddsm_rmrst# for deep S. 000 dd PWROK for deep S. PWROK VOL_UP () VRON () VOL_N () SUS# /# () S_ON (,) HMI_HP_E# () FWS SUS# PWROK_E PH_RSMRST# MINON (,,) ROTTE () NSWON# USON# () HOME_KEY# () SUSON () FNSIG () PEEP_E () SUSLE# () PUFN# () PWRLE# () POGO_EN# () +0.V_ON (,) IO_LNPWR# (0) PH_SPI_SO_E () PH_SPI_SI_E () SPI_S0#_UR_ME () PH_SPI_LK_E () 00 FWS for 00msce timing. 00 dd WLN_OFF to N pin for IO. SM US PU(K) PROHOT_E HWPG(K) (,) () (,) () () (,) HWPG_VS HWPG_VTT HWPG_.V SYS_HWPG GFX_PWRG HWPG_.V S_ON 00 hange R0 from0k to k for S current reduce.. PWROK R 00K_ PU_RMRST# MLK MT THM_LK THM_T R N_MLK N_MT Q N00 +VPU +V_S H_PROHOT# (,,) Q00 need Replacement at OT layer. R0 R R R R R0 R +V_S K_ R 0_ S S S S *S S 0K_ R *K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ +V +V R *0K_ Q SM_RMRST# *N00W 00 dd Q for S function. R 0K_ HWPG +VPU mil +VPU mil RSV for power on irst +V 00 reserve irst function. *.V/V/0P_ mil *.V/V/0P_ mil *0.u/0V_ *0.u/0V XR HE *EM--T R *00K_ LI# *.V/V/0P_ *0.u/0V XR HE *EM--T R0 *00K_ LI# *.V/V/0P_ NSWON# SW *SWITH_. (,) PI_PLTRST# IO_PIERST# R0 R0 *00K_ *00K_ U *TSH0FU PIERST# PIERST# (0) Quanta omputer Inc. PROJET : EE Size ocument Number Rev WPE & FLSH Wednesday, September, 0 ate: Sheet of

23 POWER_JK dcjk-dc0-00f-p PJ P 0.u/0V_ () P 00p/0V_ V / for nd battery P *n/0v_ PL FM T PL FM T PR 0K/F_ PR 00K/F_ V P0 0.u/0V_ P NWS recommend 00m at least. P SMJ0 P 0.u/0V_ PR0 0K_ PR0 0K_ PQ IMT0 _P _N PQ OL V P SR0SP- PR0 0_ PR 0.0/F_0 /# () PR0 0_ PR0 0 N _P P 0.u/0V_ P 00p/0V_ PR0 K/F_ PQ N00K PQ OL PR0 0K_ +VPU PR 0_ P0 n/0v_ PR0.K/F_ P 0.u/0V_ P 0.u/0V_ P 0.u/0V_ PR0 *0K_ PR 00K_ PR 00K_ P 0.u/V_ PR 0K/F ET ET P N REGN _REGN P0 u/v_ () () F-0-L_att_onn IN PRESENT S_ PJ 0 PR 0_ P P MT+ 0.u/0V_ *00p/0V_ PR00 PR *0_ PL TT_EN# () STUFF ON -TEST PR 00_ P *p/0v_ PL *0_ FM T P0 *p/0v_ TEMP_MT PR M_ PQ N00W FM T T-V +VPU +VPU TEMP_MT () PR 0K_ PR K/F_ PR *0K_ MT MLK PR *00K_ PR 0_0 PR0 0_ PR 0 V _M# _MPOUT _ILIM P 0.u/V_ 0 0 _MPIN PR *00K_ V OK# S SL M# MPOUT ILIM MPIN IOUT PU0 Q0 TST HIRV PHSE LRV SRP P SRN PR0 0 ST _H _LX _L PR 0 SRP _SRN PR._ For battery reverse +V P R00V-0 P n/0v_ P 0.u/V_ P 0.u/V_ P 0.u/V_ PQ0 MV PQ MV P 00p/0V_ PR *._ P *0p/0V_ PL0.uH_XX PR0 0 SRP _SRN P.u/V_ PR 0.0/F_0 PR0 0_ P 00p/0V_ T-V P P 0u/V_0 0u/V_0 PR 00_ PR 00_ MLK () MT () _M# PQ *N00K PR 00K/F_ () P0 0.0u/V_ IMNT PR *.K/F_ PR *0_ PR *00K_ H_PROHOT# (,,) REGN MX voltage.v V_ILIM=0*(VSRP-VSRN)=0*Ichg*Rsr =0.V for. current limit TEMP_MT PU IP-Z H VN H H VP H dd ES diode base on E FE suggestion MT +VPU MLK P00 00p/0V MPOUT PQ *N00K Limit set on 0W/. Quanta omputer Inc. PROJET : EE Size ocument Number Rev harger(qrgrr) ate: Wednesday, September, 0 Sheet of

24 MIN MIN (,) SYS_SHN# SYS_SHN# (,,) PR 0_ 0/0 remove () SYS_HWPG +VPU VL V_LO PR0 0K/F_ 0/0 remove +VPU 0/0 remove +VPU Volt +/- % T :. PEK :. OP : Width : 0mil + P 0.u/0V_ + P u/v_ PR.K/F_ PR 0K/F_ P.u/V_ PL.uH_XX PR *._ P *0p/0V_ P 00p/0V_ PQ MV PQ MVS SYS_SHN# S_ON PR *0_ P0 0.u/0V_ PR /F_ PR 0_ PR 0 EN _H _VST _SW _L _F PR *00K/F_ 0 P 0u/.V_ PGOO EN RVH VST SW RVL VF VO VLK VREG S _ P 0.u/V_ PU TPSRUKR S VREG P.u/.V_ EN RVH VST SW RVL VF 0 SYS_SHN# _H _VST _SW _L _F PR /F_ P 0.u/0V_ PQ MV PQ MVS P 00p/0V_ PR *._ PL.uH_XX P *0p/0V_ +VPU. Volt +/- % T :. PEK : OP : Width : 0mil +VPU 0/0 remove OP: L(ripple current) =(-)*/(.u*0.m*) =.0 Iocp=-(.0/)=. Vth=(.*mOhm)+mV=.mV R(Ilim)=(.mV*)/0u =.K +V +V_LWP P 0.u/0V VLK _S _S OP: L(ripple current) =(-.)*./(.u*0.m*) ~. Iocp=-(./)=. Vth=(.*mOhm)+mV=.mV R(Ilim)=(.mV*)/0u =.00K +V_S +V_S +V +VPU +VPU +VPU +VPU PR _ PR M_ 0/0 modify P0.u/V_ PR.K/F_ PR 0K/F_ P 0.u/0V_ P PS0 PR _ PR *M_ P 0.u/0V_ + P 0u/.V_ P 0u/.V_ PR _ PR.K/F_ P PS0 P 0.u/0V_ P 0.u/0V_ PR 0_ PR0 0.K/F_ PR 0_ PR M_ S MIN MIN S (,) S_ON PQ N00K PR M_ PQ N00K PQ N00K PQ N00K P *00p/0V_ PQ O0 +V_S T :. PEK : Width : 0mil T : 0. PEK : 0. Width : 0mil PQ O0 +V PQ O0 T : PEK :. Width : 0mil +V +V_S T : 0. PEK : 0. Width : 0mil PQ O0 Quanta omputer Inc. PROJET : EE Size ocument Number Rev SYSTEM V/V (TPS) ate: Wednesday, September, 0 Sheet of

25 T : 0. PEK : Width : 0mil +0.V_R_VTT T : 0. PEK : 0. Width : 0mil +SMR_VREF P 0u/.V_ P 0u/.V_ P 0.u/0V_ +VPU +V () (,,) () HWPG_.V MINON SUSON PR *0_ PR 0_ PR 00K/F_ PR 00K/F_ PR.K/F S _S _MOE _TRIP 0 VREF=.V PGOO S S MOE TRIP P P REF _REF P REFIN VTTREF PU TPSRUKR VQSNS VTT P VTTSNS P P VTT VLOIN RVH VST RVL SW P 0 P 0u/.V RVH PR VST _SW _RVL P u/0v_ P 0.u/0V_ PQ0 MV PQ MVS P 00p/0V_ PR *._ P0 *0p/0V_ P0.u/V_ PL uh_xx 0/0 remove P 0.u/0V_ + P 0u/V_ 0/0 remove +.V_SUS. Volt +/- % T :. PEK :. OP : 0 Width : 0mil +.V_SUS OP=0 L ripple current =(-.)*./(u*00k*) =. Vtrip=0-(./)*mohm =0.0V Rlimit=0.0/0u*=.Kohm P 0.u/0V_ PR 0K/F_ PR 0.K/F REFIN P 0.0u/V_ PR 0_ RSon=mohm Mode Frequency ischarge mode 00K 00K Tracking ischarge 00K 00K Tracking ischarge (,) +0.V_ON R 0 S PR *0 S S S +.V_SUS REF VTT S0 S (mainon off) S/S ON ON OFF ON ON OFF ON OFF OFF Quanta omputer Inc. PROJET : EE Size ocument Number Rev R.V(TPS) ate: Wednesday, September, 0 Sheet of

26 0/0 remove +V PR 00K_ +V_S PR 0_ P P P 0 P P P _H P 00p/0V_ P.u/V_ P.u/V_ +.0V_VTT.0 Volt +/- % T : 0. PEK : OP : Width : 0mil (,) (,,) HWPG_VTT MINON PR 0_ P *0.u/0V_ P u/.v_ PR K/F EN _V _MOE _TRIP PR.K/F_ PGOO EN V MOE TRIP VREF=V VREF PU TPSRTER REFIN GSNS VSNS OMP H ST SW L P 0 PR0 0_ PR SW _L P 0.u/V_ PQ FMS0S G S/ G S S S PL 0.uH_XX _SW PR *._ P *0p/0V_ PR *00_ P 0.u/0V_ + P 0u/V_ +.0V_VTT OP= L ripple current =(-.0)*./(0.u*00k*) =. Vtrip=-(./)*.mohm =0.0V Rlimit = 0.0/0u*=.Kohm +V_S P 0.u/0V_ PR 0 REF PR *0K/F_ PR *K/F REFIN P 0.0u/V GSNS _VSNS P n/0v_ P 0.0u/V_ P n/0v_ PR 0_ PR 0_ RSon.mOhm PR *00_ PR 0_ PR 0_ VP_SENSE () VSSP_SENSE () Size ocument Number Rev +.0V (TPS) Quanta omputer Inc. PROJET : EE ate: Wednesday, September, 0 Sheet of

27 +V 0/0 remove P 0.u/0V_ P 0u/0V_ P 0u/0V_ +VS 0. Volt +/- % T : PEK : Width : 0mil +V_S +VS () (,) HWPG_VS HWPG_VTT PR 0_ +V () P *0.u/0V_ () PR *00K_ VS_VI0 VS_VI P.u/.V_ P u/.v_ PR 0 FILT _EN EN VI0 VI VRV VFILT PGOO MOE PU TPS VREF P OMP P 0 SLEW P VOUT ST SW SW 0 SW SW SW _ST _SW 0/0 remove _MOE P 0.u/0V VREF PL 0.uH_XX _SLEW P 0.u/0V_ P u/.v_ P0 u/.v_ P u/.v_ P0 u/.v_ PR 00/F_ PR K_ PR K_ PR *K/F_ PR.K/F_ P 0.0u/V VOUT PR *0K/F_ PR 0_ VS_SENSE () PR 0_ P 0.u/0V_ P0.n/0V_ PR 0_ Huron River / hief River VI0 VI +VS V 0 0.V 0 0.V 0.V default 0.V Quanta omputer Inc. Size ocument Number Rev VS(TPS) PROJET : EE ate: Wednesday, September, 0 Sheet of

28 +V_ORE 0/0 remove () V_SENSE PR 0_ PR *0_ P0 *0p/0V_ 0_ST 0_H PR./F_ P 0.u/V_ P 0.u/0V_ P0.u/V_ P.u/V_ P 00p/0V_ + P u/v_ () VSS_SENSE Parallel PR PR 00K/F_ *0_ PR K/F_ PR 0.K/F_ PR0 0_ PR *.K/F_ PR0 0K/F_ 0_VREF PR.K/F_ PR K/F_ PR *0_ lose to the PU side. 0_VREF PR K/F_ PR 0K/F_ P0 *0.0u/0V_ PR.K/F_ PR K/F_ 0_OP-R 0_VREF 0_VREF P0 p/0v_ PR.K/F_ +V_S 0/0 modify +V_S 0_SW 0_L 0_SP lose to the VR side. 0_SN PQ FMS0S G S/ G S S S P *0.u/V_ P *0.u/V_ 0_SW P0 n/v_ PR._ P 00p/0V_ PR.K/F_ PR 00K/F 0NT PL / 0.uH_XX PR.K/F_ PR *0K/F_ PR 0_ P 0.u/0V_ R=.mOhm P 0u/.V_ + P 0u/V_ +V_ORE Spec check +V_ORE T : PEK : OP : Width : 000mil VORE Load Line :.mv/ P0 u/.v_ 0_GF 0_VF 0_OMP 0_SN 0_SP 0_THERM P 0.u/0V_ PR 0K/F_ PR0 0_ PR 0_ lose with phase inductor heck pull up resister to.0v for H_PROHOT# +.0V_VTT PR */F_ PR.K/F_ +V PR.K/F_ PR *00K/F_ +V_S 0_F-IMX 0_GOP-R 0_SLEW 0_GF-IMX 0_GSKIP# OP-R F-IMX GOP-R SLEW GF-IMX GSKIP VR 0 VREF GF VF OMP SN SP SP SN SN SP THERM VT V VRV H ST SW 0_VT 0_V 0_VRV 0_H 0_ST 0_SW P0.u/.V_ P.u/.V_ (,) () VRON IMVP_PWRG PR0 0_ 0_VRON VR_ON PGOO PU TPS0RSLR L L 0_L (,) GFX_PWRG PR *0_ GPGOO SW 0 (,,) H_PROHOT# VR_HOT ST P p/0v_ P u/.v_ () () () VR_SVI_LK VR_SVI_LERT# VR_SVI_T VR_SVI_LK VR_SVI_LERT# VR_SVI_T 0 VLK LERT VIO GVF GGF GOMP GSN GSP GSP 0 GSN GTHERM GPWM GPWM PWM P H P 0 0 TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP +V_GFX P0 *0p/0V_ 0_GVF 0_GGF 0_GSN 0_GSP 0_GTHERM 0_GPWM PR 0_ PR 0_ PR *0_ +V P 0.u/0V_ () V_XG_SENSE +V_S PR *0_ 0_VRON PR 00K/F_ () +.0V_VTT P 0.u/0V_ PR./F_ PR 0/F_ VSS_XG_SENSE Parallel lose to VR PR */F_ VR_SVI_LERT# VR_SVI_T VR_SVI_LK PR 0_ PR *0_ PR 00K/F 0NT lose to the PU side. PR.K/F_ 0_GTHERM Place NT close to the GFX_ORE Hot-Spot. P *0.0u/0V_ 0_VREF.V Thermal shutdown setting 0 PR.K/F_ 0_THERM PR 00K/F 0NT Place NT close to the VORE Hot-Spot. 0_VREF P 00p/0V_ PR0.K/F_ 0_GSKIP# 0_GPWM 0_ST PU ST SKIP PWM P P P RVH TPS0RR PR./F_ P 0.u/V_ SW V RVL P P 0 P 0_H 0_SW 0_L +V_S P u/0v_ PQ0 FMS0S 0_GSP 0_GSN G S/ G lose to the VR side. S S S P *0.u/V_ P *0.u/V_ P 0.u/0V_ 0_SW P n/v_ P.u/V_ PR._ P 00p/0V_ lose with XG inductor PR.K/F_ PR 00K/F 0NT XG P.u/V_ PL / 0.uH_XX PR K/F_ PR *K/F_ PR0 0_ P 00p/0V_ P 0.u/0V_ 0/0 remove R=.mOhm P 0u/.V_ / + P0 0u/V_ +V_GFX +V_GFX T : PEK : OP : Width : 0mil Spec check GFX_ORE Load Line : -.mv/ for GT Size ocument Number Rev Wednesday, September, 0 ate: Sheet of + P u/v_ Quanta omputer Inc. PROJET : EE +V_ORE/+VGFX (TPS0)

29 +VPU P 0u/.V_ P MINON PR 0_ PR 00K_ P0 0.u/0V_ u/v_ +VPU P *0.u/0V_ PU G-JFU VPP PGOO VEN J VO N Vout =0.(+R/R) =.0V R 0.V R PR0 *00K_ PR0 0K/F_ PR K/F_ +V HWPG_.V () +.V T : 0. PEK : 0. Width : 0mil P 0u/.V_ Thermal protection (,) Need fine tune for thermal protect point S_ON VL VL S_ON PQ TEU P J000L PR M_ PR 0_ PQ O0 SYS_SHN# (, -test remove +.V Note placement position S_ON PR0 0K NT PQ N00K PR /F_ PR0 00K/F_.V PR 00K/F_ + - PU 0F P 0.u/0V_ PR 00K_ P 0.u/0V_ PQ N00K +V +V +V + - PU 0F PR M_ PR _ PR M_ For E control thermal protection (output.v) (,) MINON_ON_G MINON_ON_G PR _ MIN (,) (,,) MINON MINON PR *00K/F_ PQ N00K PR M_ PQ N00K PQ N00K PQ N00K P *00p/0V_ 0/0 modify Quanta omputer Inc. PROJET : EE Size ocument Number Rev +.V/+.V/Thermal ate: Wednesday, September, 0 Sheet of

30 POWER TREE +VPU () < IN> Thermal Follow hart O0 O0 +V_S (0.) <S_ON> +.V (.) <MIN> NT Thermal Protection TPS +VS () <HWPG_VTT> SYSTEM V/V G +.V (0.) <MINON> PU ORE PWR H_PROHOT# H/W Throttling PU PM_THRMTRIP# WIRE-N SYS_SHN# V/ V SYS PWR TPS G +.V (0.) <MINON> PH FNSIG FN O0 +VPU (.) < IN> +V_S () <S_ON> SM-us O0 +V (0.) <MIN> E PUFN# PU ORE TPS0 +V_ORE () <VRON> HRGER Q +V_GFX TPS0 +.0 TPS R PWR TPS O0 +V_GFX () <VRON> +.0_VTT () <MINON> +._SUS (.) <SUSON> +. (.) <MIN> +0.V_R_VTT () <MINON> +SMR_VREF (0.) <SUSON> SM US RRNGEMENT TLE SMus SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SM_ME_LK SM_ME_T STM_SLK STM_ST THM_LK THM_T MLK MT Function define N/ N/ PH - E SENSOR HU E - THERML E - HRGER E - TTERY ddress 0x 0x 0x 0x US PORT TLE EHI US0 FRONT US M US PORT US TOUH PNEL US N/ US N/ US N/ US N/ US N/ EHI US RER US EUG RESERVE US0 T US SENSOR HU US POGO PIN US N/ Quanta omputer Inc. PROJET : EE Size ocument Number Rev PWR Status & GPU PWR RL & THRM ate: Wednesday, September, 0 Sheet 0 of

31 Power States POWER PLNE VOLTGE ESRIPTION +0V~+V MIN POWER +V_RT +V~+.V RT POWER +VPU +VPU +.V +V E POWER/WLN/Hall sensor/ph HRGE POWER/.V PWM +V +V_S +V +.V HRGE PUMP POWER LN/SPI/TPM POWER/PH +V_S +V US/PH POWER +V +V H/O/odec/HMI POWER +V +.V PH/GPU/Peripheral component/tp POWER +.V_SUS +.V PU/SOIMM ORE POWER +0.V_R_VTT +0.V SOIMM Termination POWER +V_GFX variation Internal GPU POWER +.V +.V PU/PH/raidwood POWER +.V +.V MINI R/NEW R POWER +.0V_VTT +.0V PH ORE POWER/IVY/SN bridge VIO +VS +0.V PU POWER +V_ORE variation PU ORE POWER LV +.V ep L POWER ONTROL SIGNL LWYS LWYS LWYS LWYS LWYS S_ON S_ON MINON MINON SUSON MINON VRON MINON MINON MINON HWPG_VTT VRON LVS_VEN LWYS S0 S S Quanta omputer Inc. PROJET : EE Size ocument Number Rev PWR SEQ Wednesday, September, 0 ate: Sheet of