DIS._eDP. edp N13P-GS N13P-GL N13M-GS PEG TX/RX GPU. Display P15~P19. DMI(x4) INT_LVDS INT_CRT. Display INT_HDMI USB3.0/2.0 USB3-2/USB2-1.

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1 IS._eP OM : igpu : dgpu : Optimus : iscrete only : Special NPGS/GL UM NPGL NP/MGS ep on. P RIII-SOIMM RIII-SOIMM P, INT._eP ual hannel R III 0//00 MHZ ep IM FI IVY ridge rpg GFX P,,, MI PEG TX/RX ep NP-GS NP-GL NM-GS GPU P~P isplay IS._HMI IS._RT IS._LVS VRM P0,P Int. MI Optimus : IV@ EV@ OP@ iscrete only : EV@ O@ FI MI MI(x) INT_LVS US- LVS//MI on. P ST - H ST - O P P US-, ST 0 ST LK ST Panther Point PH P,,, 0,, isplay US.0/.0 ST INT_RT INT_HMI US-/US- ST US harger P US- US Port M side MINI-SS P P RT on. P HMI on. P Small oard ONNETOR P luetooth on. P (amera) P US- US- P zalia TTERY US.0 RT IH LP PI-E x SPI LK X'TL.KHz X'TL MHz SPI ROM P PIE- US-0 PIE- MINI R WLN P RTL 0/00/G ardreader P RJ P ardreader ONN. P Int. MI MI JK P LX-V UIO OE HP P P Speaker P K/ on. P E NPEL EM--T Touch Pad HLL SENSOR oard on. P P P Fan river (PWM Type) P Q0 atery harger P RTP V/V P ISL PU core/vxg P TPS.0V_PH /.0V_VTT P TPS.V_SUS P RT VS P TPS VGPU ore P MV0URH.V_GFX/.0V_GFX/V_GFX P0 ischarger Thermal Protection P Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev lock iagram Friday, November, 0 ate: Sheet of

2 VG power up sequence E V dgpu_rwr_en MOSFET V_GFX dgpu_vron PWM VGORE VG_PG.0V MOSFET.0V_GFX GPU_PWROK.VSUS MOSFET.V_GFX VG_VI VG_PG.V MOSFET.V_GFX Power States POWER PLNE VOLTGE ESRIPTION ONTROL SIGNL TIVE IN 0V~V MIN POWER LWYS LWYS V_RT V~.V RT POWER LWYS LWYS VPU VPU.V V E POWER HRGE POWER LWYS LWYS LWYS LWYS Thermal Follow hart V V_S V_S V V.V V V HRGE PUMP POWER LN/T/IR POWER US POWER H/O/odec/TP/RT/HMI POWER LWYS S_ON S_ON MINON LWYS S0-S S0-S S0 NT Thermal Protection V.V PH/GPU/Peripheral component POWER MINON S0.VSUS 0.V_R_VTT.V 0.V PU/SOIMM ORE POWER SOIMM Termination POWER SUSON MINON S0-S S0 PU ORE PWR H_PROHOT# H/W Throttling PU PM_THRMTRIP# SYS_SHN# WIRE-N V/ V SYS PWR VGFX_XG variation Internal GPU POWER VRON S0.V.V.0V.V.V.0V PU/PH/raidwood POWER MINI R/NEW R POWER PH ORE POWER/IVY/SN bridge VIO MINON MINON MINON S0 S0 S0 PH SMLLERT# FN river FN VS V_ORE 0.V variation PU POWER PU ORE POWER HWPG_VTT VRON S0 S0 SM-us LV.V L POWER LVS_VEN MINON S0 S0 E PUFN# Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev PWR Status & GPU PWR RL & THRM Friday, November, 0 ate: Sheet of

3 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_omp INT_eP_HP_Q EP-ML0 EP-UX EP-UX- EP-ML0- IVY ridge Processor (MI,PEG,FI) TP TP G E F G F0 H E F 0 E G E0 G 0 F J J H0 J H F G E F U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] MI_TX[] MI_TX[] FI0_TX#[0] FI0_TX#[] FI0_TX#[] FI0_TX#[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI0_TX[0] FI0_TX[] FI0_TX[] FI0_TX[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN FI_INT FI0_LSYN FI_LSYN ep_ompio ep_iompo ep_hp ep_ux ep_ux# ep_tx[0] ep_tx[] ep_tx[] ep_tx[] ep_tx#[0] ep_tx#[] ep_tx#[] ep_tx#[] MI Intel(R) FI ep Ivy ridge_rpg_p_rev0p PI EXPRESS* - GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] J J H K M L J J H H G G0 F E E J L K H H G G F F0 E E F E M M M L L K K J0 J H G E F F E M M M0 L L K0 K J J H G E F E For Sandy ridge processor only implementation: PRO_SELET can be left N. For IVY/Sandy processor compatibility: Needs a pull-up resistor to PH VccFTERM rail (.V) through a. K±% pull-up resistor. onnect to the F_TVS of PH though a K±% series resistor. U PEG_OMP R_PEG_TX#0 R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX#0 R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX# R_PEG_TX0 R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX0 R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX R_PEG_TX PEG_OMP connect to PIN H&J W:mils/S:mils/L: 00mils. PEG_OMP connect to PIN J W:mils/S:mils/L: 00mils. PEG_RX#0 [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX#0 [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX# [] PEG_RX0 [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX0 [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] PEG_RX [] EV@0.u/.V_ 00 EV@0.u/.V_ 0 EV@0.u/.V_ 0 EV@0.u/.V_ 0 EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ 0 EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ 0 EV@0.u/.V_ PEG_TX#0 [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX#0 [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX# [] PEG_TX0 [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX0 [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] PEG_TX [] HP disable G.0 : The recommended cap value is changed to 0nF for compatibility with This signal can be left as no PIe Gen on future platforms. connect if entire ep interface For Gen only designs, it is acceptable to continue to use the 00nF capacitor. is disabled EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ EV@0.u/.V_ [,] H_PROHOT# [0] [] E_PEI H_PROHOT# [] PM_SYN apply 0 for nosie [].0V [0] PI_PLTRST# [] H_SN_IV# PM_THRMTRIP# Intel recommended UNOREPWRGOO routing on one layer H_PWRGOO R0 _ PU_PLTRST# IVY ridge Processor (LK,MIS,JTG) TP R _ R SKTO# TP_TERR# PM_THRMTRIP# PM_SYN H_PWRGOO PM_RM_PWRG_R R _ R TP H_SN_IV# H_PROHOT#_R 0.u/0V_ *.K/F_ U N IN 0K_ PU_PLTRST#_R V GNOUT [] LVG0GW [] R *0/F_ N L N L N M P V R 0.u/0V_ PU_PLTRST# SYS_PWROK PM_RM_PWRG V PRO_SELET# SKTO# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# MIS THERML PWR MNGEMENT Ivy ridge_rpg_p_rev0p R.0 : change to V(S0) V_S U LOKS R MIS JTG & PM 0.u/0V_ HG0 SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_RM_PWRG_Q LK LK# PLL_REF_LK PLL_REF_LK# PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[].V_PU wo ep and dgpu onnect PLL_REF_SSLK on Processor to GN through K ± % resistor. onnect PLL_REF_SSLK# on Processor to VP through K ± % resistor R LK_PU_LKP LK_PU_LKN LK_PLL_SSLKP_R LK_PLL_SSLKN_R PU_RMRST# Rb K N K SM_ROMP_0 R 0/F_ SM_ROMP_ R../F_ Rc K N SM_ROMP_ R0 00/F_ R.0 : SM_ROMP[..0] W:0mils, S:mils, L 00mils P P R R P0 R P L T R R0 T0 P R T R R 00/F_ R R XP_PRY# XP_PREQ# XP_TLK PH_JTG_TMS XP_TRST# PH_JTG_TI PH_JTG_TO XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM 0/F_ *_ Rb Rc R0 R R TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP PM_RM_PWRG_R Ra O@K_ O@K_ PU_RMRST# [] IV@0_PR XP_RST# [] For XP.0V Ra EV N LK_PU_LKP [] LK_PU_LKN [] LK_PLL_SSLKP [] LK_PLL_SSLKN [] UM/OPT. 0 ohm Q0 *N00K MINON_ON_G MINON_ON_G [,] FI isabling (iscrete Only) P & PEG ompensation.0v / add R O@K/F_ R R R R O@K/F_ FI_INT O@0_ FI_FSYN0 O@0_ FI_FSYN O@0_ FI_LSYN0 FI_LSYN FI_FSYN can gang all these signals together and tie them with only one K resistor to GN (G V0. h..). ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms.0v.0v Routed within 00 mils Routed within mils R./F_ R./F_ PEG_OMP PEG_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PEG_IOMPO signals should be routed within 00 mils typical impedance =. mohms Processor pull-up(pu).0v H_PROHOT# R _ PH_JTG_TO R _ PH_JTG_TMS R _ PH_JTG_TI R0 _ / modify XP_PREQ# R *_ XP_TLK R _ XP_TRST# R _ [,] IMVP_PWRG PM_THRMTRIP# Q FV0N R K_ Q MMT0 [,,,,,,,,,0,].0V [,,,0,,,,,,,,,,,,,,,,,,,,0,] V SYS_SHN# [,] Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev IVY ridge / Friday, November, 0 ate: Sheet of

4 IVY ridge Processor (R) U U [] M Q[:0] [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q F0 F G0 G F F G G K K K J J J J K M N0 N N M0 M N M G G K K H H J J J K J K H H L L P N L M M L P N J H L K L K J H E0 F0 V E F S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_S#[] S_S#[] S_OT[0] S_OT[] S_OT[] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] V V0 W W0 K L G H H G G H G J M L M R M F K N L M R M 0 W W W V V W W V W V W F V V M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M LK0 [] M LK0# [] M KE0 [] M LK [] M LK# [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M QS#[:0] [] M QS[:0] [] M [:0] [] [] M Q[:0] [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 G F F G G F F G J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_S#[] S_S#[] S_OT[0] S_OT[] S_OT[] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] E R E R0 T T0 E E E E F K N N P K P G J M N P K P T R T T T T R T R R T 0 R R M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M LK0 [] M LK0# [] M KE0 [] M LK [] M LK# [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M QS#[:0] [] M QS[:0] [] M [:0] [] Ivy ridge_rpg_p_rev0p Ivy ridge_rpg_p_rev0p.vsus R0 K/F_ [,] R_RMRST# R0 K/F_ Q _RMRST# N00K PU_RMRST# [] [,,] RMRST_NTRL_PH 0.0u/V_ R00.K/F_ Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev IVY ridge / ate: Friday, November, 0 Sheet of

5 [,,,,,,,,,0,].0V [] V_ORE [,0,,].V [] V_GFX [].V_PU VR_REF_PU [] VS PU ore Power IVY W:T IVY SPE uf_ x Socket TOP cavity uf_ x0 Socket OT cavity uf_ x Socket TOP edge 0uF_ x total : 0uF x 0, RSV x total : uf x, RSV x tatal : 0u x, RSV x SN : Spec 0uF/mohm x uf x uf x 0uF x 0. ose down 0uF x 0uF x 0 reserved x u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ *u/.v_ 0 0 u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ *u/.v_ *u/.v_ u/.v_ 0u/V_ 0 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ *0u/.V_.VSUS u/.v_ *0u/.V_ 00 0u/V_ MIN Q JP *SHORT_P 0 0u/.V_ 0u/.V_ 0u/.V_ *0p/0V_ 0uF (Reserved) *0u/V_ O 0 *0u/.V_.V_PU *0u/V_.V_PU IVY Processor (POWER) V_ORE *0u/.V_ R 0_ G G G G G G0 G G G G F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P UF V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 PU VTT PU VGT IVY W:. IVY SPE ose down IVY W:T ose down uf_ x Socket TOP cavity SN : Spec uf_ x Socket OT cavity 0uF x Spec 0uF x 0uF/mohm x uf_ x Socket TOP edge uf x 0uF/mohm x uf x uf_ x Socket OT edge uf x POWER 0uF_ x uf x 0uF x 0 UG.0V POWER ORE SUPPLY Ivy ridge_rpg_p_rev0p SENSE LINES SVI PEG N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO H H0 G0 0 Y0 U0 P0 L0 J J J J H H H G G G F F F F E E E J J J0 J J J 0 0.0V_VTT_0 H_PU_SVILRT# H_PU_SVILK H_PU_SVIT R00 0_ R 0_ VTT_VP_SENSE VTT_VSSP_SENSE uf x (Non-stuff) 0 u/.v_ 0 u/.v_ 0 *u/.v_ 0u/V_ u/.v_ *u/.v_ 0uF x 0 reserved x IVY SPE uf_ x Socket TOP cavity uf_ x Socket OT cavity uf_ x Socket TOP cavity (no stuff) uf_ x Socket OT cavity (no stuff) 0uF_ x R 0 u/.v_ R R *SHORT_ R R.0V PU VPL IVY W:. V_ORE V_SENSE [] VSS_SENSE [] VTT_VP_SENSE [] VTT_VSSP_SENSE [].0V.V Spec Real 0uF/mohm x 0uF x 0uF x uf x uf x Trace Route to Power I area. 0u/V_ 0 u/.v_ u/.v_ 00 *u/.v_ IVY SPE 0uF x, 0uF_ x, uf_ x Socket OT edge. 00/F_ 00/F_ 0/F_ 0/F_ 0 u/.v_ 0 u/.v_ *u/.v_ u/.v_ 0 u/.v_ *u/.v_ 0 u/.v_ 0 u/.v_ *u/.v_ V_GFX R 0_ R0 0_ IV@u/.V_ *IV@u/.V_ *IV@u/.V_ H_PU_SVILK H_PU_SVIT 0 IV@0u/V_.0V IV@u/.V_ *IV@u/.V_ *IV@u/.V_ IV@u/.V_ R PU_VPLL 0u/.V_ Layout note: need routing together and LERT need between LK and T R Place PU resistor close to PU R 0/F_ IV@u/.V_ IV@0u/V_ IV@u/.V_ 0 IV@u/.V_ IV@u/.V_ IV@u/.V_ O@0/J_ u/.v_ *SHORT_ R0 Place PU resistor close to PU.0V *IV@0u/V_ 0 IV@u/.V_ 0 IV@u/.V_ IV@u/.V_ IV@u/.V_ u/.v_ T T T T0 T T R R R R0 R R P P P P0 P P N N N N0 N N M M M M0 M M L L L L0 L L K K K K0 K K J J J J0 J J H H H H0 H H SVI LK Remove PU resistor./f, stuff at IMVP page IVY ridge Processor (GRPHI POWER) VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VPLL VPLL VPLL SVI T Remove PU resistor 0/F, stuff at IMVP page *SHORT_ *0u/V_ SVI LERT GRPHIS.V RIL Ivy ridge_rpg_p_rev0p VR_SVI_LK [] VR_SVI_T [] SENSE LINES S RIL R -.V RILS VREF MIS VXG_SENSE VSSXG_SENSE [,,] MIN SMR_VREF 0 mil VR_REF_PU IVY SPE 0uF x, 0uF_ x Socket OT edge. VIO_SEL_N IVY SPE 0uF x, 0uF_ x Socket OT edge, 0uF_ x Socket OT cavity. PU S IVY W: Spec 0uF/mohm x 0uF x SM_VREF S_IMM_VREFQ S_IMM_VREFQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VS VS VS VS VS VS VS VS VS_SENSE VS_VI[0] VS_VI[] VIO_SEL K K L F F F Y Y Y U U U P P P M M L J J J H H H 0 change value by R Rb Rd MIN VS_SENSE [] VS_VI0 [] VS_VI [] V_GFX VR_REF_PU Voltage selection for VIO: this pin must be pulled high on the motherboard On R H_SN_IV#_PWRTRL = low,.0v H_SN_IV#_PWRTRL = high/n,.0v Real 0uF x R R R 0u/.V_ 0u/.V_ 0u/.V_ R R *0_ TP Q N00K IV@0/F_ IV@0/F_ 0u/.V_ *0u/.V_ 0u/.V_ *K_ *K_ 0u/.V_ 0u/.V_ VR_REF_PU *0u/.V_ R 00K_ V_XG_SENSE [] VSS_XG_SENSE [] For M solution need Rb, Rd W/O M then N ball and SMR_VREF_Q0_M [] SMR_VREF_Q_M [] 0u/.V_.V_PU 0u/V_ 0u/V_.VSUS VS PU MH IVY W: Spec 0uF/mohm x 0uF x Real 0uF x 0u/.V_ R *K/F_ R *K/F_ [,] MINON_ON_G MINON_ON_G Q MN0K- [] V_GFX [] V_ORE H_PU_SVILRT# R _ R _ R *SHORT_ VR_SVI_LERT# [] Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev IVY ridge / Friday, November, 0 ate: Sheet of

6 UH T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T0 VSS0 T VSS T VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS0 R VSS R VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS0 P0 VSS P VSS P VSS P VSS N0 VSS N VSS N VSS N VSS N VSS N VSS0 N VSS N0 VSS N VSS N VSS M VSS M VSS M VSS M VSS M VSS M VSS0 M0 VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L VSS L0 VSS L VSS L VSS L VSS K VSS K0 VSS0 K VSS K VSS K VSS K VSS K VSS K VSS K0 VSS K VSS K VSS J VSS0 IVY ridge Processor (GN) VSS VSS J VSS J VSS J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS0 J VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS00 H VSS0 H VSS0 H VSS0 H VSS0 G VSS0 G VSS0 G VSS0 F VSS0 F VSS0 F VSS0 F VSS E VSS E VSS E VSS E VSS E VSS E0 VSS E VSS E VSS E VSS0 E VSS E VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS Y VSS0 Y VSS Y VSS Y VSS Y VSS Y VSS W VSS W VSS W VSS W VSS W VSS0 W0 VSS W VSS W VSS W VSS W VSS U VSS U VSS U VSS U VSS U VSS0 U UI UE T VSS T VSS T VSS T VSS T VSS T0 VSS T VSS T VSS T VSS T VSS0 P VSS P VSS P VSS P VSS P VSS P VSS N VSS N VSS N VSS N VSS0 N VSS N0 VSS N VSS N VSS N VSS N VSS M VSS L VSS L0 VSS L VSS0 L VSS L VSS L VSS L VSS L VSS L VSS L VSS L VSS K VSS K VSS00 K VSS0 K VSS0 J VSS0 J VSS0 H VSS0 H0 VSS0 H VSS0 H VSS0 H VSS0 H VSS0 H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS H VSS G VSS G VSS G VSS G VSS G VSS G0 VSS G VSS G VSS0 F VSS F VSS F VSS VSS VSS F VSS F VSS E0 VSS E VSS E VSS E VSS0 E VSS E VSS E VSS E0 VSS E VSS E VSS E VSS E VSS E VSS E VSS0 E VSS E VSS E VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS IVY ridge Processor (RESERVE, FG) TP TP TP TP0 TP XP_FG0 K FG K FG L FG L FG K FG L FG L0 FG M M M0 M M N N N M K N J FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] F RSV F RSV F RSV0 RSV G RSV G RSV E RSV RSV 0 RSV RSV 0 RSV RSV 0 RSV0 RSV 0 RSV RSV RSV FG J VXG_VL_SENSE H VSSXG_VL_SENSE J V_VL_SENSE H VSS_VL_SENSE J RSV J0 RSV RSV RESERVE Ivy ridge_rpg_p_rev0p V_IE_SENSE H VSS_IE_SENSE H RSV L RSV G RSV0 E RSV K RSV W RSV T RSV M RSV J RSV T RSV J RSV H RSV0 G RSV R RSV T RSV T RSV P RSV R RSV RSV RSV RSV RSV0 RSV J RSV K LK_ITP N LK_ITP# M RSV T RSV T RSV R KEY V_IE_SENSE VSS_IE_SENSE Rs R *SP@0_ TP TP TP TP TP TP Rs For Sandy Stuff For IVY N Ivy ridge_rpg_p_rev0p Ivy ridge_rpg_p_rev0p Processor Strapping FG (PEG Static Lane Reversal) FG (P Presence Strap) FG (PEG efer Training) The FG signals have a default value of '' if not terminated on the board. Normal Operation PEG train immediately following xxreset de assertion 0 isable; No physical P attached to ep Lane Reversed Enable; n ext P device is connected to ep PEG wait for IOS training / modify FG FG FG R R R K/F_ IV@K/F_ *K/F_ ep_en# [] FG FG R0 R *K/F_ *K/F_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev IVY ridge / ate: Friday, November, 0 Sheet of

7 [,,,,,,,,,0,],,,,,,,,,,,,,,,,0,] [,,,0,,,,0,,,,,,] [] MI_RXN0 [] MI_RXN [] MI_RXN [] MI_RXN [] MI_RXP0 [] MI_RXP [] MI_RXP [] MI_RXP [] MI_TXN0 [] MI_TXN [] MI_TXN [] MI_TXN [] MI_TXP0 [] MI_TXP [] MI_TXP [] MI_TXP.0V R R SUS_PWR_K R [] XP_RST# 0 SYS_PWROK R *0_ PWROK_E [] PM_RM_PWRG [] PH_RSMRST# [] NSWON#.0V V V_S *0_./F_ MI_OMP 0/F_ XP_RST# *u/0v_ SUSK#_R PM_RM_PWRG PH_RSMRST# SUS_PWR_K _PRESENT PT/PPT (MI,FI,PM) U0 E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H K P L L0 K E0 H0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_RESET# SYS_PWROK PWROK PWROK RMPWROK MI System Power Management RSMRST# SLP_S# V_S SUSWRN#/SUSPWRNK/GPIO0 SLP_S# PWRTN# PRESENT / GPIO U0 V LKRUN# / GPIO V_S SUS_STT# / GPIO V_S SUSLK / GPIO V_S SLP_S# / GPIO SW FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SWVRMEN PWROK WKE# SLP_# SLP_SUS# J Y E H J G0 G G F G E G J0 H W V 0 V 0 E N G N 0 H F G0 G PH_RSMRST# PIE_WKE# LKRUN# SUS_STT# PH_SUSLK PH_SLP_S# SLP_# SLP_SUS# T T T T0 FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_INT [] FI_FSYN0 [] FI_FSYN [] FI_LSYN0 [] FI_LSYN [] SWVREN [] PIE_WKE# [] LKRUN# [] SUS# [] SUS# [] SLP_# [] 0/ modify [] [] INT_HSYN INT_VSYN [] [] [] [] [] [] [] [] INT_LVS_LON [] INT_LVS_IGON [] INT_LVS_RIGHT INT_LVS_EILK INT_LVS_EIT [] [] [] [] [] [] [] [] V INT_TXLLKOUT- INT_TXLLKOUT INT_TXLOUT0- INT_TXLOUT- INT_TXLOUT- INT_TXLOUT0 INT_TXLOUT INT_TXLOUT INT_RT_LU INT_RT_GRN INT_RT_RE INT_RT_LK INT_RT_T R R IV@_ IV@_ The required series-resistors are: irect onnect - ocking Topology - 0 R place close to PH R IV@0/F_ INT_RT_LU R R R.K_.K_.K/F_ T INT_RT_LU INT_RT_GRN INT_RT_RE INT_RT_HSYN_R INT_RT_VSYN_R _IREF R K/F_ J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T PT/PPT (LVS,I) L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN PNTHER POINT LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y M M T T H F E F E J G INT_HMITXN_R INT_HMITXP_R INT_HMITXN_R INT_HMITXP_R INT_HMITX0N_R INT_HMITX0P_R INT_HMILK-_R INT_HMILK_R P_HP_PU P_HP_PU HMI_LK_SW [] HMI_T_SW [] HMI_HP [] RP IV@0_PR INT_HMITXN [] INT_HMITXP [] RP IV@0_PR INT_HMITXN [] INT_HMITXP [] RP0 IV@0_PR INT_HMITX0N [] INT_HMITX0P [] RP IV@0_PR INT_HMILK- [] INT_HMILK [] P_HP_PU R *.K_ P_HP_PU R *.K_ 0 : Port not detected INT. HMI PM_TLOW# E0 TLOW# / GPIOV_S PMSYNH P PM_SYN [] R IV@0/F_ INT_RT_GRN PM_RI# 0 RI# V_S SLP_LN# / GPIO K SLP_LN# R IV@0/F_ INT_RT_RE PNTHER POINT PH Pull-high/low(LG) V V_S R.0 change R to K PM_RI# R 0K_ System PWR_OK(LG) V_S IMVP_PWRG PU V PWROK_E P so N gate output dont need P again LKRUN# XP_RST# R R.K_.K/F_ PM_TLOW# PIE_WKE# R R.K_ 0K_ *0.u/0V_ R PH_RSMRST# R SYS_PWROK R0 *K_ 0K_ *0K_ SLP_LN# R0 *0K_ SUS_PWR_K R 0K PRESENT R0 0K_ PM_RM_PWRG R 00/F_ wo S leakage, remove R to PH Pin, XP and EE debug U [] SYS_PWROK SYS_PWROK TSH0FU PWROK_E R 00K_ IMVP_PWRG [,] PWROK_E [] Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev Panther Point / Friday, November, 0 ate: Sheet of

8 RT ircuitry(rt) 0mils VPU 0MIL 0MIL R 0_ R K_ N H us(lg) V_RT_ 0/ chnage footprint & PN RT_ON. [] [] [] [] T V_RT PH_Z_OE_ITLK PH_Z_OE_SYN PH_Z_OE_RST# PH_Z_OE_SOUT PH JTG ebug (LG) / add R 0mils R 0 u/.v_ R _ R 0/F_ 0K_ 0K_ R *00/F_ V_S N FWF0MS R 00/F_ u/.v_ R0 _ R _ R 0/F_ u/.v_ R _ R0 _ R 0/F_ PH(LG) PT/PPT (H,JTG,ST) RT_RST# p/0v_ SRT_RST# PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TK PH_JTG_TO_R R0 00/F_ J *SHORT_P J *SHORT_P battery HL0000 HL0000 Z_ITLK_R Z_SYN_OE Z_RST#_R Z_SOUT_R V Z_SYN_OE [] V_RT dd MOSFET to separate OE SYN signal R.0 R0 R M_ 0K_ Q N00K Y.KHZ p/0v_ [] R SPKR PH_Z_OE_SIN0 R 0M_ M_ TP TP0 TP RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK_R Z_SYN_R SPKR Z_RST#_R Z_SOUT_R PH_GPIO PH_GPIO PH_JTG_TK PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R G K N L T0 K E G N J H K H U0 RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# RT IH JTG ST LP ST G FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# V LRQ# / GPIO ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP H_SIN0 STRXN STRXP H_SIN STTXN STTXP H_SIN STRXN H_SIN STRXP STTXN STTXP H_SO STRXN STRXP H_OK_EN# / GPIO V STTXN STTXP H_OK_RST# / GPIO V_S STRXN STRXP STTXN JTG_TK STTXP JTG_TMS JTG_TI JTG_TO SERIRQ STIOMPO STIOMPI STROMPO E K V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 PH_RQ#0 PH_RQ# R ST_OMP ST_OMP TP TP.K_ R R V TP TP TP./F_./F_ LP_L0 [,] LP_L [,] LP_L [,] LP_L [,] LP_LFRME# [,] IRQ_SERIRQ [] ST_RXN0_ [] ST_RXP0_ [] ST_TXN0 [] ST_TXP0 [] ST_RXN_SS [] ST_RXP_SS [] ST_TXN_SS [] ST_TXP_SS [] ST_RXN_ [] ST_RXP_ [] ST_TXN [] ST_TXP [].0V ST H SS G recommended that coupling capacitors should be close to the connector (<00 mils) for optimal signal quality. ST O STOMPI PH ual SPI (LG) 0/ add V_S V_M PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO (efault for WIN) WQVSSIG / KEP0N >M WQVSSIG / KEFP0N0----->M for WQVSSIG / KEEFP0N >M R V@0_ V_PH_ME 0/ add R _ R _ R _ *p/0v_ U E# SK SI SO WP# ROM-M V HOL# VSS R0.K_ V_PH_ME 0.u/0V_ PH Strap Table [] [] [] PH_SPI_LK PH_SPI_SI VPU PH_SPI_SO PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO Pin Name Strap description Sampled onfiguration 0 = efault (weak pull-down 0K) SPKR No reboot mode setting PWROK = Setting to No-Reboot mode GNT# / GPIO Top-lock Swap Override R PWROK 0K_ T Y T V U 0 = "top-block swap" mode = efault (weak pull-up 0K) SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO PNTHER POINT SPI STLE# V ST0GP / GPIO V STGP / GPIO V STRIS R0 R H P V P *K_ *K_ ST_RIS ST_T# ST0GP S_IT0 SPKR R R0 R PI_GNT# [] 0/F_ 0K_ 0K_ V V ST_T# [] ST0GP/GPIO STGP/GPIO STGP/GPIO If these pins are unused use.k to 0k pull-up to Vcc_ or.k to 0k pull-down to ground Used as GPIO only. at chklist. V_PH_ME R.K_ INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up V_RT R 0K_ PH_INVRMEN [] V_PH_ME PH_SPI_S# PH_SPI_LK PH_SPI_SI PH_SPI_SO SPI_S0#_UR_ME R 0/ add R _ R _ R _ *p/0v_.k_ U E# SK SI SO WP# ROM-M V HOL# VSS R R *0_ R 0_ V_PH_ME.K_ 0.u/0V_ PH_SPI_S0# PH_SPI_S# GNT# / GPIO GPIO F_TVS GPIO oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] MI/FI Termination voltage On-die PLL Voltage Regulator PWROK PWROK H_SO Flash escriptor Security RSMRST PWROK RSMRST# GNT# 0 = overridden GNT0# 0 oot Location SPI * LP 0 = effect (default)(weak pull-down 0K) 0 = Set to Vss (weak pull-down 0K) = Set to Vcc 0 = isable = Enable (weak pull-up 0K) 0 = Support by.v (weak pull-down) H_SYN On-ie PLL VR Voltage Select RSMRST Z_SYN_R V_S R K_ Needs to be pulled High for Huron River platform. = Support by.v chklist. Intel ME rypto Transport Layer 0 = isable (efault) GPIO Security (TLS) cipher suite RSMRST = Enable V_S R K_ PH_GPIO [0] internal P [] ME_WR R R R R R.K_ K_ *K_ *K_ R0 *K_.V S_IT0 *SHORT_ H_SN_IV# [] F_TVS [0] S_IT [] Z_SOUT_R PLL_OVR_EN [0] 00 efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] ME_WR default E setting folating for future PU, Sandy ridge N F_TVS needs to be pulled up to VccFTERM power rail through. kohm ±% - R change to 0 or not?? [,,0,,,,,,] [,,,,,,,] [,,,0,,,,0,,,,,,] [,,,,,,,,,0,],,,,,,,,,,,,,,0,] [,0,,] VPU V V_S.0V V.V SWVREN NV_LE EEP S/S well On ie SW VR Enable Intel nti-theft H protection Only for Interposer SW PWROK High = Enable (efault) Low = isable 0 = isable (Internal pull-down 0kohm) V_RT R0 R.V R0 0K_ *0K_ *K_ SWVREN [] NV_LE [] Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev Panther Point / Friday, November, 0 ate: Sheet of

9 ,,,,,,,,,,,,,,,,,,0,] [,,,0,,,,0,,,,,,] [,,,,,,,,,0,] [] [0] [0] [0] [0] [] [0] [] [] LK_LP_EUG [] LK_PI_ S_IT OR_I PI_GNT# G_SENSOR_INT#_PH [0] dgpu_pwr_en [] GPU_HOL_RST# [] US0_RX US0_TX PI_PLTRST# LK_PI_F V V_S.0V TX cap place at connector side, cap to connector < 00mils / modify TP TP TP0 TP TP TP TP USP- USP US0_RX- US0_RX- US0_TX US0_TX PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# dgpu_eisel# dgpu_selet# REQ# G_SENSOR_INT#_PH dgpu_pwr_en GPU_HOL_RST# EXTTS_SNI_RV_PH TP R _ R _ R _ PI_PME# PI_PLTRST# LK_PI_F_ LK_LP_EUG_ LK_PI PT/PPT (PI,US,NVRM) G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 U0E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 RSV US0_RXN US0_RXN US0_RXN US0_RXN US0_RXP US0_RXP US0_RXP US0_RXP US0_TXN US0_TXN US0_TXN US0_TXN US0_TXP US0_TXP US0_TXP US0_TXP PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 V REQ# / GPIO V REQ# / GPIO V GNT# / GPIO V GNT# / GPIO V GNT# / GPIO V PIRQE# / GPIO V PIRQF# / GPIO V PIRQG# / GPIO V PIRQH# / GPIO V PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI PNTHER POINT PI US V_S O0# / GPIO V_S O# / GPIO0 V_S O# / GPIO V_S O# / GPIO V_S O# / GPIO V_S O# / GPIO V_S O# / GPIO0 V_S O# / GPIO U0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L USP- USP US0_RX US0_RX US0_TX- US_IS US_O0# US_O# US_O# US_O# US_O# US_O# US_O# US_O# NV_LE [] Port and port can be used on debug mode T T0 Reserve for US I/O function USP- [0] USP [0] US/-US-/US debug USP- [0] USP [0] M US USP- [] USP [] Mini-SS USP- [0] EHI USP [0] LUETOOTH T T Reserve for SIM card US port/ may not be available on all PH sku (HM support port only) USP- [] USP [] USP- [0] USP [0] USP0- [] USP0 [] Reserve for card reader Reserve for Touch pad Reserve for FP R0./F_ amera US/-US- Mini ard (WLN) US_O0# [0] US_O# [0] EHI LN Wireless XHI for USP0- Wireless LN [] [] [] [] [] [] [] [] [] [] [] [] LK_PH_SR# LK_PH_SR PIE_LK_REQ# [] [] US0_TX- US0_TX- US0_TX USP0- USP0 US0_RX- US0_TX- PIE_RX- PIE_RX PIE_TX- PIE_TX PIE_RX- PIE_RX PIE_TX- PIE_TX LK_PIE_LOM# LK_PIE_LOM LK_PIE_LN_REQ# For XP 0 T T T T 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_LK_US0_REQ# PIE_LKREQ# PIE_LK_REQ# PIE_LKREQ# PIE_LKREQ# LK_PH_SR# LK_PH_SR PIE_LKREQ# LK_PIE_LOM# LK_PIE_LOM LK_PIE_LN_REQ# LK_PH_SRP LK_PIE_REQ# LK_PH_SRP LK_PIE_REQ# LK_ITPN LK_ITPP PT/PPT (PI-E,SMUS,LK) G J V U E F Y G J V U F E Y G H Y J G U V G0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L V V L 0 E V0 V T V V K K K PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO V_S V_S V V LOKS V_S V_S V_S LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIOV_S LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P V_S V_S V_S SML0LERT# / GPIO0 SMUS SMLLERT# / PHHOT# / GPIO V_S SMLLK / GPIO V_S SMLT / GPIO ontroller Link V_S FLEX LOKS SMLERT# / GPIO SMLK SMT SML0LK SML0T L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP V LKOUTFLEX0 / GPIO V LKOUTFLEX / GPIO V_S V LKOUTFLEX / GPIO V LKOUTFLEX / GPIO E H G E M M T P0 M0 V U M M F E J0 G0 G E K K K H V V Y K F H K SMLERT# SM_PH_LK SM_PH_T RMRST_NTRL_PH SM_ME0_LK SM_ME0_T SMLLERT#_R SM_ME_LK SM_ME_T L_LK L_T L_RST# LK_PEG_REQ# LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LKN LK_UF_LKP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M LK_PI_F XTL_IN XTL_OUT XLK_ROMP SKU_I LK_FLEX M_LK_R R TP TP TP R For LN For E T T *0_ 0./F_ OR_I [0,].0V RMRST_NTRL_PH [,,] SMLLERT# [0,] LK_PEG_REQ# [] LK_PIE_VG# [] LK_PIE_VG [] LK_PU_LKN [] LK_PU_LKP [] LK_PLL_SSLKN [] LK_PLL_SSLKP [] R M_ Y MHz p/0v_ p/0v_ PNTHER POINT PLTRST#(LG) PI/USO# Pull-up(LG) V LK_REQ/Strap Pin(LG) SMus(E) SMus(PH) PI_PLTRST# V 0/ modify 0 0.u/0V_ U TSH0FU R 00K_ PLTRST# [,,,] US_O# US_O# US_O# US_O# V_S R 0 0K_0PR US_O# US_O0# US_O# US_O# / modify PI_PIRQ# R PI_PIRQ# R PI_PIRQ# R PI_PIRQ# R0 V R 0 G_SENSOR_INT#_PH REQ# dgpu_pwr_en 0K_0PR.K_.K_.K_.K_ / modify GPU_HOL_RST# EXTTS_SNI_RV_PH dgpu_eisel# dgpu_selet# V_S R 0K_ R 0K_ R 0K_ R 0K_ R0 0K_ R 0K_ R 0K_ V R 0K_ R 0K_ / modify PIE_LK_US0_REQ# PIE_LKREQ# PIE_LKREQ# PIE_LKREQ# LK_PIE_LN_REQ# LK_PIE_REQ# LK_PIE_REQ# PIE_LKREQ# PIE_LK_REQ# [] N_MLK V_S R.K_ SM_ME_LK Q N00K V_S S SM_PH_T V V R0.K_ Q N00K S0 LK_ST [,,,,] V R R *SP@K_ SP@00K_ dgpu_pw_trl# [0] UM Only dgpu_pw_trl# (GPIO) TL : dgpu_vron SKU_I SKU_I0 VG H/W (GPIO) (GPIO) Signal 0 0 UM Setup Menu Hidden UM boot R LK_UF_LKN LK_UF_LKP *0K_ LK_PEG_REQ# R 0K_ R 0K_ [] N_MT R0.K_ SM_ME_T Q N00K SM_PH_LK R0.K_ Q0 N00K LK_SLK [,,,,] V R R V R R OP@0K_ SP@0K_ EV@0K_ SP@0K_ SKU_I SKU_I0 [0] dgpu Only 0 0 GPU Hidden GPU boot Switchable (Mux) UMGPU dgpu/sg UM boot Optimize (Muxless) 0 UM UM/SG UM boot dgpu_pw_trl# = GPU power is control by H/W (pure iscrete SKU) 0 = GPU power is control by PH GPIO (iscrete, SG or Optimize) --->(efault) LK_UF_PIE_GPLLN R 0K_ LK_UF_PIE_GPLLP R 0K_ LK_UF_REFLKN R 0K_ LK_UF_REFLKP R0 0K_ LK_UF_REFSSLKN R0 0K_ LK_UF_REFSSLKP R 0K_ LK_PH_M R 0K_ LOK TERMINTION for FIM V_S R R R0 R R R R K_ 0K_.K_.K_.K_.K_ 0K_ RMRST_NTRL_PH SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SMLLERT#_R Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev Panther Point / Friday, November, 0 ate: Sheet of

10 ,,,,,,,,,,,,,,,,0,] [,,,,,,,0,,,,,,] [] SIO_EXT_SMI# [] SIO_EXT_SI# [] PH_GPIO [] SKU_I0 [,] GPU_PWROK / modify [] PLL_OVR_EN [,] SMLLERT# V V_S TP TP [,0] dgpu_vron TP R S_GPIO SIO_EXT_SMI# OR_I SIO_EXT_SI# GPIO G_SENSOR_I PH_GPIO PH_GPIO PLL_OVR_EN STP_PI# MI_OVRVLTG FI_OVRVLTG MFG_MOE OR_I0 TEST_SET_UP SV_ET_N R *SHORT_ STGP : strap for reserved at chklist. STGP : strap for reserved at chklist. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled. R 00_ 00K_ 0/ modify PT/PPT (GPIO,VSS_NTF,RSV) U0F T MUSY# / GPIO0 V V TH / GPIO 0 TH / GPIO V V TH / GPIO H TH / GPIO V V TH / GPIO0 E TH / GPIO V V TH / GPIO 0 0 GPIO V_S LN_PHY_PWR_TRL / GPIO V_S G GPIO V_S 0GTE P U PEI U STGP / GPIO V RIN# P 0 TH0 / GPIO V PROPWRG Y T SLOK / GPIO V THRMTRIP# Y0 E GPIO / MEM_LE V_S INIT_V# T E GPIO SW F_TVS Y P GPIO V_S TS_VSS H K STP_PI# / GPIO V TS_VSS K K GPIO V TS_VSS H0 V STGP / GPIO V TS_VSS K0 M STGP / GPIO V N SLO / GPIO V N_ P M STOUT0 / GPIO V V STOUT / GPIO V VSS_NTF_ G RIT_TEMP_REP# V STGP / GPIO V VSS_NTF_ G GPIO V_S VSS_NTF_ H E E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ PNTHER POINT GPIO NTF PU/MIS VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ H J J J J J J E E F F R SIO_0GTE PH_PEI SIO_RIN# OR_I PH_THRMTRIP# F_TVS 0K_ TP V R 0_ dgpu_pw_trl# [] LE_I [] SIO_0GTE [] SIO_RIN# [] H_PWRGOO [] PM_THRMTRIP# [] F_TVS [] TEST_SET_UP SGPIO S_GPIO SV_SET_UP High = Strong (efault) R R R0 R V V 0/ modify V PH_GPIO PLL_OVR_EN SIO_EXT_SMI# SIO_EXT_SI# STP_PI# SIO_0GTE SIO_RIN# RIT_TEMP_REP# F_TVS PH_GPIO R 0K_ OR_I0 R *0K_ R 0K_ OR_I R *0K_ GPIO Pull-up/Pull-down(LG) Follow the Emerald Lake R GPIO : If not used then use.-k to 0-k pull-down to GN. K_ *K_ 0K_ *K_ R0 R R R Reserve for future *0K_ *0K_ OR_I OR_I OR_I R R0 R0 R0 R R R Layer >High * Layer >Low *0K_ 0K_ R0 R0 R R R0 *0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ *K_ 0K_ 0K_ 0K_ OR_I [] OR_I [,] OR_I [] V_S V.V V R0 FI TERMINTION VOLTGE OVERRIE V V V R 00K_ FI_OVRVLTG R *K_ MI_OVRVLTG R *00K/F_ G_SENSOR_I SP@0K_ R SP@K_ LOW - Tx, Rx terminated to same voltage MI TERMINTION VOLTGE OVERRIE Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) IOS REOVERY High = W/O G_SENSOR Low = W G_SENSOR MFG-TEST MFG_MOE R R V 0K_ *K_ Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev Panther Point / ate: Friday, November, 0 Sheet 0 of

11 PH(LG) PT/PPT (POWER) V V Vcc =m(mils) L0 PT/PPT (POWER) U0G POWER KP0HS-T/0ohm/._.0V.0V_PH_V.0V R0 *0_ VccORE =. (0mils) 0 R 0.00/F_0 u/.v_ 0.u/0V_ 0u/.V_ VORE[] V U 0.0u/V_ U0J POWER VORE[] VLK VORE[] VLVS V u/.v_ VORE[] VSS U VLK VIO[] u/.v_ u/.v_ 0u/.V_ F VccLVS=m(mils) VSW_= m VORE[] F R IV@0_ V_S R0 *SHORT_ VPSW VIO[0] T VORE[] VSW_ G R near PH ball for VP GN sense VORE[] G R0 O@0_ VIO[] VORE[] G PH_VSW.0V.0V_PH_VPLL_EXP VORE[] VLVS K V When is sku, LVS power can short to GN 0.u/0V_ PSUSYP VIO[] G VORE[0] G R *SHORT_ VORE[] VSSLVS K G V_TX_LVS.V 0 V_SUS_LKF VIO[] VORE[] T J.0V VPLL_PY_PH VccTX_LVS=0m(0mils) *0.u/0V_ V_[] VORE[] J.0V.0V_VPLL_EXP VORE[] VTX_LVS[] M L J IV@0.uH/0m_ L *0uH/00m_ VSUS_[] VORE[] H VPLLMI J L *uh/m_ VORE[] VTX_LVS[] M J R O@0_.0V R *SHORT_ VPLL_PY VSUS_[] VORE[] L IV@0.0u/V_ IV@u/.V_ VIO[] VTX_LVS[] P *0u/.V_ VSUS_[] IV@0.0u/V_ VSUS *0u/.V_ VTX_LVS[] P L PSUS[] VSUS_[0] N VIO[] VME(.0V) =??(??mils) VSUS_[] J V_V_GIO V *u/.v_.0v.0v_vio VPLLEXP VSW[].0V.0V_VEPW VccIO =. (0mils) V_[] V R *SHORT_ VIO[] R 0.00/F_0 VSW[] N VIO[] VccSW =.0 (0mils) VMI = m(0mils) R V@0.00/F_0.0V VSW[] VREF_SUS N 0 0 VIO[].V_V_MI.0V_M R u/.v_ u/.v_ V_[] V 0.u/0V_ VSW[] N R *SHORT_ u/.v_ u/.v_ u/.v_ PSUS[] VIO[] VSW[] VSUS_[] N 0/ add VIO[] VSW[] V R.0V N VIO[] P u/.v_ 0u/.V_ VIO[0] P VIO[] P VIO[] P VIO[] T V_V_EXP VIO[] *SHORT_ N VIO[] N VIO[] 0.u/0V_ H V_[] VFI_VRM VFI_VRM P VVRM[] V ORE VIO RT LVS FT / SPI MI HVMOS R *0_.0V_VPLL_FI G VSPI = 0m(mils) R *SHORT_ VccFIPLL V_VME_SPI V_S R *SHORT_.0V_VPLL_FI P VIO[] 0/ add VSPI V R V@0_.V_V_MI U0 VMI[] PNTHER POINT VFI_VRM FI VFI_VRM VVRM[] T VFI_VRM VSW[] u/.v_ 0 VSW[] VLKMI = 0m(mils) u/.v_ u/.v_ VMI[] T0 VSW[].V_V_MI_I V_MI_I.0V VSW[0] L R */F_ VLKMI *0uH/00m_ VSW[] R 0_ 0 VSW[] u/.v_ *0u/.V_ VSW[] W VSW[] VFTERM[] G VP_NN.V VPNN = 0 m(mils) W VSW[] VFTERM[] G R00 *SHORT_ W VSW[] W VSW[] VFTERM[] J 0.u/0V_ W VSW[].0V VFTERM[] J W VSW[] V_M R *SHORT_ Reserve V_S to VSPI for E u/.v_ R *SHORT_.0V R *0_ W VSW[0] 0.u/0V_ VRTEXT N u/.v_ PRT VFI_VRM VFI_VRM Y VVRM[] m(0mils).0v_v PL u/.v_ VPLL m(mils).0v_v PL F VPLL VIFFLK F VIFFLKN VIO[] F VIFFLKN[] VIFFLKN= m(0mils) F u/.v_ VIFFLKN[] G VIFFLKN[] VSS= m(0mils) V.0V_SSV G VSS lock and Miscellaneous ST PI/GPIO/LP US M N N VREF P N0 VSUS_[] N VSUS_[] P0 VSUS_[] P VSUS_[] V_[] V_[] W V_[] T.0V_VUSORE.0V R0 *SHORT_ N P u/.v_ VSUS_ = m(mils) P V_S T R *SHORT_ T 0.u/0V_ T V_VPUS T R *SHORT_ V V 0 0.u/0V_ P V_VUG T VUPLL R0 *SHORT_.0V VREFSUS=m V_PH_VREFSUS V_USSUS V_VPSUS *u/.v_ V_PH_VREF V_VPSUS V_VPORE V 0.u/0V_ V_[] J VIO[] F V.0S_ST VIO[] H VIO[] H VIO[] F V.LN_VPLL VPLLST K VVRM= m(mils) VFI_VRM VVRM[] F R *SHORT_ VIO[] VIO[] u/.v_ VIO[] R 0/F_ V_S R00V-0 V_S 0 0.u/0V_ VREF= m R 0/F_ V R00V-0 V 0 u/.v_ R *SHORT_ V_S VSUS_ = m(mils) u/0v_ R *SHORT_ V VPORE = m(0mils) 0.u/0V_ V 0.u/0V_ R *SHORT_.0V u/0v_??m(??mils) L.0V *0uH/00m_ *0u/.V_.0V.V.0V R 0_ R *0_ VVRM:.V (estop).v (Mobile).0V m(mils) VRT<m(mils) R *u/.v_ *SHORT_ 0.u/.V_ 0.u/0V_ VSST V.0M_VSUS VTT_VPPU 0.u/0V_ 0.u/0V_ V PSST T PSUS[] V PSUS[] J V_PRO_IO PU MIS VSW[] T VSW[] V VSW[] T.0V_VEPW R VME =.0(0mils) *0_.VSUS V_RT u/.v_ 0.u/0V_ 0.u/0V_ VRT PNTHER POINT RT H VSUSH P V._._H_IO *u/.v_ 0.u/0V_ R0 0_ V_S VSUSH= 0m(mils) [,,,,0,,,0,,,,,,] [,0,,,,,,] [,,,,,0] V_S V_S.VSUS [,,,,,,,] V 0,,,,,,,,,,,,,,,,,,,0,] V [,,].V [,,,,,,,,,0,].0V [,,0,].V [] V_RT.0V L 0uH/00m_ 0u/.V_.0V_V PL u/.v_ V R /F_ L 0uH/00m_ V_SUS_LKF L 0uH/00m_.0V_V PL 0u/.V_ u/0v_ 0u/.V_ u/.v_ Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev Panther Point / ate: Friday, November, 0 Sheet of

12 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Friday, November, 0 ZQT/ZQS IEX PEK-M (GN) PH(LG) U0H PNTHER POINT U0H PNTHER POINT VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L U0I PNTHER POINT U0I PNTHER POINT VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J

13 M 0 M M M M M M 0 M M M M M M M M M LK_SLK LK_ST M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q IMM0_S0 IMM0_S PM_EXTTS#0 SMR_VREF_Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q SMR_VREF_Q0 SMR_VREF_Q0_M M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LK0 [] M LK0# [] M LK [] M LK# [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M OT0 [] M OT [] M Q[:0] [] LK_SLK [,,,,] LK_ST [,,,,] R_RMRST# [,] SMR_VREF_Q0_M [] RMRST_NTRL_PH [,,] M QS#[:0] [] M QS[:0] [] 0.V_R_VTT [,,].VSUS [,,,,,0] SMR_VREF [,,] V [,,,,0,,,,,,,,,,,,,,,,,,,0,] SMR_VREF_IMM [].VSUS V 0.V_R_VTT SMR_VREF_IMM V.VSUS 0.V_R_VTT SMR_VREF_Q0 SMR_VREF.VSUS SMR_VREF_IMM V SMR_VREF_IMM.VSUS SMR_VREF SMR_VREF_Q0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 Friday, November, 0 ZQT/ZQS Place these aps near So-imm0.. M solution change to K/F_ change to K/F_ M solution REV: dd.u/.v_.u/.v_ R *M@0_ R *M@0_ 0.u/V_ 0.u/V_ R0 0K_ R0 0K_ 0 0.u/V_ 0 0.u/V_.u/.V_.u/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 u/.v_ u/.v_ 0.u/V_ 0.u/V_ 0.u/V_ 0.u/V_ R K/F_ R K/F_ 0.u/.V_ 0.u/.V_.u/.V_.u/.V_ R *0_ R *0_ 0p/0V_ 0p/0V_.u/.V_.u/.V_ 0u/.V_ 0u/.V_.u/.V_.u/.V_ R K/F_ R K/F_ 0u/.V_ 0u/.V_ R K/F_ R K/F_ 0.u/V_ 0.u/V_ 0u/.V_ 0u/.V_ 0.u/V_ 0.u/V_ 0u/.V_ 0u/.V_ R0 *0K_ R0 *0K_ 0u/.V_ 0u/.V_ R *0_ R *0_ 0.u/V_ 0.u/V_ R0 0K_ R0 0K_ u/.v_ u/.v_ 0u/.V_ 0u/.V_ u/.v_ u/.v_ *0u/V_ *0u/V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 0.u/V_ 0.u/V_ 00 0p/0V_ 00 0p/0V_ u/.v_ u/.v_ R K/F_ R K/F_

14 M 0 M M M M M M 0 M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q IMM_S0 IMM_S PM_EXTTS# M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q SMR_VREF_Q SMR_VREF_Q_M SMR_VREF_Q M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LK0 [] M LK0# [] M LK [] M LK# [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M OT0 [] M OT [] M Q[:0] [] LK_SLK [,,,,] LK_ST [,,,,] R_RMRST# [,] M QS#[:0] [] M QS[:0] [] 0.V_R_VTT [,,] SMR_VREF_IMM [].VSUS [,,,,,0] SMR_VREF [,,] V [,,,,0,,,,,,,,,,,,,,,,,,,0,] SMR_VREF_Q_M [] RMRST_NTRL_PH [,,].VSUS V 0.V_R_VTT V SMR_VREF_IMM V.VSUS 0.V_R_VTT SMR_VREF_Q SMR_VREF_IMM V SMR_VREF.VSUS SMR_VREF_Q Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Friday, November, 0 ZQT/ZQS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM- Friday, November, 0 ZQT/ZQS Place these aps near So-imm.. M solution M solution change to K/F_ REV: dd 0 0.u/V_ 0 0.u/V_ u/.v_ u/.v_ 0 0u/.V_ 0 0u/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 0.u/V_ 0.u/V_ R *0_ R *0_ R 0K_ R 0K_ 0p/0V_ 0p/0V_ 0 u/.v_ 0 u/.v_ 0u/.V_ 0u/.V_ u/.v_ u/.v_ 0.u/V_ 0.u/V_.u/.V_.u/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R 0K_ R 0K_.u/.V_.u/.V_ 0u/.V_ 0u/.V_ 0 0u/V_ 0 0u/V_ 0.u/V_ 0.u/V_ R *0K_ R *0K_ R0 *M@0_ R0 *M@0_ 00 0.u/V_ 00 0.u/V_ R K/F_ R K/F_ 0.u/.V_ 0.u/.V_ R K/F_ R K/F_.u/.V_.u/.V_ u/.v_ u/.v_ 0 0.u/V_ 0 0.u/V_ 0u/.V_ 0u/.V_ 0 0u/.V_ 0 0u/.V_.u/.V_.u/.V_ 0.u/V_ 0.u/V_ 0 0u/.V_ 0 0u/.V_ 0.u/V_ 0.u/V_.u/.V_.u/.V_

15 .0V_GFX To be placed no further from the GPU than bewteen the PS and GPU PLE UNER G PLE NER LLS.0V_GFX To be placed no further from the GPU than bewteen the PS and GPU PLE UNER G PLE NER LLS 0 EV@u/.V_ EV@u/.V_ EV@0u/.V_ EV@0u/.V_ EV@.u/.V_ EV@u/.V_ EV@u/.V_ EV@u/.V_ EV@u/.V_ EV@0u/.V_ EV@0u/.V_ EV@.u/.V_ EV@u/.V_ EV@u/.V_ U G PEG_TX IV@:iGPU PEX_IOV_ PEX_RX0 N PEG_TX [] G PEG_TX# PEX_IOV_ PEX_RX0_N M PEG_TX# [] PEG_TX EV@:dGPU G PEX_IOV_ PEX_RX N PEG_TX [] G PEG_TX# PEX_IOV_ PEX_RX_N M PEG_TX# [] H PEG_TX PEG_TX [] OP@:Optimus PEX_IOV_ PEX_RX P H PEG_TX# PEX_IOV_ PEX_RX_N P PEG_TX# [] PEG_TX PEG_TX [] O@:iscrete only V_S PEX_RX N G PEG_TX# V_GFX PEX_IOVQ_ PEX_RX_N M PEG_TX# [] G PEG_TX PEX_IOVQ_ PEX_RX N PEG_TX [] SP@:Special G PEG_TX# PEX_RX_N M PEG_TX# [] R 0K/F_ PEX_IOVQ_ G PEG_TX0 PEX_IOVQ_ PEX_RX P PEG_TX0 [] G PEG_TX#0 PEX_RX_N P PEG_TX#0 [] R PEX_IOVQ_ LK_PEG_REQ# [] H PEG_TX PEG_TX [] 0/ modify PEX_RX N EV@0K/F_ PEX_IOVQ_ H PEG_TX# PEX_IOVQ_ PEX_RX_N M PEG_TX# [] H PEG_TX PEX_IOVQ_ PEX_RX N0 PEG_TX [] H PEG_TX# PEX_RX_N M0 PEG_TX# [] [0,] GPU_PWROK R *EV@0K/F_ PEX_IOVQ_ Q J PEG_TX PEX_RX P0 PEG_TX [] EV@TEU PEX_IOVQ_0 K PEG_TX# PEX_IOVQ_ PEX_RX_N P PEG_TX# [] L PEG_TX PEX_IOVQ_ PEX_RX N PEG_TX [] M PEG_TX# PEG_TX# [] PEX_LKREQ# PEX_IOVQ_ PEX_RX_N M Q N PEG_TX PEX_IOVQ_ PEX_RX0 N PEG_TX [] PEG_TX# PEX_RX0_N M PEG_TX# [] PEG_TX PEX_RX P PEG_TX [] EV@PTTT PEG_TX# V_GFX PEX_RX_N P PEG_TX# [] PEG_TX PEG_TX [] 0/ chnage type 0/ modify PEX_RX N PEG_TX# PEX_RX_N M PEG_TX# [] PEG_TX PEX_RX N PEG_TX [] PEG_TX# PEX_RX_N M PEG_TX# [] PEG_TX PEX_RX P PEG_TX [] PEG_TX# PEX_RX_N P PEG_TX# [] 0 PEG_TX0 PEX_RX N PEG_TX0 [] EV@0.u/0V_ PEG_TX#0 PEX_RX_N M PEG_TX#0 [] [,,,] PLTRST# R_PEG_RX PEG_RX [] PEGX_RST# PEX_TX0 K EV@0.u/.V_ R_PEG_RX# PEX_TX0_N J EV@0.u/.V_ PEG_RX# [] [] GPU_HOL_RST# R_PEG_RX PEX_TX H 0 EV@0.u/.V_ PEG_RX [] R_PEG_RX# PEG_RX# [] R PEX_TX_N G EV@0.u/.V_ R_PEG_RX EV@0.u/.V_ PEG_RX [] U PEX_TX K R_PEG_RX# PEG_RX# [] EV@00K_ PEX_TX_N J 0 EV@0.u/.V_ R_PEG_RX PEG_RX [] EV@MVHG0FTG PEX_TX L 0 EV@0.u/.V_ R_PEG_RX# PEX_TX_N K EV@0.u/.V_ PEG_RX# [] R_PEG_RX PEX_TX K EV@0.u/.V_ PEG_RX [] R_PEG_RX# EV@0.u/.V_ PEX_TX_N J PEG_RX# [] R_PEG_RX0 PEX_TX H 0 EV@0.u/.V_ PEG_RX0 [] R_PEG_RX#0 EV@0.u/.V_ N_ PEX_TX_N G PEG_RX#0 [] J R_PEG_RX PEX_TX K 00 EV@0.u/.V_ N_ PEG_RX [] J R_PEG_RX# 0 EV@0.u/.V_ N_ PEX_TX_N J PEG_RX# [] J R_PEG_RX PEX_TX L EV@0.u/.V_ N_ PEG_RX [] L R_PEG_RX# EV@0.u/.V_ N_ PEX_TX_N K PEG_RX# [] R_PEG_RX PEX_TX K0 EV@0.u/.V_ N_ PEG_RX [] R_PEG_RX# EV@0.u/.V_ N_ PEX_TX_N J0 PEG_RX# [] 0 R_PEG_RX PEX_TX H0 EV@0.u/.V_ N_ PEG_RX [] R_PEG_RX# EV@0.u/.V_ N_ PEX_TX_N G0 PEG_RX# [] R_PEG_RX N_0 PEX_TX0 K EV@0.u/.V_ PEG_RX [] H R_PEG_RX# EV@0.u/.V_ N_ PEX_TX0_N J PEG_RX# [] T R_PEG_RX N_ PEX_TX L EV@0.u/.V_ PEG_RX [] V R_PEG_RX# N_ PEX_TX_N K EV@0.u/.V_ PEG_RX# [] R_PEG_RX PEX_TX K EV@0.u/.V_ PEG_RX [] R_PEG_RX# PEX_TX_N J EV@0.u/.V_ PEG_RX# [] R_PEG_RX PEX_TX H EV@0.u/.V_ PEG_RX [] R_PEG_RX# PEX_TX_N G EV@0.u/.V_ PEG_RX# [] R_PEG_RX EV@0.u/.V_ PEX_TX K PEG_RX [] R_PEG_RX# PEX_TX_N J EV@0.u/.V_ PEG_RX# [] R_PEG_RX0 EV@0.u/.V_ PEX_TX L PEG_RX0 [] R_PEG_RX#0 PEX_TX_N K EV@0.u/.V_ PEG_RX#0 [] PEX_REFLK PEX_REFLK_N L K LK_PIE_VG LK_PIE_VG# LK_PIE_VG [] LK_PIE_VG# [] V_GFX J K L M V_ V_ V_ V_ PEX_TSTLK_OUT PEX_TSTLK_OUT_N PEX_WKE PEX_RST_N PEX_LKREQ_N J K J J K PEX_TSTLK PEX_TSTLK# PEGX_RST# PEX_LKREQ# R R0 *EV@00_ EV@K_ TP 0/ change to k V_GFX V_GFX PLE LOSE TO G EV@.u/.V_ EV@u/0V_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ EV@0.u/0V_ PLE LOSE TO GPU LLS EV@Nx NP PEX_TERMP TESTMOE PEX_PLLV PEX_PLL_HV PEX_SV_V.V_UX_N V_SENSE GN_SENSE P PEX_TERMP TESTMOE K G PEX_PLLV H G P L L R R R L EV@.K/F_ EV@0K/F_ GSS@0_ GL@00-0 EV@.u/.V_ EV@u/.V_ EV@0.u/0V_ EV@0.u/0V_ EV@.u/.V_ EV@.u/.V_ V_GFX.0V_GFX PLE NER G LOSE TO PS PLE UNER G PLE NER LLS PLE NER G GPUV_SENSE [] GPUVSS_SENSE [] [,,,0].0V_GFX [,,,,0] V_GFX [,,,,0,,,0,,,,,,] V_S [,,,,0,,,,,,,,,,,,,,,,,,,,0,] V I/O.V PEX_RST Trise >= us Tfail <=00nS Quanta omputer Inc. PROJET : ZQT/ZQS Size ocument Number Rev GPU / (PEG) ate: Friday, November, 0 Sheet of