K72JK Schematic R2.0

Transcript

1 PGE ontent lock iagram System Setting PU()_MI,PEG,FI,LK,MIS PU()_R PU()_FG,RSV, PU()_PWR PU()_XP R SOIMM_0 R SOIMM_ R _Q VOLTGE 9 VI controller 0 PH_IEX()ST,IH,RT,LP PH_IEX()_PIE,LK,SM,PEG PH_IEX()_FI,MI,SYS PWR PH_IEX()_P,LVS,RT PH_IEX()_PI,NVRM,US PH_IEX()PU,GPIO,MIS PH_IEX()_POWER, PH_IEX()_POWER, PH_SPI ROM,OTH 9 LK_IS9LPR 0 E_IT(/) E_IT(/)K, TP RST_Reset ircuit HNKSVILLE LN_RJ OEL9 U_mp & Jack 0 _R _R _in ardreader _Neward UG_ebug RT_L Panel RT_Sub TV_HMI 0 FN_Fan & Sensor X_H & O US_US Port * MINIR(WLN) LE_Indicator SG_ischarge 0 _ & T onn. T_luetooth ME_onn & Skew Hole PH_XP, ONFI 0 VG_M9 Main () VG_M9 Main () VG_M9 MEM HNNEL VG_M9 MEM HNNEL VG_M9 Power () VG_M9 Power () VG_M9 THERML/Memory SS VG_M9 Straps VG_POWER_VG_ORE & RM 9 VG_POWER_VG_+.VS_+.VS PW_VORE(MX0) PW_SYSTEM(MX00) PW_I/O_VTT_PU&+.VM PW_I/O_R & VTT& +.VS PW_I/O_VM & ME_+VM_PWEG PW_+VGFX_ORE(MX0) PW_HRGER(MX0) PW_ETET PW_LO SWITH PW_PROTET PW_SIGNL PW_FLOWHRT HMI RT PGE PGE L Panel PGE Touchpad Keyboard INT. MI Jack PGE PGE PGE PGE KJK Schematic R.0 PRKXT E ITE IT0 ebug onn. zalia odec IT 9H lock Generator & TT. onn. PGE 0 PGE 0 PGE PGE PGE 9 st H PGE VI controller PWM Fan PU rrandale PH HM O PGE PGE PGE 0 ischarge ircuit Reset ircuit PGE 9 PGE PGE 0 PGE 0 PGE nd H PGE R SOIMM GigaLN R PGE PGE Miniard WiFi US Port() US Port() US Port() US Port() ardreader lcor MOS amera luetooth RJ PGE PGE PGE PGE PGE PGE PGE PGE PGE SUSTeK OMPUTER IN. N ustom Power VORE System.VS &.0VS R & VTT +.VS harger etect Load Switch Power Protect Page 0 Page Page Page Page Page Page 90 Page 9 Page 9 Friday, January, 00 ate: Sheet of 99.0

2 E IT E GPIO Use s Signal Name GP0 GP GP GP GP GP GP GP O O O O PWR_LE# HG_LE# HG_FULL_LE# L_L_PWM FN0_PWM GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GPE0 GPE GPE GPE GPE GPE GPE GPE GPF0 GPF GPF GPF GPF GPF GPF GPF GPG0 GPG GPG O O IO IO O O O IO IO O I O I I I I I O O O I O O O O I I O I I IO O I O TSEL_0 TSEL_ ME PRESENT_E SM0_LK SM0_T 0GTE RIN# PM_RSMRST# SM_LK SM_T PM_PWRTN# _IN_O# OP_S# T_IN_O# PWRLIMIT# PM_SUS# UF_PLT_RST# EXT_SI# EXT_SMI# L_KOFF# FN0_TH S_#_E VSUS_ON PWR_SW# LI_SW# TP_LK TP_T THRO_PU PH_SPI_OV ME_SusPwrnck_E PM_SUS# OMV_TL0 GPG O OMV_TL GPH0 IO PM_LKRUN# GPH O GPH O HG_EN GPH O SUS_E# GPH O SUS_E# GPH O NUM_LE# GPH O P_LE# GPI0 GPI I SUS_PWRG GPI I LL_SYSTEM_PWRG GPI I VRM_PWRG GPI I PH_TEMP_LERT# GPI I GPI I GPI I GPJ0 O PU_VRON GPJ O PM_PWROK GPJ O VSET_E GPJ O ISET_E GPJ O GPJ E GPIO Use s Signal Name GPIO0 GPIO I I GPIO GPIO GPIO GPIO GPIO I I O GPIO GPIO GPIO9 GPIO0 GPIO GPIO O GPIO GPIO O GPIO GPIO GPIO GPIO GPIO9 GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO9 GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO SM_US RESS : evice Identification PIE PIE Minicard WLN PIE PIE PIE PIE GLN PIE PIE ST 0 ST H () ST ST O ST ST H () ST KJ 0 US port US port US port ( / ) US port ( / ) 9 0 Miniard ( Full ) Miniard ( Half ) amera ard Reader luetooth SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 99.0

3 FI disable: (For discrete graphic). N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XGSENSE,VSS_XGSENSE. Pulldown to via K ± % resistor: FI_FSYN[0:],FI_LSYN[0:],FI_INT,GFX_IMON ~mw power saving.(g R0. P.0). onnected to : VXG,. an be connected to directly: PLL_REF_LK,PLL_REF_LK#. onnect to +V.0S rail: VFIPLL FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN FI_INT G R. P.: *FI_FSYN[0],FI_FSYN[], FI_LSYN[0], FI_LSYN[] can be ganged together with one resistor. *On the other hand,fi_fsyn[0], FI_FSYN[], FI_LSYN[0], FI_LSYN[], and FI_INT signals on PH side can be left as no connect without any power or functional impact SL00 SL00 SL00 RN00 KOhm RN00 KOhm 0, 0 PWRLIMIT# THRO_PU For E request, to read PEI via E. onnection: R0.>Q00.>U RV0 G S Q00 N00ETG, H_PEI H_THRMTRIP# H_PURST# PM_SYN# H_PUPWRG H_RM_PWRG H_VTTPWRG +VTT_PU H_PWRG_XP +VTT_PU T00 R00 % R00 % R00 9.9Ohm % R00 9.9Ohm % THRO_PU SL00 R0 T00 R00 9.9Ohm % 00 T00 R0 SL0 SL0 SL0 SL0 OHM U00 H_OMP T OMP H_OMP T OMP H_OMP G OMP H_OMP0 T OMP0 TP_SKTO# H SKTO# H_TERR# K TERR# H_PEI_ISO T PEI H_PROHOT_S# N PROHOT# K THERMTRIP# P RESET_OS# PM_SYN#_R L PM_SYN VPWRGOO R N VPWRGOO_ VPWRGOO_0_R N VPWRGOO_0 VPWRGOO_R K SM_RMPWROK M VTTPWRGOO M TPPWRGOO MIS THERML LOKS PWR MNGEMENT R MIS JTG & PM LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R0 T0 E F L M N N P T P N P T T9 R R9 P9 N J K K J J H K H LKREF SL09 LKREF# 00 SL00 00 SM_ROMP0 R0 0 % SM_ROMP R0.9Ohm % SM_ROMP R0 % PM_EXTTS# RN00 0KOHM 0KOHM RN00 XP_TI_R XP_TO_R XP_TI_M XP_TO_M H_R#_R R0 XP_OS0 XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS LK_PU_P_PH LK_PU_N_PH LK_ITP_LK LK_ITP_LK# LK_MI_PH LK_MI#_PH M_RMRST#, PM_EXTTS#0, +VTT_PU XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_RESET#,, XP_OS[:0],,0,,,,,,0 UF_PLT_RST# R0.KOhm % PLT_RST#_R L RSTIN# MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN U00 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] 9 FI_TX#[] FI_TX#[] G FI_TX#[] E9 FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G9 FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] MI Intel(R) FI PI EXPRESS GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[9] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[9] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[9] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[9] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] SOKET99 K J J G G F F E 0 J H H F G E F F L M M M0 L K M9 J K9 H0 H9 F9 E 9 L M M L0 M K M H K G0 G9 F E PEG_IROMP_R EXP_RIS PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN9 PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP9 PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X00 PIEN_TXN X009 PIEN_TXN9 X00 PIEN_TXN0 X0 PIEN_TXN X0 PIEN_TXN X0 PIEN_TXN X0 PIEN_TXN X0 PIEN_TXN X0 PIEN_TXP0 X0 PIEN_TXP X0 PIEN_TXP X09 PIEN_TXP X00 PIEN_TXP X0 PIEN_TXP X0 PIEN_TXP X0 PIEN_TXP X0 PIEN_TXP X0 PIEN_TXP9 X0 PIEN_TXP0 X0 PIEN_TXP X0 PIEN_TXP X09 PIEN_TXP X00 PIEN_TXP X0 PIEN_TXP X0 R00 9.9Ohm % R00 % PIEN_RXN[:0] 0 PIEN_RXP[:0] 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V GFX_VG_RXN0 GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN9 GFX_VG_RXN0 GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXN GFX_VG_RXP0 GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP9 GFX_VG_RXP0 GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP GFX_VG_RXP VPWRGOO_R GFX_VG_RXN[:0] 0 GFX_VG_RXP[:0] 0 R09 % LK_PU_P_PH H_VTTPWRG VPWRGOO_0_R VPWRGOO R PLT_RST#_R XP_TRST# +.V R00.KOhm % R0.0KOHM % SOKET99 XP_TLK XP_TMS XP_TI_R XP_TO_R XP_TI_M XP_TO_M For PU oundary Scan T00 T00 T00 T00 T00 T009 T00 T0 T0 T0 T0 T0 H_PURST# XP_TMS XP_TI_R XP_PREQ# XP_TO XP_TLK XP_TRST# JTG MPPING XP_TI_R XP_TO_M XP_TI_M XP_TO_R G R. P.09: *On larksfield rpg only designs, VPWRGOO_ on the larksfield processor can be left as No onnect. 00 R0 R0 R0 R0 R0 R0 R0 00 R00 SL0 R0 00 +VTT_PU SUSTeK OMPUTER IN. N XP_TI XP_TO ustom OHM Ohm Ohm Ohm Ohm Ohm Ohm SL00 SL009 Friday, ecember, 009 ate: Sheet of 99.0

4 U00 U00 M Q[:0] M S0 M S M S M S# M RS# M WE# M Q0 0 M Q 0 M Q M Q M Q 0 M Q 0 M Q E0 M Q M Q M Q9 F0 M Q0 E M Q F M Q E9 M Q M Q E M Q M Q H0 M Q G M Q K M Q9 J M Q0 G M Q G0 M Q J M Q J0 M Q L M Q M M Q M M Q L9 M Q L M Q9 K M Q0 N M Q P9 M Q H M Q F M Q K M Q K M Q F M Q G M Q J M Q9 J M Q0 J0 M Q J9 M Q L0 M Q K M Q K M Q L M Q K M Q L M Q N M Q9M0 M Q0R M Q L M Q M9 M Q N9 M Q T M Q P M QM M QN M QM M Q9 T M Q0 T M Q L M QR M Q P U E E9 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[9] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F9 9 H M G M N0 N M M0 M M M M M M M M M M M M M M 9 F J9 M QS#0 M QS# M QS# N9 M QS# H M QS# K9 M QS# P M QS# T M QS# F9 H9 M9 H K0 N R Y W V 9 V T Y9 U T U G T V9 M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_S#0 M_S# M_OT0 M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] M Q[:0] M S0 M S M S M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T9 T P9 R0 T0 W R Y S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[9] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[9] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W9 M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M 9 M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_S# M_S# M_OT M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] SOKET99 SOKET99 SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 99.0

5 0 mil IMM0_VREF_Q IMM_VREF_Q T0 T0 T0 T0 T09 T0 T0 T0 T0 T00 T0 T0 T0 T0 T09 T0 T00 T09 T0 R00 R00 R.,item L T0 T00 T0 T0 T0 T0 U00E P RSV L RSV L RSV L RSV J RSV G9 RSV M RSV L RSV J S_IMM_VREFQ H S_IMM_VREFQ G RSV G RSV E RSV E0 RSV FG0 M0 FG FG[0] M FG FG[] P FG FG[] L FG FG[] L0 FG FG[] M FG FG[] N9 FG FG[] M FG FG[] K FG9 FG[] K FG0 FG[9] K FG FG[0] J FG FG[] N0 FG FG[] N FG FG[] J FG FG[] J9 FG FG[] J0 FG FG[] K0 FG FG[] H RSV_TP_ 9 RSV 9 RSV H_RSV_R 0 H_RSV_R RSV 0 RSV U9 RSV9 T9 RSV0 9 RSV 9 RSV RSV_NTF_ RSV_NTF_ J9 RSV J RSV RSV_NTF_ RSV_NTF_9 RSV_NTF_0 RSV_NTF_ RESERVE RSV RSV RSV RSV RSV RSV_NTF_ RSV RSV9 RSV_NTF_0 RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV9 RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_9 RSV_TP_0 KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_9 RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_9 RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS J J H K L R J J P T T R L L9 P0 P L T T P R T T P R R E F J H R R9 G E V V N W W N E 9 P T00 T00 T00 T00 T00 T00 T009 T00 T00 RSV_R RSV_R R00 R00 R.,item L U00H T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS9 R VSS0 R VSS R9 VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS9 P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M9 VSS M VSS M VSS9 M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS9 L0 VSS0 L VSS L VSS L9 VSS L VSS L VSS K9 VSS K VSS K VSS K0 VSS9 K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS9 H VSS0 H VSS H VSS H VSS H VSS H0 VSS H9 VSS H VSS H VSS H VSS9 H0 VSS0 H VSS H VSS H9 VSS H VSS H VSS G0 VSS F VSS F VSS F VSS9 E VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS90 VSS9 VSS9 VSS9 VSS9 VSS9 VSS9 VSS9 VSS9 VSS99 VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS09 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 VSS0 E E E E E0 E9 E E E E Y Y Y W W W W W W0 W9 W W W W V0 U U U T T T T T T0 T9 T T T T R0 P P P N N N N N N0 N9 N N N N M0 L L L9 L L L K K K0 U00I K VSS K9 VSS K VSS K VSS J VSS J0 VSS J VSS J9 VSS H VSS9 H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS9 H VSS0 H VSS G VSS G VSS G0 VSS G9 VSS G VSS G VSS F0 VSS F VSS9 F VSS90 F VSS9 F9 VSS9 F VSS9 E VSS9 E VSS9 E9 VSS9 E VSS9 E VSS9 E VSS99 E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 9 VSS0 VSS09 VSS0 VSS VSS 9 VSS VSS VSS VSS 0 VSS 9 VSS VSS9 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS9 9 VSS0 VSS VSS 9 VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T TP_MP_VSS_NTF T TP_MP_VSS_NTF R TP_MP_VSS_NTF TP_MP_VSS_NTF T0 T0 T0 T0 SOKET99 SOKET99 SOKET99 FG strapping information: FG[:0]: PI Express Port ifurcation:(larksfield Only) = x PEG (efault) 0 = x PEG FG[]: PIE Static Numbering Lane Reversal.(uburndale Only) :Normal Operation (efault) 0:Lane Numbers Reversed > 0, >,... FG[]: Embedded isplayport etection.(uburndale Only) :isabled No Physical isplay Port attached to Embedded isplayport 0:Enabled n external isplay Port device is connected to the Embedded isplay Port Intel sighting #: 00(9) To drive a value of zero on FG[0] pin use a 0 Ohm pull down resistor to Vss. FG0 R0.0KOHM % FG R0.0KOHM % ep=.k P FG[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples prees) onnect to with.0k Ohm/% resistor For a common motherboard design (for U and F), the pulldown resistor should be used. oes not impact U functionality. Unmount if Intel has fixed this issue. FG R0.0KOHM % FG R0.0KOHM % Note: (uburndale)hardware Straps are sampled on the asserting edge of VPWRGOO_0 and VPWRGOO_ and latched inside the processor. Note: (larksfield)hardware Straps are sampled after RSTIN# deassertion. Unmount R00& R00 & R00 & R00 for Intel R sugesstion. SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 99.0

6 SL00 +VGFX_ORE U00G +VORE U00F G V G V G V G V G V G0 V G9 V G V G V9 G V0 F V F V F V F V F V F0 V F9 V F V F V9 F V0 V V V V V 0 V 9 V V V9 V0 V V V V V 0 V 9 V V V9 V0 V V V V V 0 V 9 V V V9 V0 Y V Y V Y V Y V Y V Y0 V Y9 V Y V Y V9 Y V0 V V V V V V V V V V V0 V V9 V V V V V9 V V0 U V U V U V U V U V U0 V U9 V U V U V9 U V0 R V R V R V R V R V R0 V R9 V R V R V9 R V90 P V9 P V9 P V9 P V9 P V9 P0 V9 P9 V9 P V9 P V99 P V00 PU ORE SUPPLY POWER SENSE LINES PU VIS.V RIL POWER VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_9 VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_9 VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_9 VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_9 VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE V_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M G N J J PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI PU_VI H_VTTVI VSENSE_R VSSSENSE_R 00 0UF/.V 0 0UF/.V 0 UF/.V VTT_SENSE TP_VSS_SENSE_VTT I_MON 0 T0 T0 00 0UF/.V 0 0UF/.V +VORE 0 UF/.V R00 0 % R00 0 % 00 0UF/.V 0 0UF/.V +VTT_PU T0 PM_PSI# 0 PU_VI[0:] 9 PM_PRSLPVR 0 VSENSE 0 VSSSENSE UF/.V 0 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 09 0UF/.V +VTT_PU +VORE +VORE +VTT_PU 0 UF/.V +VTT_PU 0 UF/.V Processor ecoupling 0 UF/.V 09 0UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V T00 ecoupling guide from Intel 00 0 UF/.V 0 UF/.V 0 0UF/.V 09 UF/.V T T9 T T R R9 R R P P9 P P N N9 N N M M9 M M L L9 L L K K9 K K J J9 J J H H9 H H J J H K J J J H G G G F E E 0 UF/.V 0 0UF/.V VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG9 VXG0 VXG VXG VXG VXG VXG VXG VTT_ VTT_ VTT_ VTT_ VTT_9 VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ SOKET99 0 UF/.V 0 0UF/.V FI PEG & MI GRPHIS POWER 0 UF/.V 0 0UF/.V SENSE LINES GRPHIS VIs R.V RILS.V.V 09 UF/.V 0 0UF/.V VXG_SENSE VSSXG_SENSE GFX_VI[0] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ9 VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT0_9 VTT0_0 VTT0_ VTT0_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL 00 UF/.V 0 0UF/.V R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H9 L L M 0 UF/.V 0 0UF/.V GFX_VRON_EN GFXVR_PRSLPVR GVR_PWR_MON 0 UF/.V 09 0UF/.V.KOHM RN00.KOHM RN00 R0 KOhm UF/0V 0 UF/0V 0 UF/0V 0 UF/0V 0 UF/0V 0 0 0UF/.V 0 UF/.V 0 UF/0V 0 UF/.V 00 0UF/.V G R.,P xbuck Stuffing option +VTT_PU +VTT_PU 0 0UF/.V 0 UF/.V 09 UF/0V 0 UF/.V 0 0UF/.V UF/.V 0 UF/.V 0 0.UF/0V 0 UF/.V 0 0UF/.V +.V 0.UF/.V 0 UF/.V 0 0UF/.V E00 0UF/V ESR=mOhm/Ir= +.VS 0 UF/.V 0 0UF/.V Schematic R0.9: Schematic hecklist R0.: SOKET99 VORE uf * pcs 0uF * pcs 0uF* pcs( no stuff). VORE uf * pcs 0uF * pcs 0uF* pcs( no stuff). SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 99.0

7 PU XP connector +VTT_PU J00 SIE SIE 0 0 FP_ON_0P /XP T00 T0 R009 /XP H_PWRG_XP () PUPWRG_XP XP_TRST# () H_PUPWRG, (9) T0 T0 R00 KOhm /XP T0 XP_PREQ# ( ) T0 XP_PRY# ( ) T0 HPM# T0 T0 HPM# HPM# HPM0# T0 T0 T09 T0 T09 T00 XP_RST#_R R00 KOhm /XP R0 /XP XP_TO XP_TI XP_TMS XP_TLK XP_RESET#,, H_PURST# SM_T_S,,9,,9, SM_LK_S,,9,,9, LK_ITP_LK# LK_ITP_LK () () () () () () () (0) () +VTT_PU UF_PLT_RST#,,0,,,,,,0 J00 FF path Put these test point near J00. Put it away from the FF path. XP_OS0 XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS PM_PWRTN#_R SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 99.0

8 ustom SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 99.0

9 Main oard SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet 9 of 99.0

10 Main oard SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet 0 of 99.0

11 Main oard SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet of 99.0

12 Main oard SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet of 99.0

13 Main oard SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet of 99.0

14 SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 99 Ryan_Wang.0

15 SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 99 Ryan_Wang.0

16 M M M M M M M M M M M M M M M M0 M QS M QS# M QS M QS M QS M QS# M QS M QS# M QS# M QS M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M 9 M M 0 M M M M M 0 M M M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q0 M Q M Q M Q0 M M Q M Q9 M Q M Q M Q M Q9 M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q9 M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M S# M_LK_R#0 M S M S0 M S M M[:0] M QS#[:0] M QS[:0] SM_T_S,,9,,9, SM_LK_S,,9,,9, M WE# PM_EXTTS#0, M_S# M RS# M_S#0 M_OT0 M_OT M_RMRST#, +VS +.V +0.VS M_VREF_IMM0 M_VREFQ_IMM0 +0.VS +.V +.V ate: Sheet of ustom Friday, January 9, 00 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, January 9, 00 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, January 9, 00 SUSTeK OMPUTER IN. N.0 99 SMus Slave ddress: 0H Layout Note: Place these caps near SO IMM 0 0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 09 0UF/.V 09 0UF/.V.UF/0V.UF/0V 0.UF/V 0.UF/V /P 0 /# S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 QS#0 0 QS# QS# QS# QS# QS# QS# 9 QS# QS0 QS 9 QS QS QS QS QS QS J0 R_IMM_0P R IMM 0P 0.mm ST.H G000 J0 R_IMM_0P R IMM 0P 0.mm ST.H G UF/V 0 0.UF/V.UF/0V.UF/0V EVENT# N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 9 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VSP 99 VREF VREFQ VSS9 VSS 0 VSS 9 VSS VSS 9 VSS 9 VSS0 90 VSS VSS9 9 VSS VSS VSS 9 VSS VSS VSS VSS VSS VSS0 VSS 9 VSS9 VSS VSS VSS VSS 0 VSS VSS VSS 9 VSS VSS0 VSS VSS9 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS9 VSS 9 VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P 0 0.UF/V 0 0.UF/V UF/0V UF/0V.UF/0V.UF/0V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V E0 0UF/V ESR=0mOhm/Ir=.9 E0 0UF/V ESR=0mOhm/Ir=.9 00 SL0 00 SL0 R0 R0 UF/0V UF/0V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 9 UF/0V 9 UF/0V 00 SL0 00 SL0 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V UF/0V UF/0V

17 M M M M M M M M M M M M0 M QS# M QS M QS M QS M QS M QS# M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M 9 M M 0 M M M M M 0 M M M M Q M Q M Q M Q M Q9 M Q M Q0 M Q M M Q M Q M Q M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q9 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M M M M M QS M QS M QS# M QS# M Q M Q0 M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q M WE# M_S# M_LK_R M_KE M_LK_R# M_LK_R M_KE M S# M RS# M_LK_R# M_S# M_OT M_OT SM_T_S,,9,,9, SM_LK_S,,9,,9, M M[:0] M QS#[:0] M QS[:0] M S M S0 M S M_RMRST#, M [:0] M Q[:0] PM_EXTTS#0, +0.VS +0.VS +.V +.V M_VREF_IMM M_VREFQ_IMM +.V +VS +VS ate: Sheet of ustom Friday, January, 00 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, January, 00 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, January, 00 SUSTeK OMPUTER IN. N.0 99 SMus Slave ddress: H Layout Note: Place these caps near SO IMM 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0.UF/V 0.UF/V.UF/0V.UF/0V UF/0V UF/0V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V UF/0V UF/0V 0 0.UF/V 0 0.UF/V E0 0UF/V ESR=0mOhm/Ir=.9 E0 0UF/V ESR=0mOhm/Ir=.9.UF/0V.UF/0V /P 0 /# S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 QS#0 0 QS# QS# QS# QS# QS# QS# 9 QS# QS0 QS 9 QS QS QS QS QS QS J0 R_IMM_0P R IMM 0P,.V,9.H,ST G00 J0 R_IMM_0P R IMM 0P,.V,9.H,ST G00.UF/0V.UF/0V 0 0.UF/V 0 0.UF/V 9 UF/0V 9 UF/0V UF/0V UF/0V 0.UF/V 0.UF/V 0UF/.V 0UF/.V 00 SL0 00 SL0 R0 R0 EVENT# N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 9 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VSP 99 VREF VREFQ VSS9 VSS 0 VSS 9 VSS VSS 9 VSS 9 VSS0 90 VSS VSS9 9 VSS VSS VSS 9 VSS VSS VSS VSS VSS VSS0 VSS 9 VSS9 VSS VSS VSS VSS 0 VSS VSS VSS 9 VSS VSS0 VSS VSS9 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS9 VSS 9 VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P 0UF/.V 0UF/.V 00 SL0 00 SL0 0 0UF/.V 0 0UF/.V 09 0UF/.V 09 0UF/.V

18 efault M R Vref Intel ocument Number: 00 +.V M_VREF_R R0 KOhm % For R_VREF command & address. M_VREF_IMM0 RN0 R0 KOhm % 0.UF/V M_VREF_IMM RN0 M_VREFQ_IMM0 M_VREFQ_IMM +.V RN0 R R RN0 KOhm % R 0 KOhm % 0.UF/V IMM0_VREF_Q R0 IMM_VREF_Q R0 M M: Processor Generated SOIMM VREFQ +V +.V R 0KOhm R 0KOhm 0 0.UF/0V 0 0.UF/0V U0 LMVIVR V+ + V SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 9.0

19 +VTT_PU_VO R90 KOhm PU_VI PU_VI PU_VI PU_VI PU_VI0 PU_VI PU_VI PU_VI RNX90 RNX90 RNX90 RNX90 RNX90 RNX90 RNX90 RNX90 VR_VI 0 VR_VI 0 VR_VI 0 VR_VI0 0 VR_VI 0 VR_VI 0 VR_VI 0 +VS,,,,9,,,,,9,,, +VS 90 0.UF/V /VI SM_T_S SM_LK_S FORE_OFF# T90 T90 PU_VI0 PU_VI PU_VI PU_VI PU_VI PU_VI T90 T90 T90 U90 VS SEL GPIO/VIOUT GPIO/VIIN GPIO GPIO/VIOUT VIIN0 GPIO/VIIN VIIN VIOUT0 VIIN VIOUT VIIN VIOUT VIIN VIOUT 9 VIIN VIOUT 0 0 GPIO0 VIOUT 9 GPIO VT GPIO SLOTO# S SL RSTOUT# ITR_L /VI SEL (ddress Select) 0: 'h : 'he T90 VR_VI PU_VI VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI R90 0KOhm /VI R909 0KOhm R90 0KOhm /VI R90 SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet 9 of 99.0

20 MOS Settings lear MOS Keep MOS TPM Settings lear ME RT Registers Keep ME RT Registers JRST00 Shunt Open (efault) JRST00 Shunt +RTT Open (efault) +V +V_RT 0 esign Guide R. Update: page9 0 PH_SPI_OV +RT_T RTRST# R delay should be ms~ms +V_RT T00 T0 H_SYN: Select VVRM.V or.v GPIO: This signal should be only asserted low through an external pulldown in manufacturing or debug environments ONLY. Without connecting GPIO, customers may not be able to override SPI flash contents. T00 G00000J ( Main ) R00 KOhm J00 TT_HOLER G00000 R00 MOhm JP00 R00 0KOhm % R00 MM_OPEN_MIL 0KOhm % T00 +VS T0 +V_RT 00 T0 00 T UF/0V T0 00 UF/0V 00 UF/0V JRST00 SGL_JUMP JRST00 SGL_JUMP G R00 00KOhm S R00 0KOhm Z_LK_U Z_SYN_U Internal P 0K +VS, Q00 N00ETG R09 KOhm 00 PF/0V 00 PF/0V Z_RST#_U Z_SIN0_U Z_SOUT_U +V_RT XRT R00: For Xtal measurement T0 Internal PU 0K PH_JTG_TK PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# SPI_LK SPI_S#0 SPI_S# +VM_SPI SPI_SI SPI_SO RX0 RX0 R00 R0 R0 R0 X00.Khz R00 RX0 R00 RX0 T00 R00 0MOhm 0KOhm T0 Ohm Ohm KOhm Ohm T0 T00 T00 Ohm X_RT X_RT RTRST# SRTRST# SM_INTRUER# Z_LK Z_SYN S_SPKR Z_RST# Z_SIN_M Z_SIN_VG Z_SOUT H_OK_EN# H_OK_RST# Ohm Ohm KOhm S_SPIS0# S_SPIS# 0 9 P 0 G0 F0 E F 9 H J0 M K K J J V Y Y V U00 RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO H_OK_EN#/GPIO H_OK_RST#/GPIO JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IEXPEKM RT IH SPI JTG LP ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# ST0GP/GPIO STGP/GPIO9 F 9 K K K K9 H H H9 H F F9 F F H H F F 9 F F T Y9 V PH_RQ#0 LP_RQ# ST0GP STGP ST_OMP T00 T00 +VS R0 +VTT_PH_VIO 0KOhm +VS LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, INT_SERIRQ 0 ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP ST_RXN ST_RXP ST_TXN ST_TXP ST_LE# R0 0KOhm +VSUS_ORG +VSUS_ORG +VSUS_ORG PH_JTG_TO +VTT_PH_VIO Strap information: H_SPKR: No reboot strap Low: isable. High:Enable R0 0 % R0 0 % R0 0KOhm R00.Ohm % +VS R0 0KOhm T09 R0 Ohm R0 0 % PH_JTG_TO PH_JTG_TMS PH_JTG_TI T0 T0 T009 PH_JTG_TMS PH_JTG_TI PH_JTG_RST# R0 Ohm R0 Ohm R0 Ohm H_OK_EN#:.Flash descriptor security: Sampled low: override Sampled high: in effect..gpio low on the rising edge of PWROK, Will also disable Intel ME. R0 R0 R % % % T0 PH_JTG_TK R0 Ohm SPI_MOSI: itpm strap. Mount R0: Enable Unmount R0: isable(default) SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of

21 U00 +VSUS_ORG PIE_RXN_M PIE_RXP_M PIE_TXN_ PIE_TXP_ PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_ PIE_TXP_ PIE_RXN_GLN PIE_RXP_GLN PIE_TXN_ PIE_TXP_ LK_PIE_M#_PH LK_PIE_M_PH LKREQ_M# LK_PIE_WLN#_PH LK_PIE_WLN_PH LKREQ_WLN# +VSUS_ORG +VSUS_ORG PIE_TXN_M PIE_TXP_M PIE_TXN_WLN PIE_TXP_WLN PIE_TXN_GLN PIE_TXP_GLN R R R R9 R R R R X0 X0 X0 X0 X X 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm LK_REQ0# LK_REQ# LK_REQ# LK_REQ# LK_REQ# LK_REQ# PEG LK_REQ# G0 PERN J0 PERP F9 PETN H9 PETP W0 PERN 0 PERP 0 PETN 0 PETP U0 PERN T0 PERP U PETN V PETP PERN PERP PETN E PETP F PERN H PERP G PETN J PETP PERN W PERP PETN PETP T PERN U PERP U PETN V PETP G PERN J PERP G PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P PIE* P9 PIELKRQ0#/GPIO M LKOUT_PIEN M LKOUT_PIEP U PIELKRQ#/GPIO M LKOUT_PIEN M LKOUT_PIEP N PIELKRQ#/GPIO0 H LKOUT_PIEN H LKOUT_PIEP PIELKRQ#/GPIO M LKOUT_PIEN M LKOUT_PIEP M9 PIELKRQ#/GPIO J0 LKOUT_PIEN J LKOUT_PIEP H PIELKRQ#/GPIO K LKOUT_PEG N K LKOUT_PEG P P PEG LKRQ#/GPIO IEXPEKM From LK UFFER lock Flex SMus ontroller PEG Link SMLERT#/GPIO SMLK SMT SML0LERT#/GPIO0 SML0LK SML0T SMLLERT#/GPIO SMLLK/GPIO SMLT/GPIO L_LK L_T L_RST# PEG LKRQ#/GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_9N LKIN_OT_9P LKIN_ST_N/KSS_N LKIN_ST_P/KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO LKOUTFLEX/GPIO 9 H J G M E0 G T T T9 H N N T T W P P F E H H P J H H F T P T N0 SML0LERT# SML0_LK SML0_T SMLLERT# LKREQ_PEG# X_IN X_OUT XLK_OMP LK_OUT0 LK_OUT LK_OUT LK_OUT R R T0 T T09 T0 T T T T T 90.9Ohm %.9Ohm % T0 T0 T0 T0 EXT_SI# 0 SL_ S_ SML_LK SML_T L_LK L_T L_RST# LK_PIE_PEG#_VG 0 LK_PIE_PEG_VG 0 LK_MI#_PH LK_MI_PH LK_MI# 9 LK_MI 9 LK_PH_LK# 9 LK_PH_LK 9 LK_OT9# 9 LK_OT9 9 LK_ST# 9 LK_ST 9 LK_IH 9 LK_PI_F +VTT_PH_ORG LK_R_REER_ EXT_SI# SML0LERT# SL_ S_ SML0_LK SML0_T SML_LK SML_T SMLLERT# G R.,page : The pullup resistor value for SML0T and SML0LK has been updated from. K ±% to. K ±% to support 00kHz bus speed PH LKREQ Setting: onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. LK_REQ# LK_REQ# LKREQ_PEG# R R0 R R R R R R R R R R9 RN0.KOHM RN0.KOHM 0KOhm.KOhm 0KOhm 0KOhm 0KOhm 0KOhm G., pg.9 +VS R MOhm X0 Mhz R0 XOUT 0 PF/0V R0: For Xtal measurement 0KOhm.KOhm.KOhm.KOhm 0KOhm 0 PF/0V SUSTeK OMPUTER IN. N ustom.0 Friday, ecember, 009 ate: Sheet of 99

22 MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP U00 MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP G MIRXP 0 MIRXP G0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT H J E F G W J +VS +VTT_PH_ORG R 0 KOhm SSPT +VS R0 9.9Ohm % MI_OMP R 0KOhm H F MI_ZOMP MI_IROMP MI FI FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN F H J G +VS +VSUS_ORG R R.KOhm KOhm,, XP_RESET# R SYS_RESET# T SYS_RESET# WKE# J PIE_WKE#, ES.0: Intel LN 0,, LL_SYSTEM_PWRG 0,,0 VRM_PWRG Enabled : LN_RST# connected to the same source as MEPWROK isabled : LN_RST# must be grounded isabled : SLP_LN#>N. P. isabled : VLN connected to. +VSUS_ORG R0 0KOhm ME_SusPwrnck 0 PM_PWROK_PH H_RM_PWRG ME_SusPwrnck PM_PWRTN#_R 0 PM_PWRTN# +VSUS_ORG T0 R ME PRESENT_PH R R R R SL0 R R SL KOhm 0KOhm.KOhm MPWROK_R UXPWROK_R PM_RSMRST#_PH PM_TLOW# PM_RI# T T0 T09 M K T0 0 9 M P P F SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# SUS_PWR_N_K/GPIO0 PWRTN# PRESENT/GPIO TLOW#/GPIO RI# System Power Management LKRUN#/GPIO SUS_STT#/GPIO SUSLK/GPIO SLP_S#/GPIO SLP_S# SLP_S# SLP_M# TP PMSYNH SLP_LN#/GPIO9 Y P F E H P K N J0 F PM_SUS_STT# SUS_LK SLP_S# SLP_S#_R SLP_S#_R SLP_M#_R PM_SLP_SW# ME_PM_SLP_LN#_PH SL0 SL0 T0 T0 T0 T0 T0 T0 PM_LKRUN# 0 PM_SUS# 0 PM_SUS# 0,, PM_SYN# IEXPEKM 09'MoW0: Optional if ME FW is Ignition FW 0KOhm R +VSUS_ORG 0KOhm R 0KOhm R Power failure solution (S0>G,S>G): PM_PWROK,PM_RSMRST#: previous platform solution. ME_PWROK,ME PRESENT: reserved for test. PM_PWROK_PH R9 0 0KOhm SS PM_PWROK 0 PM_RSMRST#_PH R0 0 0KOhm SS PM_RSMRST#,,0 ME PRESENT_PH R 0 0KOhm SSPT ME PRESENT 0 0 0: Prevent E drive hign, SUS_PWRG sink low in S>G. R9 T SUS_PWRG 0,, 0 T 0KOhm ustom SUSTeK OMPUTER IN. N Friday, ecember, 009 ate: Sheet of 99.0

23 U00 T T L_KLTEN L_V_EN SVO_TVLKINN SVO_TVLKINP J G +VS RN0 RN0 0KOHM 0KOHM L_TRL_LK L_TRL_T Y Y V L_KLTTL L LK L T L_TRL_LK L_TRL_T SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP J G F H P9 P LV_IG LV_VG SVO_TRLLK SVO_TRLT T T T T V V Y V 0 Y9 V P P Y T9 U T Y T U0 T LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T igital isplay Interface P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P G J U J G 0 0 W Y9 9 E V0 E0 0 F H RT_LUE RT_GREEN RT_RE P_TRLLK P_TRLT U0 U V V RT LK RT T P_UXN P_UXP P_HP T R KOhm % Y RT_HSYN Y RT_VSYN _IREF RT_IRTN IEXPEKM RT P_0N P_0P P_N P_P P_N P_P P_N P_P J0 G0 J G F H E SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 99.0

24 GNT0#,GNT#: oot IOS Strap. oot IOS Strap PI_GNT# PI_GNT0# PI_GNT# PI_GNT# PI_GNT0# LK_PI_F 0 LK_KPI_PH LK_EUG oot IOS Location 0 0 LP 0 PI 0 Reserved SPI (PH) Sampled on rising edge of PWROK. GNT#: swap override Strap/ Toplock swap override jumper Low=Enabled swap override/ Toplock swap override High=efault R0 KOhm R KOhm R KOhm 0 0PF/0V RX0 RX0 RX0 KJ 0 US port US port US port ( / ) US port ( / ) Miniard ( Full ) Miniard ( Half ) 9 amera 0 ard Reader luetooth T0 T0 T T T0 T0 T0 T0 Ohm Ohm Ohm PI_/E0# PI_/E# PI_/E# PI_/E# PI_INT# PI_INT# PI_INT# PI_INT# PI_INTE# PI_INTF# PI_INTG# PI_INTH# PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_PR PI_EVSEL# PI_FRME# PI_LOK# PI_STOP# PI_TRY# PI_PME# PLT_RST# U00E H0 0 N J 0 E H 9 E0 0 0 M M F M0 M J K F0 9 0 K M J K L F J0 G F 9 M 0 H J0 /E0# G /E# H /E# G /E# G PIRQ# H PIRQ# PIRQ# PIRQ# PI_REQ0# F PI_REQ# REQ0# GPU_SELET#_R REQ#/GPIO0 PI_REQ# REQ#/GPIO M REQ#/GPIO PI_GNT0# PI_GNT# PI_GNT# PI_GNT# F GNT0# K GNT#/GPIO F GNT#/GPIO H GNT#/GPIO PIRQE#/GPIO K PIRQF#/GPIO PIRQG#/GPIO PIRQH#/GPIO K PIRST# E SERR# E0 PERR# IRY# H PR F EVSEL# FRME# 9 M PLOK# STOP# TRY# PME# PLTRST# N LK_PI_F_R LKOUT_PI0 P LK_KPI_PH_R LKOUT_PI P LK_EUG_R LKOUT_PI P LKOUT_PI P LKOUT_PI IEXPEKM PI NVRM US NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q9/NV_IO9 NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP9N USP9P USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0#/GPIO9 O#/GPIO0 O#/GPIO O#/GPIO O#/GPIO O#/GPIO9 O#/GPIO0 O#/GPIO Y9 P V9 G P P T T9 V E J J G Y U V Y Y V F H J N0 P0 J0 L0 F0 G0 0 0 M N H J E F G H L M N J F L E G F T USRIS_PN US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN9 US_PP9 US_PN US_PP R.,item L0 US_PN US_PP R.Ohm % PI_INTG# PI_INT# PI_INT# PI_STOP# PI_PERR# PI_LOK# PI_EVSEL# PI_SERR# PI_INTE# PI_IRY# PI_INT# GPU_SELET#_R RN0 PI_REQ0# PI_INT# PI_INTF# PI_REQ# PI_REQ# PI_FRME# PI_TRY# PI_INTH# Place within 00 mils of PH 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM 0KOHM +VSUS_ORG +VS PLT_RST# U0 V +V Y NSZ0PX_NL R UF_PLT_RST#,,0,,,,,,0 ustom SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 99.0

25 U00F 0 T9 T90 T9 T9 EXT_SMI# T9 PH_GPIO0_R OKING_ET# OKING_UNOK_UTTON# XIE_Y_IN# PM_LNPHY_EN Y J F0 K9 MUSY#/GPIO0 TH/GPIO TH/GPIO TH/GPIO GPIO MIS LN_PHY_PWR_TRL/GPIO LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP 0GTE H H F F U LK_PIE_GLN_N_PH LK_PIE_GLN_P_PH 0GTE 0 GPIO : efault internal P 0K. T_LE GPU_HOL_RST# GPU_PWROK T F GPIO STGP/GPIO TH0/GPIO LKOUT_LK0_N/LKOUT_PIEN LKOUT_LK0_P/LKOUT_PIEP M M LK_PU_N_PH LK_PU_P_PH +VTT_PU GPIO :Enable VVRM,Low=disable. efault internal pull up. GPIO : efault internal PU 0K. +VS LKREQ_GLN# +VS R 0KOhm R 0KOhm R 0KOhm R 0KOhm P_I0 P_I WLN_LE T9 WLN_ON# SL0 00 T9 0 PH_TEMP_LERT# T_ON T9 T T T99 O_LN_RST# VRM_EN STP_PI# ST_LK_REQ# GPU_PWR_EN# GPU_PRSNT# Y SLOK/GPIO H0 GPIO GPIO V GPIO M STP_PI#/GPIO V GPIO STGP/GPIO STGP/GPIO GPIO P_I0 V SLO/GPIO P_I P STOUT0/GPIO9 LK_REQ# H PIELKRQ#/GPIO LK_REQ# F PIELKRQ#/GPIO EMIL_LE STOUT/GPIO STGP/GPIO9/TEMP_LERT# F GPIO T TP_VSS_NTF T TP_VSS_NTF VSS_NTF_ 9 T TP_VSS_NTF VSS_NTF_ T TP_VSS_NTF VSS_NTF_ 0 T TP_VSS_NTF VSS_NTF_ T TP_VSS_NTF VSS_NTF_ T TP_VSS_NTF VSS_NTF_ T TP_VSS_NTF VSS_NTF_ T9 TP_VSS_NTF9 VSS_NTF_ T0 TP_VSS_NTF0 VSS_NTF_9 T TP_VSS_NTF VSS_NTF_0 E T TP_VSS_NTF VSS_NTF_ E T TP_VSS_NTF VSS_NTF_ F T TP_VSS_NTF VSS_NTF_ F T TP_VSS_NTF VSS_NTF_ H T TP_VSS_NTF VSS_NTF_ H T TP_VSS_NTF VSS_NTF_ H T9 TP_VSS_NTF VSS_NTF_ H T0 TP_VSS_NTF9 VSS_NTF_ J T TP_VSS_NTF0 VSS_NTF_9 J T TP_VSS_NTF VSS_NTF_0 J T TP_VSS_NTF VSS_NTF_ J9 T TP_VSS_NTF VSS_NTF_ J T TP_VSS_NTF VSS_NTF_ J0 T TP_VSS_NTF VSS_NTF_ J T TP_VSS_NTF VSS_NTF_ J T TP_VSS_NTF VSS_NTF_ T9 TP_VSS_NTF VSS_NTF_ T0 TP_VSS_NTF9 VSS_NTF_ T TP_VSS_NTF0 VSS_NTF_9 E T TP_VSS_NTF VSS_NTF_0 E VSS_NTF_ IEXPEKM NTF RSV PU PEI RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP9 TP0 TP TP TP TP TP TP TP TP TP9 N_ N_ N_ N_ N_ INIT_V# TP G0 T E0 0 W Y Y V V F M N J K K M N M0 N0 H T9 P 0 PM_THRMTRIP# TP9_PH TP0_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP9_PH TP_PH_N TP_PH_N TP_PH_N TP_PH_N TP_PH_N INT_V# TP_PH_SST T T9 T T T T T T T T T T0 T T T T T9 T0 T T T T T T T9 T H_PEI RIN# 0 H_PUPWRG, EXT_SMI# GPU_PWR_EN# GPU_HOL_RST# PH_TEMP_LERT# GPU_PRSNT# LK_REQ# GPU_PWROK ST_LK_REQ# R0 OHM +VSUS_ORG R 0KOhm R KOhm 0KOHM RN0 0KOHM RN0 0KOHM RN0 0KOHM RN0 R0 0KOhm R 0KOhm R 0KOhm +VS R OHM +VSUS_ORG H_THRMTRIP# SUSTeK OMPUTER IN. N ustom ate: Friday, January, 00 Sheet of 99.0

26 +VTT_PH_VPLL_FI +VTT_PU_V_MI +.VS_VT_LV +VS_V_GIO +V_NVRM_VPNN +VM_VPEP +V +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VFI_VRM +VS_VGG +VTT_PH_VPLL_EXP +VS_V_LVS PM_RSMRST#,,0 +VTT_PH_V +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_ORG +VTT_PH_ORG +.VS +VTT_PH_.VS_.VS +.VS +VTT_PH_ORG +VS +VTT_PU +VM +VTT_PH_ORG +.VS_VMI_VRM +VS +VTT_PH_ORG +VTT_PH_VIO +VS +VTT_PH_.VS_.VS +.VS +VS +.VS +V_NVRM_VQ +VTT_PH_.VS_.VS +VS +VSUS +VSUS ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N m S0 max Resered for IT R0 R0 0 0UF/.V 0 0UF/.V R0 R0 R / R / 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V R R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 00 SL0 00 SL0 L0 KOhm/00Mhz L0 KOhm/00Mhz R R R9 R9 R R 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V R R Q UMKN Q UMKN 0 UF/.V 0 UF/.V 0 T /0 0 T /0 0.UF/V 0.UF/V T0 T0 0.UF/V 0.UF/V VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[9] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K9 VPNN[] K0 VIO[] N VIO[] N VIO[9] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[9] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[9] E VIO[0] E VIO[] G VIO[] G VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LVS[] P VTX_LVS[] P VLVS H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LVS[] T VTX_LVS[] T VSS_[] F VSS_LVS H9 VSS_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M9 VME_[] P VME_[] P9 VPNN[] K VPNN[9] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N POWER V ORE MI PI E* RT LVS FI NN / SPI HVMOS U00G IEXPEKM POWER V ORE MI PI E* RT LVS FI NN / SPI HVMOS U00G IEXPEKM Q UMKN Q UMKN JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R R0 R0 JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R T0 T UF/V UF/V R R 0 0UF/.V 0 0UF/.V R R VSS[] 9 VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[9] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] 9 VSS[] VSS[9] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[9] VSS[0] VSS[] VSS[] VSS[] VSS[] 9 VSS[] VSS[] E VSS[] E VSS[9] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F9 VSS[9] F VSS[0] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[9] H VSS[0] H VSS[] H VSS[] J9 VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[9] J VSS[0] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[9] K VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K9 VSS[9] K VSS[90] K VSS[9] L VSS[9] L VSS[9] M VSS[9] M0 VSS[9] M VSS[9] M VSS[99] M VSS[00] M VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M9 VSS[09] M VSS[0] U0 VSS[] M VSS[] V VSS[] M9 VSS[] M VSS[] 0 VSS[] N VSS[] N0 VSS[9] N VSS[0] P VSS[] P VSS[] P VSS[] P9 VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[9] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V9 VSS[] V VSS[] V VSS[] W VSS[9] W VSS[0] W VSS[] F9 VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] U VSS[] N VSS[] 0 VSS[0] VSS[] V VSS[] U VSS[] M9 VSS[] M VSS[] N9 VSS[] H9 VSS[9] VSS[0] H VSS[0] VSS[9] VSS[9] U00H IEXPEKM U00H IEXPEKM R0 R0 R 0KOhm R 0KOhm 0.UF/V 0.UF/V T0 T0 00 SL0 00 SL0 R R L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 00 SL0 00 SL0 0 UF/.V 0 UF/.V UF/.V UF/.V 0.UF/V 0.UF/V L0 KOhm/00Mhz L0 KOhm/00Mhz 0 UF/.V 0 UF/.V

27 +V.0_INT_VSUS +VTT_PH_V PL TP_PH_VSW +VSST PRT +VTT_PH_V PL +V_VPSUS +.0VM_ORG +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU +V_RT +VTT_PH_VIO +VS_V_ +VTT_PU +VTT_PH_.VS_.VS +VSUS_ORG +VTT_PH_VPLL +VS_PH_VREF +VSUS_VPUS +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_ORG +VS +.0VM_ORG +VS_V_ +VTT_PH_VIO +VS +VPLLVRM +VSUS_PH_VREFSUS +VTT_PH_ORG +VTT_PH_.VS_.VS +VS +VSUS_H +VSUS_ORG +.0VM_ORG +VTT_PH_ORG +VTT_PH_ORG +VSUS +VSUS_ORG +VSUS +VSUS_ORG ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N.0 99 ate: Sheet of ustom Friday, ecember, 009 SUSTeK OMPUTER IN. N.0 99 R.,item L R R R R L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V UF/.V UF/.V R R 0.UF/V 0.UF/V R9 R9 L0 KOhm/00Mhz L0 KOhm/00Mhz 9 UF/.V 9 UF/.V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V T0 T0 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V E0 0UF/V ESR=0mOhm/Ir=.9 E0 0UF/V ESR=0mOhm/Ir=.9 UF/.V UF/.V 0 T 0 T T0 T0 0UF/.V 0UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V R R 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/.V UF/.V R 0 R 0 UF/.V UF/.V.UF/.V.UF/.V T0 T0 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V 0 T 0 T R 0 R 0 UF/.V UF/.V R R E0 0UF/V ESR=0mOhm/Ir=.9 E0 0UF/V ESR=0mOhm/Ir=.9 JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL T0 T0 R R 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL PSUSYP Y0 VME[] VME[] 9 VME[] VME[] F VME[] F VSUSH L0 VSUS_[] U VIO[] V VIO[] 9 VIO[] F0 VIO[] F9 VME[] V9 VME[] V VME[9] V VME[0] Y9 VME[] Y VME[] Y VREF K9 V_[] J V_[9] L V_[0] M V_[] N V_[] P V_[] U VRT VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] E VSUS_[] E VSUS_[0] F VSUS_[9] F VSUS_[] G VSUS_[] G VSUS_[] H VSUS_[] H VSUS_[] J VSUS_[] J VSUS_[] L VSUS_[] L VSUS_[0] M VSUS_[9] M VSUS_[] N VSUS_[] N VSUS_[] P VSUS_[] P VSUS_[] U VSUS_[] U VSUS_[] U VSUS_[] V VIO[] 0 VIO[0] VIO[0] H9 VPLL[] VPLL[] VIO[] J VREF_SUS F VIO[] H0 VIO[] 9 VIO[] 0 VIO[9] VIO[] F V_[] VIO[9] H VVRM[] T0 PSUS Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V9 VIO[] F VME[] F VIO[] H VIO[] H PSST V VSTPLL[] K VSTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VSUS_[9] P VSUS_[0] U9 VSUS_[] U0 VSUS_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U POWER ST US lock and Miscellaneous H PU PI/GPIO/LP RT PI/GPIO/LP U00J IEXPEKM POWER ST US lock and Miscellaneous H PU PI/GPIO/LP RT PI/GPIO/LP U00J IEXPEKM R0 R0 VSS[9] Y VSS[0] VSS[] VSS[] 9 VSS[] VSS[] VSS[] VSS[] 9 VSS[] VSS[] VSS[9] VSS[0] G VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[9] 9 VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[9] VSS[90] VSS[9] H9 VSS[9] VSS[9] 9 VSS[9] VSS[9] E VSS[9] E VSS[9] E0 VSS[9] E VSS[99] E0 VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] F VSS[09] F9 VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[] H VSS[] H VSS[] H9 VSS[] H VSS[9] H VSS[0] H VSS[] H9 VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] E VSS[9] E VSS[0] E0 VSS[] E VSS[] E0 VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[9] L VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] M VSS[] M VSS[] M0 VSS[] N VSS[] M VSS[9] M VSS[0] M VSS[] M VSS[] M9 VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[9] P0 VSS[90] P VSS[9] P VSS[9] P VSS[9] P VSS[9] P VSS[9] R VSS[9] R VSS[9] T VSS[9] T VSS[99] T VSS[00] T9 VSS[0] T VSS[0] T VSS[0] U0 VSS[0] U VSS[0] U VSS[0] U VSS[0] P VSS[0] V VSS[09] P VSS[0] V9 VSS[] V0 VSS[] V VSS[] V0 VSS[] V VSS[] V VSS[] V VSS[] E VSS[9] E VSS[0] F9 VSS[] F VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[9] G0 VSS[0] G VSS[] G VSS[] V VSS[] V VSS[9] V VSS[0] V VSS[] V VSS[] V VSS[] V9 VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[9] Y VSS[0] Y VSS[] Y VSS[] Y9 VSS[] Y VSS[] Y VSS[] Y0 VSS[] Y VSS[] Y VSS[] Y VSS[9] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P9 VSS[] P VSS[] VSS[] F9 VSS[] H VSS[] H0 VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[9] VSS[0] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K9 VSS[] V VSS[] K VSS[] K VSS[9] H9 VSS[0] H VSS[] J U00I IEXPEKM U00I IEXPEKM 0.UF/V 0.UF/V 9 UF/.V 9 UF/.V 0.UF/V 0.UF/V

28 +VM R +VSUS R +V_E /0 / R +VM_SPI 0 T PH SPI ROM R EN0000 +VM_SPI 0 0 SPI_S#0 SPI_SO R R U0 E# V SO HOL# WP# SK VSS SI SSTVF0 (Mb) +VM_SPI_00 SPILK0 SPISI0 SPI_LK 0 SPI_SI 0 R R0 +V,,0 PM_RSMRST# 0 E_SE#_PH 0 E_SO_PH SPI_S#0_S SPI_S#_ON SPI_SO_S SPI_SO_ON SPI_LK_S SPI_LK_ON SPI_SI_S SPI_SI_ON E_SK_PH 0 E_SI_PH 0 +VS +VS +VSUS 0 SM_LK SML_LK SL_ SM_LK_S,,,9,9, E PH 0 SM_T SML_T S_ SM_T_S,,,9,9, +VS +VS R0.KOhm 0 0.UF/V R0.KOhm R 0.KOhm SPIS#0 SPISO0 +VM_SPI_WP0# 0.UF/V R R U0 IN V S EN# S S S S S S S 0 9 TSV0QR R0.KOhm Q0 UMKN Q0 UMKN R.KOhm R0 R R / R9 / R R0 R / R / R Q0 UMKN R0.KOhm Q0 UMKN R9 Q0 UMKN R R9 SM_LK_S 0, PU,VG Thermal SM_T_S 0, Q0 UMKN ustom SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 99.0

29 Layout note: R9 LK FSL 0 00 RX90 FSL R.,item L0 +V_. +V +V_.0 R9 R9,R9:as close as possible to the net FSL of RX90. +V_. R9 0KOhm R.,item L LK_PWRG LK_O LK_U T90 T90 LK_PH_LK LK_PH_LK# R.,item L 0 LK_PWRG# LK_IH +V_. R9 0KOhm R90: For Xtal measurement 90 R90 XLK R90 0KOhm R9 0KOhm RX90 Ohm Q90 N00ETG G S PF/0V 90 PF/0V X90.Mhz,,,9,, SM_T_S,,,9,, SM_LK_S X_LK X_LK FSL +V_. 9 0 VPU_. PUT0_LPR PU0_LPR PU LKPWRG/P#_. REF X X VREF_. REF_L/FSL_.** ST_. SLK_. PUT_LPR 0 PU_LPR 9 VPU_IO VSR_. VOT9MHz_. OT9MHz OT9T_LPR OT9_LPR V_MHz MHz_nonSS MHz_SS MHz U90 IS9LRS9KLFT PU_STOP# VSR_IO SR_LPR SRT_LPR SR ST_LPR STT_LPR 0 ST 9 +V_.0 STP_PU# +V_. R9 0KOhm /9 LK_MI# LK_MI LK_ST# LK_ST R.,item L Pin : Ttrack Áª +V LK_VG_VG RN90 OHM LK_FIX 9 0PF/0V LK_VGSS_VG RN90 OHM 9 0PF/0V LK_SS +V_. LK_OT9# LK_OT9 +VS L90 Layout note: V_.: pin >0.uF to each pin put it at pin,9 +V_. /00Mhz VS +.VS 0UF/0V 0.UF/V 0.UF/V 9LRS9mount L90,unmount L90 9LVSmount L90,unmount L90,R9 L90 /00Mhz /9 L90 /00Mhz / Layout note: V: pin >0.uF to each pin put it at pin,, +V UF/0V 0.UF/V 0.UF/V 0.UF/V +VTT_PH_ORG L90 Layout note: V_.0 : pin >0.uF to each pin put it at pin, +V_.0 /00Mhz UF/0V 0.UF/V 0.UF/V SUSTeK OMPUTER IN. N ustom ate: Friday, January, 00 Sheet 9 of 00.0

30 +V_E +VPLL +V +VS T0 T0 T0 +V For IT Power JP00 +V_E +V_E V_E 00 0UF/0V SL VPLL 00 For +VPLL 0.UF/V Put beside pin 0, LP_0 RNX00 OHM 0, LP_ RNX00 OHM 0, LP_ RNX00 OHM 0, LP_ RNX00 OHM LK_KPI_PH 0, LP_FRME#,,,,,,,,0 UF_PLT_RST# 0 INT_SERIRQ EXT_SMI# EXT_SI# 0GTE RIN# E_RST# ME_SusPwrnck_E E_SK R09 Ohm SK_E OMV_TL E_SO E_SI R0 Ohm SI_E E_SE# R00 Ohm SE#_E 00 0.UF/V 0 0.UF/V VSUS_ON attery Thermal sensor 0 0.UF/V PM_PWRTN#, OP_S# R00 / TP_LK TP_T T0 T0 T0 SM0_LK SM0_T SM_LK SM_T THRO_PU PH_SPI_OV PH_SPI_OVL H: override PH SPI OMV_TL0 KSI0 KSI KSI KSI KSI KSI KSI KSI KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO9 KSO0 KSO KSO KSO KSO KSO E_XIN E_XOUT VSUS_ON_ EXP_GTE# ISTP# T U00 L0 L L L LPLK LFRME# LPRST#/WUI/GP SERIRQ ESMI#/GP ESI#/GP G0/GP KRST#/GP WRST# GPG0 FSK GPG FMISO FMOSI FSE# GPG KSI0/ST# KSI/F# KSI/INIT# KSI/SLIN# KSI KSI KSI KSI KSO0/P0 KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/K# KSO9/USY KSO0/PE KSO/ERR# KSO/SLT KSO KSO KSO KSO/GP KSO/GP KK KKE PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF PSLK/WUI0/GPF PST/WUI/GPF SMLK0/GP SMT0/GP SMLK/GP SMT/GP SMLK/WUI/GPF SMT/WUI/GPF ITEL 0 9 VSTY VSTY VSTY VSTY VSTY VSTY KMX LP FLSH ROM PS/ SMus VT V V VSS VORE VSS VSS VSS VSS VSS VSS 9 9 PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP PWM/GP RX/GP0 TX/GP TX0/GP RING#/PWRFIL#/LPRST#/GP RX0/GP0 TMRI0/WUI/GP TMRI/WUI/GP PWUREQ#/GP RI#/WUI0/GP0 RI#/WUI/GP GINT/GP TH0/GP TH/GP L0HLT/GPE0 EG/GPE EGS#/GPE EGLK/GPE PWRSW/GPE WUI/GPE LPP#/WUI/GPE L0LLT/WU/GPE GPIO GPG/I LKRUN#/WUI/GPH0/I0 RX/WUI/GPH/I TX/WUI/GPH/I WUI9/GPH/I GPH/I GPH/I GPH/I 0/GPI0 /GPI /GPI /GPI /GPI /GPI /GPI /GPI 0/GPJ0 /GPJ /GPJ /GPJ /GPJ /GPJ GME_LE_E# T00 T00 TSEL_0_ SL00 TSEL SL00 ME PRESENT_E RX0 RFON_SW# T_IN_O# GFX_VR_ON SUS_E#_ SUS_E#_ NV_OVERT# T0 T0 T00 PH_TEMP_LERT#_E R00 T0 T0 PWR_LE# HG_LE# HG_FULL_LE# T0 L_L_PWM FN_PWM T00 PM_RSMRST#,, T00 _IN_O# T_IN_O# 0 PWRLIMIT#, PM_SUS# L_KOFF# FN0_TH 0 S_#_E R00 /0 LI_SW#, SL00 00 SL00 00 NUM_LE# P_LE# T0 PU_VRON PM_PWROK VSET_E ISET_E PM_SUS#,, PM_LKRUN# PWR_SW# TSEL_0 TSEL_ VSUS_ON OVTT_TL0 OVTT_TL HG_EN SUS_E#, SUS_E#,, SUS_PWRG,, LL_SYSTEM_PWRG,, VRM_PWRG,,0 PH_TEMP_LERT# T09 For PU / P +V_E R0 R0 RN00 RN00 RN00 RN00 PM_SUS# PM_SUS# PU_VRON MM_OPEN_MIL.KOHM.KOHM.KOHM.KOHM RN00 RN00 RN00 RN00 For X'tal E_XIN R00 00KOhm T_IN_O# 00KOhm T_IN_O# SM0_LK SM0_T SM_LK SM_T 00KOhm 00KOhm 00KOhm 00KOhm 0 0PF/0V T009 R0 0MOhm X00.Khz +/0ppm/.PF E_XOUT +VSUS +VS Note: load=.pf place close to E R0 0 0PF/0V +V_E RN00 RN00 RN00 RN00 +VS RN00 RN00 RN00 RN00 0UF/0V RN00 RN00 RN00 RN00 R009 E_ +VS EXP_GTE# PWRLIMIT# _IN_O# TP_LK TP_T SUS_E#_ SUS_E#_ 0GTE RIN# PM_PWRTN# PM_RSMRST# For E Hardware Strap I/O ase ddress Note: It can be programmable by E fireware Share Memory Note: It can be programmable by E fireware. PP Enable 0.UF/V 0KOHM 0KOHM 0KOHM 0KOHM.KOHM.KOHM.KOHM.KOHM 0KOHM 0KOHM 0KOHM 0KOHM Note: efault Int. PullLow 0.UF/V R0: For Xtal measurement 00 0.UF/V +V R UF/V VSUS_ON E_ For imt pin name _PRESENT PM_S_STTE# S_STTE_ON PM_SLP_M# SLP_M_ON E_WLN_PWR MP_PWRG _PRESENT LN_WOL_EN +VM_PG +.VM_+VMLK_PG SUSPWR_K R00 00KOhm Note: EXT_SMI#, EXT_SI#, PU power plane depend on IH9 GPIO. E_ 00 0.UF/V R0 for ITX & ITX 009 & 00 for ITX +V_E +V_E_SPI +V_E 00 T ME_SusPwrnck_E R0 ME PRESENT_E R09 ME_SusPwrnck ME PRESENT ME_SusPwrnck G R0 0KOhm ME_SusPwrnck_E Q00 N00 S E_SE#_PH E_SO_PH R00 R00 / 0 R00 0.UF/V / E_SO +V_E_SPI R0.KOhm E_SE# SO_ROM ROM_WP# R0 Ohm /0 U00 E# V SO HOL# WP# SK VSS SI SSTVF00 /0 (Mb) ROM_H# E_SK E_SI R0.KOhm +V_E_SPI 09 0.UF/V R00 / R00 / E_SK_PH E_SI_PH alpella G R.,page : ME_SusPwrnck: Required for all platforms ME PRESENT: Required for all platforms except platforms with Ignition Firmware.(0K PU optional) SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of

31 0 KSO KSO KSO0 PN0Y 0 KSO KSO0 KSI PN0Y 0 KSI KSI KSO PN0Y 0 KSO KSO KSO PN0Y 0 KSI0 KSO KSI KSO9 KSI KSI KSO KSO KSO EMI N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V N0 00PF/0V KSO KSO0 KSI KSI KSO9 KSI KSI KSO KSI KSI KSO KSI KSI0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO Keyboard TOP connector PIN KSO ; KSO J0 SIE SIE KSO 0 KSO0 0 KSI 0 KSI 0 KSO9 0 KSI 0 KSI 0 KSO 0 KSI 0 KSI 0 KSO 0 KSI 0 KSI0 0 KSO 0 KSO 0 KSO 0 KSO 0 KSO 0 KSO 0 KSO 0 KSO0 0 KSO 0 KSO 0 KSO 0 Main oard KSO KSO PN0Y KSI FP_ON_P G00 Pin TouchPad onn. +V +V +VS SL0 00 +VS_TP TP M/ TOP PIN LK ; TP SMLL OTTOM. able ÀÏ WLN_LE R0 00KOhm +VS Q0 UMKN T_WLN_LE# RN0 0KOHM RN0 0KOHM PWR_LE Q0 UMKN 0 0.UF/V PWR_ON_LE# 0 TP_LK 0 TP_T 0 ST_LE# 0 HG_FULL_LE# 0 HG_LE# +VS_TP +VS +VSUS +V T_WLN_LE# PWR_ON_LE# J0 SIE SIE FP_ON_P T_LE Q0 UMKN 0 PWR_LE# Q0 UMKN G00 SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

32 Main oard Thermal Policy +VS VG_THERM# R0 R0 0KOhm 0 PU_THERM# R0 PU_VG_THERM#,,,0,,,,,0 UF_PLT_RST# T0 G S Q0 N00ETG +V_E IT has builtin level detection for poweron reset circuit R0 00KOhm T0 0 SSPT T0 9,, FORE_OFF# R0 E_RST# 0 0.UF/.V Output Signal SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 00.0

33 R.,item L L0 /00Mhz +V_LN +VSUS UF/.V 0UF/.V UF/0V close to pin For esign IP: R: 0 Ohm +._Pin V_+.V R UF/V UF/0V 0.UF/V 0 close to pin +VL UF/0V 0.UF/V 0.UF/V 0.UF/V 0 close to pin/ 0 0.UF/V 0 0.UF/V +._Pin,,,0,,,,,0 +V_._LN, PIE_WKE# UF_PLT_RST# 0UF/.V T0 UF/0V +V_LN +._Pin LX VV_ PERSTn +._Pin WKEn +._Pin VV_ SEL_M V +VL SEL_MHz X_LN V_REG 9 X_LN XTLO 0 +V_VO XTLI 0.UF/V RIS V_REG RIS +VS +VL +VL V_+.V +VL V_+.V +V_VO +VL +VL 0.UF/V PIE_TXN_ PIE_TXP_ LK_PIE_GLN_P_PH LK_PIE_GLN_N_PH PIE_RXP_GLN PIE_RXN_GLN PIE Tx,Rx ö hip pin Tx,Rx chip ground pad œ +VL +VL +VL V_+.V LKREQ_GLN# L_TRP0 L_TRM0 L_TRP L_TRM L_TRP L_TRM L_TRP L_TRM 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9.9OHM RN0 9 0.UF/V R with overclock: Remove R, R0 Not overclock: Remove R0 R/MHz: Remove +V_VO R0 0.UF/V SL 00 0.UF/V R0.UH L0 S S F F SL 00 R.KOHM % R 99Ohm R.KOHM U0 RLE 9 LE_0_00n LE_Tn V_REG_ V_REG_ RX_N RX_P VL REFLKP REFLKN 0 VL_ 9 TX_P TX_N TRXP0 TRXN0 VHO VL_ TRXP TRXN VH_ TRXP TRXN VL_ TRXP TRXN UF/V VL_ N TESTMOE SMT VL_ SMLK TWSI_T TWSI_LK VL_ LKREQn LE_LINK000n VH_ UF/V +VL 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V +VL R0 +V_VO X_LN X_LN R0 X0 XLN EXT_/ T0 0PF/0V 0.UF/V 0.UF/V 9 PF/0V Mhz 0 PF/0V SUSTeK OMPUTER IN. N ate: Friday, ecember, 009 Sheet of 00.0

34 R.,item L R.,item L connector without modem +V_._LN U0 L_TRP0 L_TRM0 L_TRP L_TRP0 L_TRM0 L_TRP T+ TT T T+ TT MX+ MT MX MX+ MT 0 L_TRLP0 L_MT0 L_TRLM0 L_TRLP L_MT L_TRLM_L L_TRLP_L L_TRLM_L L_TRLM_L L_TRLP_L L_TRLP_L L_TRLM0_L L_TRLP0_L J0 P_ NP_N NP_N P_ 0 9 L_TRM L_TRP L_TRM L_TRP T T+ MX MX+ 9 L_TRLM L_TRLP MOULR_JK_P G00 L_TRM L_TRP L_TRM L_TRP 9 TT T T+ MT MX MX+ L_MT L_TRLM L_TRLP L_MT L_MT0 L_MT L_MT RN0 RN0 RN0 RN0 Ohm Ohm Ohm Ohm _LN_T 0 0 TT MT L_MT 000PF/KV L_TRM L_TRM T MX L_TRLM LFE99_R LN_ 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 UF/.V st source: 09G0090 nd source: 09G0090 ost down 0,0,0,0 close to U0 pin, pin, pin and pin0 each L_TRLP0 SL0 RP L_TRLP0_L L_TRLM0 SL0 RP L_TRLM0_L L_TRP0 L_TRP L_TRP L_TRP 0 IPZ L_TRM0 VI/O VI/O +V_LN VUS VI/O VI/O L_TRM 0 IPZ L_TRM VI/O VI/O +V_LN VUS VI/O VI/O L_TRM 0.UF/V 0 0.UF/V 0 LN_ Place near chassis L_TRLP L_TRLM L_TRLM L_TRLP L_TRLP L_TRLM SL0 SL0 SL0 SL0 SL0 SL0 RP RP RP RP RP RP L_TRLP_L L_TRLM_L L_TRLM_L L_TRLP_L L_TRLP_L L_TRLM_L SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 00.0

35 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

36 udio Power +VS +VS_UIO_MP T SL FOR JUST MOE: Vo=.*(+R0/R0) =.*( + 00K/.K) =. SL T0 0.UF/V +VS UF/0V 0.UF/V +VS 0UF/.V ( m) 9 U0 V_ORE V V_IO V V PV PV 9 +VS_UIO (. m) _UIO 0.UF/V _UIO UF/0V ( m) 0UF/.V UF/0V +VS_UIO_MP 0.UF/V +VS,0, L0 /00Mhz PM_SUS# 0UF/0V +VS_U 0.UF/V U0 SHN# IN G90TUF SET OUT 0G000 SL 00 R0.KOhm Try 0 ohm 000PF/0V R9 00KOhm R UF/V c00 0UF/0V +VS_UIO 9 0.UF/V _UIO 0 0.UF/V 0 Z_LK_U ITLK SENSE_ SENSE_ SENSE_ SENSE_ T _UIO _UIO _UIO 0, OP_S# , 0 Z_SIN0_U Z_SOUT_U Z_SYN_U Z_RST#_U TW R 0 0PF/0V /EMI R R 0KOhm +VS.UF/.V T T T EP Ohm 0 ST_IN ST_OUT SYN RESET# MI_LK/GPIO MI_0/GPIO MI/GPIO0/SPIFOUT SPIF_OUT0 EP P P+ PORT PORT PORT PORT PORT E PORT F HP0_L HP0_R 9 VREFOUT_ HP_L HP_R 9 PORT_L PORT_R 0 VREFOUT_ PORT_+L PORT_L 0 PORT_R PORT_+R PORTE_L PORTE_R PORTF_L PORTF_R PEEP MONO_OUT T T9 T.UF/0V _HP_L _HP_R.UF/0V _SPK_L_P 9 _SPK_L_N 9 _SPK_R_N 9 _SPK_R_P 9 INT_MI MI0_VREFOUT_L EXT_MI MI_VREFOUT_L IFEQIPOF,TQEJG FYU!NJ TQFLFS JOU!NJ SENSE SENSE_ +VS_UIO _UIO R.9KOhm % 0.UF/V R9 0KOhm % R 0KOhm % EXT_MI_J HP_J PORT PORT VSS 0 VSS VSS VSS PVSS P VREFFILT V +VS_UIO 9 0 9HXNLGXYX VREG(+.V).UF/.V 9.UF/.V 0.UF/.V UF/0V R 00KOhm _UIO _UIO _UIO _UIO _UIO SENSE_ L99 /00Mhz SL 00 SL 00 SL 00 P EEP Remove P_EEP ircuit 009/0/ Please remove the P eep function from Verb table. R <Variant Name> R SUSTeK OMPUTER IN. N _UIO ustom Friday, ecember, 009 ate: Sheet of 00.0

37 HP_J SL0 00 +VS +VSUS +V R J0 0, OP_S# 0, Z_RST#_U 09 TW RN0 0KOHM MP_MUTE# RN0 0KOHM Q0 UMKN R9.MOhm Q0 UMKN HP_R HP_L R 0KOhm _UIO _JK EXT_MI_J MI_VREFOUT_L +VS_UIO EXT_MI _UIO R.KOhm SL9 00 EXT_MI_ON_L 00PF/0V R.KOhm _HP_R MUTE_POP# 0 _HP_L 0.UF/V Q0 Q0 UMKN UMKN Q0 Q0 UMKN UMKN R R R R 0KOhm Ohm Ohm HP_R_ON HP_L_ON 0.UF/V 0.UF/V 0 NP_N 9 NP_N P_ P_ 00PF/0V PHONE_JK_P G0000M IFEQIPOF SL 00 J0 UF/0V R.KOhm 0 9 NP_N NP_N P_ P_ 00PF/0V PHONE_JK_P G0000M R FYU`NJ _UIO _JK Title : SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 00.0

38 MI0_VREFOUT_L 0 UF/0V R.KOhm _UIO INT_MI 0 0.0UF/V SL0 00 SL0 00 OMNI_MI_P OMNI_MI_N U0 OUTPUT GROUN MIROPHONE_P _UIO <Variant Name> SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 00.0

39 Main oard SPEKER ONNETOR _SPK_L_P _SPK_L_N SL90 SL L_WOO+_ON L_WOO_ON TOP connector PIN L+ ; PIN R 00PF/0V 00PF/0V _SPK_R_P _SPK_R_N SL90 SL R_WOO+_ON R_WOO_ON J90 SIE SIE Wto_ON_P 90 00PF/0V PF/0V G0000F SUSTeK OMPUTER IN. N ustom Ryan_Wang ate: Friday, ecember, 009 Sheet 9 of 00.0

40 Ryan_Wang SUSTeK OMPUTER IN. N Friday, ecember, 009 ate: Sheet of

41 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

42 Main oard SUSTeK OMPUTER IN. N Ryan_Wang Friday, ecember, 009 ate: Sheet of 00.0

43 Main oard KJ US oard_0 Pin ON TOP connector PIN0 US_PP ; PIN9 US_PN PIN US_PN ; PIN US_PP R.,item L0 J0 NP_N 0 NP_N0 NP_N NP_N NP_N NP_N 0 NP_N0 NP_N NP_N NP_N NP_N NP_N NP_N9 NP_N NP_N NP_N NP_N NP_N9 NP_N NP_N NP_N NP_N 9 9 US_PP LK_R_REER_ +V US_PP US_PN US_PN HEER_X0P US_PN +V +V S_#_E 0 US_PP SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

44 Main oard LP ebug Port +V 0,0 LP_0 0,0 LP_ 0,0 LP_ 0,0 LP_ 0,0 LP_FRME# LK_EUG 0 0.UF/0V J0 SIE SIE FP_ON_P TP M/ TOP PIN LK ; Pin +V SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

45 +VS Main oard +V +VS 0 0 L_VEN RN0 00KOhm Q0 UMKN RN0 00KOhm +VSL 00KOhm +VS_L R0 +V +V R0 R +V_ 0 UF/.V Q0 UMKN Q0 S G SIV 0 0.UF/V 0.0UF/V RN0 L0 /00Mhz UF/V 0UF/0V 0 UF/.V 0 0.UF/V 0.UF/V RN0 00KOhm +VS R :.K G S Q0 N00ETG US_P9 US_P9+ L0 RN0 RN0 9/00Mhz US_PN9 US_PP9 0 0.UF/V.KOHM RN0.KOHM RN0 J0 +VS_L _T_SYS_INV 0 0.UF/V 000PF/0V JP99 MM_OPEN_MIL Q0 P0EMG EI_LK EI_T 0 LVS_U0N 0 LVS_U0P 0 LVS_UN 0 LVS_UP 0 LVS_UN 0 LVS_UP 0 LVS_ULKN 0 LVS_ULKP R.,item L _T_INV L0 /00Mhz 09 0UF/V 0.UF/V +V_ US_P9 US_P SIE SIE WTO_ON_0P G000 L_PWM L_EN LVS_L0N 0 LVS_L0P 0 LVS_LN 0 LVS_LP 0 LVS_LN 0 LVS_LP 0 LVS_LLKN 0 LVS_LLKP 0 _T_INV 0PF/0V R SL0 00 +VS KOhm 0 TW 0 TW 0 UF/0V L_L_PWM 0 LI_SW# 0, L_KOFF# 0 L_KEN 0 PM_SUS#,0, UF/V R 00KOhm G S 0.0UF/V R 00KOhm SUSTeK OMPUTER IN. N Ryan_Wang.0 ate: Friday, ecember, 009 Sheet of 00

46 Main oard RT_RE RT_R_ LX0 RT_R_ON JP0 SHORT_PIN R0 0 0PF 0.0uH 0 0PF J0 RT_GREEN JP0 SHORT_PIN RT_G_ R0 0 0PF LX0 0.0uH 0 0PF RT_G_ON RT_R_ON RT_G_ON RT ON 9 0 _T_ON HSYN_ON VSYN_ON _LK_ON PLE ES iodes near connector +VS RT_R_ON RT ON RT_LUE JP0 SHORT_PIN RT R0 0 0PF LX0 0.0uH 0 0PF RT ON _SU_PR G00 RT_G_ON VI/O VI/O VUS VI/O VI/O 0 IPZ HSYN_ON 09G000 +VS, RT_HSYN, RT_VSYN +VS Q0 UMKN UMKN Q0 HSYN_RT VSYN_RT R0 Ohm R0 Ohm PF/0V PF/0V HSYN_ON VSYN_ON RT_VSYN RT_HSYN U0 OE# OE# V 0.UF/0V LVGUR HSYN_RT VSYN_RT 0 +VS V99 _LK_ON _T_ON VSYN_ON 09 EG00V0 0 RT T RT LK +VS Q0 UMKN UMKN Q0 _T _LK SL0 00 SL0 00 _T_ON 09 PF/V _LK_ON 0 PF/V +VS 0 SSPT +VS _T.KOHM RN0 _LK.KOHM RN0 RT T.KOHM RN0 RT LK.KOHM RN0 SUSTeK OMPUTER IN. N EG00V0 Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

47 Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

48 Main oard PLE HMI 0.uF near connector J0 HMI_LKP_VG HMI_LKN_VG HMI_TXP0_VG HMI_TXN0_VG HMI_TXP_VG HMI_TXN_VG HMI_TXP_VG HMI_TXN_VG UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V HMI_LKP HMI_LKN HMI_TXP0 HMI_TXN0 HMI_TXP HMI_TXN HMI_TXP HMI_TXN +VS 0 SS00 0 SS00 JP0 MM_OPEN_MIL HMI_HP F0 changed to 0G0000 POLYSWITH SM 0./V(0) +VS_F 0 0.UF/V 0 V99 F0./V R0 R0 KOhm 0KOhm +VS_HMI HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP0_ON HMI_TXN0_ON HMI_LKP_ON HMI_LKN_ON HMI_SL HMI_S HMI_HP_ON J0 P_ P_ P_ 9 9 P_ 0 HMI_ON_9P G09T HMI_LKP +VS HMI_LKN HMI_TXP0 +VS RN0.KOHM RN0.KOHM HMI_TXN0 HMI_TXP HMI_TXN HMI_TXP HMI_TXN HMI_TXP0 HMI_TXN0 HMI_LKP SL0 SHORT_LN_RP RP HMI_TXP_ON SL0 SHORT_LN_RP RP HMI_TXN_ON SL0 SHORT_LN_RP RP HMI_TXP_ON SL0 SHORT_LN_RP HMI_TXN_ON RP SL0 SHORT_LN_RP RP HMI_TXP0_ON SL0 SHORT_LN_RP HMI_TXN0_ON RP SL0 SHORT_LN_RP HMI_LKP_ON RP +VS HMI_TXP HMI_TXN HMI_TXP HMI_TXN G S R 00KOhm R 99Ohm R 99Ohm R09 99Ohm R0 99Ohm R 99Ohm R 99Ohm Q0 N00ETG R 99Ohm R 99Ohm HMI LK HMI T Q0 UMKN Q0 UMKN HMI_LK HMI_T SL0 00 HMI_SL 0 PF/V SL0 00 HMI_S 0 PF/V HMI_LKN SL0 SHORT_LN_RP HMI_LKN_ON RP SUSTeK OMPUTER IN. N Ryan_Wang ate: Monday, February 0, 00 Sheet of 00.0

49 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 9 00

50 Main oard PU Thermal Sensor PHILIP PMS90 Pleace in the center of PU socket. Q00 PMS90 E PU_THRM_ 0mil trace 00 00PF/0V +VS 00 0.UF/V U00 V SMLK XP SMT XN LERT# THERM# G SM_LK_S, SM_T_S, PU Thermal Sensor Rset: please refer to the Rsettable R0 KOhm % U00 SET V OT# HYST G09TUF R0 R0 R00: for common part, can use %. G09_V +VS R00 % 00 0.UF/V HYST=V: 0 degree HYST=: degree (efault)!! o not N HYST. PU_THRM_ 0mil trace O/ O/ PU_THERM# PU_THERM# SMUS addr=0000x (9) U00: Remote(Local) thermal sensor,use remote mode. Layout note: Place U00 at the center of the PU socket. Rset(Kohm)=0.00T*T0.90*T+9. Resistor ccuracy: +/ % PWM Fan OTTOM connector PIN +VS ; +VS G09 Temperature Threshold ccuracy:. degree ~ +. degree Set center temperature=9.0 degree Rset value is depend on thermal request. For M0J,possible board shutdown temperature: 9 ~ 0 degree. 00 put besides J00. 0 FN_PWM 0 FN0_TH 00 00PF/0V +VS R00 0KOhm 00 00PF/0V 00 0UF/0V E00 UF/.V J00 SIE SIE Wto_ON_P Remove diode(+vs to ) for using wires PWM FN. G00000 SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet 0 of 00.0

51 O J0 NP_N S P_ S NP_N S S S S S P P P NP_N P P_ P NP_N P ST_ON_P S S S S S S S P P P P P P ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ T0 T UF/V X09 X X X0 XR 0% 0 0UF/0V 0.0UF/V 0.0UF/V 0.0UF/V 0.0UF/V +VS_O ST_TXP 0 ST_TXN 0 ST_RXN 0 ST_RXP 0 SL0 00 +VS G00 H (nd) Right side H (st) Left side J0 NP_N NP_N NP_N NP_N S S S S S S S P P P P P P P P P9 P0 P P P P P S S S S S S S P P P P P P P P P9 P0 P P P P P ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ 000PF/0V 000PF/0V 0 0.UF/V 0 0.UF/V XR 0% X0 0.0UF/V X0 0.0UF/V X0 0.0UF/V X0 0.0UF/V +VS_H 0 0UF/0V +VS_H 09 0UF/0V ST_TXP 0 ST_TXN 0 ST_RXN 0 ST_RXP 0 SL0 00 SL0 00 +VS +VS J0 NP_N NP_N NP_N NP_N S S S S S S S P P P P P P P P P9 P0 P P P P P S S S S S S S P P P P P P P P P9 P0 P P P P P 000PF/0V XR 0% ST_TXP0_ X0 0.0UF/V ST_TXN0_ X0 0.0UF/V ST_RXN0_ X0 0.0UF/V ST_RXP0_ X0 0.0UF/V +VS_H 000PF/0V 0 0.UF/V 0 0.UF/V 0 0UF/0V +VS_H 0 0UF/0V SL0 00 SL0 00 ST_TXP0 0 ST_TXN0 0 ST_RXN0 0 ST_RXP0 0 +VS +VS ST_ON_P ST_ON_P G0J G0J SUSTeK OMPUTER IN. N ustom Friday, ecember, 009 ate: Sheet of 00.0

52 US_PN0 US_PP0 L0 L0 +V +V_US /00Mhz +V_US_ F0 RN0 RN0 9/00Mhz./V EN0099 E0 UF/.V 0 0UF/.V 0 0.UF/V US_P0 US_P0+ J0 P_ P_ US_ON_XP G000L _JK 0 US_P0+ VI/O VI/O US_P0 +V_US_ VUS US_P+ VI/O VI/O US_P IPZ US_PN US_PP L0 RN0 RN0 9/00Mhz EN0099 E0 0UF/.V 0 0UF/.V +V_US_ US_P US_P+ 0 0.UF/V J0 P_ P_ US_ON_XP G000L SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 00.0

53 +.VS +.VS_WLN WLN R +VUX_WLN R +V Shirley Peak/ Echo Peak R RF_EV_ON +VS LK_PIE_WLN#_PH LK_PIE_WLN_PH J0, PIE_WKE# WKE#.V_ Q0 Reserved N00ETG Reserved.V_ LKREQ_WLN# LKREQ# UIM_PWR 9 G UIM_T 0 S R REFLK UIM_LK 0KOhm REFLK+ UIM_RESET UIM_VPP WLN_ON# PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_ PIE_TXP_ +VUX_WLN L_LK L_T L_RST# Reserved/UIM_ Reserved/UIM_ W_ISLE# PERST# PERn0 +.Vaux PERp0 9.V_ SM_LK PETn0 SM_T PETp0 0 US_ Reserved US_+ Reserved Reserved LE_WWN# Reserved LE_WLN# Reserved LE_WPN# Reserved.V_ Reserved9 Reserved0.V_ US_PN_ US_PP_ SL0 SHORT_LN_RP RP RP SL0 SHORT_LN_RP UF_PLT_RST#,,,0,,,,,0 US_PN US_PP NP_N NP_N MINI_PI_P G000N WLN +VUX bypass capactor: Place 0.UF near pin,,,9. Place 0UF near +VUX_WLN source side. +VUX_WLN WLN +.VS bypass capactor: Place 0.UF near pin,,. Place 0UF near +.VS source side. +.VS WLN nuts: Minicard spec R.: Full size card= pcs. Half size card= pcs. H0 H UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 9 0UF/.V 0.UF/V 0 0.UF/V 0.UF/V T T G000 N : G00000 G000 SUSTeK OMPUTER IN. N ustom ate: Friday, ecember, 009 Sheet of 00.0

54 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

55 Main oard SUSTeK OMPUTER IN. N Ryan_Wang Friday, ecember, 009 ate: Sheet of 00.0

56 Main oard +V 0, LI_SW# T0 R09 0KOhm RN0 Ohm 0 0.UF/V LI_SW_ON# +V 0 0.UF/V 0 UF/.V Hall sensor J0 Vdd LI_SW_ON# OUTPUT H0WG 0 0.UF/V POWER UTTON POWER_SW# SW0 +V TT_SWITH_P T0 nd : 0G PWR_SW# 0 RN0 Ohm POWER_SW# T0 ( rd : 0G0000 ) 0.UF/V nd : 0G000 ( rd : 0G0000 ) nd : 0G000 ( rd : 0G0L00 ) +VS +VS +VS +VS +VS +VS +VSUS RN0 0KOHM RN0 0KOHM RN0 0KOHM R0 R0 + LE0 GREEN RN0 0KOHM + R0 0KOhm R LE0 GREEN + LE0 WHITE Q0 UMKN Q0 UMKN PWR_ON_LE# T0 0 NUM_LE# Q0 UMKN 0 P_LE# Q0 UMKN R0 R SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

57 Main oard +VS +VS +0.VS +V 0,, SUS_E# +VS_ISHRG Q0 UMKN +VS_ISHRG +0.VS_ISHRG +V +V +V R0 00KOhm +V_ISHRG +V_ISHRG 0, SUS_E# Q0 UMKN R0 R G S Q0 N00ETG R R0 R 00KOhm Q0 UMKN Q0 UMKN Q0 UMKN R0 Q0 UMKN SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

58 Main oard POWER GOO ETETER +VO +VS SYSTEM_PWRG R_PWRG,0, SUS_PWRG RN0 00KOHM SL T RN0 00KOHM T0 U0 NSZ0PX V Y +VSUS 00 SSPT Q0 UMKN T0 SUS_E# 0,, FORE_OFF# 9,, +VTT_PU_PWRG,,, TI_PWRG_VG +.VS_PWRG +.VS_PWRG +VS +VS +VO,0,0 VRM_PWRG O/ +VTT_PU_PWRG SYSTEM_PWRG U00 V Y NSZ0PX Vihmin=0.Vcc Vilmin=0.Vcc T0 LL_SYSTEM_PWRG,0, H_VTTPWRG R KOhm % R0 0KOhm 00.UF/.V c00 Q0 UMKN R R 90 0.UF/V R R R R0 00KOhm 0 0.UF/V T0 R0 00KOhm +VTT_SYS_PWRG R SL0 00 KOHM SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet of 00.0

59 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 9 00

60 Main oard +V_JK urrent setting= epend on the current of the adaptor. /_OK_IN J00 P_ P PWR_JK_P T00 T00 T00 T UF/V JP00 MM_OPEN_MIL JP00 MM_OPEN_MIL 00 PSMJ0 00 0UF/V 00 UF/V 00 0.UF/V Jack G00 T00 T00 T00 T00 T_ON T T009 T00 T0 L00 /00Mhz Irat= J00 T0 NP_N 0 L00 /00Mhz Irat= T0 T0 T00 R00 R00 R NP_N 0.UF/V TT_ON_9P G T0 T0 T0 T0 T0 +V T0 T09 00 PF/0V VI/O VI/O VUS 00 PF/0V VI/O VI/O For Q0Z90 rising time spec. 00 IPZ 00 PF/0V SM0_LK 0 SM0_T 0 T_IN_O# 0 attery onnector SUSTeK OMPUTER IN. N Ryan_Wang ate: Friday, ecember, 009 Sheet 0 of 00.0

61 LUETOOTH TOP connector PIN LE ; PIN +V 0 0.UF/V +V T_ON 0 T T_ON_ R0 0KOhm US_PP US_PN T0 T_Link_LE J0 SIE SIE WTO_ON_P G000 SUSTeK OMPUTER IN. N Ryan_Wang ustom ate: Friday, ecember, 009 Sheet of 00.0

62 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

63 Main oard Ryan_Wang SUSTeK OMPUTER IN. N.0 Friday, ecember, 009 ate: Sheet of 00

64 +V R0 +VS +V_TUN R0 0 0.UF/V 0 0UF/0V 0 UF/.V LKREQ_M# LK_PIE_M#_PH LK_PIE_M_PH J0 WKE# Reserved Reserved LKREQ# 9 REFLK REFLK+.V_.V_ UIM_PWR UIM_T 0 UIM_LK UIM_RESET UIM_VPP R0 Max: m +.VS_TUN 0 0.UF/V 0 0.UF/V 0 0UF/0V +.VS PIE_RXN_M PIE_RXP_M PIE_TXN_ PIE_TXP_ Reserved/UIM_ 9 Reserved/UIM_ W_ISLE# PERST# PERn0 +.Vaux PERp0 9.V_ 9 SM_LK PETn0 SM_T PETp0 0 US_ Reserved US_+ 9 Reserved Reserved LE_WWN# Reserved LE_WLN# Reserved LE_WPN# Reserved.V_ 9 Reserved9 Reserved0.V_ NP_N NP_N MINI_R_LTH_P R0 US_PN US_PP UF_PLT_RST#,,,0,,,,,0 Reserved for SS G00000 H0 H0 0M0S 0M0S G00900 G00900 SUSTeK OMPUTER IN. N Ryan_Wang ustom ate: Friday, ecember, 009 Sheet of 00.0

65 Screw Hole S * H OxOxN H RTX s00 Tooling Hole R * s0 Screw Hole Q * Screw HoleS * H RTX s00 Screw Hole K * H NP_N RT9X0N s0 Screw Hole J * H T s09 H T s09 Screw Hole G * H0 NP_N RT9X0N s09 H09 NP_N RT9X0N s09 Screw Hole H * H0 NP_N TN s09 Screw Hole * H0 NP_N RT9X0N s0 Screw Hole * H0 NP_N ST9RX0N s0 Screw Hole P * H H NP_N TOXN For LVS cable H0 T NP_N RTX0N s00 GNER0S00 s000 Screw Hole N * H NP_N Screw Hole S * H RTX s00 Tooling Hole * s0 H0 OxOxN RTX0N s09 Screw Hole * Screw Hole S * H0 NP_N H RTX TN s00 Screw Hole Z * s09 P (TOP) * U0 SMx temp hl0 Screw Hole I * H NP_N H NP_N T9N s0 Screw Hole E * H0 NP_N RTX90N Screw Hole L * H9 NP_N RTXR0N s09 Tooling Hole T * H9 HOLE_NPTH temp gc RTX9R0N s09 H9 NP_N T9N s0 _JK SUSTeK OMPUTER IN. N Ryan_Wang ustom s090 Friday, ecember, 009 ate: Sheet of 00.0