FM9 XXXX Intel Discrete GFX

Transcript

1 FM XXXX Intel iscrete GFX VER : PW: PW: POWER /TT ONNETOR PG R-SOIMM PG R-SOIMM SYSTEM RESET IRUIT TT HRGER RUN POWER SW +.V_SUS/+V_SUS +V/+.V/+.V PG PG PG ual hannel R //.V uburndale/ larksfield ( rpg ) FN & THERML SMS PG PIEx R x (M bits) PG LOK SLGSPVTR (QFN-) PG TI M-XT PI EXPRESS GFX PG,,,,, POWER REGULTOR +.V_SUS/+.V_R_VTT +.V_R_VTT LVS HMI VG PG +.V PG PG Panel onnector HMI ONN. RT ONN. PU VR / +.V_LW/+V_LW/ +V_LW VG ore PG PG PG PG PG PG PG PG,,, E-ST ombo with US ONN UIO/MP H PG PG ST-O PG ST-H & Fall Sensor PG PIEQXHE PG amera + -MI PG ST ST ST IH US. FI PH MI X PG,,,,, US. x PIEx PIEx US. PIEx US. US. US conn x PG, LN RTLL\RJ\Transformer PG EXPRESS/ard Reader ONN. MINI-R WLN MINI-R WWN PG PG PG udio udio SPK conn Jacks x PG PG USER INTERFE PG SPI FLSH Mbyts LP K ITE PG PG X PS/ Touchpad PG Keyboard PG luetooth T onn PG QUNT OMPUTER Schematic lock iagram Size ocument Number Rev FM ate: Thursday, February, Sheet of

2 Table of ontents PGE ESRIPTION Schematic lock iagram Front Page - larksfield/uburndale - PH - RIII SO-IMM(P) lock Generator - M-S-XT LNK PGE L ONN / HMI ONN RT ONN OZGSLN LNK PGE Express/Rard/ SIO (ITE) FLSH / RT MINI-ard (WWN) MINI-ard (WLN\WPN) Left PUS/EST Right US ST (H & _ROM) TP / KEYOR SWITH / /LE FN / THERML zelia OE UIO ONN LN(RTLL/RJ-) System Reset ircuit lank Page.V_RUN(RT/RT) harger (ISL) V/V (TPS)._R/.(TPS).V_PH(TPS)._VTT(TPS) VG_M-XT(MX) V_ORE(ISL) Run Power Switch in & att P & SREW EMI P SMUS LOK THERML MP Power lock iagram XP POWER PLNE +PWR_SR +RT_ELL +.V_LW +V_LW +.V_LN +V_SUS +.V_SUS +.V_SUS +.V_R_VTT +V_RUN +.V_RUN +.V_RUN +.V_RUN +.V_RUN_GFX +V_GFX_ORE +.V_PH +V_ORE +LV +V_MO +V_H GN_HG GN_.V GN_VG GN_SIGNL GN_/ VOLTGE V~+V +.V~+.V +.V +V +.V +V +.V +.V +.V +V +.V +.V +.V +.V +.V~+.V +.V~+.V +.V +V +V PGE,,,,,,,,,,, Power States,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, GN PLNE PGE ESRIPTION,, ESRIPTION MIN POWER RT POWER LRGE POWER LN POWER SLP_S# TRL POWER SLP_S# TRL POWER SOIMM POWER SOIMM POWER SLP_S# TRL POWER SLP_S# TRL POWER SVO POWER LISTOG/IH POWER VG POWER VG POWER PU ORE POWER L Power Module Power H Power ONTROL SIGNL LWON RUN_ON UX_ON SUS_ON SUS_ON SUS_ON RUN_ON RUN_ON RUN_ON RUN_ON RUN_ON +.V,,,, PU/LISTOG/IH POWER.V_RUN_ON +.V_VTT +.V,,,,, +.V_GFX_PIE +.V, RUN_ON RUN_ON IMVP_VR_ON LV_TST_EN & ENV MO_EN H_EN TIVE IN S~S S~S S~S S~S GN LL QUNT OMPUTER Index & Power Status Size ocument Number Rev FM ate: Thursday, February, Sheet of

3 UURNLE/LRKSFIEL PROESSOR (MI,PEG,FI) S(V.),P: Should be shorted at the pins and then routed to one end of the.-ω ±% resistor, pulled-down to GN on the board. UURNLE/LRKSFIEL PROESSOR (LK,MIS,JTG) PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N H_TERR# H_PROHOT#_ H_PURST# MI_TXN MI_TXN MI_TXN MI_TXN MI_TXP MI_TXP MI_TXP MI_TXP MI_RXN MI_RXN MI_RXN MI_RXN MI_RXP MI_RXP MI_RXP MI_RXP G(V.),P: should be tied to GN (through K ±% resistors), if these signals are left floating, there are nofunctional impacts but a small amount of power (~ mw) maybe wasted. G(V.) P: FI_FSYN[], FI_FSYN[], FI_LSYN[],FI_LSYN[] can be ganged together with one resistor. Processor Pullups.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U.U R./F +.V_VTT R./F R K R *_N G F H F E G E G E F G G E F G F E F U MI_RX#[] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[] MI_RX[] MI_RX[] MI_RX[] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[] MI_TX[] MI_TX[] MI_TX[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_FSYN[] FI_FSYN[] FI_INT FI_LSYN[] FI_LSYN[] larksfield/uburndale PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N PIE_MTX_GRX_N MI Intel(R) FI PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] S(.V),P: H_PROHOT# use: pull to ohm if it isn'tt used: pull to ohm S(.V),P: H_TERR#.-Ω ±% Pull-Up to the VTT rail (+V.S_VTT) K J J G G F F E J H H F G E F F L M M M L K M J K H H F E L M M L M K M H K G G F E PEG_IOMPI R PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_N PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MRX_GTX_P PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX N PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P./F R /F PIE_MRX_GTX_N[..] PIE_MRX_GTX_P[..] +.V_SUS PM_RM_PWRG H_OMP H_OMP H_OMP H_OMP TP_SKT# H_TERR# H_PEI_ISO H_PROHOT#_ H_PURST# PM_RM_PWRG PIE_MTX_GRX_N[..] PIE_MTX_GRX_P[..] PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P PIE_MTX_GRX P.U.U.U.U PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX_P PIE_MTX_GRX_P SM_RMPWROK:(Intell Feedback) Either way works. PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P T PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P PIE_MTX_GRX P.U.U PIE_MTX_GRX_P PIE_MTX_GRX_P R(V.) P: PIE_MTX_GRX P.U PIE_MTX_GRX_P is it necessery? T PIE_MTX_GRX P.U PIE_MTX_GRX_P PIE_MTX_GRX P.U PIE_MTX_GRX_P H_OMP H_OMP H_OMP H_OMP H_PEI H_THERM PM_RM_PWRG,,,,,,, Processor ompensation Signals G(V.),P: OMP[.].-Ω ±% pull-down to GN OMP[.] -Ω ±% pull-down to GN S(V.),P: SKTO# an be left No onnect or tied to GN H_PURST# PM_SYN S(V.),P,: This signal should be connected to the processor's VPWRGOO_ and VPWRGOO_ input to indicate when the, H_PWRGOO processor power is valid. VTTPWRGOO S(V.)P: VTT_. VR power good signal to processor. Signal voltage level is. V. R./F R.K/F R K/F R./F R /F R /F H_VTTPWRG H_PWRG_XP PLTRST# R R T R.K/F T T R RSTIN#: /F larksfield/uburndale G(V.)(oc.# ),P: Need a voltage divider network to scale down from.v (PH driven) to.v/.v (larksfield/uburndale) SM_RMPWROK: G(V.) P&S(V.) P:recommend.-kΩ pull-up to R Power Rail (VQ) of +V.U and a -kω pull-down to ground to convert to processor s VTT level. R(V.) P:R uses a.v (always ON) rail with K and K combination. R Implementation is different for the alpella Platform esign Guide. ustomers to follow the latest alpella Platform esign Guide for RMPWROK Implementation. G T H K T N K P L N N K M M L H_THERM Q MMST--F XP_TMS XP_TI_R XP_PREQ# XP_TLK +.V_RUN R ompensation Signals R /F U OMP OMP OMP OMP SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_ SM_RMPWROK VTTPWRGOO TPPWRGOO RSTIN# R./F R /F SM_ROMP_ SM_ROMP_ SM_ROMP_ MIS THERML PWR MNGEMENT R M LOKS R MIS JTG & PM R R R R.U +.V_VTT *_N *_N *_N *_N Q NW--F Layout Note: Place these resistors near Processor PM_THRMTRIP# G(V.),P: SM_ROMP[] -Ω ±% pull-down to GN SM_ROMP[].-Ω ±% pull-down to GN SM_ROMP[] -Ω ±% pull-down to GN LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R T E F L M N N P T P N P T T R R P N J K K J J H K H SM_ROMP_ SM_ROMP_ SM_ROMP_ XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO_R XP_TI_M XP_TO_M H_R#_R XP_OS_R XP_OS_R XP_OS_R XP_OS_R XP_OS_R XP_OS_R XP_OS_R XP_OS_R XP_TI_R XP_TO_M XP_TI_M XP_TO_R LK_PU_LK LK_PU_LK# LK_ITP LK_ITP# LK_PIE_GPLL LK_PIE_GPLL# PLL_REF_SSLK and PLL_REF_SSLK# can be connected to GN on uburndale directly if motherboard only supports discrete graphics. R R R R R R R R R R_RMRST#, XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# T T T XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS JTG MPPING Scan hain (efault) PU Only GMH Only R K/F R K/F R R G(v.) table UURN / QUNT OMPUTER +.V_VTT PM_EXTTS# PM_EXTTS# XP_RESET#, XP_OS[:] STUFF -> R, R, R NO STUFF -> R, R XP_TI STUFF -> R, R NO STUFF -> R, R, R STUFF -> R, R NO STUFF -> R, R, R R(v.) P. R#: S(V.) P:onnected to the R# pin of the Processor.-Ω to -kω pull-up to.vs R(V.) P,P:R uses a -kω pull-up to.vs. On the R this signal is Ned with Master Reset to generate SYS_RESET. R#:(Intell feedback) Nothing wrong w/ R design. If you want to connect it to PH directly, make sure pull high to.v (S) main power. R R R R *_N *_N R R *.K/F_N XP_TO XP_TRST# Size ocument Number Rev FM R TRST# S(V.)P: should be routed as a single daisy chain to all loads and terminated at the end of the trace. Ω ± % pull down resistor. R()V.)P Thursday, February, ate: Sheet of

4 U UURNLE/LRKSFIEL PROESSOR (R) U M Q[:] M S M S M S M S# M RS# M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] F S_Q[] E S_Q[] F S_Q[] E S_Q[] S_Q[] E S_Q[] S_Q[] H S_Q[] G S_Q[] K S_Q[] J S_Q[] G S_Q[] G S_Q[] J S_Q[] J S_Q[] L S_Q[] M S_Q[] M S_Q[] L S_Q[] L S_Q[] K S_Q[] N S_Q[] P S_Q[] H S_Q[] F S_Q[] K S_Q[] K S_Q[] F S_Q[] G S_Q[] J S_Q[] J S_Q[] J S_Q[] J S_Q[] L S_Q[] K S_Q[] K S_Q[] L S_Q[] K S_Q[] L S_Q[] N S_Q[] M S_Q[] R S_Q[] L S_Q[] M S_Q[] N S_Q[] T S_Q[] P S_Q[] M S_Q[] N S_Q[] M S_Q[] T S_Q[] T S_Q[] L S_Q[] R S_Q[] P S_Q[] S_S[] S_S[] U S_S[] E S_S# S_RS# E S_WE# R SYSTEM MEMORY S_K[] S_K#[] S_KE[] S_K[] S_K#[] S_KE[] S_S#[] S_S#[] S_OT[] S_OT[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F H M G M N N F J N H K P T F H M H K N R Y W V V T Y U T U G T V M M M M M M M M M M M M M M M M M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS M QS M M M M M M M M M M M M M M M M M LK M LK# M KE M LK M LK# M KE M S# M S# M OT M OT M M[:] M QS#[:] M QS[:] M [:] M Q[:] M S M S M S M S# M RS# M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T T P R T W R Y S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_S[] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY - S_K[] S_K#[] S_KE[] S_K[] S_K#[] S_KE[] S_S#[] S_S#[] S_OT[] S_OT[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E H K H L R T F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M M M M M M M M M M M M M M M M M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS M QS M QS M QS M QS M QS M QS M QS M M M M M M M M M M M M M M M M M LK M LK# M KE M LK M LK# M KE M S# M S# M OT M OT M M[:] M QS#[:] M QS[:] M [:] larksfield/uburndale hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. larksfield/uburndale hannel Q[,,,,,,,,] Requires minimum mils spacing with all other signals, including data signals. UURN / QUNT OMPUTER Size ocument Number Rev FM ate: Thursday, February, Sheet of

5 PU ore Power +V_ORE UF +.V_VTT UURNLE/LRKSFIEL PROESSOR (GRPHIS POWER) G G G G G G G G G G F F F F F F F F F F Y Y Y Y Y Y Y Y Y Y V V V V V V V V V V U U U U U U U U U U R R R R R R R R R R P P P P P P P P P P V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V larksfield/uburndale PU ORE SUPPLY POWER SENSE LINES PU VIS.V RIL POWER VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ ISENSE VTT_SENSE VSS_SENSE_VTT +VTT_ +VTT_ VI VI VI VI VI VI VI PRSLPVR TP_VSS_SENSE_VTT H_PSI# VI VI VI VI VI VI VI PRSLPVR H_VTTVI I_MON VTT_SENSE UURNLE/LRKSFIEL PROESSOR (POWER) PSI# VI[] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET V_SENSE VSS_SENSE H H H H J J H H G G G G F F F F E E F E Y W U T J J J J U U U U U +.V_VTT VTT_,VTT_: R(V.)P Why add ohm?? Is it trace width control?? VTT_,VTT_:(Intel feedback) They are connected to hidden page for intel validation purpose. N K K K L L M M M G N J J T VSS_SENSE_VTT: S(V.)P onnect VSS_SENSE_VTT to GN or can be left floating. Note: R has the VSS_SENSE_VTT floating. U U U +.V_VTT +V_ORE +.V_VTT VTT_SELET: High level.v for uburndale Low level.v for larksfield R /F R /F U U U U *U_N U U V_SENSE & VSS_SENSE: S(V.)P - ±% pull-down to GN near processor VSENSE VSSSENSE U *U_N U U U PRO_PRSLPVR: S(V.)P: It is important to have the resistor stuffing options in the design for the Turbo functionality. The stuffing and no-stuffing of the resistors will depend on the PO configuration of U and F R(V.)P: uses K pull-up and pull-down resistors R default setting is "" T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H G G G F E E UG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ larksfield/uburndale GRPHIS FI PEG & MI POWER SENSE LINES GRPHIS VIs VI VI VI VI VI VI VI PRSLPVR H_PSI# Note: For Validating IMVP VR R should be STUFF and R NO_STUFF R -.V RILS.V.V VXG_SENSE VSSXG_SENSE GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON R K R *K_N VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL R K R *K_N R T M P N P M P N R T M J F E E Y W W U T T P N N L H P N L K J J J H H H L L M R K R R *K_N U U +.V_VTT R *K_N R K *K/F_N R *K_N R K U U GFX_VI[..],GFX_VR_EN,GFX_PRSLPVR,GFX_IMON: ould this be left unconnected when not in use? GFX_VI[..],GFX_VR_EN,GFX_PRSLPVR,GFX_IMON:(Intel feedback) Yes, see G rev. U U R K R *K_N U U U.U R *K_N R K U + U. +.V_VTT + *U_N. +.V_RUN.U R K R *K_N +.V_SUS U U U R *K_N R K U +V_ORE U U U U + *U_N U U UURN / U U U U + *U_N U U U U QUNT OMPUTER U U U U U U U U U U U U U U Size ocument Number Rev FM Thursday, February, ate: Sheet of

6 UURNLE/LRKSFIEL PROESSOR (GN) UH UI UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) UE T T R R R R R R R R R R R R P P P P P P P N N N N N M M M M M M M M M M L L L L L L L L L K K K K K J J J J J J J J J H H H H H H H H H H H H H H H H G F F F E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E E E E E E E E E E Y Y Y W W W W W W W W W W W V U U U T T T T T T T T T T T R P P P N N N N N N N N N N N M L L L L L L K K K K K K K J J J J H H H H H H H H H H H H H G G G G G G F F F F F F E E E E E E E E E E E VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R +M_VREF_Q_IMM +M_VREF_Q_IMM R R FG FG FG FG TP_RSV_R TP_RSV_R P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV J S_IMM_VREF H S_IMM_VREF G RSV G RSV E RSV E RSV M FG[] M FG[] P FG[] L FG[] L FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[] J FG[] N FG[] N FG[] J FG[] J FG[] J FG[] K FG[] H RSV_TP_ RSV RSV RSV RSV U RSV T RSV RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ larksfield/uburndale RESERVE RSV RSV RSV RSV RSV RSV_NTF_ RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_ KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS J J H K L R J J P T T R L L P P L T T P R T T P R R E F J H R R G E V V N W W N E P RSV_R RSV_R R R R an be left N is Intel RM implementation; ES/G recommendation to GN larksfield/uburndale larksfield/uburndale The larkfield processor's PI Express interface may not meet PI Express. jitter specifications. Intel recommends placing a.k +/- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. FG FG FG FG R *.K/F_N R *.K/F_N R.K/F R *.K/F_N PIE LNE is Lane Numbers Reversed FG (isplay Port Presence) FG (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed QUNT OMPUTER UURN / Size ocument Number Rev FM ate: Thursday, February, Sheet of

7 IEX PEK-M (MI,FI,GPIO) LKRUN# PH_PWRG IH_RSMRST# LN_RST# MI_RXN MI_RXN MI_RXN MI_RXN MI_RXP MI_RXP MI_RXP MI_RXP MI_TXN MI_TXN MI_TXN MI_TXN MI_TXP MI_TXP MI_TXP MI_TXP, XP_RESET# PH_PWRG PM_RM_PWRG IH_RSMRST# SUS_PWR_K SIO_PWRTN# _PRESENT +.V_VIO R +.V_RUN./F MI_ZOMP S(V.) P PWROK and SYS_PWROK should be tied together on the platform.mepwrok can be connected to PH_PWROK pin on PH when Intel MT is not enabled. MEPWROK S(V.)P: It can be connected to PH_PWROK pin on PH when Intel MT is not enabled. R R R R R R R K/F K/F K/F K/F SYS_PWROK PWROK MEPWROK LN_RST# IH_RSMRST# PM_TLOW# PM_RI# LN_RST# G(V.) P If integrated LN is not used, recommend to connect LN_RST# to GN via an.-kω to -kω pull-down resistor. ES(V.)P must be grounded if Intel LN is disabled. PM_RI# PIE_WKE# U MIRXN J MIRXN W MIRXN J MIRXN MIRXP G MIRXP MIRXP G MIRXP E MITXN F MITXN MITXN E MITXN MITXP H MITXP MITXP MITXP H F T M K M P P F MI_ZOMP MI_IROMP SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# PWRTN# PRESENT / GPIO TLOW# / GPIO RI# IbexPeak-M_RP MI System Power Management SUS_PWR_N_K / GPIO R R K/F K +.V_SUS FI FI_RXN FI_RXN H FI_RXN FI_RXN J FI_RXN FI_RXN E FI_RXN FI_RXN FI_RXP FI_RXP F FI_RXP FI_RXP G FI_RXP W FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN FI_FSYN FI_LSYN FI_LSYN WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SLP_S# SLP_M# PMSYNH PM_TLOW# LKRUN# RSV_LPP# IH_SUSLK SLP_S#_R SLP_S#_R SLP_S#_R SLP_M#_R PM_SLP_LN#_R +.V_SUS PM_TLOW#: ES(V.)P: K~K (+.V_SUS) R(V.)P:.K (+.V_LW) PM_TLOW#:(Intel feedback) K ~ K is a simulation result, the expected value should be K internal pull high in PH. PWROK.K is external pull high. S(V.)P:. kω to kω pull-down resistor to GN. PWROK and SYS_PWROK should be tied together on the platform. TP SLP_LN# / GPIO J F H J G J Y P F E H P K N J F R G(V.)P: If the LVS interface is not implemented, all signals associated with the interface can be left as No onnects. The supply pins VccTX_LVS and V_LV can be connected to ground. G(V.) P:FI_FSYN[], FI_FSYN[], FI_LSYN[], FI_LSYN[], and FI_INT signals on PH side can be left as no connect without any power or functional impact. T R.K/F T R T T T PIE_WKE#,,, LKRUN# SIO_SLP_S# SIO_SLP_S# SIO_SLP_S# PM_SYN R K G(V.)P: If the RT interface is not implemented, all signals associated with the interface can be left as No onnects. The pins RT_IRTN onnect this signals to GN and _IREF onnect to GN via a. k ±.% pull-down resistor IEX PEK-M (LVS,I) U T L_KLTEN T L_V_EN Y L_KLTTL L LK Y L T L_TRL_LK V L_TRL_T P LV_IG P LV_VG T LV_VREFH T LV_VREFL V LVS_LK# V LVS_LK LVS LVS_T# LVS_T# Y LVS_T# V LVS_T# LVS_T LVS_T Y LVS_T V LVS_T P LVS_LK# P LVS_LK Y LVS_T# T LVS_T# U LVS_T# T LVS_T# Y LVS_T T LVS_T U LVS_T T LVS_T RT_LUE RT_GREEN RT_RE V RT LK V RT T Y RT_HSYN Y RT_VSYN _IREF RT_IRTN RT IbexPeak-M_RP igital isplay Interface SVO_TVLKINN J SVO_TVLKINP G SVO_STLLN J SVO_STLLP G SVO_INTN F SVO_INTP H SVO_TRLLK T SVO_TRLT T P_UXN G P_UXP J P_HP U P_N P_P P_N J P_P G P_N P_P P_N W P_P P_TRLLK Y P_TRLT P_UXN E P_UXP P_HP V P_N E P_P P_N F P_P H P_N P_P P_N P_P P_TRLLK U P_TRLT U P_UXN P_UXP P_HP T P_N J P_P G P_N J P_P G P_N F P_P H P_N E P_P IEX PEK-M / QUNT OMPUTER Size ocument Number Rev FM isplay port isplay port isplay port SVO ate: Thursday, February, Sheet of

8 +RT_ELL R K/F PF IEX PEK-M (H,JTG,ST) U Y.KHZ R M U R M R K/F U PF ap values depend on Xtal +RT_ELL R K RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN RT LP FWH / L FWH / L FWH / L FWH / L FWH / LFRME# LRQ# LRQ# / GPIO SERIRQ F LP_L, LP_L, LP_L, LP_L, LP_LFRME#, IRQ_SERIRQ IH_Z_OE_ITLK R Z_IT_LK INTVRMEN(Internal Voltage Regulator Enable) : This signal enables the internal. V regulators. This signal must be always pulled-up to VccRT. SPKR Z_IT_LK Z_SYN SPKR P H_LK H_SYN SPKR STRXN STRXP STTXN STTXP K K K K ST_RX- ST_RX+ ST_TX- ST_TX+ ST H, IH_Z_OE_SYN IH_Z_OE_RST# IH_Z_OE_SOUT *P_N Z_SYN Z_RST# Z_SOUT Place all series terms close to PH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point. asically, keep the same distance from T for all series termination resistors. R R R Flash escriptor Security Override GPIO Low = Enabled High = isabled R *K/F_N GPIO (Internal K/F pull high to +.V_RUN) IH_Z_OE_SIN K_LE_ET Z_RST# Z_SOUT GPIO G F E F H J H_RST# H_SIN H_SIN H_SIN H_SIN H_SO IH H_OK_EN# / GPIO H_OK_RST# / GPIO ST STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP H H H H F F F F H H F F ST port / are not support in HM. They are only in PM ST_RX- ST_RX+ ST_TX- ST_TX+ ST_RX- ST_RX+ ST_TX- ST_TX+ ST O istance between the PH and cap on the "P" signal should be identical distace between the PH and cap on the "N" signal for the same pair. E-ST Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. +.V_RUN SPKR R *K_N No Reboot strap. SPKR Low = efault. High = No Reboot. T T T T T SPI_LK SPI_S# SPI_SI T SPI_SO PH_JTG_TK_UF PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# SPI_LK SPI_S# SPI_S# SPI_SI SPI_SO M JTG_TK K JTG_TMS K JTG_TI J JTG_TO J TRST# SPI_LK V SPI_S# Y SPI_S# Y SPI_MOSI V SPI_MISO IbexPeak-M_RP SPI JTG STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# STGP / GPIO STGP / GPIO F F T Y V ST_OMP ST_T# R R R R K/F K/F./F K +.V_RUN +.V_PH +.V_RUN ST_T# JTG Test Pads are need to put on the same side of mother board. IEX PEK-M / QUNT OMPUTER Size ocument Number Rev FM Thursday, February, ate: Sheet of

9 LK_LP_EUG R /F LK_PI_ LK_PI_F R /F LKOUT_PI[..]: ohm series resistor is recommend (single & double load) on PG v. LK_LP_EUG LK_PI_ US_MR_ET# GNT# PH_IRQH_GPIO PIRST#: G(V.) P an be left unconnected. PR: S(V.) P an be left unconnected if not using PI. PME: G(V.) P an be left unconnected. Reserve capacitor pads for improving WWN. *P_N *P_N T T T T T T T T T T T R /F PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ# REQ# S_WWN_PIE_RST# US_MR_ET# PI_GNT# GNT# GNT# S_WPN_PIE_RST# S_WLN_PIE_RST# PIRQG# PH_IRQH_GPIO PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# PME# PI_PLTRST# RSV_SMLERT# RSV_IH_L_RST# IH_SMLK IH_SMT SM_LK_ME SM_T_ME SM_LK_ME SM_T_ME LP_SPI_INTR# IEX PEK-M (PI,US,NVRM) LK_LP_EUG_ LK_PI LK_PI_F_ K/F K/F.K/F.K/F.K/F.K/F.K/F.K/F K/F H N J E H E M M F M M J K F K M J K L F J G F M H J G H G G H F M F K F H K K E E H F M N P P P P UE IbexPeak-M_RP +.V_SUS R R R R R R R R R /E# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ# REQ# / GPIO REQ# / GPIO REQ# / GPIO GNT# GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PIRST# SERR# PERR# IRY# PR EVSEL# FRME# PLOK# STOP# TRY# PME# PLTRST# LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI PI NVRM US PIRQG# S_WPN_PIE_RST# S_WWN_PIE_RST# S_WLN_PIE_RST# NV_E# NV_E# NV_E# NV_E# NV_QS NV_QS NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#_RE# NV_WR#_RE# NV_WE#_K NV_WE#_K USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USRIS# USRIS O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO Y P V G P P T T V E J J G Y U V Y Y V F H J N P J L F G M N H J E F G H L M N J F L E G F T R R R R US_IS O# O# O# O# O# O# O# O# +.V_RUN NV_LE NV_LE IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ IH_USP- IH_USP+ O# O# Left Side pair Top Left Side pair bottom Right Side pair top (able) Mini ard (WLN) Mini ard (WWN) MiniWWN MiniWLN Express ard Giga it LOM US port / are not support in HM. They are only in PM PIE_RX-/GLN_RX- PIE_RX+/GLN_RX+ PIE_TX-/GLN_TX- PIE_TX+/GLN_TX+ PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ PIE_RX- PIE_RX+ PIE_TX- PIE_TX+ LK_PIE_MINI# LK_PIE_MINI LK_PIE_REQ# IH_USP- MINILK_REQ# IH_USP+ amera IH_USP- IH_USP+ Touch Screen Module LK_PIE_EXPR# Express ard LK_PIE_EXPR O#~O#: G(V.)P Pin efault Port Mapping O# Port,Port O# Port,Port.K/F.K/F.K/F.K/F R./F Mini ard (WPN) Express ard Note : place these resistors near to PIe Slots Place TX blocking caps close PH. ard Reader +.V_SUS +.V_RUN MiniWWN MiniWLN ard Reader Giga it LOM R R R R R LK_PIE_MINI# LK_PIE_MINI R_LK_REQ# LK_PIE_R_REER# LK_PIE_R_REER K K K K K LK_PIE_REQ# LK_PIE_LOM# LK_PIE_LOM LOM_LK_REQ# MINILK_REQ# R_LK_REQ# LK_PIE_REQ# LK_PEG_REQ# LOM_LK_REQ#.U.U.U.U.U.U.U.U.U.U LK_PIE_REQ# LK_PIE_REQ# MINILK_REQ# R_LK_REQ# LK_PIE_REQ# LOM_LK_REQ# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PI-E port / are not support in HM. They are only in PM LK_PEG_REQ# R R R R R R PIELKRQ{,,,,,}# should have a K pull-up to +V..PIELKRQ{,} should have a K pull-up to +.S IEX PEK-M (PI-E,SMUS,LK) G J F H W U T U V E F H G J W T U U V G J G J K K P M M U M M N H H M M M J J H K K P U PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP PI-E* PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO From LK UFFER lock Flex SMus ontroller PEG IbexPeak-M_RP LKOUT_PEG P/N,LKOUT_PEG P/N, LKOUT_MI_P/N,support GEN- and GEN- Link +.V_SUS SMLERT# / GPIO SMLK SMT SMLLERT# / GPIO SMLLK SMLT SMLLERT# / GPIO SMLLK / GPIO SMLT / GPIO L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N / LKOUT_LK_N LKOUT_P_P / LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N / KSS_N LKIN_ST_P / KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO H J G M E G T T T H N N T T W P P F E H H P J H H F T P T N RSV_SMLERT# IH_SMLK IH_SMT RSV_IH_L_RST# SM_LK_ME SM_T_ME LP_SPI_INTR# SM_LK_ME SM_T_ME PEG_LKREQ# LK_PI_F XLK_ROMP R LK_FLEX LK_FLEX LK_FLEX LK_FLEX T T T LKOUTFLEX: ES(V.) :support MHz MHz and.mhz. IH_SMLK,, IH_SMT,, SMLLK/SMLT: G(V.) P: The SMus signals (SM_T and SM_LK) cannot be connected to any other devices other than the PH. onnect the SM_T and SM_LK pins to the PH SMLT and SMLLK pins, respectively. T LK_PIE_VG# LK_PIE_VG LK_PIE_GPLL# LK_PIE_GPLL LK_UF_PIE_GPLL# LK_UF_PIE_GPLL LK_UF_LK_N LK_UF_LK_P LK_UF_REFLK# LK_UF_REFLK LK_UF_REFSSLK# LK_UF_REFSSLK LK_IH_M LKIN_PILOOPK: PG (V.): ohm series resistor is recommend G(V.) P: XTL_OUT and XTL_IN are the signal names for the PHY../F T T T T +.V_PH LKOUTFLEX[..]: PG v.: ohm series resistor is recommend (PI & non PI routing, single & double load) Non-iMT PEG_LKREQ# K/F R dd uffers as needed for Loading and fanout concerns. O# O# O# O# +.V_SUS RP PR-.K O# O# O# O# +.V_SUS R R R R K K K K LK_PIE_REQ# LK_PIE_REQ# PI_GNT# GNT# SM_LK_ME +.V_SUS Q NW--F Q NW--F SMLK.U PI_PLTRST# +.V_SUS U TSZFU(TL,F,T) PLTRST#,,,,,,, PH_IRQH_GPIO PI_REQ# PI_PIRQ# US_MR_ET# +.V_RUN PI_STOP# PI_PIRQ# PI_PIRQ# PI_IRY# +.V_RUN RP PR-.K RP PR-.K +.V_RUN PI_TRY# PI_FRME# REQ# PI_PIRQ# +.V_RUN PI_SERR# PI_PERR# PI_PLOK# PI_EVSEL# oot IOS Strap PI_GNT# GNT# oot IOS Location LP Reserved (NN) PI SPI SM_T_ME SMT IEX PEK-M / QUNT OMPUTER Size ocument Number Rev FM ate: Thursday, February, Sheet of

10 UF IEX PEK-M (GPIO,VSS_NTF,RSV) +.V_SUS, LN_PIE_PWR_TRL PIE_MR_ET# T_RIO_IS# WWN_RIO_IS# RIT_TEMP_REP# SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# TEST_WOOFER_EN WLN_RIO_IS# S_GPIO SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# RSV_WOL_EN *_N LN_PHY_PWR_TRL K TEST_WOOFER_EN STGP PIE_MR_ET#_R PIE_MR_ET# PIE_MR_ET# GPIO register not cleared by Fh reset event. GPIO reserve for internal VR. R US_MR_ET# R R *K_N R R R TP_PH_GPIO GPIO STGP STGP WLN_RIO_IS# R_SV_ET GPIO GPIO SV_SET_UP STGP GPIO GPIO US_MR_ET# Y J F T F Y H V M V V P H F F MUSY# / GPIO TH / GPIO TH / GPIO TH / GPIO GPIO GPIO GPIO GPIO GPIO GPIO MIS LN_PHY_PWR_TRL / GPIO GPIO STGP / GPIO TH / GPIO SLOK / GPIO STP_PI# / GPIO STLKREQ# / GPIO STGP / GPIO STGP / GPIO SLO / GPIO STOUT / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO STOUT / GPIO STGP / GPIO PU LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP GTE LKOUT_LK_N / LKOUT_PIEN LKOUT_LK_P / LKOUT_PIEP PEI RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP H H F F U M M G T E W Y Y V V F M PH_THRMTRIP#_R SIO_GTE LK_PU_LK# +.V_VTT LK_PU_LK H_PEI SIO_RIN# R /F H_PWRGOO, R./F (oth these should be close to PH) H_THERM TEST_WOOFER_EN R RSV_WOL_EN R TP_PH_GPIO R GPIO R GPIO R GPIO R LN_PHY_PWR_TRL R SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# PIE_MR_ET# PIE_MR_ET#_R WLN_RIO_IS# R_SV_ET R R R R R R R SIO_RIN# SIO_GTE STGP R R R STGP STGP R R STGP R US_MR_ET# R RIT_TEMP_REP# R K K/F K/F K/F K/F K/F K/F +.V_RUN K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F K/F TP N VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_ IbexPeak-M_RP NTF RSV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M N H T P MI Termination Voltage NV_LE NV_LE NV_LE Set to Vcc when LOW anbury Technology Enabled NV_LE Set to Vcc/ when HIGH R R High = Enable Low = isable *K_N *K_N +NVRM_VQ R R GPIO swap override Strap/Top-lock Swap Override jumper GNT# K/F *K/F_N GNT# Low = swap override/top-lock Swap Override enabled High = efault SV_SET_UP S_GPIO SV_SET_UP R R +.V_RUN K/F K/F -X High = Strong (efault) MUSY#: If not used, require a weak pull-up (.- KΩ to kω) to Vcc_. R(V.)P: it has K PU and ohm on this net for validation purpose. MUSY#:(Intel feedback) Follow R checklist, K is for intel IOS validation purpose. IEX PEK-M / QUNT OMPUTER Size ocument Number Rev FM ate: Thursday, February, Sheet of

11 IEX PEK-M (POWER) +.V_PH VPLLEXP = m max +.V_PH POWER_JP VIO =. max +.V_PH L +.V_VIO V_ =. max VORE=. max +.V_PH U U F F F F H H H H J J +.V_PH VPLLEXP: This pin can be left as no connect in On-ie VR enabled mode (default). PJP U VFIPLL = m max L *uh_n U +.V_RUN *uh_n.u +.V_LN_VPLL_EXP U VVRM =. max +.VS_.VS +.V_VFIPLL +.V_PH M *U_N VIO =. max +.V_PH *U_N U U K J N N N N N N J J T T U U V V W W E E G G H N N N T J +.V_PH +.V_RUN +.V_RUN +.V_RUN UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VFIPLL VIO[] IbexPeak-M_RP +.V_VPLL +.V_VPLL POWER V ORE PI E* FI RT LVS HVMOS MI NN / SPI +.VS_.VS +NVRM_VQ V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VME_[] VME_[] VME_[] VME_[] PH ES(V.) P +NVRM_VQ:. V supply for ual hannel NN interface. This power is supplied by core well. If unused, this pin should be connected to Vcc_. L L R R R R R uh uh *_N *_N *_N + U E E F F H H P P T T T T U M K K K K K M M M M M P P +V +.V_RUN UJ VLK = m max +.V_PH L *uh_n +.V_LN_V_LK P +.V_PH VIO =. max VLK[] VIO[] V VIO[] V P VLK[] VIO[] Y *U_N *U_N U VME =. max VIO[] Y +.V_PH F +.V_SUS VSUS_ =. max VLN[] VSUS_[] V VSUS_[] U F VSUS_[] U VLN[] VSUS_[] U U PSUSYP VSUS_[] P Y.U.U PSUSYP VSUS_[] P VSUS_[] N V_ =. max VSUS_[] N VME[] VSUS_[] M +.V_RUN.U VSUS_[] M VME[] VSUS_[] L VSUS_[] L.U VME[] VSUS_[] J VSUS_[] J F VME[] VSUS_[] H VSUS_[] H F VME[] VSUS_[] G VSUS_[] G F VME[] VSUS_[] F VSUS_[] F V VME[] VSUS_[] E VSUS_[] E +.V_PH V VVRM =. max VME[] VSUS_[] +.VS_.VS VSUS_[] V VME[] VSUS_[] VMI =. max U VSUS_[] U U Y VME[] VSUS_[] R +.V_VTT Y VME[] VSUS_[] U R *_N +.V_PH Y +.V_PH VIO =. max VME[] VIO[] V U +VREF_SUS VREF_SUS F R +V_SUS VREF_SUS>m.U PRT V RV- PRT +.V_SUS U VPNN =. max +NVRM_VQ VME_ =. max +.V_RUN VME_: ES(V.)P:supply for the Intel Management Engine.This is a separate power plane that may or may not be powered in S S states. This plane must be on in S and other times the Intel Management Engine is used. U.U.U.U U.U L HKF-T +.VS_.VS VPLL =. max +.V_VPLL VPLL =. max +.V_PH +.V_SUS +.V_RUN +.V_VTT +RT_ELL +.V_VPLL VIO =. max PSST PSUS VSUS_ =. max V_ =. max V_PU>m V = m max U.U.U U U.U.U U.U.U.U.U U H J H F H F V Y P U U U V V Y T U.U VVRM[] VPLL[] VPLL[] VPLL[] VPLL[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] PSST PSUS VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_PU_IO[] V_PU_IO[] VRT IbexPeak-M_RP POWER lock and Miscellaneous RT PU PI/GPIO/LP ST PI/GPIO/LP US H VREF V_[] V_[] V_[] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VIO[] VVRM[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VME[] VME[] VME[] VME[] VSUSH K J L M N P U K K H T H F F F H Y Y L +VREF *U_N U.U.U +.VS_.VS +.V_PH +.V_VSTPLL *U_N VVRM =. max U +.V_RUN VIO =. max VME =. max R R RV- U L +.V_SUS +V_RUN +.V_RUN V_ =. max *uh_n VREF>m +.V_PH +.V_PH VSUSH = m max + U U VRT = m max IEX PEK-M / QUNT OMPUTER Size ocument Number Rev FM Thursday, February, ate: Sheet of

12 Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IEX PEK-M / Thursday, February, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IEX PEK-M / Thursday, February, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM IEX PEK-M / Thursday, February, IEX PEK-M (GN) UI IbexPeak-M_RP UI IbexPeak-M_RP VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] G VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] N VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U VSS[] U VSS[] U VSS[] P VSS[] V VSS[] P VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[] F VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[] H VSS[] J UH IbexPeak-M_RP UH IbexPeak-M_RP VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] U VSS[] M VSS[] V VSS[] M VSS[] M VSS[] VSS[] N VSS[] N VSS[] N VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] F VSS[] W VSS[] W VSS[] W VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] U VSS[] N VSS[] VSS[] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[] H VSS[] VSS[] VSS[]

13 R R +.V_SUS U +.V_RUN K/F_ K/F_ U M [:] M S M S M S M S# M S# M LK M LK# M LK M LK# M KE M KE M S# M RS# M WE#,, E_SMLK,, E_SMT U M OT M OT M M[:] M QS[:] M QS#[:].U/.V_.U U +.V_R_VTT M M M M M M M M M M M M M M M M IMM_S IMM_S E_SMLK E_SMT M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# Place these aps near So-imm. U U.U U.U U.U.U.U U JIM /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# + U. P R SRM SO-IMM (P) S-URN-F +SMR_VREF_IMM.U/.V_.U/.V_.U U Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q U.U U U M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q,, E_SMLK,, E_SMT R M Q[:] +.V_RUN PM_EXTTS#, R_RMRST# P/V *K/F_N +SMR_VREF_Q +SMR_VREF_IMM U +.V_SUS E_SMLK E_SMT R R R +.V_SUS PM_EXTTS# U V SL S *K/F_N R RH RW GN ISLWIEZ-TK +.V_SUS *_N JIM V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS +.V_SUS +SMR_VREF_IMM +R_VTTREF +M_VREF_Q_IMM +SMR_VREF_Q P R SRM SO-IMM (P) S-URN-F R U.K/F R.K/F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT G G G G + - SIO_SLP_S# +.V_SUS U OPN/K +.V_R_VTT R IMM- PP_SGT +.V_RUN +V_LW QUNT OMPUTER *K/F_N PM_EXTTS# Intel is requesting that customers implement all methods (M and M and M described below) to generate and control Reference voltage for ata/strobe inputs (VREFQ) on larksfield based platforms. for fine tuning of the VREFQ levels to optimize the voltage and timing margins. M:Fixed voltage resistor divider or R Voltage Regulator drives the Vref M: set of igital potentiometers and op amps are added on the motherboard (one pair for each channel). This circuit is controlled by SMUS (SM_LK & SM_T) on PH. M:Intel investigating future processor VREF_Q generation to replace M and M. This would require routing processor signal balls J and H to SO-IMM connectors directly. NW--F Q R. *U_N R R R K R R M PP_SGT +SMR_VREF_Q *_N NW--F Q Size ocument Number Rev FM ate: Thursday, February, Sheet of

14 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M QS M QS M QS M QS M QS M QS M QS M QS M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S IMM_S PM_EXTTS# PM_EXTTS# E_SMT E_SMLK E_SMLK E_SMT M [:] M S M S M S M S# M S# M LK M LK# M LK M LK# M KE M KE M S# M RS# M WE# M QS[:] M QS#[:] M M[:] M OT M OT M Q[:] R_RMRST#, PM_EXTTS# PP_SGT E_SMLK,, E_SMT,, E_SMLK,, E_SMT,, +.V_SUS +.V_RUN +.V_R_VTT +SMR_VREF_IMM +.V_RUN +.V_SUS +.V_R_VTT +SMR_VREF_IMM +.V_RUN +.V_RUN +SMR_VREF_Q +SMR_VREF_Q +SMR_VREF_IMM +.V_SUS +.V_SUS +.V_SUS +M_VREF_Q_IMM +SMR_VREF_Q Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R IMM- Thursday, February, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R IMM- Thursday, February, Size ocument Number Rev ate: Sheet of QUNT OMPUTER FM R IMM- Thursday, February, Place these aps near So-imm..U/.V_.U/.V_ U U.U.U.U.U + - U OPN/K + - U OPN/K U U + U. + U. R *K/F_N R *K/F_N R *_N R *_N R K/F_ R K/F_ P R SRM SO-IMM (P) JIM S-URN-F P R SRM SO-IMM (P) JIM S-URN-F V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT G G G G U U.U.U R K/F_ R K/F_ U U R R U ISLWIEZ-TK U ISLWIEZ-TK V GN SL S RW RH R R.U.U R *_N R *_N.U.U R.K/F R.K/F R.K/F R.K/F U U U U *U_N *U_N U U U U Q NW--F Q NW--F U U.U/.V_.U/.V_ U U U U.U.U.U.U U U.U/.V_.U/.V_ R. R..U.U U U U U P R SRM SO-IMM (P) JIM S-URN-F P R SRM SO-IMM (P) JIM S-URN-F /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q U U

15 +.V_RUN LLMPGSN K_PWRG_R LK_IH_M +.V_RUN Realtek:.uFxpcs, ufxpcs IT:.uFxpcs, ufxpcs U/.V.uF near the every power pin. LK_IH_M mil +.V_LK_V +VIO_LK.U.U.U.U.U V_REF V_SR_IO K R K R PU_SEL U V_US V_L V_SR V_PU V_PU_IO VSS_ST VSS_US VSS_L VSS_SR VSS_PU VSS_REF PU_STOP# K_PWRG/P#_. REF_/PU_SEL QFN PU- PU-# PU- PU-# OTT_LPR OT_LPR SR- SR-# ST ST# MHz_nonSS MHz_SS LK_UF_LK_P LK_UF_LK_N LK_UF_REFLK LK_UF_REFLK# LK_UF_PIE_GPLL LK_UF_PIE_GPLL# LK_UF_REFSSLK LK_UF_REFSSLK# LK_VG_M_R LK_VG_M_SS_R Place within." of LKGEN R R LK_UF_LK_P LK_UF_LK_N LK_UF_REFLK LK_UF_REFLK# LK_UF_PIE_GPLL LK_UF_PIE_GPLL# LK_UF_REFSSLK LK_UF_REFSSLK# LK_VG_M LK_VG_M_SS Place the ohm resistors close to the K,, E_SMT,, E_SMLK XTL_OUT XTL_IN E_SMT E_SMLK XOUT XIN ST SLK GN SLGSPVTR Realtek:.uFxpcs, ufxpcs IT:.uFxpcs, ufxpcs +.V_RUN +VIO_LK dd capacitor pads for improving WWN. LK_IH_M XTL_IN Y XTL_OUT +.V_PH R *_N LLMPGSN mil *P_N P.MHZ P R SLG,IT: +.V Realtek: +.V U HP: u xpcs.u.u Place each.uf cap as close as possible to each V IO pin. Place the uf caps on the V_IO plane. +.V_RUN R *.K_N PU_SEL R.K *P_N EMI apacitor PIN PU_ PU_ (default) MHz MHz (.V-.V) MHz MHz PU_SEL: SLG date sheet (V.) P: High Voltage: Min.V, Max.V. Low Voltage: Min Vss-.V, Max.V. Realtek date sheet(v.) P: High Voltage: Min.V, Max.V. Low Voltage: Min Vss-.V, Max.V. IT date sheet(v.) P: High Voltage: Min.V, Max.V. Low Voltage: Min Vss-.V, Max.V. +VIO_LK: SLG date sheet (V.) P: Min.V,Max.V. Realtek date sheet(v.) P: Min.V,Max.V. IT date sheet(v.) P: Min.V,Max.V. lock Generator QUNT OMPUTER Size ocument Number Rev FM ate: Thursday, February, Sheet of

16 U PIE_MTX_GRX_P[..] PRT OF PIE_MRX_GTX_P[..] PIE_MTX_GRX_N[..] PIE_MRX_GTX_N[..] LK_PIE_VG LK_PIE_VG# PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N PIE_MTX_GRX_P PIE_MTX_GRX_N MHz (+/- ppm) input frequency, -. V single-ended swing. clock must be provided less than ns after LKREQ# is asserted F E E Y Y W W V V U U T T R R P P N N M M L L K K K PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_REFLKP PIE_REFLKN PI-EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_LRN PIE_LRP H G G F F F Y Y Y Y W W V U U U T T T T P P P P M N Y PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX P PIE_MRX_GTX N PIE_LRN PIE_LRP.K R.K R (.V) +PIE_V PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P PIE_MRX_GTX_P.U.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_P.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX_N.U PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX P PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N PIE_MRX_GTX N,,,,,,, PLTRST# L PERST M-S/M-XT M-S XT JT -G(-) M-S JT -G(-) QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev FM ate: Thursday, February, Sheet of

17 MEMORY SIZE M M M M +.V_ELY GPIO Straps table GPIO GPIO GPIO GPIO GPIO GPIO GPIO +.V_ELY MEMORY PERTURE SIZE SELET R R R R R R R R R R R R R R FG FG FG FG GPIO GPIO GPIO GPIO R R R K *K_N *K_N RM_FG RM_FG RM_FG ESRIPTION OF EFULT SETTINGS GPIO() - TX_PWRS_EN (Transmitter Power Savings Enable) : % Tx output swing for mobile mode : full Tx output swing (efault setting for esktop) GPIO() - TX_EEMPH_EN (Transmitter e-emphasis Enable) : Tx de-emphasis disabled for mobile mode : Tx de-emphasis enabled (efault setting for esktop),, GFX_ON FM setting *.U_N R +.V_ELY *K/F_N OPTIONL R NETWORK TO FINE TUNE POWER SEQUENING *.U_N R Q *SIS-T-E_N RM_TYPE_FG RM_TYPE_FG RM_TYPE_FG GPIO() - IF_GEN_EN (. GT/s Enable) : efault. (river ontrolled Gen) : Strap ontrolled Gen s M design, for GPIO use R *_reserve TI reserved configuration straps. OS_SPRE TI reserved configuration straps. GPIO GPIO GPIO TT R *_N GPIO : attery saving mode =. V LK_VG_M_SSIN_R GPIO LK_VG_M_SS : (Performance mode) =. V GPIO GPIO R TI Internal use only GFX_ORE_NTRL *K_N PNEL_KEN R HMI_H_EN R /F LK_VG_M T P T P R /F RM_FG RM_FG *K_N GPIO RM_FG *K_N GPIO OS_OUT XTLIN T P *K_N GPIO R *R_reserve GFX_ORE_NTRL *K_N GPIO LK_VG_M_SSIN_R *K_N GPIO R R */F_reserve R THERML_INT# *_N *K_N GPIO *M_reserve T P Y TEMP_FIL XTLOUT GFX_ORE_NTRL R *_reserve _EN K HMI_H_EN *MHZ_reserve T P *K_N TEMP_FIL GFX_LKREQ# K GFX_LKREQ# R K K VGVSYN T P K VGHSYN R *M_reserve T P T P T P *K_N VGVSYN *P_reserve *P_reserve *K_N VGHSYN K TEMP_FIL R *K_N Q *NW--F_N +.V_RUN For Park S: Install ll components in this ox L,,,,L,,,,R, R,R,R R P_V# and P_V# are for Future SI For M-S: O NOT Install any omponent in this ox. +.V_RUN_GFX +PIE_V L L *LMSN_N *LMSN_N +P_V +P_V *U_N *U_N R *_N R R R *_N *_N *_N *_N U PRT OF VP PORT U VPLK VPNTL_ Y VPNTL_ U VPNTL_ VPNTL_MVP_ Y VPNTL_MVP_ Y VPT_ V VPT_ Y VPT_ V VPT_ VPT_ W VPT_ VPT_ W VPT_ VPT_ W VPT_ VPT_ W VPT_ VPT_ VPT_ VPT_ VPT_ E VPT_ VPT_ E VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ I/O U GPIO_ U GPIO_ T GPIO_ U GPIO SMT U GPIO SMLK T GPIO TT T GPIO TH T GPIO LON P GPIO ROMSO P GPIO ROMSI P GPIO ROMSK N GPIO_ N GPIO_ N GPIO_ Y GPIO HP N GPIO PWRNTL_ M GPIO SSIN R GPIO THERML_INT W GPIO HP M GPIO TF P GPIO PWRNTL_ P GPIO EN N GPIO ROMS N GPIO LKREQ L JTG_TRST L JTG_TI L JTG_TK L JTG_TMS K JTG_TO R R G G HSYN VSYN V VSSQ VI VSSI RSET R R G G HSYN VSYN Y OMP M K L J H G H J G E E RSET M K L J K L L J H M J +.V_RUN_GFX V=m max *.U_N HP +.V_RUN_GFX VI=m max *.U_N R R VG_RE VG_RE VG_GRN VG_GRN VG_LU VG_LU VGHSYN VGHSYN VGVSYN VGVSYN R /F R /F R K VG_LU VG_GRN VG_RE R /F Q MMST--F +.V_ELY +.V_ELY IS only Layout Note: Place ohm termination resistors close to TI HIP. R K Q TTUT R K HMI_ET Spread Spectrum If U, the discrete spread spectrum chip is not used, then pop R in order to pull-down XTLOUT for EMI reasons. R OS_OUT *K_reserve U XIN/LKIN XOUT +.V_RUN R *K_reserve R *K_reserve +.V_RUN_GFX R /F R /F T T T T T HP P P P P P VREFG W W W GENERI GENERI GENERI GENERI GENERIE_HP HP VREFG V VQ E E +V nf.u U +VQ.U U L.uF L LMSN V=m max +.V_RUN_GFX LMSN VQ=m max OS_SPRE R *_reserve VSS SO SSLK +VL V L +.V_RUN *LMS_reserve.U P# *U_reserve *.U_reserve REFLK T P *PGF-SR_reserve S T T P P N RESERVE N_PWRGOO RSV# RSV# VSSQ VI E Keep VSSQ away from noisy ground. +VI L +.V_RUN_GFX LMSN VI=m max +.V_RUN_GFX R R R -.% (OWN) T P ENV R I_PWM K RM_TYPE_FG RM_TYPE_FG *K_N R *K_N RM_TYPE_FG R K K T T P P L N F N# N# RSV# RSV# RSV# TESTEN VSSI RSET G RSET nf Place very close to SI balls. R.U U Memory Straps MHz M(M*) Samsung MHz M(M*) Hynix RM_TYPE _FG RM_TYPE _FG RM_TYPE Quanta PN _FG (Quantauy) KLGGT KLZGTW Quanta PN (Winuy) Vendor PN KWGE-H HTQGFR- level PN M-S/M-XT QUNT OMPUTER VG-M-XT (PIe) Size ocument Number Rev FM Thursday, February, ate: Sheet of