UM8 UMA SYSTEM DIAGRAM

Transcript

1 +V/+V PG. PG. +.0V/+.V PG. PU ore PG. VG ore/+.v PG. +.V/+0.V PG. +.0VTT PG. UM VGORE harger LN PG. LNE theros/r 0/00 K ITE 0 PG. UM UM SYSTEM IGRM SOIMM Max. G PG. SOIMM Max. G PG. M ROM PG. LNEO WWN PI-E x PI-E x LNE est SNLVP ombo port PG. K TP M ROM PG. LNE WLN PG. R hannel R hannel US.0 PORT US.0 PORT US.0 PORT LP INTEL rrandale.mm X.mm pin PG TP W FI PG.~ MI INTEL PH Ibex Peak-m mm X mm 0pin FG TP W PG.~ zalia UIO OE L-GR ST0 ST US.0 US.0 X ard Reader RTS Speaker HP/MI PIVPLSZE PG. H O PORT0,, PORT PG. nalog MI PG. PG. US.0 X PG. T T HMI RT LVS PORT0,, PORT PG. FN & THERML GMT G0/ EM--IZL-TR PG.0 Webcam.MHz LOK GEN PG. PORT PG. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev LOK IGRM ate: Wednesday, February 0, 00 Sheet of HMI RT LVS PG. PG. Stackup TOP V IN IN GN OT

2 m +.0V_PH +VIO_LK L 0.U/ 0V/XR H0KF-T_ 0 0.U/ 0V/XR 0U/.V_/XR Place each 0.uF cap close to pin 00m +.V_RUN +VSE_LK L 0 H0KF-T_ U/.V_/XR 0.U/ 0VXR 0.U/ 0V/XR 0.U/ 0V/XR 0.U/ 0V/XR 0.U/ 0V/XR P (Power ap quantities follow UM) 0 /0 Wait Victor check Place each 0.uF cap close to pin +VSE_LK heck LK P/N and footprint U V_L V_REF PU-0 PU-0# LK_UF_LKP_R LK_UF_LKN_R Place within 0." of /G RP 0X LK_UF_LKP LK_UF_LKN +VIO_LK,0 SMT,0 SMLK +.V_RUN R LK_PH_M R LK_PH_M *0P/0V N/OG Place R0 within 0." of /G 0K /J_ PU_SEL K_PWRG_R XTL_OUT XTL_IN 0 V_US V_SR V_PU V_PU_IO V_SR_IO ST SLK PU_STOP# REF_0/PU_SEL K_PWRG/P#_. XOUT XIN VSS_ST VSS_US VSS_L LRS LRS QFN PU- PU-# OTT_LPR OT_LPR SR- SR-# 0 ST 0 ST# MHz_nonSS MHz_SS GN VSS_REF VSS_PU VSS_SR LK_UF_REFLKP_R LK_UF_REFLKN_R LK_UF_PIE_GPLLP_R LK_UF_PIE_GPLLN_R LK_UF_REFSSLKP_R LK_UF_REFSSLKN_R iscrete only RP RP RP 0X 0X 0X LK_UF_REFLKP LK_UF_REFLKN LK_UF_PIE_GPLLP LK_UF_PIE_GPLLN LK_UF_REFSSLKP LK_UF_REFSSLKN SLG: SLGSP0VTR Seligo QPN: LSP0000 SLG: SLGSPVTR Seligo QPN: LSP000 RS: RTMN--V-GRT Realtek QPN: L V_RUN R0 *0K_N OM check +.V_RUN R0 K/J_ XTL_IN Y XTL_OUT PU_SEL R0 0K VR_PWRG_LKEN# K_PWRG_R Q FNN R0 *00K/F N.MHZ P/0V_/NPO 00 P/0V_/NPO PU_SEL 0 PU0/=MHz (default) PU0/=00MHz R => UM POP UM E-POP 0 check Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev lock Gen(LRS)/HOLES ate: Wednesday, February 0, 00 Sheet of

3 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] MI Intel(R) FI I,U_F_rPG,RP0 PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_OMP R./F_ PEG_RIS R 0/F_ K J J G G F F E 0 J H H F G E H_PWRGOO F F *00P_N 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K G0 G F E 0 0 H_PUET# H_PEI H_THERM PM_SYN 0 H_PWRGOO PM_RM_PWRG H_VTTPWRG,, PLTRST# H_VTTPWRG TP0 H_PWRGOO H_PURST# H_TERR# R H_PROHOT# R0 PU_PLTRST# R H_PURST# R0 PLL_REF_SSLK/PLL_REF_SSLK#: Embedded isplay Port PLL ifferential lock in. R R R R *00P_N U 0/F_ H_OMP T 0/F_ H_OMP OMP T./F_ H_OMP OMP G./F_ H_OMP0 OMP T OMP0 H SKTO# H_TERR# K TERR# T H_PROHOT# PEI N PROHOT# K THERMTRIP# +.0V_VTT MIS P RESET_OS# L PM_SYN N VPWRGOO_ N VPWRGOO_0 K SM_RMPWROK M TPPWRGOO H_VTTPWRG M PU_PLTRST# VTTPWRGOO L R.K/F_ RSTIN# R 0/F_ TP TP TP TP TP TP TP TP TP THERML PWR MNGEMENT J PM#[0] K PM#[] K PM#[] J PM#[] J PM#[] H PM#[] K PM#[] H PM#[] I,U_F_rPG,RP0./F_./F_ */J N */J N LOKS R MIS JTG & PM SM_RMRST# F PLL_REF_SSLK PLL_REF_SSLK# TP LK LK# TP For ITP Lk LK_ITP R0 LK_ITP# T0 PEG_LK E PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# LK_REFSSLKP_R LK_REFSSLKN_R R_RMRST# SM_ROMP_0 SM_ROMP[0] L R SM_ROMP_ R0 SM_ROMP[] M SM_ROMP_ SM_ROMP[] N R R PM_EXT_TS#[0] N PM_EXT_TS#[] P R R PRY# T TP PREQ# P TP XP_TLK TK N TMS TRST# P T TI T TO R TI_M R TO_M P R# N XP_TMS XP_TRST# XP_TI XP_TO XP_TI_M XP_TO_M R0 *0_N R R 00/F_./F_ 0/F_ 0K/J_ IS GN GN 0K/J_ *.K/F_N *0_N *0_N UM PH PH +.0V_VTT PM_EXTTS#0 PM_EXTTS# +.0V_VTT TP TP TP TP TP TP TP0 0 LK_PU_LKP 0 LK_PU_LKN 0 LK_PIE_GPLLP LK_PIE_GPLLN LK_REFSSLKP LK_REFSSLKN R_RMRST#, XP_RESET# JTG MPPING PU THERMTRIP *.K/J NR0 H_THERM Q *MMST0--F_N +.V_RUN R *0M_N *0.U_N 0 PM_THRMTRIP# Q *N00W--F_N R K/F +.V_SUS R.K/F Use a voltage divider with VQ (. V) rail (ON in S) and resistor combination of.k ± (to VQ)/K ± (to GN) to convert to processor VTT level. PM_RM_PWRG *00P_N XP_TO_M XP_TI_M XP_TRST# R0 /J_ R00 0 Intel Suggest to reserve 0 ohm below for PU P and R pins. (S 0 Page ) Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(HOST&PEX) ate: Wednesday, February 0, 00 Sheet of

4 UURNLE/LRKSFIEL PROESSOR (R) 0 M Q[0..] U M Q0 0 M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] M Q S_Q[] 0 M Q S_Q[] 0 M Q S_Q[] E0 M Q S_Q[] M Q S_Q[] M Q S_Q[] F0 M Q0 S_Q[] E M Q S_Q[0] F M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] H0 M Q S_Q[] G M Q S_Q[] K M Q S_Q[] J M Q0 S_Q[] G M Q S_Q[0] G0 M Q S_Q[] J M Q S_Q[] J0 M Q S_Q[] L M Q S_Q[] M M Q S_Q[] M M Q S_Q[] L M Q S_Q[] L M Q S_Q[] K M Q0 S_Q[] N M Q S_Q[0] P M Q S_Q[] H M Q S_Q[] F M Q S_Q[] K M Q S_Q[] K M Q S_Q[] F M Q S_Q[] G M Q S_Q[] J M Q S_Q[] J M Q0 S_Q[] J0 M Q S_Q[0] J M Q S_Q[] L0 M Q S_Q[] K M Q S_Q[] K M Q S_Q[] L M Q S_Q[] K M Q S_Q[] L M Q S_Q[] N M Q S_Q[] M0 M Q0 S_Q[] R M Q S_Q[0] L M Q S_Q[] M M Q S_Q[] N M Q S_Q[] T M Q S_Q[] P M Q S_Q[] M M Q S_Q[] N M Q S_Q[] M M Q S_Q[] T M Q0 S_Q[] T M Q S_Q[0] L M Q S_Q[] R M Q S_Q[] P S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F M M0 M M H M M M M M G M M M M M N0 M M N M M M QSN0 F M QSN J M QSN N M QSN H M QSN K M QSN P M QSN T M QSN M QSP0 F M QSP H M QSP M M QSP H M QSP K0 M QSP N M QSP R M QSP Y M 0 W M M M V M M V T M M Y M U M M 0 T M U M G M T M V M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M M[0..] M QSN[0..] M QSP[0..] M [0..] M Q[0..] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U S_Q[0] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] F S_Q[0] F S_Q[] S_Q[] F S_Q[] F S_Q[] G S_Q[] H S_Q[] G S_Q[] J S_Q[] J S_Q[] G S_Q[0] G S_Q[] J S_Q[] J S_Q[] J S_Q[] K S_Q[] L S_Q[] M S_Q[] K S_Q[] K S_Q[] M S_Q[0] N S_Q[] F S_Q[] G S_Q[] J S_Q[] K S_Q[] G S_Q[] G S_Q[] J S_Q[] H S_Q[] K S_Q[0] K S_Q[] M S_Q[] N S_Q[] K S_Q[] K S_Q[] M S_Q[] M S_Q[] P S_Q[] N S_Q[] T S_Q[0] N S_Q[] N S_Q[] N S_Q[] T S_Q[] T S_Q[] N S_Q[] P S_Q[] P S_Q[] T S_Q[] T S_Q[0] P S_Q[] R0 S_Q[] T0 S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E M M0 M M H M M K M M H M M L M M R M M T M M M QSN0 F M QSN J M QSN L M QSN H M QSN L M QSN R M QSN R M QSN M QSP0 E M QSP H M QSP M M QSP G M QSP L M QSP P M QSP R M QSP U V T V M 0 M M M R M T R M M R M R M R M M 0 P M R F M M P M N M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M M[0..] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to GN on So-IMM side for larkfield design only M QSN[0..] M QSP[0..] M [0..] M S#0 M S# M S# U S_S[0] S_S[] S_S[] M S#0 M S# M S# W R S_S[0] S_S[] S_S[] M S# M RS# M WE# E S_S# S_RS# E S_WE# I,U_F_rPG,RP0 M S# M RS# M WE# S_S# Y S_RS# S_WE# I,U_F_rPG,RP0 hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. hannel Q[,,,,,,0,,] Requires minimum mils spacing with all other signals, including data signals. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(R) ate: Wednesday, February 0, 00 Sheet of

5 Name different with power UF +V_ORE G 0 *U/.V_/XR_N V G U/.V_/XR V G 0 *U/.V_/XR_N V G 0 U/.V_/XR V G U/.V_/XR V G0 U/.V_/XR V G U/.V_/XR V G U/.V_/XR V G 0 *U/.V_/XR_N V G *U/.V_/XR_N V0 F U/.V_/XR V F U/.V_/XR V F 0 *0U/.V_/XR_N V F 0 0U/.V_/XR V F *0U/.V_/XR_N V F0 0 0U/.V_/XR V F *0U/.V_/XR_N V F 0 0U/.V_/XR V F 0U/.V_/XR V F 0U/.V_/XR V0 0U/.V_/XR V 0 0U/.V_/XR V *0U/.V_/XR_N V 0U/.V_/XR V *0U/.V_/XR_N V 0 0U/.V_/XR V 0 *0U/.V_/XR_N V *0U/.V_/XR_N V V 0 *0U_N V0 V *0U_N V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V PU ORE SUPPLY I,U_F_rPG,RP0 POWER.V RIL POWER SENSE LINES PU VIS VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE VTT_SENSE VSS_SENSE_VTT V_SENSE VSS_SENSE H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M G TP_VSS_SENSE_VTT V_VTT 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR *0U/.V_/XR_N *0U/.V_/XR_N *0U/.V_/XR_N *0U/.V_/XR_N *0U/.V_/XR_N U/.V_/XR U/.V_/XR *U/.V_/XR_N Please note that +V_GFX_ORE should be.0v in uburndale U/.V_/XR U/.V_/XR H_PSI# +.0V_VTT VTT Rail Values are uburndal VTT=.0V larksfield VTT=.V VI0 VI VI VI VI VI VI PRSLPVR H_VTTVI=Low,.V H_VTTVI=High,.0V N J J TP I_MON VTT_SENSE T VSS_SENSE_VTT: S(V.0)P0 onnect VSS_SENSE_VTT to GN or can be left floating. Note: R has the VSS_SENSE_VTT floating U/V_ +V_ORE +.0V_VTT +.0V_VTT VSENSE VSSSENSE +V_GFX_ORE VTT_SELET: High level.0v for uburndale Low level.v for larksfield R 00/F R 00/F 0 0U/.V_/XR 0U/.V_/XR U/.V_/XR U/.V_/XR V_SENSE & VSS_SENSE: S(V.0)P 00- ±% pull-down to GN near processor PRO_PRSLPVR: S(V.0)P: It is important to have the resistor stuffing options in the design for the Turbo functionality. The stuffing and no-stuffing of the resistors will depend on the PO configuration of U and F R(V.0)P: uses K pull-up and pull-down resistors R default setting is "" UG T VXG T VXG T VXG T VXG R VXG R VXG R VXG R VXG P VXG P VXG0 P VXG P VXG N VXG N VXG N VXG N VXG M VXG M VXG M VXG M VXG0 L VXG L VXG L VXG L VXG K VXG K VXG K VXG K VXG J VXG J VXG0 J VXG J VXG H VXG H VXG H VXG H VXG J U/.V_/XR VTT_ J *U/.V_/XR_N VTT_ H VTT_ K U/.V_/XR VTT_ J U/.V_/XR VTT_ J *U/.V_/XR_N VTT_0 J *U/.V_/XR_N VTT_ H VTT_ G VTT_ G VTT_ G VTT_ F VTT_ E VTT_ E VTT_ GRPHIS POWER FI PEG & MI I,U_F_rPG,RP0 SENSE LINES VI0 VI VI VI VI VI VI PRSLPVR H_PSI# 0 Steg : s an option, VTT_SENSE pin on the processor can be left floating. ut the platform needs to have the F (feedback) pin of the VR tied to the VTT plane regulation. GRPHIS VIs R -.V RILS.V.V VXG_SENSE R VSSXG_SENSE T GFX_VI[0] M GFX_VI[] P GFX_VI[] N GFX_VI[] P GFX_VI[] M GFX_VI[] P GFX_VI[] N GFX_VR_EN R GFXVR_EN GFX_PRSLPVR T GFX_IMON M VQ J VQ F VQ E VQ E VQ VQ VQ VQ Y VQ W VQ0 W VQ U VQ T VQ T VQ P VQ N VQ N VQ L VQ H VTT0_ P0 VTT0_0 N0 VTT0_ L0 VTT0_ K0 VTT_ J VTT_ J0 VTT_ J VTT_ H VTT_ H0 VTT_ H VPLL L VPLL L VPLL M R0 R0 R R R R R R R R R R R R R R R R HFM_VI : Max.V LFM_VI : Min 0.V K/J_ *K/J N K/J_ *K/J N K/J_ *K/J N *K/J N K/J_ *K/J N K/J_ K/J_ *K/J N *K/J N K/J_ K/J_ *K/J N *K/J N K/J_ 0 V_XG_SENSE VSS_XG_SENSE GFXVR_VI_0 GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ U/.V/XR U/.V/XR U/.V/XR U/.V/XR U/.V/XR U/.V_/XR *U/.V_/XR_N + 0U/V_ U/.V_/XR.U/.V/XR.U/.V/XR U/.V/XR U/.V/XR +.0V_VTT R0 R +.0V_VTT 0U/.V_/XR *0U/.V_/XR_N U/.V_/XR *U/.V_/XR_N +.V_RUN 0 GFXVR_EN GFXVR_IMON +.V_SUS Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER /(POWER).K/F_ *K/F N ate: Wednesday, February 0, 00 Sheet of

6 UURNLE/LRKSFIEL PROESSOR (GN) UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) 0 UH T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 VSS I,U_F_rPG,RP0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E E E E E0 E E E E E Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 UI K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS G VSS G VSS G0 VSS G VSS G VSS G VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS T VSS_NTF T VSS_NTF R VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS NTF I,U_F_rPG,RP0 FG FG0 FG R R R0 R R0 +M_VREF_Q_IMM0 +M_VREF_Q_IMM *0_N *0_N *.0K/F N *.0K/F N *.0K/F N FG0 FG FG FG TP_RSV_R TP_RSV_R TP TP TP TP UE J S_IMM_VREF H S_IMM_VREF M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV G RSV G RSV E RSV E0 RSV RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ J RSV J RSV H RSV K RSV L RSV R RSV_NTF_ J RSV J RSV P RSV_NTF_0 RESERVE I,U_F_rPG,RP0 RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV_NTF_ RSV RSV_TP_ RSV_TP_0 KEY RSV RSV RSV RSV RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ RSV_TP_ VSS T T R L L P0 P L T T P R T T P R R E F J H R R G E V V N W W N E P TP0 RSV_R RSV_R FG R0 R R 0 R => UM POP UM E-POP 0 check R0 *0_N *0_N *.0K/F N The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k +/- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. FG (isplay Port Presence) FG0 (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) 0 isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed -> 0, -> Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PROESSER / (GN) ate: Wednesday, February 0, 00 Sheet of

7 +RT_ELL Y.KHZ Z_SPKR Z_SIN0 PH_MELOK TP P/0V_/OG P/0V_/OG TP TP TP0 SPI_LK TP SPI_S0# TP TP SPI_SI TP SPI_SO TP RT_RST# RT_X RT_X SRT_RST# Z_ITLK 0 Z_SYN P Z_RST# 0 G0 F0 E F Z_SOUT PH_GPIO H *0_N J0 PH_JTG_TK_UF PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# TP must add test point. 0 SPI_LK SPI_S0# SPI_S# SPI_SI SPI_SO Flash escriptor Security Override GPIO T P T P R 0K/J_ PH_INVRMEN T P R R R 0M/J_ Low = Enabled High = isabled INTVRMEN - Integrated SUS.V VRM Enable High - Enable Internal VRs IEX PEK-M (H,JTG,ST) U RTX RTX RTRST# SRTRST# SM_INTRUER# INTRUER# M K K J J V Y Y V *00P/NPO_N *K_N INTVRMEN PH_GPIO Ibex-M OF 0 RT H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN IH H_SIN H_SIN H_SO H_OK_EN# / GPIO (+V) H_OK_RST# / GPIO (+V_S) JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IbexPeak-M_Rev_0 JTG SPI +.V_RUN 0 The STLE# signal is open-collector and requires a weak external pull-up (. k to 0 k ) to +V.. +.V_RUN FWH0 / L0 FWH / L LP FWH / L FWH / L FWH / LFRME# LRQ0# (+V) LRQ# / GPIO F SERIRQ ST ST0RXN K ST0RXP K ST0TXN K ST0TXP K STLE# T ST_LE# ST_ET0# ST_ET# ST_OMP R ST_ET0# ST_ET# itpm ENLE/ISLE ST_LE# L0, L, L, L, LFRME#, SERIRQ ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 STRXN H ST_RXN STRXP H ST_RXP STTXN H ST_TXN STTXP H ST_TXP STRXN F G: Place TX cap close to connector STRXP F ST port / are not support in HM. STTXN F STTXP F They are only in PM STRXN H STRXP H STTXN F STTXP F STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI F F (+V) ST0GP / GPIO Y (+V_S) STGP / GPIO V R R R0 0K/J_ 0K/J_ 0K/J_ EST ST_RXN ST_RXP ST_TXN ST_TXP istance between the PH and cap on the "P" signal should be identical distace between the PH and cap on the "N" signal for the same pair../f_ +.0V_PH ST_LE# H O Serial T LE: This signal is an open-drain output pin driven during ST command activity. It is to be connected to external circuitry that can provide the current to drive a platform LE. When active, the LE is on. When tri-stated, the LE is off. n external pull-up resistor to Vcc_ is required., PNEL_KEN ENV ENV I_PWM L_LK L_T L_LK- L_LK+ L_0- L_- L_- T P L_0+ L_+ L_+ T P VG_LU VG_GRN VG_RE R T T T P P P LK T VGHSYN VGVSYN UM 0.% IS % PNEL_KEN R R L_TRL_LK L_TRL_T.K/F_ T LVS_VG P R UM RT,LVS&HMI signals T P T0 P INT_TXLOUTN INT_TXLOUTP VG_LU VG_GRN VG_RE R R LK T 00K/J_ 00K/J_ IEX PEK-M (LVS,I) Y U PNEL_KEN T ENV L_KLTEN T L_V_EN L_KLTTL L_LK L_T L LK Y L T /J_ Y /J_ Y L_TRL_LK V L_TRL_T P LV_IG P LV_VG T LV_VREFH T LV_VREFL V LVS_LK# V LVS_LK L_T L_LK L_TRL_LK L_TRL_T LVS-- LVS_T#0 LVS_T# Y LVS_T# V LVS_T# LVS_T0 0 LVS_T Y LVS_T V LVS_T P LVS_LK# P LVS_LK LVS-- Y LVS_T#0 T LVS_T# U LVS_T# T LVS_T# Y LVS_T0 T LVS_T U0 LVS_T T LVS_T RT_LUE RT_GREEN RT_RE RT V RT LK V RT T RT_HSYN RT_VSYN K/ IREF RT_IRTN IbexPeak-M_Rev_0 R0 R R R Ibex-M SVO_TVLKINN OF 0 J SVO_TVLKINP G SVO igital isplay Interface ISPLY PORT ISPLY PORT ISPLY PORT SVO_TRLLK T SVO_TRLT T.K/J_ 0K/F_ SVO_STLLN J SVO_STLLP G SVO_INTN F SVO_INTP H P_UXN G P_UXP J P_HP U +.V_RUN HMI_SL HMI_S INT_HMI_HP INT_HMI_HP +.V_RUN INT_HMI_TXN0 P_0N INT_HMI_TXP0 P_0P INT_HMI_TXN P_N J INT_HMI_TXP P_P G INT_HMI_TXN P_N 0 INT_HMI_TXP P_P 0 INT_HMI_TXN P_N W INT_HMI_TXP P_P P_TRLLK Y P_TRLT P_UXN E P_UXP P_HP V0 P_0N E0 P_0P 0 P_N F P_P H P_N P_P P_N P_P P_TRLLK U0 P_TRLT U.K/J_ 0K/F_ P_UXN P_UXP P_HP T P_0N J0 P_0P G0 P_N J P_P G P_N F P_P H P_N E P_P R 00K/J_ R.K/J_ lose to VG side VG_LU VG_GRN VG_RE R +V_RUN R.K/J_ 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR 0.U/0V_/XR R 0 R HMI_SL HMI_S INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN0_ INT_HMI_TXP0_ INT_HMI_TXN_ INT_HMI_TXP_ *P_N 0 R *P_N 0 Q N00K-T-E *0/J N 0/F_ *P_N 0/F_ 0/F_ HMI_ET (Internal 0K/F pull high to +.V_RUN) R *K_N SPI_SI Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. TPM Function Enable isable Mount N (efault) +.V_SUS Res. of TI near PH R R R0 R *00_N *00_N *00_N *0K/F N For UIO, Z_RST#_UIO Z_SOUT_UIO Z_SYN_UIO Z_ITLK_UIO +.V_RUN R *K/F N Z_SPKR R R R R SPKR /J_ Z_RST# /J_ Z_SOUT *0P/0V N/OG /J_ Z_SYN *0P/0V N/OG /J_ Z_ITLK 0P/0V_/OG No Reboot strap. Low = efault. High = No Reboot. m +RT_ELL R R R RT 0K/F_ 0K/F_ M/J_ RT_RST# U/.V/XR SRT_RST# U/.V/XR SM_INTRUER# R *00_N R *00_N R *00_N R PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# *0K_N N all Res. when PH is production stage. Res. of TO PH ES stage : N PH ES stage : pop R /J_ PH_JTG_TK_UF Note : Only pop when PH is production stage & need "JTG boundary Scan". Remember to depop XP side Res. Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (ST,H,LP) ate: Wednesday, February 0, 00 Sheet of

8 IEX PEK-M (GN) UI Y VSS[] VSS[] H VSS[0] VSS[0] H VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L G VSS[0] VSS[0] L VSS[] VSS[] L VSS[] VSS[] L0 0 VSS[] VSS[] L VSS[] VSS[] M 0 VSS[] VSS[] M VSS[] VSS[] M0 VSS[] VSS[] N VSS[] VSS[] M VSS[] VSS[] M VSS[0] VSS[0] M 0 VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] N VSS[] VSS[] P VSS[] VSS[] 0 VSS[] VSS[] P VSS[] VSS[] P0 VSS[0] VSS[0] P H VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P E VSS[] VSS[] R E VSS[] VSS[] R E0 VSS[] VSS[] T E VSS[] VSS[] T E0 VSS[] VSS[] T E VSS[00] VSS[00] T E VSS[0] VSS[0] T E VSS[0] VSS[0] T E VSS[0] VSS[0] U0 E VSS[0] VSS[0] U E0 VSS[0] VSS[0] U E VSS[0] VSS[0] U E VSS[0] VSS[0] P F VSS[0] VSS[0] V F VSS[0] VSS[0] P F VSS[0] VSS[0] V G VSS[] VSS[] V0 G VSS[] VSS[] V G VSS[] VSS[] V0 G0 VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[0] VSS[0] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V VSS[] VSS[] V 0 VSS[] VSS[] V VSS[] VSS[] W E VSS[] VSS[] W E VSS[] VSS[] Y E0 VSS[0] VSS[0] Y E VSS[] VSS[] Y E0 VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y0 E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y F VSS[0] VSS[0] Y F VSS[] VSS[] P G0 VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] P G VSS[] VSS[] T G VSS[] VSS[] G VSS[] VSS[] T G0 VSS[] VSS[] G VSS[0] VSS[0] Y G VSS[] VSS[] T F VSS[] VSS[] M H VSS[] VSS[] T H0 VSS[] VSS[] M H0 VSS[] VSS[] K H VSS[] VSS[] K H VSS[] VSS[] V H VSS[] IbexPeak-M_Rev_0 PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ0# R PIE_LK_REQ# R0 PIE_LK_REQ# R PIE_LK_REQ#_R R PIE_LK_REQ# PEG_LKREQ# SM_LK_ME +.V_SUS SM_T_ME PIE lock Request +.V_RUN 0K/J_ 0K/J_ +.V_SUS PIELKRQ{0,,,,,}# should have a 0K pull-up to +V..PIELKRQ{,} should have a 0K pull-up to +.S (S 0 Table-) R Q FNN Q0 FNN R R R 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ +.V_SUS SMLK SMT [WLN] [LN] MiniWLN PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN LK_PIE_WLNN LK_PIE_WLNP PIE_LK_REQ# R *0_N LK_REFSSLKN LK_REFSSLKP R *0_N LK_PIE_LNN LK_PIE_LNP LN PIE_LK_REQ#_R U +.V_SUS Ibex-M G0 SMus PERN OF 0 J0 SMLERT# PERP (+V_S) SMLERT# / GPIO 0K/J_ R F IH_SMLK.K/J_ R PETN SMLK H H IH_SMT PETP SMT.K/J_ R SML0LERT# (+V_S) PIE_RXN SML0LERT# / GPIO0 J 0K/J_ R W0 SM_LK_ME0 PIE_RXP PERN SML0LK.K/J_ R 0 SM_T_ME0 PIE_TXN_ PERP SML0T G.K/J_ R 0.U/ 0V/XR 0 SMLLERT# 0.U/ 0V/XR PIE_TXP_ PETN (+V_S) SMLLERT# / GPIO M 0K/J_ R 0 SM_LK_ME PETP (+V_S) SMLLK / GPIO E0.K/J_ R SM_T_ME U0 (+V_S) SMLT / GPIO G.K/J_ R PERN T0 PERP SM heck R value... U PETN (R, R) V PETP L_LK T PERN ontroller IH_SMLK PERP L_T T IH_SMLK PETN Link E IH_SMT PETP L_RST# T IH_SMT 0 UM IS PIE_LK_REQ0# PIE_LK_REQ# IEX PEK-M (PI-E,SMUS,LK) 0 F PERN H PERP G PETN J PETP PIE_RXN_LN PIE_RXP_LN PERN W 0.U/ 0V/XR PIE_TXN_LN_ PERP 0.U/ 0V/XR PIE_TXP_LN_ PETN PETP T PERN U PERP U PETN V PETP G PERN J PERP G PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P PI-E* P PIELKRQ0# / GPIO M (+V_S) LKOUT_PIEN M LKOUT_PIEP U PIELKRQ# / GPIO (+V) M LKOUT_PIEN M LKOUT_PIEP N PIELKRQ# / GPIO0 (+V) POP Y0,, and R0, de-pop R for Internal GFX de-pop Y0,, and R0, POP R for Internal GFX PEG (+V_S) PEG LKRQ# / GPIO H LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N N LKOUT_MI_P N LKOUT_P_N / LKOUT_LK_N T LKOUT_P_P / LKOUT_LK_P T From LK UFFER XTL_IN XTL_OUT LKIN_MI_N W LKIN_MI_P LKIN_LK_N P LKIN_LK_P P LKIN_OT_N F LKIN_OT_P E LKIN_ST_N / KSS_N H LKIN_ST_P / KSS_P H PEG_LKREQ# LK_REFSSLKN LK_REFSSLKP ate: Wednesday, February 0, 00 Sheet of LK_PIE_GPLLN LK_PIE_GPLLP LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LKN LK_UF_LKP LK_UF_REFLKN LK_UF_REFLKP LK_REFSSLKN LK_REFSSLKP LK_UF_REFSSLKN LK_UF_REFSSLKP H LKOUT_PIEN REFLKIN P LK_PH_M H LKOUT_PIEP *.P/0V N/OG PIE_LK_REQ# LK_PI_F PIELKRQ# / GPIO (+V_S) LKIN_PILOOPK J LK_PI_F T M LKOUT_PIEN Intel recommendation M XTL_IN LKOUT_PIEP XTL_IN H R *0_N XTL_OUT PIE_LK_REQ# XTL_OUT H R00 M PIELKRQ# / GPIO (+V_S) XLK_ROMP XLK_ROMP F +.0V_PH R 0./F_ J0 LKOUT_PIEN J LK_FLEX0 LKOUT_PIEP (+V) LKOUTFLEX0 / GPIO T T LK_FLEX T PIE_LK_REQ# (+V_S) (+V) LKOUTFLEX / GPIO P H LK_FLEX T PIELKRQ# / GPIO (+V) LKOUTFLEX / GPIO T LK_FLEX (+V) LKOUTFLEX / GPIO N0 LK_M_R R /J_ K LKOUT_PEG N K lock Flex LKOUT_PEG P PIE_LK_REQ#_R P PEG LKRQ# / GPIO R => UM POP ohm.p/0v_/og (+V_S) UM POP ohm IbexPeak-M_Rev_0 0 check MHz R0 Y M/F_ p/npo p/npo T Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (PIE, SMUS, K)

9 +.V_RUN PI_IRY# PI_STOP# PI_PIRQ# PI_PIRQ# +.V_SUS US_O# US_O# US_O# US_O# R *0K/F N LK_M_LP LK_M_K LK_PI_F US_MR_ET# LK_M_K GNT0# R *K/F N R0, R0 and R0 => UM POP ohm UM POP ohm 0 check GNT# GNT# T_ET# PI_PIRQ# PI_SERR# REQ# PI_FRME# US_O# US_O0# US_O# US_O# PI_PLOK# PI_PERR# REQ0# PI_PIRQ# LK_M_LP +.V_RUN +.V_SUS +.V_RUN PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# REQ0# REQ# REQ# US_MR_ET# PIRQE# PIRQF# T_ET# INTH# PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# PME# LKOUT_PI[0..]: ohm series resistor is recommend (single & double load) on PG v. RP.KX RP.KX +.V_RUN RP US_MR_ET# PI_EVSEL# PI_TRY# INTH#.KX R R R R *K/F N Reserve capacitor pads for improving WWN. 0 0P/0V/OG TP TP IEX PEK-M (PI,US,NVRM) PLT_RST-R# *.P/0V N/OG swap override Strap/Top-lock Swap Override jumper UE H0 0 N J 0 E H E0 0 0 M M F M0 M J K F0 0 K M J K L F J0 G F M 0 H J0 /E0# G /E# H /E# G /E# G PIRQ# H PIRQ# PIRQ# PIRQ# GNT# Ibex-M OF 0 PI F REQ0# REQ# / GPIO0 (+V) REQ# / GPIO (+V) M REQ# / GPIO (+V) F GNT0# K GNT# / GPIO (+V) F GNT# / GPIO (+V) H GNT# / GPIO (+V) PIRQE# / GPIO K (+V) PIRQF# / GPIO (+V) PIRQG# / GPIO (+V) PIRQH# / GPIO (+V) K PIRST# E SERR# E0 PERR# M /J_ LK_M_LP_R N P /J_ LK_M_K_R P /J_ LK_PI_F_R P P IRY# H PR F EVSEL# FRME# PLOK# STOP# TRY# PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI IbexPeak-M_Rev_0 NVRM Low = swap override/top-lock Swap Override enabled High = efault US (+V_S) O0# / GPIO (+V_S) O# / GPIO0 (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO (+V_S) O# / GPIO0 (+V_S) O# / GPIO NV_E#0 Y NV_E# NV_E# P NV_E# NV_QS0 V NV_QS G NV_Q0 / NV_IO0 P NV_Q / NV_IO P NV_Q / NV_IO T NV_Q / NV_IO T NV_Q / NV_IO NV_Q / NV_IO V NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO E NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO J NV_Q / NV_IO J NV_Q / NV_IO G NV_LE NV_LE Y NV_ROMP NV_R# GNT0# U V NV_WR#0_RE# Y NV_WR#_RE# Y NV_WE#_K0 V NV_WE#_K F USP0N H USP0P J USPN USPP USPN N0 USPP P0 USPN J0 USPP L0 USPN F0 USPP G0 USPN 0 USPP 0 USPN M USPP N USPN USPP USPN H USPP J USPN E USPP F USP0N USP0P USPN G USPP H USPN L USPP M USPN USPP NV_LE NV_LE US_IS R USRIS# USRIS N J F US_O0# US_O# US_O# L US_O# E US_O# G US_O# F US_O# T US_O# oot IOS Strap GNT# USP0- USP0+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ US_O0# US_O#./F_ PH_PWROK PLT_RST-R# +.0V_PH LKRUN# XP_RESET# RSMRST# RSV_IH_LN_RST# PH_PWROK MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP +.V_SUS IEX PEK-M (MI,FI,GPIO) +.V_RUN REQ# PIRQE# PIRQF# T_ET# PM_RI# PM_TLOW# PIE_WKE# SUS_PWR_K _PRESENT NV_LE NV_LE +.V_RUN +.V_SUS 0 XP_RESET# T SYS_RESET# SLP_S# P SIO_SLP_S# TP M SYS_PWROK SLP_S# H TP R0 *0_N PH_PWROK PWROK SLP_M# EPWROK K MEPWROK SLP_M# K TP0 RSV_IH_LN_RST# TP N TP 0 LN_RST# PM_RM_PWRG RMPWROK (+V_S) SUS_PWR_N_K / GPIO0 M SUS_PWR_K RSMRST# RSMRST# (+V_S) PRESENT / GPIO P _PRESENT TP (+V) LKRUN# / GPIO Y LKRUN# PM_PWRTN#_R P PWRTN# (+V_S) SUS_STT# / GPIO P (+V_S) SUSLK / GPIO F TP SIO_SLP_S# (+V_S) SIO_SLP_S# PM_RI# SLP_S# / GPIO E F PM_TLOW# RI# (+V_S) TLOW# / GPIO PIE_WKE# J WKE# PM_SYN J0 PMSYNH (+V_S) SLP_LN# / GPIO F US #0 US # US # (est) WLN WWN T *00P_N Webcam ard Reader oot IOS Location LP Reserved (NN) PI SPI R 00K/F_ R0 R.K R 0K/J_ onnect this signal on PH directly to the reset button and pull up this signal to +V. (ore rail) through a weak pull up resistor (. to 0 k ). U *MVHG0FTG_N R H MI_OMP F./F_ R R R0 *0_N 0K/J_ 0K/J_ 0K/J_ U MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP G MIRXP 0 MIRXP G0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP *0.U/0V_N/XR MI_ZOMP MI_IROMP IbexPeak-M_Rev_0 R *00K/F N MI PLTRST#,, Ibex-M OF 0 FI System Power Management MI Termination Voltage NV_LE anbury Technology Enabled NV_LE FI_RXN0 FI_RXN H FI_RXN FI_RXN J FI_RXN FI_RXN E FI_RXN FI_RXN FI_RXP0 FI_RXP F FI_RXP FI_RXP G FI_RXP W FI_RXP FI_RXP FI_RXP FI_INT J FI_FSYN0 F FI_FSYN H FI_LSYN0 J FI_LSYN G R.K R0.K R.K R.K Set to Vcc when LOW Set to Vcc/ when HIGH R R R R R R R High = Enable Low = isable *K_N *K_N FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN 0K/J_ 0K/J_ K/J_ 0K/J_ 0K/J_ +.V_RUN Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (PI,ONFI,US,MI) ate: Wednesday, February 0, 00 Sheet of

10 PIE_MR_ET# GPIO reserve for internal VR. T_RIO_IS# WWN_RIO_IS# RIT_TEMP_REP# GPIO register not cleared by Fh reset event. US_MR_ET# WLN_RIO_IS# SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# VG_TYPE R 0K/F_ R R0 TP PH_GPIO0 IEX PEK-M (GPIO,VSS_NTF,RSV) UF Y MUSY# / GPIO0 (+V) TH / GPIO (+V) TH / GPIO (+V) J TH / GPIO (+V) IbexPeak-M_Rev_0 Ibex-M OF 0 GPIO MIS PH_GPIO F0 GPIO (+V_S) LN_PHY_PWR_TRL K LN_PHY_PWR_TRL / GPIO (+V_S) 0GTE U T GPIO (+V_S) STGP STGP / GPIO (+V) LKOUT_LK0_N/LKOUT_PIEN M *0_N PIE_MR_ET#_R F TH0 / GPIO (+V) LKOUT_LK0_P/LKOUT_PIEP M PIE_MR_ET# Y SLOK / GPIO (+V) PEI G0 *0K_N GPIO GPIO (+V_S) RIN# T TP_PH_GPIO V PU GPIO (+V_S) PROPWRG E0 STGP PH_THRMTRIP#_R STGP / GPIO (+V) THRMTRIP# 0 R /F STGP STGP / GPIO (+V) TP +.0V_VTT R /F T_RIO_IS# TP W P STOUT0 / GPIO (+V) TP TP Y GPIO TP Y F PIELKRQ# / GPIO (+V_S) TP V WWN_RIO_IS# TP V STOUT / GPIO (+V) TP F RIT_TEMP_REP# TP M STGP / GPIO (+V) TP0 N H_PEI RSV TP J TP K TP K TP M H0 0 GPIO GPIO H (+V_S) TP N *00P_N VG_TYPE PIELKRQ# / GPIO F (+V_S) TP M0 US_MR_ET# GPIO (+V_S) TP N0 M GPIO STP_PI# / GPIO (+V) TP H V WLN_RIO_IS# STLKREQ# / GPIO V (+V) TP SLO / GPIO (+V) N_ N_ N_ N_ N_ T INIT_V# P TP 0 VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ NTF LKOUT_PIEN H LKOUT_PIEP H LKOUT_PIEN F LKOUT_PIEP F VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_0 J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J0 VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E GTE0 LK_PU_LKN LK_PU_LKP H_PEI RIN# H_PWRGOO H_THERM 0 UM-0_.SN PH_THRMTRIP#_R *00P_N IEX PEK-M (GN) UH VSS[0] VSS[] 0 VSS[] VSS[] M VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[0] VSS[] U VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] Y VSS[0] H VSS[] U VSS[] F VSS[] P VSS[] N VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] V VSS[] H VSS[] H VSS[0] H VSS[] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[0] T VSS[] J VSS[] K VSS[] M VSS[] N VSS[] K VSS[] K VSS[] K VSS[] K VSS[] IbexPeak-M_Rev_0 VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K VSS[] L VSS[] L VSS[] M VSS[] VSS[] VSS[] M0 VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] U0 VSS[] M VSS[] V VSS[] M VSS[] M VSS[] 0 VSS[] 0 VSS[] N VSS[] N0 VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] VSS[0] H VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[0] W VSS[] F VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y R0 TP_PH_GPIO GPIO GPIO LN_PHY_PWR_TRL 0K GPIO R R R R +.V_SUS 0K 0K 0K *0K_N RIN# GTE0 R R T_RIO_IS# R STGP R STGP R STGP R PIE_MR_ET#_R R PIE_MR_ET# R SIO_EXT_SMI# SIO_EXT_SI# SIO_EXT_WKE# R R R WLN_RIO_IS# R RIT_TEMP_REP# R US_MR_ET# R 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K 0K +.V_RUN PH_GPIO0 WWN_RIO_IS# R R WWN_RIO_IS# 0K 0K +.V_RUN MUSY#:(Intel feedback) Follow R checklist, K is for intel IOS validation purpose. MUSY#: If not used, require a weak pull-up (.- K to 0 k ) to Vcc_. R(V.0)P: it has K PU and 00 ohm on this net for validation purpose. -X High = Strong (efault) Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (GPIO & Strap) ate: Wednesday, February 0, 00 Sheet 0 of

11 L +.0V_PH +.0V_PH +.0V_PH..0 *uh_n +.0V_LN_VPLL_EXP J *0U/.V_00_N/XR VPLLEXP.0 N0 VIO[] +.0V_PH N 0U/.V_/XR VIO[] N U/.V/XR VIO[] N U/.V/XR VIO[] N U/.V/XR VIO[] N U/.V/XR VIO[0] J VIO[] J VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[] W VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[] E VIO[0] G VIO[] G VIO[] H VIO[] N0 VIO[] N VIO[] 0. +.V_RUN N 0.U/ 0V/XR V_[] 0.0 U/.V/XR 0U/.V_/XR UG VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[] H VORE[0] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VORE[] K V ORE VIO[] POWER Ibex-M OF 0 PI E* T VVRM[] +.V_RUN L *uh_n +.0V_VFIPLL J VFIPLL +.0V_PH 0 *0U/.V_00_N/XR M VIO[].0 IbexPeak-M_Rev_0 +.0V_PH FI RT LVS HVMOS MI NN / SPI +.0V_PH V[] V[] VSS_[] VSS_[] ap quantities follow UM need check to change to 0 ohm VPNN[] M VPNN[] K VPNN[] K0 VPNN[] K VPNN[] K VPNN[] K VPNN[] M VPNN[] M VPNN[] M L L E0 E F F VLVS H VSS_LVS H L0 +V H0KF-T VTX_LVS[] P VTX_LVS[] P VTX_LVS[] T VTX_LVS[] T 0. V_[] V_[] V_[] VVRM[] T 0.0 VMI[] T VMI[] U VME_[] M VME_[] M VME_[] P VME_[] P U/.V_/XR 0.U/ 0V/XR 0.0U/V_/XR 0U/.V_/XR +.V_RUN 0uH 0uH +VTX_LVS +.V_RUN +.V_RUN +.0V_VTT +.V_RUN +.V_RUN +.V_VPLL +.V_VPLL +.V_RUN 0.0U/V_/XR 0.0U/V_/XR U/.V_/XR 0.U/ 0V/XR U/.V/XR 0.U/ 0V/XR 0.U/ 0V/XR L + U/.V_ <Size> U/.V/XR + U/.V_ <Size> U/.V/XR UJ VLK = 00m max +.0V_PH L *0uH_N +.V_LN_V_LK 0 *U/.V_N/XR P VLK[] *0U/.V_00_N/XRP VLK[] Y0 PSUSYP 0.uH +.V_RUN +.V_RUN 0U/.V_/XR +.0V_PH PSUSYP 0.U/ 0V/XR R *0_N +VLN 0 U/.V/XR 0.U/ 0V/XR +VSST +V.LN_INT_VSUS Y 0.U/ 0V/XR PSUS PI/GPIO/LP 0. P VSUS_[] +.V_SUS U VSUS_[0] U0 0.U/ 0V/XR VSUS_[] U VSUS_[] U/.V/XR F VME[] U/._/XR VME[] U/._/XR VME[] F F V V V Y Y Y VLN[] *U/.V_N/XR F VLN[] F VME[] VME[] VME[] VME[] VME[] VME[0] VME[] VME[] +VRTEXT 0.U/ 0V/XR V PRT V_RUN U VVRM[] V_VPLL VPLL[] VPLL[] V_VPLL VPLL[] VPLL[].0 +.0V_PH H VIO[] J U/.V/XR VIO[] H U/.V/XR VIO[] F U/.V/XR VIO[] H VIO[] F VIO[] POWER lock and Miscellaneous V V_[] 0. V V_[] +.V_RUN Y 0.U/ 0V/XR V_[] >m +.0V_VTT T.U/.V/XR V_PU_IO[] U 0.U/ 0V/XR V_PU_IO[] PU 0 0.U/ 0V/XR m +RT_ELL 0.U/ 0V/XR VRT RT 0.U/ 0V/XR U/.V/XR L0 VSUSH m +.V_SUS R *0_N H V VME[] PSST Ibex-M 0 OF 0VIO[] VIO[] VIO[] VIO[] US VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] PI/GPIO/LP ST VIO[] VREF_SUS VREF V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VVRM[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VME[] VME[] VME[] VME[] V V Y Y V U U U P P N N M M L L J J H H G G F F E E U V F +VREF_SUS >m K +VREF J L M N P U >m +.0V_PH +.V_SUS +.0V_PH +.V_RUN K +.0V_VSTPLL L *0uH_N K *U/.V_N/XR *0U/.V_00_N/XR T0 H H 0 F F0 F H0 0 Y Y 0.0. U/.V/XR 0.U/ 0V/XR 0.U/ 0V/XR R 00 0.U/ 0V/XR 0.U/ 0V/XR +.V_RUN +.0V_PH U/.V/XR U/.V/XR R V_PH +.V_SUS R00V-0 R00V-0 U/.V/XR 0U/.V_/XR +V_SUS +.V_SUS +V_RUN +.V_RUN +.0V_PH IbexPeak-M_Rev_0 Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev PH / (POWER) ate: Wednesday, February 0, 00 Sheet of

12 +.V_SUS M [0..] SO-IMM SP ddress is 0X0 SO-IMM TS ddress is 0X0 M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# M WE# R R, WLN_SMLK, WLN_SMT M OT0 M OT M M[0..] M QSP[0..] M QSN[0..] Place these aps near So-imm0. +0.V_R_VTT M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S M M0 M M M M M M M M M M M M M M +SMR_VREF_IMM0 M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN Some Projects replace 0UF 00 by.uf 00 It can cost down 0% 0 0 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR 0.U/ 0V/XR 0.U/ 0V/XR 0.U/ 0V/XR 0.U/ 0V/XR 0.U/ 0V/XR *0U_N. + 0K/F_ 0K/F_ JIM /P /# S0# S# 0 K0 0 K0# 0 K 0 K# KE0 KE S# 0 RS# WE# S0 0 S 0 SL 00 S OT0 0 OT M0 M M M M M 0 M M QS0 QS QS QS QS QS QS QS 0 QS#0 QS# QS# QS# QS# QS# QS# QS# U/.V/XR U/.V/XR U/.V/XR U/.V/XR 0U/.V_/XR 0U/.V_/XR 0U/.V_/XR R-IMM0 P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q +.V_SUS M Q[0..], R_RMRST# R0 K/F +VTT_R_REF The EVENT# pin is reserved for use to flag critical module temperature. resistor may be connected from EVENT# bus line to Vddspd on the system planer to act as a pullup. (R S REV0.) 00 *0.0U/V/XR N +.V_SUS +VTT_R_REF R *0_N R0 K/F R K/F R +.V_SUS +.V_RUN for S power reduction PM_EXTTS#0 +SMR_VREF_Q0 +SMR_VREF_IMM0 R +SMR_VREF_IMM0 *0_N 0 0.U/V_/YV M VREF.U/.V/XR +.V_SUS PM_EXTTS#0 M VREF +SMR_VREF_Q0 +SMR_VREF_Q0 +M_VREF_Q_IMM0 *0_N R *K/F N JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS R-IMM0 Remove M VREF Function Intel esign Guide. had remove M VREF (I programble VREF) M VREF P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 +0.V_R_VTT M => support for larksfield processor R *0_N GN 0 +.V_RUN.U/.V/XR 0.U/ 0V/XR 0.U/ 0V/XR.U/.V/XR.U/.V/XR 0.U/ 0V/XR R K/F 0.U/V_/YV Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev R IMM-0 ate: Wednesday, February 0, 00 Sheet of

13 M [0..] M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# M WE# R +.V_RUN R0, WLN_SMLK, WLN_SMT M OT0 M OT M M[0..] SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X M QSP[0..] M QSN[0..] M 0 M M M M M M M M M M 0 M M M M M M M0 M M M M M M M M M M M M M M JIM /P /# S0# S# 0 K0 0 K0# 0 K 0 K# KE0 KE S# 0 RS# 0K/F_ IMM_S0 WE# 0K/F_ IMM_S S0 0 S 0 SL 00 S OT0 0 OT M0 M M M M M 0 M M M QSP0 M QSP QS0 M QSP QS M QSP QS M QSP QS M QSP QS M QSP QS M QSP QS M QSN0 QS 0 M QSN QS#0 M QSN QS# M QSN QS# M QSN QS# M QSN QS# M QSN QS# M QSN QS# QS# R-IMM P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[0..], R_RMRST# 0 0.0U/V/XR_ +.V_SUS +VTT_R_REF R K/F R K/F PM_EXTTS# +SMR_VREF_Q +SMR_VREF_IMM +.V_RUN R +SMR_VREF_IMM *0_N 0.U/V_/YV +.V_SUS.U/.V/XR JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS R-IMM P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 +0.V_R_VTT Remove M VREF Function Intel esign Guide. had remove M VREF (I programble VREF) M => support for larksfield processor GN 0 GN 0 Place these aps near So-imm. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% +.V_SUS +0.V_R_VTT Wait Victor check 0U/.V_/XR 0 U/.V/XR 0 0U/.V_/XR U/.V/XR 0U/.V_/XR U/.V/XR 0U/.V_/XR 0 U/.V/XR 0U/.V_/XR 00 0U/.V_/XR 0U/.V_/XR 0 0U/.V_/XR 0.U/ 0V/XR 0U/.V_/XR +.V_SUS +VTT_R_REF 0 0.U/ 0V/XR 0 0.U/ 0V/XR 0.U/ 0V/XR 0 0.U/ 0V/XR R R K/F *0_N 0U + for arrandal nc, for clesfied connect M VREF M VREF +SMR_VREF_Q +SMR_VREF_Q +M_VREF_Q_IMM. R *0_N R *0_N +.V_RUN 0 0.U/.V/XR 0.U/ 0V/XR +SMR_VREF_IMM U/ 0V/XR 0.U/ 0V/XR.U/.V/XR.U/.V/XR R K/F 0.U/V_/YV Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev R IMM- ate: Wednesday, February 0, 00 Sheet of

14 Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev lank Wednesday, February 0, 00 ate: Sheet of

15 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

16 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

17 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

18 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

19 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

20 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet 0 of

21 Size ocument Number Rev lank Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

22 Support the new imbeded diagnostics. ENV LV_TST_EN T T/R EN_LV +.V_SUS +V_LW +.V_RUN Q FN R 0K R0 K LV_ON Q TEU--F R0 *00K_N Q N00W--F 0.0U/V_/XR R0 00 Q N00W--F +LV 0U/V_0/XS 0U/V_0/XS 0 0 +LV 0.U/V_/YV 0.0U/0V_/XR 0 +.V_RUN +.V_RUN +.V_RUN 0 0.U/V_/YV 0.U/V_/YV 0U/.V_/YV 0 L_K L_KLIGHT, PNEL_KEN T T/R R0 0K J L_KLIGHT LT_PWM L_LK- L_LK+ L_- L_+ L_- L_+ +.V_RUN L *0_N MI_LK_L 0 MI_LK USP_- USP_+ L *0_N MI_T_L 0 MI_T L_0- L_0+ L_LK L_T +LV MI_T_L *P_N/OH 0 L_- L_+ L_- L_+ L_0- L_0+ L_LK L_T L_TST +GFX_PWR_SR MI_LK_L *P_N/OH 0 +PWR_SR 0mil R0 *00K_N R *0.U/YV_N 0 0mil Q *FP_N +GFX_PWR_SR *0.U/YV_N 0 Shunt capacitors on LVS for improving WWN. L_0- L_- L_- 00 *.P_N/NPO 0 0 *.P_N/NPO 0 *.P_N/NPO 0 L_0+ L_+ L_+ USP_- USP_+ L PLWS00SQT 0 USP- USP+,,,,0 RUN_ON Q *N00W--F_N *00P_N R *00K_N UM-IS-0_.SN L_LK- L_LK+ R *0_N 0 0 *.P_N/NPO L_LK- L_LK+ I_PWM PWM_VJ T T/R LT_PWM R0 0K Quanta omputer Inc. PROJET : UM IS Size ocument Number Rev L ONN ate: Wednesday, February 0, 00 Sheet of

23 S_ S_ S_ S_M S_ MS_LK MS_ MS_INS# MS_ MS_0 MS_ MS_S S_LK S_ S_ S_0 S_ *0P/0V N/OG R 0 R 0 *P_N/NPO 0 NPO MS_LK_R S_LK_R ON S-() S-() MM-0() S-(S_M) MM-() S-(VSS) S-(V) MS-0(VSS) MS-(V) 0 MS-(SLK) MS-() MS-(INS) MS-() MS-(0) MS-() MS-(S) MS-(VSS) S-(LK) MM-() 0 S-(GN) MM-() S-(0) S-() LPS IN-SF000-P-V S(SW.OM) S(SW.) X-(SW) X-0(GN) X-(R/-) X-(RE) X-(E) X-(LE) X-(LE) X-(WE) X-(-WP) X-(GN) X-0(0) X-() X-() X-() X-() X-() X-() X-() X-(V) S(SW.WP) 0 0 R0 R_V 0 S_# X_# X_RY X_RE# X_E# X_LE X_LE X_WE# X_WP X_0 X_ X_ X_ X_ X_ X_ X_ S_WP 0.U/V_/YV RTS-QFN +.V_RUN.U/.V/XR. XR 0 LK_M_R R.K RREF USP_- USP_+ R_V 0.U/V_/YV R_V VREG U/.V/XR 0.U/V_/YV U0 RREF M P V_IN R_V V GN RTS X_ SP SP SP SP LK_IN X_ SP SP SP 0 SP X_# SP SP SP SP SP X_# SP SP SP SP SP I ottom Ground 0 SP0 GPIO0 SP SP SP SP SP0 SP SP SP SP *0P_N/NPO 0.U/V_/YV 0 0.U/V_/YV old ONN SP X_RY S_WP MS_LK SP X_RE# MS_INS# SP X_E# S_ SP X_LE S_0 MS_ SP X_LE S_ MS_ SP X_WE# S_# SP X_WP S_ MS_ SP X_0 S_LK MS_ SP X_ S_ MS_0 SP0 X_ S_M SP X_ S_ MS_ SP X_ S_ MS_ SP X_ S_ MS_ SP X_ MS_S USP_+ USP_- L PLWS00SQT 0 USP+ USP- Share Pin Quanta omputer Inc. PROJET : UM IS Size ocument Number Rev ard Reader(RST) ate: Wednesday, February 0, 00 Sheet of

24 HMI_TX+_L HMI_TX-_L EXG00U L HMI_TX+ HMI_TX- HMI_TX0-_L HMI_TX0+_L L EXG00U HMI_TX0- HMI_TX0+ UM_UM_000_00_Ray.pdf HMI N FHSFR0 Female HMI_TX+_L HMI_TX-_L L0 EXG00U UM POP O ohm and E-POP L UM POP L and E-POP 0 ohm 0 check HMI_TX+ HMI_TX- HMI_LK+_L HMI_LK-_L L EXG00U HMI_LK+ HMI_LK- +V_RUN HMIF +V_HMI R R0.K/J_.K/J_ +V_HMI +V_HMI_R +V_HMI HMI_TX+ HMI_TX- HMI_TX0+ HMI_TX0- HMI_LK+ HMI_TX- HMI_TX+ HMI_LK- HMI_SL_S HMI_S_S HMI_ET_R 0 TYPE + - GN GN E SL GN HP GN + - GN K+ K- RSV S +V 0L0WR *0.U_N/XR 0.U/0V_/XR 0 0 GN FHSFR0 +.V_RUN L LMPGSN U SLZ/SZ Low-level input/output Voltage FG0:FG00=0:0 VIL:<0.V VOL:0.V (efault) GF0:GF00=0: VIL:<0.V VOL:0.V GF0:GF00=:0 VIL:<0.V VOL:0.V GF0:GF00=: VIL:<0.V VOL:0.V 0.U/XR 0.U/XR 0 0.U/XR 0.U/XR 0.U/XR +V_HMI 0.U/XR 0.U/XR 0.U/XR 0 V V V V V V V V POWER EQULIZTION SETTING P:P0=0:0 d P:P0=0: d Recommanded P:P0=:0 d P:P0=: 0d +.V_RUN +.V_RUN R 00K/J_ HMI_ET Q N00W--F INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXN_ INT_HMI_TXP_ INT_HMI_TXP0_ INT_HMI_TXN0_ HMI_SL HMI_S HMI_ET R R R R R.K/J EN *.K/J N P0.K/J_ P *.K/J N FG00 *.K/J N FG0 R 0 R.K 0 SL S HP _EN P0 P UF_EN FG 0 RT_EN# OE# REXT ONTROL GN IN_- IN_+ IN_- IN_+ IN_- IN_+ IN_- IN_+ OUT_- OUT_+ OUT_- 0 OUT_+ OUT_- OUT_+ OUT_- OUT_+ SL_SINK S_SINK HP_SINK 0 GN GN GN GN GN GN GN GN GN GN EP PIVPLSZE HMI_LK-_L HMI_LK+_L HMI_TX-_L HMI_TX+_L HMI_TX-_L HMI_TX+_L HMI_TX0+_L HMI_TX0-_L HMI_SL_S HMI_S_S HMI_ET_L R PIM: PIVPLSZE QPN: LPLS000 TI: SNPRGZR QPN: L K/J_ HMI_ET_R _EN P0 P FG00 FG0 HMI_TX0+ HMI_TX+ HMI_TX+ R R R HMI_PWR_TRL 0 is Enable is isable R0 *0/J N R *0/J N R *0_N R 0/J_ R0 *0/J N *00_N HMI_TX0_ *00_N HMI_TX_ *00_N HMI_TX_ Reserve for EMI R *00_N *0.U/XR_N HMI_LK+ HMI_LK_ HMI_LK- *0.U/XR_N HMI_TX0- *0.U/XR_N HMI_TX- *0.U/XR_N HMI_TX- Size ocument Number Rev HMI Quanta omputer Inc. PROJET : UM UM ate: Wednesday, February 0, 00 Sheet of

25 +.V_LW UM Place these caps close to ITE0. SERIRQ S(V.0)P:.-k pull-up to +V.S R uses a 0-k pull-up to +V.S.,, PLTRST# LK_M_K, LFRME#, L0, L, L, L LKRUN# SERIRQ 0 SIO_EXT_SMI# 0 SIO_EXT_SI# 0 GTE0 L_TST 0 RIN# L_K N_MUTE# KSO[0..] KSI[0..] 0 0U/.V_/XR 0.U/V_/YV 0.U/V_/YV 0.U/V_/YV 0.U/V_/YV 0. T P KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSI KSI KSI KSI KSI KSI KSI KSI0 SERIRQ SMK00L--F SMK00L--F SMK00L--F SMK00L--F WRST# L_K# IH_Z_OE_RST0# U KSO/GP KSO/GP KSO KSO KSO KSO/SLT KSO/ERR KSO0/PE KSO/USY KSO/K KSO/P KSO/P KSO/P 0 KSO/P KSO/P KSO/P KSO/P KSO0/P0 KSI KSI KSI KSI KSI/SLIN 0 KSI/INT KSI/F KSI0/ST R *0_N LPRST/WUI/GP LPLK LFRME 0 L0 L L L LKRUN/GPH0/I0 SERIRQ ESMI/GP ESI/GP G0/GP LPP/WUI/GPE KRST/GP WRST PWUREQ/GP L0HLT/GPE0 0 L0LLT/WUI/GPE ITE0E LQFP-L KEYOR LP / PWM IR/URT VT V VSTY VSTY 0 VSTY VSTY VSTY VSTY 0/GPI0 /GPI /GPI /GPI /GPI 0 /GPI /GPI /GPI 0/GPJ0 /GPJ /GPJ /GPJ /GPJ 0 /GPJ PWM0/GP0 PWM/GP PWM/GP PWM/GP PWM/GP 0 PWM/GP PWM/GP PWM/GP TH0/GP TH/GP TMRI0/WUI/GP 0 TMRI/WUI/GP RX/GP0 0 TX/GP 0 GP0 TX0/GP RX/GPH/I TX/GPH/I HWPG V_I SIO_SLP_S# US_LEFT_EN# IMVP_VR_ON +.V_RUN +.V_LW SMK00L--F +RT_ELL R *0_N 0.U/V_/YV HWPG 0,, P T SUS_PWR_K P T0 PT_PRES# IINP SIO_SLP_S# RIT_TEMP_REP# 0 SIO_EXT_WKE# 0 US_LEFT_EN# FN_ 0 RSMRST# PM_PWRTN#_R RETH_LE# P T FN_PWM 0 PWM_VJ P T P T P T E_EEP FN_TH 0 PNEL_KEN, LI_SW# SIO_SLP_S# P T H_PUET# IMVP_PWRG RUN_ON,,,,0 T_LE IMVP_VR_ON heck, Z_RST#_UIO SMT0 SMLK0 SMT SMLK US_LEFT_EN# SUS_ON IMVP_VR_ON SERIRQ SMT SMLK R R *0K_N Q0 *MMST0--F_N +.V_RUN R R R *0_N RP.KX RP0 0KX +.V_LW UM POP.k UM POP 0k 0 check UM E-POP UM POP *0K_N 0 check 00K *00K_N +.V_RUN R 0K/F_ R *00K_N RP 0KX *0.U/0V_N/XR 0 IH_Z_OE_RST0# Q *N00W--F_N harge and T PH LN, lock Thermal I KHz lock. W ITE0_XTL, SMLK0, SMT0 +.V_LW SMLK SMT,0 SMLK,0 SMT PH_MELOK T P PS_I T P LK_TP_SIO T_TP_SIO R 00K WRST# 0 U/ 0V/YV 0 0 SMLK0 SMT0 SMLK SMT SMLK SMT LK_M_K PH_MELOK ITE0_XTL ITE0_XTL 0 SMLK0/GP SMT0/GP SMLK/GP SMT/GP SMLK/GPF SMT/GPF PSLK0/GPF0 PST0/GPF PSLK/GPF PST/GPF PSLK/GPF 0 PST/GPF KKE ITE0IX_JX ITE0_XTL R 0 0.U/V_/YV.KHZ P/0V_/OG P/0V_/OG P/NPO 0 KK ITE0IX_JX VORE VSS VSS VSS VSS +.V_LW VSS L LM0S VSS 0 V VSS 0.U/V_/YV L 0 LM0S SMUS PS/ LP/FWH FLSH EGP GPIO FLFRME/GPG/LF 00 FLRST/GPG0/TM 0 FL/GPG 0 FL/SO 0 FL/SI 0 FL0/SE 0 FLLK 0 EG/GPE EGS/GPE EGLK/GPE GPH/I GPH/I GPH/I GPH/I GPG/I 0 ITE0E lqfp-x- SUS_ON EPWROK I US_RIGHT_EN# I L_SIZE_I L_SIZE_I RI/WUI0/GP0 RI/WUI/GP WUI/GPE SMK00L--F 0 RING/PWRFIL/LPRST/GP PWRSW/GPE GINT/GP R P T0 P T P T P T *00K_N +.V_LW SUS_ON,0 K_ET# P T E_FLSH_SPI_O E_FLSH_SPI_IN E_FLSH_SPI_S# E_FLSH_SPI_LK EPWROK LW_ON I US_RIGHT_EN#, I L_SIZE_I P T V_IN, T_LE _PRESENT SYS_PWR_SW# LV_TST_EN L_SIZE_I () " 0 " " 0 Madison R 0K R *0K_N Park VG_TYPE L_SIZE_I (0) 0 0 R *0K_N R 0K iscrete UM VG_IENTIFY I R *0K_N R 0K US_RIGHT_EN# R 0K R 0K +.V_LW US_RIGHT_EN# I L_SIZE_I I L_SIZE_I V_I Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev SIO ITE0 UM(UM) SSI (X00) PT (X0) ST (X0) QT (00) (0) R0 *0K_N UM (is) SSI (X00) PT (X0) ST (X0) QT (00) (0) ate: Wednesday, February 0, 00 Sheet of R R R *0K_N *0K_N 0K

26 UM For E Mbit (M yte) RT TTERY nd source:kegzn0n00 +.V_LW +.V_LW +RT_ELL +.V_LW E_FLSH_SPI_S# E_FLSH_SPI_LK E_FLSH_SPI_IN E_FLSH_SPI_O R.K U R E_FLSH_SPI_LK_R E# V R E_FLSH_SPI_IN_R SK R0 /J_E_FLSH_SPI_O_R SI SO HOL# *P/0V N/NPO WP# VSS MXL00M-G 0 MRONIX: MXL0MI-G QPN: KEFP0Z00 WINON: WXVSSIG QPN: KEZP0N00 R.K 0.U/V_/YV.U/.V/XR 0. RT +RT_ RTR K/F SMK00L--F U/ 0V/YV 0 0 SMK00L--F +RT heck P/N & Footprint RTT TT_ONN OIN TTERY IN OM need modify the location of this portions RT-TTERY For PH Mbit (M yte) MRONIX: MXL00M-G QPN: KEGFK0Z0 WINON: WX0VSSIG QPN: KEZP0N00 +.V_RUN +.V_RUN SPI_S0# SPI_LK SPI_SI SPI_SO SPI_S0# R SPI_S0#_R SPI_LK R SPI_LK_R SPI_SI R SPI_SI_R SPI_SO R SPI_SO_R close to PH 0 *00P/NPO_N R0.K R U.K E# V SK SI SO HOL# 0 *P/0V N/NPO WP# VSS MXL0MI-G 0.U/ 0V/XR 0 0 R *0_N R *0_N I R *0_N US_RIGHT_EN#, R *0_N L_SIZE_I I lose to U For HSPI Function Quanta omputer Inc. PROJET : UM UM Size ocument Number Rev FLSH/RT ate: Wednesday, February 0, 00 Sheet of