Intel Calpella BlOCK DIAGRAM

Transcript

1 Intel alpella lok IGRM POWER /TT ONNETOR R-SOIMM H R-SOIMM H ST-O ST-H UIO/MP L SYSTEM RESET IRUIT TT HRGER RUN POWER SW +V_S/+V_S +V_SUS/+V_SUS +V_RUN/+V_RUN/+.V_RUN ual hannel R 0.V INTEL ISRETE SYSTEM IGRM ST ST IH PU rrandale W.mm X.mm ( rpg ) MI X PH 0IM (HM) mm X mm PI-E x US.0 x US.0 PIEx PIEx FN & THERML LOK SLGSPVTR (QFN-) M PRK-LP mm X mm TP W ( S ) R 00MHz VRM Mxx,bit POWER REGULTOR +.V_SUS/+0.V_R_VTT +.0V_PH +.0V_VTT RT LVS US conn x LN Realtek 0/00/ LN RTL0EL MINI-R WLN RT PU VR / +VPU/+VPU/ LVS ard Reader S MS R RTS 0 udio SPK conn udio Jacks LP E ITE0 X SPI FLSH Mbyts Keyboard SPI PS/ FLSH Mbyts Touchpad Quanta omputer Inc. PROJET : FH Size ocument Number Rev LOK IGRM ate: Tuesday, ecember, 00 Sheet of

2 PGE Table of ontents ESRIPTION Schematic lock iagram Front Page lock Generator rrandale Ibex Peak-M RIII SO-IMM(0P) L/ ONN RT ONN ard Reader (RTS) LN RTL0EL/RJ H/O/HOLE US/LUE TOOTH MINI-ard (WLN)/ XP K/TOUH P/LE OE (L) E_ ITE0 FN/SW ON +V/+V (RT0) +.0V/ +.V (RT0) PU ore ( P) +.0V_VTT (VT) R (RT0) ISHRGE/VS/VS/LN HRGER (ISL) lock istribution Power Tree SMUS ddress PRK-S_PIE_Interface PRK-S_Main PRK-S_GN/LVS/Straps PRK-S_Power_and_N PRK-S_MEM_Interface PRK_VRM (R G) +VGORE (RT0/.V) +.V_VG/+.0V_VG IN +VPU/+VPU NSWON# RV_ON IH_RSMRST# NSWON# SUS#,SUS#,SUS# SUSON MINON GPU_PWR_EN MINON +.VSUS/+VSUS/+VSUS +.V_RUN/+.V_RUN /+V_RUN/+V_RUN +VGPU_ORE/+V_GPU/+.V_GPU /+.V_GPU/+.0V_GPU +.0V_PH/+.0V_VTT /+0.V_R_VTT HWPG VRON +V_ORE VR_PWRG_LKEN# T T T Power Sequence T ms~0ms 0 IMVP_PWRG T MPWROK H_VTTPWRG RMPWROK VPPWRGOO PLTRST# PU_RST# T: RVON TO RSMRST# = 0ms (spec:mini 0ms) T: RSMRST# TO-NSWON = 0ms (spec:mini 00ms) T: MINON TO VRON = 0ms (spec:mini ms) T: VRON TO MPWROK = 0ms (HWPG NEE TO E HIGH at that time) Note: IMVP_LK_EN# (inverted) assertion to SYS_PWROK/PH_PWROK assertion. SPE:ms~0ms T: MINON to MINON =00us Quanta omputer Inc. PROJET : FH Size ocument Number Rev Frontpage ate: Tuesday, ecember, 00 Sheet of

3 +V_RUN L LMPG00SN 0U/0V_ 0 LK_PH_M 0.U/V_ 0.uF near the every power pin. +V_RUN 0.U/V_ K_PWRG_R LK_PH_M R R 0mil 0.U/V_ Place the ohm resistors close to the K 0 0.U/V_ 0K/J_ /J_ +.V_LK_V +VIO_LK 0.U/V_ PU_SEL XTL_OUT XTL_IN 0 V_US V_L V_SR V_PU V_REF V_SR_IO V_PU_IO K0 QFN PU-0 PU-0# PU- 0 PU-# VSS_ST OTT_LPR VSS_US OT_LPR VSS_L VSS_SR SR- VSS_PU SR-# VSS_REF SR-/ST 0 SR-#/ST# PU_STOP# MHz_nonSS K_PWRG/P#_. MHz_SS REF_0/PU_SEL XOUT XIN LK_UF_LK_P LK_UF_LK_N LK_UF_REFLKP LK_UF_REFLKN LK_UF_PIE_GPLLP LK_UF_PIE_GPLLN LK_UF_REFSSLKP LK_UF_REFSSLKN MHZ_NONSS MHZ_SS R _ R *_ EVG-XTLI LK_M_SS LK_UF_LK_P 0 LK_UF_LK_N 0 LK_UF_REFLKP 0 LK_UF_REFLKN 0 LK_UF_PIE_GPLLP 0 LK_UF_PIE_GPLLN 0 LK_UF_REFSSLKP 0 LK_UF_REFSSLKN 0 EVG-XTLI LK_M_SS -0 0,, GT_SM 0,, GLK_SM ST SLK GN *P/0V_ SLGSPVTR *P/0V_ U Realtek: 0.uFxpcs, ufxpcs IT: 0.uFxpcs, 0uFxpcs +V_RUN +VIO_LK +V_S XTL_IN P/0V_ Y XTL_OUT.MHZ P/0V_ R +.0V_PH R *0/J_ 0/J_ L LMPG00SN 0 0mil 0U/0V_ 0.U/V_ 0 0.U/V_ HP: 0u xpcs 0.U/V_ SLG,IT: +.0V Realtek: +.V Place each 0.uF cap as close as possible to each V IO pin. Place the 0uF caps on the V_IO plane. VR_PWRG_LKEN# U TSZ0FU(TL,F,T) R0 0/J_ K_PWRG_R +VIO_LK: SLG date sheet (V0.) P: Min.0V,Max.V. Realtek date sheet(v.) P: Min.0V,Max.V. IT date sheet(v0.) P0: Min 0.V,Max.V. +V_RUN R *.K/J_ PU_SEL R.K/J_ *0P/0V_ EMI apacitor PIN 0 PU_0 PU_ 0(default) MHz MHz (0.V-.V) 00MHz 00MHz PU_SEL: SLG date sheet (V0.) P: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. Realtek date sheet(v.) P: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. IT date sheet(v0.) P0: High Voltage: Min 0.V, Max.V. Low Voltage: Min Vss-0.V, Max 0.V. Quanta omputer Inc. PROJET : FH Size ocument Number Rev lock Generator ate: Tuesday, ecember, 00 Sheet of

4 0 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP -0 FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN isable Integrated Graphics -0 R K/F_ FI_INT RN KX-00 FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] MI Intel(R) FI PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_IOMPI R./F_ R 0/F_ K PEG_RXN PEG_RXN J PEG_RXN PEG_RXN J PEG_RXN PEG_RXN G PEG_RXN PEG_RXN G PEG_RXN PEG_RXN F PEG_RXN0 PEG_RXN0 F PEG_RXN PEG_RXN PEG_RXN PEG_RXN E PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN 0 PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN0 J PEG_RXP PEG_RXP H PEG_RXP PEG_RXP H PEG_RXP PEG_RXP F PEG_RXP PEG_RXP G PEG_RXP PEG_RXP E PEG_RXP0 PEG_RXP0 F PEG_RXP PEG_RXP PEG_RXP PEG_RXP F PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP 0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP 0 PEG_RXP0 PEG_RXP0 L PEG_TXN_ 0.U/0V_ PEG_TXN M PEG_TXN_ 0.U/0V_ PEG_TXN M PEG_TXN_ 0 0.U/0V_ PEG_TXN M0 PEG_TXN_ 0.U/0V_ PEG_TXN L PEG_TXN_ 0.U/0V_ PEG_TXN K PEG_TXN0_ 0.U/0V_ PEG_TXN0 M PEG_TXN_ 0.U/0V_ PEG_TXN J PEG_TXN_ 0.U/0V_ PEG_TXN K PEG_TXN_ 0.U/0V_ PEG_TXN H0 PEG_TXN_ 0.U/0V_ PEG_TXN H PEG_TXN_ 0.U/0V_ PEG_TXN F PEG_TXN_ 0.U/0V_ PEG_TXN E PEG_TXN_ 0 0.U/0V_ PEG_TXN PEG_TXN_ 0.U/0V_ PEG_TXN PEG_TXN_ 0.U/0V_ PEG_TXN PEG_TXN0_ 0.U/0V_ PEG_TXN0 L PEG_TXP_ 0.U/0V_ PEG_TXP M PEG_TXP_ 0.U/0V_ PEG_TXP M PEG_TXP_ 0.U/0V_ PEG_TXP L0 PEG_TXP_ 0.U/0V_ PEG_TXP M PEG_TXP_ 0.U/0V_ PEG_TXP K PEG_TXP0_ 0.U/0V_ PEG_TXP0 M PEG_TXP_ 00 0.U/0V_ PEG_TXP H PEG_TXP_ 0 0.U/0V_ PEG_TXP K PEG_TXP_ 0 0.U/0V_ PEG_TXP G0 PEG_TXP_ 0 0.U/0V_ PEG_TXP G PEG_TXP_ 0 0.U/0V_ PEG_TXP F PEG_TXP_ 0 0.U/0V_ PEG_TXP E PEG_TXP_ 0 0.U/0V_ PEG_TXP PEG_TXP_ 0 0.U/0V_ PEG_TXP PEG_TXP_ 0 0.U/0V_ PEG_TXP PEG_TXP0_ 0 0.U/0V_ PEG_TXP0-0 H_PEI H_PROHOT#_ H_THERM H_PURST# PM_SYN PEG_TXN PEG_TXN PEG_TXN, H_PWRGOO PEG_TXN PEG_TXN PEG_TXN0 PM_RM_PWRG PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN H_PWRG_XP PEG_TXN PEG_TXN PEG_TXN 0,,, PLTRST# PEG_TXN0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 R H_PROHOT#_ H_THERM H_PURST# PM_RM_PWRG H_VTTPWRG R0 T 0/J_ R0.K/F_ R0 0/F_ H_OMP H_OMP H_OMP H_OMP0 TP_SKT0# H_TERR# H_PEI_ISO 0/J_ T T G T H K T N K P L N N K M M L U OMP OMP OMP OMP0 SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_0 SM_RMPWROK VTTPWRGOO TPPWRGOO RSTIN# larksfield/uburndale PU THERMTRIP, IMVP_PWRG MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM +.0V_VTT Q N00E R LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] 00K/J_ LK_PU_LKP LK_PU_LKN R0 LK_LK_ITPP T0 LK_LK_ITPN E LK_PIE_GPLLP 0 LK_PIE_GPLLN 0-0 isable UM F R_RMRST#_ for S power reduction L SM_ROMP_0 M SM_ROMP_ N SM_ROMP_ +.0V_VTT N R 0K/J_ P R 0K/J_ R0 0/J_ PM_EXTTS#0 R 0/J_ PM_EXTTS# T XP_PRY# P XP_PREQ# XP_PREQ# R0 *.K/F_ N XP_TLK P XP_TLK XP_TMS XP_TMS T XP_TRST# XP_TRST# T T XP_TI_R T R XP_TO_R T R XP_TI_M P XP_TO_M N H_R#_R R 0/J_ XP_RESET#, XP_OS[0:] J XP_OS0_R R 0/J_ XP_OS0 K XP_OS_R R 0/J_ XP_OS K XP_OS_R R 0/J_ XP_OS J XP_OS_R R 0/J_ XP_OS J XP_OS_R R 0/J_ XP_OS H XP_OS_R R0 0/J_ XP_OS K XP_OS_R R 0/J_ XP_OS H XP_OS_R R 0/J_ XP_OS XP_TI_R XP_TI R 0/J_ XP_TO_M XP_TO R *0/J_ R XP_TRST# 0/J_ R XP_TI_M /J_ R0 *0/J_ XP_TO_R R 0/J_ For S power reduction +.V_SUS larksfield/uburndale isable Integrated Graphics Processor Pullups Processor ompensation Signals +.0V_VTT H_OMP0 H_OMP,, HWPG HWPG R0 K/F_ H_VTTPWRG R K/F_ R ompensation Signals SM_ROMP_ SM_ROMP_ H_THERM TEMP_FIL -0 R R *.K_ R K/J_ Q /J_ H_THERM_R SYS_SHN# MMT0 PM_THRMTRIP# STUP S SHORT S PSSPLE Q *MMT0--F R0 *0/J_ N00W--F R Q K/F_ R_RMRST#_ SYS_SHN# R R *0/J_ 00K/J_ R 0/J_ 0 0.U/V/XR +.V_RUN R_RMRST#, R_ORL_E R_ORL_PH R./F_ H_TERR# H_PROHOT#_ H_PURST# R /F_ R */J_ R./F_ R./F_ R 0/F_ H_OMP H_OMP R 0/F_ R 0/F_ R./F_ SM_ROMP_0 R 00/F_ PU THERM SENSOR +V_RUN U SYS_SHN_# V OS R R0 TRL *0_ *0.U/0V_ GN Vtemp *E000G SYS_SHN# *0/J_ R *.K/F_ R 0/F_ PM_RM_PWRG R.K/F_ HWPG T +.0V_VTT T XP_TMS XP_TI_R XP_PREQ# XP_TLK R R R R */J_ */J_ */J_ */J_ R *0_ ES-0 Quanta omputer Inc. PROJET : FH Size ocument Number Rev RRNLE / Tuesday, ecember, 00 ate: Sheet of

5 U RRNLE PROESSOR (R) U 0 M Q[:0] M S0 M S M S M S# M RS# M WE# M Q0 0 M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] M Q S_Q[] 0 M Q S_Q[] 0 M Q S_Q[] E0 M Q S_Q[] M Q S_Q[] M Q S_Q[] F0 M Q0 S_Q[] E M Q S_Q[0] F M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] H0 M Q S_Q[] G M Q S_Q[] K M Q S_Q[] J M Q0 S_Q[] G M Q S_Q[0] G0 M Q S_Q[] J M Q S_Q[] J0 M Q S_Q[] L M Q S_Q[] M M Q S_Q[] M M Q S_Q[] L M Q S_Q[] L M Q S_Q[] K M Q0 S_Q[] N M Q S_Q[0] P M Q S_Q[] H M Q S_Q[] F M Q S_Q[] K M Q S_Q[] K M Q S_Q[] F M Q S_Q[] G M Q S_Q[] J M Q S_Q[] J M Q0 S_Q[] J0 M Q S_Q[0] J M Q S_Q[] L0 M Q S_Q[] K M Q S_Q[] K M Q S_Q[] L M Q S_Q[] K M Q S_Q[] L M Q S_Q[] N M Q S_Q[] M0 M Q0 S_Q[] R M Q S_Q[0] L M Q S_Q[] M M Q S_Q[] N M Q S_Q[] T M Q S_Q[] P M Q S_Q[] M M Q S_Q[] N M Q S_Q[] M M Q S_Q[] T M Q0 S_Q[] T M Q S_Q[0] L M Q S_Q[] R M Q S_Q[] P S_Q[] S_S[0] S_S[] U S_S[] E S_S# S_RS# E S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F M M0 M M H M M M M M G M M M M M N0 M M N M M F J N H K P T F H M H K0 N R Y W V V T Y U T U G T V M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S0# M S# M OT0 M OT M M[:0] M QSN[:0] M QSP[:0] M [:0] M Q[:0] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to GN on So-IMM side for larkfield design only M S0 M S M S M S# M RS# M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q E F F F F G H G J J G G J J J K L M K K M N F G J K G G J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY - S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E M M0 M M H M M K M M H M M L M M R M M T M M F J L H L R R E H M G L P R U V T V R T R R R R P R F P N M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S0# M S# M OT0 M OT M M[:0] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to GN on So-IMM side for larkfield design only M QSN[:0] M QSP[:0] M [:0] larksfield/uburndale hannel Q[,,,], M[] Requires minimum mils spacing with all other signals, including data signals. hannel Q[,,,,,,0,,] Requires minimum mils spacing with all other signals, including data signals. larksfield/uburndale Quanta omputer Inc. PROJET : FH Size ocument Number Rev RRNLE / ate: Tuesday, ecember, 00 Sheet of

6 PU ore Power +V_ORE=. max +V_ORE UF +.0V_VTT=. max +.0V_VTT RRNLE PROESSOR (GRPHIS POWER) 0 G G G G G G0 G G G G F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 larksfield/uburndale PU ORE SUPPLY POWER SENSE LINES PU VIS H_PSI# VI0 VI VI VI VI VI VI PRSLPVR UURNLE/LRKSFIEL PROESSOR (POWER).V RIL POWER VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ PSI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRSLPVR VTT_SELET ISENSE V_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT H H H H0 J J H H G G G G F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J 0 0U/.V_ 0 0U/.V_ +.0V_VTT VTT_SENSE 0 VSS_SENSE_VTT 0 H_PSI# VI0 VI VI VI VI VI VI PRSLPVR H_VTTVI 0 I_MON +.0V_VTT VTT0_,VTT0_:(Intel feedback) They are connected to hidden page for intel validation purpose. N K K K L L M M M G N J J 0U/.V_ 0 0U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ VSS_SENSE_VTT: S(V.0)P0 onnect VSS_SENSE_VTT to GN or can be left floating. Note: R has the VSS_SENSE_VTT floating. 0 0U/.V_ 0U/.V_ *0U/.V_ 0U/.V_ 0 U/.V_ +V_ORE R 00/F_ 0 *0U/.V_ +.0V_VTT U/.V_ U/.V_ U/.V_ V_SENSE & VSS_SENSE: S(V.0)P 00- ±% pull-down to GN near processor VSENSE VSSSENSE -0 0 U/.V_ U/.V_ U/.V_ T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H UG VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VTT_ VTT_ VTT_ larksfield/uburndale VI0 R VI 00/F_ VI VI VI VI PRO_PRSLPVR: VI S(V.0)P: PRSLPVR It is important to have the resistor stuffing options H_PSI# in the design for the Turbo functionality. The stuffing and no-stuffing of the resistors will depend on the PO configuration of U and F Note: R(V.0)P: For Validating IMVP VR R should be STUFF uses K pull-up and pull-down resistors and R NO_STUFF R default setting is "" J J H K J J J H G G G F E E VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ GRPHIS FI PEG & MI POWER SENSE LINES GRPHIS VIs R -.V RILS.V.V VXG_SENSE VSSXG_SENSE GFX_VI[0] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VI[] GFX_VR_EN GFX_PRSLPVR GFX_IMON R K/J_ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT0_ VTT0_0 VTT0_ VTT0_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VPLL VPLL VPLL R *K/J_ R K/J_ R *K/J_ R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M R0 K/J_ R *K/J_ R0 U/.V_ +.0V_VTT R *K/J_ R K/J_ K/F_ 0 0U/.V_ 0 U/.V_ U/.V_ R *K/J_ R K/J_ R0 *K/J_ U/.V_ R K/J_ -0 isable UM U/.V_ U/.V_ U/.V_ U/.V_ + 0U/.V_. 0 U/.V_ R K/J_ 0 0U/.V_.U/.V_ R *K/J_ U/.V_ R0 K/J_ R *K/J_ +.0V_VTT + 0 *0U/.V_.U/.V_ R0 *K/J_ R K/J_ 0 U/.V_ +.V_RUN +.V_RUN U/.V_ +V_ORE U/.V_ U/.V_ 0U/.V_ 0 0U/.V_ 0U/.V_ For S power reduction heck to ensure that stitching caps per SOIMM connector between SOIMM.V and GN are placed as close as possible to the connectors caps should be evenly distributed between the connectors + *0U/.V_ U/.V_ U/.V_ 0U/.V_ 00 0U/.V_ 0U/.V_ 0 U/.V_ U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ + 0 *0U/.V_ U/.V_ U/.V_ 0U/.V_ 0 0U/.V_ 0 0U/.V_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev RRNLE / U/.V_ 0 U/.V_ 0U/.V_ 0U/.V_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ Tuesday, ecember, 00 ate: Sheet of

7 UH T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 RRNLE PROESSOR (GN) VSS UI VSS E VSS E VSS E K VSS VSS E K VSS VSS E0 K VSS VSS E K VSS VSS E J VSS VSS E J0 VSS VSS E J VSS VSS0 E J VSS VSS 0 H VSS VSS H VSS0 VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS00 0 H VSS VSS0 H VSS VSS0 H VSS0 VSS0 H VSS VSS0 G VSS VSS0 G VSS VSS0 0 G0 VSS VSS0 Y G VSS VSS0 Y G VSS VSS0 Y G VSS VSS0 W F0 VSS VSS W F VSS VSS W F VSS0 VSS W F VSS VSS W F VSS VSS W0 F VSS VSS W E VSS VSS W E VSS VSS W E VSS VSS W E VSS VSS0 W E VSS VSS V0 E VSS VSS U E VSS00 VSS U E VSS0 VSS U E VSS0 VSS T E VSS0 VSS T E VSS0 VSS T VSS0 VSS T 0 VSS0 VSS T VSS0 VSS0 T0 VSS0 VSS T VSS0 VSS T VSS0 VSS T VSS VSS T VSS VSS T VSS VSS R0 VSS VSS P VSS VSS P VSS VSS P 0 VSS VSS0 N VSS VSS N VSS VSS N VSS0 VSS N VSS VSS N VSS VSS N0 VSS VSS N VSS VSS N VSS VSS N VSS VSS N VSS VSS0 N VSS VSS M0 VSS VSS L VSS0 VSS L VSS VSS L VSS VSS L VSS VSS L VSS L VSS K VSS K VSS0 K0 VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R FG0 FG FG FG RRNLE PROESSOR( RESERVE, FG) UE P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV J S_IMM_VREF H S_IMM_VREF G RSV G RSV E RSV E0 RSV M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ larksfield/uburndale RESERVE RSV J RSV J RSV H RSV K RSV L RSV_NTF_ R RSV J RSV J RSV_NTF_0 P RSV_NTF_ T RSV_NTF_ T RSV_NTF_ R RSV L RSV L RSV P0 RSV P RSV L RSV0 T RSV T RSV P RSV R RSV_NTF_ T RSV_NTF_ T RSV_NTF_ P RSV_NTF_ R RSV R RSV_TP_ E RSV_TP_0 F KEY RSV RSV RSV J RSV H RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ G RSV_TP_ E RSV_TP_ V RSV_TP_ V RSV_TP_ N RSV_TP_ RSV_TP_0 RSV_TP_ W RSV_TP_ W RSV_TP_ N RSV_TP_ E RSV_TP_ VSS P R 0/J_ an be left N is Intel RM implementation; ES/G recommendation to GN 0 larksfield/uburndale larksfield/uburndale The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k +/- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. FG0 FG FG FG R R R R *.0K/F_ *.0K/F_ *.0K/F_ *.0K/F_ FG (isplay Port Presence) FG0 (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) 0 isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed Quanta omputer Inc. PROJET : FH Size ocument Number Rev RRNLE / ate: Friday, ecember 0, 00 Sheet of

8 MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP +.0V_PH, XP_RESET# PH_PWRG PM_RM_PWRG IH_RSMRST# SUS_PWR_K NSWON# _PRESENT R R0 R R./F_ 0/J_ 0/J_ 0/J_ MI_ZOMP XP_RESET# SYS_PWROK PWROK MEPWROK LN_RST# IH_RSMRST# SUS_PWR_K _PRESENT PM_TLOW# 0 IEX PEK-M (MI,FI,GPIO) J W0 J0 G 0 G0 E F 0 E H 0 H F T M K 0 M P P U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# MI System Power Management SUS_PWR_N_K / GPIO0 PWRTN# PRESENT / GPIO TLOW# / GPIO FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# SLP_S# SLP_M# TP PMSYNH H J E F G W J F H J G J Y P F E H P K N J0 PIE_WKE# LKRUN# RSV_LPP# IH_SUSLK SLP_M#_R -0 isable UM T T T T PIE_WKE# SIO_SLP_S# SIO_SLP_S# SIO_SLP_S# PM_SYN -0 R IEX PEK-M (LVS,I) T T Y Y V P P T T V V Y V 0 Y V P P Y T U T Y T U0 T V V Y Y K/_ U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE LVS RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P J G J G F H T T G J U J G 0 0 W Y E V0 E0 0 F H U0 U T J0 G0 J G F H E PM_RI# F RI# SLP_LN# / GPIO F PM_SLP_LN#_R IbexPeak-M_RP0 IbexPeak-M_RP0 +V_RUN LKRUN# R00.K_ XP_RESET# R K/J_ PH_PWRG R 0K/J_ IH_RSMRST# R 0K/J_ LN_RST# R 0K/J_ +V_S PM_SLP_LN#_R R 0K/J_ PM_RI# PIE_WKE# PM_TLOW# _PRESENT SUS_PWR_K R R R R R0 0K/J_ 0K/J_.K/J_.K/J_.K/J_ +V_RUN +V_S R *K_ 0 *0.U/0V_, IMVP_PWRG, MPWROK U MVHG0FTG PH_PWRG *0.U_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev IEX PEK-M / Tuesday, ecember, 00 ate: Sheet of

9 RT TTERY +VPU OE R Z_SYN_R Z_RST#_R Z_SOUT_R Z_IT_LK_R +V_RUN +V_S *.K/F_ +VPU PEEP R *K/J_ +VRT Place all series terms close to PH except for SIN input lines,which should be close to source.placement of R, R, R & R should equal distance to the T split trace point. asically, keep the same distance from T for all series termination resistors. R 00/J_ R 00/J_ R *.K_ R0 *K_ Res. of TI near PH R0 00/J_ R0 00/J_ R 00/J_ R0 00/J_ Q *MMT0 R0 *0K/J_ R0 *0K/J_ R K/J_ H0H-0 R K/J_ H0H-0 ON ME_FW_OVERRIE MEFW_OVERRIE Low = Enabled GPIO High = isabled R /J_ Z_SYN PR R R /J_ Z_RST# /J_ Z_SOUT (Internal 0K/F pull high to +.V_RUN) R /J_ Z_IT_LK T0 *P/0V_ 0 PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# No Reboot strap. PEEP Low = efault. High = No Reboot. +V_RT JTG Test Pads are need to put on the same side of mother board. N all Res. when PH is production stage. -T-0-K0 bat-ap-aaa-bat-0-k0-p -0-0 Res. of TO PH ES stage : N PH ES stage : pop R M/F_ R R 0K/F_ Flash escriptor Security Override Note : GPIO is a signal used for Flash escriptor Security Override/ME ebug Mode.This signal should be only asserted lowthrough an external pull-down in manufacturing or debug environments ONLY. 0 U/.V_ PH_JTG_TK_UF Note : Only pop when PH is production stage & need "JTG boundary Scan". Remember to depop XP side Res. +V_RT INTVRMEN(Internal Voltage Regulator Enable) : This signal enables the internal.0 V regulators. This signal must be always pulled-up to VccRT. R0 0K/F_ /J_ 0 U/.V_ SPI_S0# SPI_LK SPI_SI SPI_SO ap values depend on Xtal OE 0 PEEP Z_SIN0 Z_IT_LK Z_SYN PEEP Z_RST# -0 Z_SOUT GPIO_PH 0K/F_ SPI_SI RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN PH_JTG_TK_UF PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# SPI_LK SPI_S0# SPI_S# SPI_SO For PH Mbit (M yte) R R R R P/0V_ Y.KHZ P/0V_ R0 T T T T T0 /J_ /J_ /J_ /J_ 0K/J_ R R 0M/J_ SPI_S0#_R SPI_LK_R SPI_SI_R SPI_SO_R +V_RUN P/0V_ 0 IEX PEK-M (H,JTG,ST) K/F_ R 0K/J_ 0 0 G0 F0 E F H J0 V Y Y V U0 P M K K J J E# SK SI SO WP# U RTX RTX MXL0MI RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO IbexPeak-M_RP0 V HOL# VSS RT IH H_OK_EN# / GPIO H_OK_RST# / GPIO JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO SPI JTG LP ST +V_RUN 0.U/0V_ 0 FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# ST0GP / GPIO STGP / GPIO R 0K/J_ F K K K K H H H H F F F F H H F F F F T Y V R R_L0 R_L R_L R_L ST_OMP ST_T# RT_RST# +V_RUN SRT_RST# +.0V_PH +V_RUN L0, L, L, L, LFRME#, +V_RUN IRQ_SERIRQ ST_RXN0 0 ST_RXP0 0 ST_TXN0 0 ST_TXP0 0 ST_RXN 0 ST_RXP 0 ST_TXN 0 ST_TXP 0 ST port / are not support in HM. R R RP R R R 0K/J_ 0K/J_ X-00 /F_ 0K/J_./F_ 0K/J_ RESET JUMP G *SHORT_ P ST_LE# ST H ST O (Near ROOM OOR) T *P_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev IEX PEK-M / 0 Tuesday, ecember, 00 ate: Sheet of

10 LK_LP_EUG LK_LP_EUG R LK_PI_0 R /F_ LK_PI_0 LK_PI_F R /F_ LKOUT_PI[0..]: ohm series resistor is recommend (single & double load) on PG v. LK_LP_EUG LK_PI_0 PI_PLTRST# Non-iMT GNT# PIRST#: G(V.0) P an be left unconnected. PR: S(V.0) P an be left unconnected if not using PI. PME: G(V.0) P an be left unconnected. -0 Reserve capacitor pads for improving WWN. 0 0.U/V_ - 0 *P/0V_ 0 *P/0V_ +V_RUN PI_PLTRST# T T PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_REQ0# HMI_PWR_TRL S_WWN_PIE_RST# US_MR_ET# PI_GNT0# GNT# GNT# GNT# PH_IRQH_GPIO S_WLN_PIE_RST# T_ET# PH_IRQH_GPIO PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# PME# IEX PEK-M (PI,US,NVRM) PI_PLTRST# LK_LP_EUG_ LK_PI_0_ LK_PI_F_ dd uffers as needed for Loading and fanout concerns. U T T T T T T0 T MVHG0FTG /F_ PLTRST#,,, H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 G F M H J0 G H G G H F M F K F H K K E E0 H F M N P P P P UE /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ0# REQ# / GPIO0 REQ# / GPIO REQ# / GPIO GNT0# GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PIRST# SERR# PERR# IRY# PR EVSEL# FRME# PLOK# STOP# TRY# PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI IbexPeak-M_RP0 PI +V_S O# O# O# O# T_ET# PH_IRQH_GPIO S_WWN_PIE_RST# S_WLN_PIE_RST# PH_IRQH_GPIO PI_REQ0# PI_PIRQ# US_MR_ET# +V_RUN 0 PI_STOP# PI_PIRQ# PI_PIRQ# PI_IRY# +V_RUN NVRM US 0 0 NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / GPIO O# / GPIO0 O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO0 O# / GPIO RP 0PR-.K RP 0PR-.K RP Y P V G P P T T V E J J G Y U V Y Y V F H J N0 P0 J0 L0 F0 G0 0 0 M N H J E F G H L M N J F L E G F T 0PR-.K US_IS O0# O# O# O# O# O# O# O# O# O# O# O0# PI_TRY# PI_FRME# HMI_PWR_TRL PI_PIRQ# PI_SERR# PI_PERR# PI_PLOK# PI_EVSEL# NV_LE NV_LE USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ USP- USP+ O0#~O#: G(V.0)P Pin efault Port Mapping O0# Port0,Port O# Port,Port O# Port,Port +V_RUN +V_S +V_RUN +V_RUN US PORT () US PORT (M) US PORT (M) 0 +V_S +V_RUN oot IOS Strap PI_GNT0# PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP LK_PIE_MININ LK_PIE_MINIP MINILK_REQ# LK_PIE_LOMN LK_PIE_LOMP LK_LN_REQ# PIE_TXN_ PIE_TXP_ LK_PEG0_REQ# LK_PIE_REQ#_R LK_PIE_REQ# R 0K/J_ LK_PIE_REQ# N00E Q R 0K/J_ R_LK_REQ#_R SM_LK_ME R0 0K/J_ LK_PIE_REQ# R 0K/J_ LK_PEG0_REQ# R 0K/J_ LOM_LK_REQ#_R R R0 *0K/J_ PEG_LKREQ#.K/F_ GNT# MiniWLN LN US port / are not support in HM. MiniWLN R R R R R0.K/J_.K/J_.K/J_.K/J_ MER T WLN R REER./F_ LN PIE lock Request R0 R R 0K/J_ 0K/J_ 0K/J_ Place TX blocking caps close PH. MINILK_REQ#_R LK_PIE_REQ#_R PIELKRQ{0,,,,,}# should have a 0K pull-up to +V..PIELKRQ{,} should have a 0K pull-up to +.S R R PI_GNT0# GNT# oot IOS Location LP PI Reserved (NN) SPI 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PIE_TXN_ PIE_TXP_ PIE port / are not support in HM. K/J_ K/J_ R R0 0/J_ MINILK_REQ#_R LK_PIE_REQ# R_LK_REQ#_R LOM_LK_REQ#_R PH_SMT 0/J_ PH_SMLK IEX PEK-M (PI-E,SMUS,LK) G0 J0 F H W U0 T0 U V E F H G J W T U U V G J G J K K P M M U M M N H H M M M J0 J H K K P +V_RUN SM_T_ME PH_SMT +V_RUN U PH_SMLK PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP IbexPeak-M_RP0 LKOUT_PEG P/N,LKOUT_PEG P/N, LKOUT_MI_P/N,support GEN- and GEN- N00E Q PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO Q Q N00E N00E SMus From LK UFFER lock Flex ontroller PEG Link R.K/F_ R.K/F_ SMLERT# / GPIO MLK, - MT, GT_SM,, SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T SMLLERT# / GPIO SMLLK / GPIO SMLT / GPIO L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N / LKOUT_LK_N LKOUT_P_P / LKOUT_LK_P R.K/F_ LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N / KSS_N LKIN_ST_P / KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO H J G M E0 G T T T H N N T T W P P F E H H P J H H F T P T N0 RSV_SMLERT# 0K/J_ PH_SMLK PH_SMT RSV_IH_L_RST# 0K/J_ SM_LK_ME0 SM_T_ME0 LP_SPI_INTR# SM_LK_ME SM_T_ME PEG_LKREQ# LK_PI_F XTL_IN XTL_OUT XLK_ROMP R XTL_IN XTL_OUT LK_FLEX0 LK_FLEX LK_FLEX +V_S LK_PIE_VGN LK_PIE_VGP LK_PIE_GPLLN LK_PIE_GPLLP 0 FOR INTEL LN LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LK_N LK_UF_LK_P LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M 0 LKIN_PILOOPK: PG (V.): ohm series resistor is recommend EMI USE -0 LKOUTFLEX: ES(V.0) :support MHz MHz and.mhz. +.0V_PH LK_M_R LKOUTFLEX[0..]: PG v.: ohm series resistor is recommend (PI & non PI routing, single & double load) - R R0 *M/F_.K/J_.K/J_.K/J_.K/J_ 0K/J_.K/J_.K/J_ /J_ Quanta omputer Inc. PROJET : FH GLK_SM,, Size ocument Number Rev R IEX PEK-M / 0 FOR R SP/LOK GE EXPRESS R/MINI R FOR E R SML0LK/SML0T: G(V.) P: The SMus signals (SM_T and SM_LK) cannot be connected to any other devices other than the PH. onnect the SM_T and SM_LK pins to the PH SML0T and SML0LK pins, respectively. R 0 - Tuesday, ecember, 00 ate: Sheet of 0 T 0./F_ T T T *0P_ R R R R R0 R R 0/J_ *P/0_ Y *.0000 MHz *P/0_

11 SIO_EXT_SMI# SIO_EXT_SI# SWI# S_GPIO SIO_EXT_SMI# SIO_EXT_SI# GPIO SWI# GPIO_PH PH_GPIO STGP GPIO GPIO_PH GPIO register not cleared by Fh reset event. GPIO reserve for internal VR. R *0K/J_ GPIO R_ORL_PH TEMP_LERT# IOS_WP# T T T T T T TP_PH_GPIO GPIO GPIO STGP STGP GPIO GPIO GPIO R_ORL_PH SV_SET_UP TEMP_LERT# IOS_WP# Y J F0 K T F Y H0 V M V V P H F F UF TH / GPIO TH / GPIO GPIO GPIO GPIO GPIO GPIO IEX PEK-M (GPIO,VSS_NTF,RSV) MUSY# / GPIO0 TH / GPIO GPIO MIS LN_PHY_PWR_TRL / GPIO GPIO STGP / GPIO TH0 / GPIO SLOK / GPIO STP_PI# / GPIO STLKREQ# / GPIO STGP / GPIO STGP / GPIO SLO / GPIO STOUT0 / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO STOUT / GPIO STGP / GPIO PU LKOUT_PIEN H LKOUT_PIEP H LKOUT_PIEN F LKOUT_PIEP F 0GTE LKOUT_LK0_N / LKOUT_PIEN LKOUT_LK0_P / LKOUT_PIEP PEI RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP U M M G0 T E0 0 W Y Y V V F M SIO_0GTE SIO_RIN# PH_THRMTRIP#_R SIO_0GTE +.0V_VTT LK_PU_LKN LK_PU_LKP H_PEI R SIO_RIN# /J_ H_PWRGOO, R /J_ (oth these should be close to PH) H_THERM GPIO TP_PH_GPIO SWI# PH_GPIO IOS_WP# GPIO_PH R_ORL_PH GPIO GPIO GPIO_PH GPIO GPIO GPIO SIO_EXT_SMI# SIO_EXT_SI# SIO_RIN# SIO_0GTE STGP TEMP_LERT# STGP STGP R R R R0 R0 R R00 R R0 R R R R R R R0 R R R0 R0 R0 +V_S 0K/J_ 0K/J_ 0K/J_ K/J_ 0K/J_ 0K/J_ 0K/J_ +V_RUN 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ TP0 N VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_ J VSS_NTF_0 J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J0 VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_0 E VSS_NTF_ IbexPeak-M_RP0 NTF RSV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P 0 T MI Termination Voltage 0 0 NV_LE NV_LE NV_LE Set to Vcc when LOW anbury Technology Enabled NV_LE Set to Vcc/ when HIGH R R High = Enable Low = isable *K/J_ *K/J_ +.V_RUN +V_RUN R R 0K/J_ GPIO *K/J_ GNT# 0 R *K/J_ SWI# S_GPIO R SV_SET_UP R0 0K/J_ 0K/J_ MUSY#: If not used, require a weak pull-up (.- KΩ to 0 kω) to Vcc_. R(V.0)P: it has K PU and 00 ohm on this net for validation purpose. swap override Strap/Top-lock Swap Override jumper GNT# Low = swap override/top-lock Swap Override enabled High = efault Integrated lock hip Enable (Reserve to validate for future platforms) RSV_WOL_EN (GPIO) Enable when sampled low isable when sampled high SV_SET_UP -X High = Strong (efault) MUSY#:(Intel feedback) Follow R checklist, K is for intel IOS validation purpose. Quanta omputer Inc. PROJET : FH Size ocument Number Rev IEX PEK-M / ate: Monday, ecember 0, 00 Sheet of

12 IEX PEK-M (POWER) VPLLEXP = 00m max VPLLEXP: This pin can be left as no connect in On-ie VR enabled mode (default). VIO =.0 max +.0V_PH T0 0 0U/0V_ 0 0 V_ = 0. max VORE=. max +.0V_PH 0U/0V_ 0 U/.V_ F F F0 F H H H0 H J0 J +.0V_PH +V_RUN VFIPLL = 00m max T 0.U/V_ +.0V_LN_VPLL_EXPJ U/.V_ U/.V_ U/.V_ U/.V_ VVRM = 0.0 max +.V_RUN +.0V_VFIPLL +.0V_PH VIO =.0 max +.0V_PH PH ES(V.0) P +NVRM_VQ:. V supply for ual hannel NN interface. This power is supplied by core well. If unused, this pin should be connected to Vcc_. L L K N0 N N N N N J J T T U U V V W W E E G G H N0 N N T J M UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VFIPLL VIO[] IbexPeak-M_RP0 0uH 0uH +.V_VPLL + 0 *0U/.V_ +.V_VPLL POWER V ORE PI E* FI RT LVS HVMOS MI NN / SPI - +V - +V_RUN VVRM = 0.0 max +.V_RUN VMI = 0.0 max R VPNN = 0. max +.V_RUN VME_ = 0.0 max +V_RUN R 0_ VTX_LVS = 0.0 max V_ = 0. max +.0V_PH +.0V_VTT +.0V_PH VME_: ES(V.0)P:supply for the Intel Management Engine.This is a separate power plane that may or may not be powered in S S states. This plane must be on in S0 and other times the Intel Management Engine is used. U/.V_ V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VME_[] VME_[] VME_[] VME_[] E0 E F F H H P P T T T T U M K K0 K K K M M M M M P P 0.U/V_ U/.V_ 0.U/V_ 0.U/V_ R0 0/J_ *0/J_ T +V_RUN U/.V_ +.V_RUN VLK PSUSYP VPLL = 0.0 max +.V_VPLL VPLL = 0.0 max +.V_VPLL VIO =.0 max +.0V_PH 0 U/.V_ VSUS_ = 0. max +V_S V_ = 0. max +V_RUN V_PU>m +.0V_VTT +V_RT V = 00m max 00.U/0V_ U/.V_ 0.U/V_ U/.V_ U/.V_ 0.U/V_ 0.U/V_ 0.U/V_ PRT U/.V_ PSST PSUS 0.U/V_ 0.U/V_ 0.U/V_ 0.U/V_ P P F F Y0 F F F V V V Y Y Y V U H J H F H F V Y P U U0 U V V Y T U UJ VLK[] VLK[] VLN[] VLN[] PSUSYP VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[0] VME[] VME[] PRT VVRM[] VPLL[] VPLL[] VPLL[] VPLL[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] PSST PSUS VSUS_[] VSUS_[0] VSUS_[] VSUS_[] V_[] V_[] V_[] V_PU_IO[] V_PU_IO[] VRT IbexPeak-M_RP0 U/.V_ 0.U/V_ 0.U/V_ POWER lock and Miscellaneous RT PU PI/GPIO/LP ST PI/GPIO/LP US H VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VIO[] VREF_SUS VREF V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VIO[] VVRM[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VME[] VME[] VME[] VME[] VSUSH V V Y Y V U U U P P N N M M L L J J H H G G F F E E U V F K J L M N P U K K H T0 H 0 F F0 F H0 0 Y Y L0 +VREF_SUS +VREF U/.V_ 0.U/V_ +.0V_PH U/.V_ U/.V_ 0 0.U/V_ 0.U/V_ +.0V_PH +.0V_VSTPLL VVRM = 0.0 max +.V_RUN R U/.V_ 0.U/V_ R R +.0V_PH +V_S VIO =.0 max +V_RUN VIO =.0 max VME =. max 0/J_ U/.V_ +V_S 00/J_ SM0K--F 00/J_ SM0K--F VIO =.0 max VSUS_ = 0. max +V_S +V_S +V_RUN +V_RUN V_ = 0. max T VREF_SUS>m VREF>m +.0V_PH VSUSH = m max + *0U/.V_ U/.V_ VRT = m max Quanta omputer Inc. PROJET : FH Size ocument Number Rev IEX PEK-M / Tuesday, ecember, 00 ate: Sheet of

13 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Friday, ecember 0, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Friday, ecember 0, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : IEX PEK-M / Friday, ecember 0, 00 FH IEX PEK-M (GN) UH IbexPeak-M_RP0 UH IbexPeak-M_RP0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[0] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K VSS[] L VSS[] L VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] U0 VSS[] M VSS[] V VSS[] M VSS[] M VSS[] 0 VSS[] N VSS[] N0 VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[0] W VSS[] F VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] U VSS[] N VSS[] 0 VSS[0] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[0] H VSS[0] VSS[] VSS[] UI IbexPeak-M_RP0 UI IbexPeak-M_RP0 VSS[] Y VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] G VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] E VSS[] E0 VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] E VSS[] E VSS[0] E0 VSS[] E VSS[] E0 VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] M VSS[] M VSS[] M0 VSS[] N VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P0 VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] T VSS[0] T VSS[0] U0 VSS[0] U VSS[0] U VSS[0] U VSS[0] P VSS[0] V VSS[0] P VSS[0] V VSS[] V0 VSS[] V VSS[] V0 VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[0] F VSS[] F VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G0 VSS[0] G VSS[] G VSS[] V VSS[] V VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y0 VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H0 VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[0] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[0] H VSS[] J

14 R *0K R 0K *P/0V_ M [:0] +V_RUN R *0K IMM0_S0 IMM0_S SMbus address 0 M S0 M S M S M S0# M S# M LKP0 R M LKN0 0K M LKP M LKN M KE0 M KE M S# M RS# M WE# GLK_SM GT_SM,0, GLK_SM,0, GT_SM M OT0 M OT M M[:0] *P/0V_ M QSP[:0] M QSN[:0] M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S GLK_SM GT_SM M M0 M M M M M M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q[:0] PM_EXTTS#0, R_RMRST# +.V_SUS +R_VTTREF R K/J_ R0 K/J_ +V_RUN +SMR_VREF_Q0 +SMR_VREF_IMM0 R *0/J_ +SMR_VREF_IMM0 0.U/V_ +.V_SUS PM_EXTTS# JIM V VSS V VSS V VSS V VSS V VSS0 V VSS V VSS V VSS V VSS V0 VSS V VSS V VSS V VSS V VSS V VSS0 V VSS V VSS V VSS VSS VSP VSS VSS N VSS N VSS NTEST VSS VSS0 EVENT# VSS RESET# VSS VSS VSS VREF_Q VSS VREF_ VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VTT VSS VTT VSS VSS G VSS G VSS -0- P00 R SRM SO-IMM (0P) G G Intel is requesting that customers implement all methods (M and M and M described below) to generate and control Reference voltage for ata/strobe inputs (VREFQ) on larksfield based platforms. for fine tuning of the VREFQ levels to optimize the voltage and timing margins. +0.V_R_VTT M:Fixed voltage resistor divider or R Voltage Regulator drives the Vref M: set of igital potentiometers and op amps are added on the motherboard (one pair for each channel). This circuit is controlled by SMUS (SM_LK & SM_T) on PH. M:Intel investigating future processor VREF_Q generation to replace M and M. This would require routing processor signal balls J and H to SO-IMM connectors directly V_SUS 0U/.V_ 0U/.V_ Place these aps near So-imm. 0U/.V_ 0.U/0V_ 0.U/0V_ +SMR_VREF_IMM0.U/.V_ +SMR_VREF_Q0.U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0 0.U/0V_ 0 0.U/0V_ + 0 *0U/.V_. 0.U/V_ 0.U/V_ 0.U/V_ +.V_SUS +R_VTTREF R R K/J_ *0/J_ M VREF +SMR_VREF_Q0 +V_RUN +0.V_R_VTT R 0_.U/.V_ 0.U/V_ U/.V_ U/.V_ U/.V_ U/.V_ 0U/0V_ 0 0 R K/J_ 0.U/V_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev R IMM- ate: Tuesday, ecember, 00 Sheet of

15 M M Q M QSN M Q M Q M Q M Q M M QSP IMM_S M M QSN M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M M QSP M Q0 M 0 M QSN M Q M Q M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M QSP M M QSN M Q M M QSP M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M M M QSN M Q M QSP M 0 M Q0 M Q M Q M Q M M QSN M Q M QSP M M QSP0 M M QSN M M Q M QSN0 IMM_S0 M PM_EXTTS# M QSP GLK_SM GT_SM GT_SM GLK_SM IMM_S IMM_S0 M M M M M M M M M M M M M M M M0 M [:0] M S0 M S M S M S0# M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# M WE# M QSP[:0] M QSN[:0] M OT0 M OT M Q[:0] R_RMRST#, PM_EXTTS# M M[:0] +.V_SUS +R_VTTREF +.V_SUS +V_RUN +0.V_R_VTT +SMR_VREF_IMM +V_RUN +.V_SUS +0.V_R_VTT +SMR_VREF_IMM +SMR_VREF_Q +SMR_VREF_Q +.V_SUS +R_VTTREF +SMR_VREF_IMM +SMR_VREF_Q +V_RUN GT_SM,0, GLK_SM,0, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, 00 FH Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Tuesday, ecember, 00 FH Place these aps near So-imm. M VREF SMbus address 0U/.V_ 0U/.V_ 0.U/V_ 0.U/V_ 0U/.V_ 0U/.V_ P00 R SRM SO-IMM (0P) JIM -00- P00 R SRM SO-IMM (0P) JIM /P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q.U/.V_.U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0.U/V_ 0.U/V_ R K/J_ R K/J_ R *0/J_ R *0/J_ 0U/.V_ 0U/.V_ R K/J_ R K/J_ 0.U/V_ 0.U/V_ 0U/.V_ 0U/.V_ P00 R SRM SO-IMM (0P) JIM -00- P00 R SRM SO-IMM (0P) JIM -00- V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 G G G G 0.U/V_ 0.U/V_ 00 0.U/V_ 00 0.U/V_ R 0K R 0K R0 K/J_ R0 K/J_ R K/J_ R K/J_ 0.U/V_ 0.U/V_ *P/0V_ *P/0V_ U/.V_ U/.V_ 0U/0V_ 0 0 0U/0V_ U/.V_ 0 U/.V_ 0 0U/.V_ 0 0U/.V_ R *0K R *0K 0U/.V_ 0U/.V_.U/.V_.U/.V_ 0.U/V_ 0.U/V_ R *0K R *0K 0.U/V_ 0.U/V_ 0.U/V_ 0.U/V_.U/.V_.U/.V_ R 0K R 0K R *0/J_ R *0/J_ R 0_ R 0_ 0.U/V_ 0.U/V_ *P/0V_ *P/0V_ + 0 *0U/.V_. + 0 *0U/.V_.

16 acklight ontrol(ls) KLIGHT POWER LE Panel POWER SWITH(LVS) +V_RUN +VIN 0mils F /VS_0 V_LIGHT R 0K +V_RUN + 0U/V_0 000P/0V_ 0 0.U/V/XR, MPWROK LI# PNEL_KEN S S 0 U ISPON MVHG0FTG item +VPU LV_ 0mils F /VS_0 0 LV *0.u/0V_ 0.u/0V_ p/0v_.u/0v_ 0.U/0V_ MR PT- 0p/0V_ LI# +V_S +V_RUN U - LV_ LVS/ ENV, MPWROK u/0v_ U INT_LVS_IGON_U MVHG0FTG item IN IN ON/OFF R PLI-TRG 00K/J_ OUT GN GN +V_RUN F MINI_PS-HS _POWER + 0u/0V_ 000p/0V_ 0.u/0V_ V_LIGHT LV +VPU R *00K LV R 0 0 USP- USP+ USP- USP+ MI_LK L *WM-0-00T USP- USP+ MI_LK *000p/0V_ L_LK L_T R 0_ R0 0_ ON 0 0 MER ISPON LVS_VJ MI_LK MI_T _POWER +V_RUN 0.U INT_LVS_IGON_U Q *TEU *R/J/00 Q0 *N00E-T-E MI_T I_PWM ONTRST R R *0/J_ 0/J_ MI_T 0 *000p/0V_ LVS_VJ 0.U/0V_ TXLOUT0- TXLOUT0+ TXLOUT- TXLOUT+ TXUOUT0- TXUOUT0+ TXUOUT- TXUOUT+ TXLOUT- TXLOUT+ 0 0 L_ON0P -00-0P-LUV TXUOUT0- TXUOUT0+ TXUOUT- TXUOUT+ TXLOUT0- TXLOUT0+ TXLOUT- TXLOUT+ TXLLKOUT- TXLLKOUT+ TXUOUT- TXUOUT+ TXULKOUT- TXULKOUT+ *000PF TXLOUT- TXLOUT+ TXLLKOUT- TXLLKOUT+ TXUOUT- TXUOUT+ TXULKOUT- TXULKOUT+ Quanta omputer Inc. PROJET : FH Size ocument Number Rev L/LE Panel/ ate: Monday, ecember 0, 00 Sheet of

17 RT ONN/ LEVEL SHIFT +V_RUN INT_RT_RE INT_RT_GRE INT_RT_LU INT_RT_RE INT_RT_GRE INT_RT_LU 0mils F./V_POLY R 0/F_ HPT R.P/0V_ 0/F_.P/0V_ R L K0LL0_ L K0LL0_ L K0LL0_ 0/F_.P/0V_ 0.U/0V_ V_RT RT_RE_L RT_GRE_L RT_LU_L.P/0V_.P/0V_.P/0V_ 0 T N00 FOOTPRINT N RT T +V_RUN V_RT 0.U/0V_ V_RT RT_RE_L RT_GRE_L RT_LU_L U V_SYN SYN_OUT SYN_OUT V_ YP SYN_IN V_VIEO SYN_IN VIEO IN VIEO IN VIEO OUT GN _OUT M00 0 RT_VSYN_Q R RT_HSYN_Q R INT_RT_VSYN INT_RT_HSYN G_LK_ G_T_ RTLK RTT /F_ /F_ INT_RT_VSYN INT_RT_HSYN G_LK_ G_T_ RT_VSYN_R RT_HSYN_R R.K/J_ L L V_RT R.K/J_ LM0SN LM0SN RT_VSYN_L RT_HSYN_L 0P/0V_ 0P/0V_ +V_RUN 0P/0V_ 0P/0V_ +V_RUN +V_RUN 0.U/0V_ 0.U/0V_ G_LK_ G_T_ R R.K/J_.K/J_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev RT ONN/ LEVEL SHIFT ate: Monday, ecember 0, 00 Sheet of

18 ard Reader E 0 0 USP- USP+ 0 LK_M_R USP- USP+ +V_RUN,0,, PLTRST# XI XO MOE_SEL PLTRST# X- R short_ S_T For E *p/0v_ *p/0v_ R0 0/F_ R L *WM-0-00T Y *MHz R 0K/J_ U X_LE/F_ X_E#/F_ F_# X_LE/F_ GPIO0 F_0 S_T/X_RE#/F_ 0 F_ S_T/X_WE#/F_ F_ X_RY/F_ F_/SM_# S_T/X_WP#/F_ S_WP F_/X_# 0 S_# F_0/SM_WPM#/S_WP S_M F_0/S_# S_T/X_0/F_ X- F_MK# S_LK/X_/MS_LK/F_ F_/X_ S_T/X_/MS_/F_ F_MRQ F_S0# 0.K/F_ RREF MS_INS#/F_IOR# RREF S_T/X_/MS_/F_IOWR# S_T0/X_/MS_0/F_RST# S_T/X_/MS_/F_IORY X_/MS_S/F_ M P V_PLL_IN R *0_ R *0K_ *P/0V_ XTLI XTLO MOE_SEL RST# U/.V_ Realtek RTS-GR VREG_OUT 0 V_IN V_ IN V_ IN SP SP S_M SP SP0 MS_# MS_T SP SP SP 0.u/0V_ V_OUT 0mil at least 0.u/0V_ VREG 0mil at least Vreg out.v from Internal.VLO 0mil at least 0.u/0V_ V_OUT R_V_OUT 0mil at least G G_PLL GN GN 0.u/0V_ +VR +V_RUN 0.U/.V_ 0 U/.V_ *0.u/0V_ *0.u/0V_ 0.u/0V_ *0.u/0V_ *0U/0V_ R.U/.V_ +V_RUN *short_ +VR +V_RUN u/0V_ 0.u/0V_ 0.u/0V_ s close U0 pin as possible SP SP SP R R R short_ short_ short_ MS_T0_S_T0 MS_T S_T MS_T0_S_T0 S_T S_T S_T S_LK S_M S_# S_WP +VR N 0 S-V S-T0 S-T 0 S-T S-T S-LK S-M S-/ S-WP S-GN S-GN SP SP R0 R short_ short_ MS_S S_T MS_T0_S_T0 MS_T MS_T MS_T MS_LK MS_# MS_S MS-V MS-T0 MS-T MS-T MS-T MS-SLK MS-INS MS-S MS-GN MS-GN GN GN R short_ S_LK R_REER_PROONN SP R short_ MS_LK *P +VR +VR SP0 R short_ MS_T 0.U/.V_ R 0K/F_ 0 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ Quanta omputer Inc. PROJET : FH Size ocument Number Rev ard Reader RTS ate: Monday, ecember 0, 00 Sheet of E

19 Placement close to LN chip.0000 MHz V 0 MI0+ MI0- TRL RSET MLKX MLKX LE/EESK LE/EEI LE/EEO EES V 0 V/V PERST PLTRST#,0,, LN_WKE# EES 0 PIE_TXP 0 PIE_TXN 0 LK_PIE_LOMP 0 LK_PIE_LOMN 0 PIE_RXP 0 PIE_RXN X-TX- MI0+ MI0-0.u/0V_ *u/0v_ LN V PIE_TXP PIE_TXN LK_PIE_LOMP LK_PIE_LOMN 0.u/0V_ PERX+ 0.u/0V_ PERX- V EV V ISOLTE# LKREQ ISOLTE# V V V V MI+ MI- X-TX+ X-TX0- X-TX0+ V LK_LN_REQ# 0 LFE-R /F_ /F_ GN_LN +V_RUN 0/00 Transformer RJ EMI 0.u/0V_ signal swap *0u/0V_ 0.u/0V_ R 0_ PIE_WKE# heck point:. LOM_LK_REQ# and PIE_WKE# needsto be pull up by PH side. PIE_TX must have cap at PH side LN_PIE_PWR_TRL# GN_LN V X'tal MHz MLKX MLKX LN EEPROM LE/EESK LE/EEI LE/EEO GN_LN V LN Power u/0v_ u/0v_ Isolate# is for power saving. 0_ R00 It needs to pull low when system state in S, S, and S. pull high when system at S0 state 0_ R 0.0U/V_ 0.0U/V_ U U R.K/F_ V MIP0 MIN0 N/F MIP MIN GN N/MIP N/MIN N/MIP N/MIN MI+ MI- X-TX0+ X-TX0- X-TX-G0 X-TX-G X-TX+ X-TX- T- T+ T N N T R- R+ TX- TX+ 0 T N N T RX- RX+ VTRL/SROUT GN RSET VTRVSR N/VSR N/ENSWREG KTL KTL N/V 0 N/LV_PLL LE0 V RTL0EL-GR V GN HSIP HSIN REFLK_P REFLK_N EV HSOP HSON EGN N/SMLK N/SMT 0 R V LE/EESK LE/EEI LE/EEO EES GN V 0 V ISOLTE LNWKE LKREQ R 000p/KV_ R0 R R0 R R K/F_ R K/F_ R */F_ */F_ */F_ */F_ 0.u/0V_ R 0.u/0V_ *0K_ *00/F_ *R0V-0_N 0.u/0V_ ON 0.u/0V_ u/0V_ RJ RJ-000FR00S0ZL-P 0.u/0V_ - 0_ R 0_ R 0_ R 0_ R R M/F_ R K/J_ R.K_ U S SK I O Y *TN V ORG GN +V_S V P/0_ P/0_ R *short_ E V Quanta omputer Inc. PROJET : FH Size ocument Number Rev LN_RTL0EL/RJ ate: Tuesday, ecember 0, 00 Sheet of E *0.u/0V_ REQ by layout

20 ." ST H ST O N GN TXP TXN GN RXN RXP GN XX XX XX XX.V.V.V 0 GN GN GN V V V GN RSV GN V 0 V V ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ 0.(0mils) +V_ST 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ +V_ST ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 Place these ST ap close to device, not S F /VS_0 ST_TXP ST_TXN ST_RXN ST_RXP +V_RUN 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ O ONN GN TX TX# GN RX# RX GN ON P V V 0 M GN GN GN GN GN GN O_V 0 mils 0 0.U/0V 0.U/0V 0U/0V_ F /VS_0 +V_RUN f_x_-_ ST_H sata-0fr0gzr-p-r *0.u/0V_ 0.u/0V_ 0u/0V_ SLS-G Hole PU Nut H h-cdpb H0 h-cdpb H h-cdpb H h-cdpb Hole for ES H *H-P- H *hg-cdp H *hg-cdp ecoupling ap EMI request +VIN 0 *.U/V_ *.U/V_ *.U/V_ *.U/V_ MINI R ntenna Hole H *H-N H *FH H *FH +VIN *.U/V_ *.U/V_ Thermal Module - VG Nut H h-bcdpb H *FH EMI(ecoupling ap) H *H-P- 0 *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ H H h-cdpb h-cdpb H *FH *.U/V_ *.U/V_ *.U/V_ H h-bcdpb H *FH H *FH H *FH H *FH H *FH H *FH +V_RUN +V_RUN +VPU H *FH H *FH H *FH H *FH H *FH GN_LN Fan Hole H *O-FH- - 0.U/V_ 0.U/V_ 0.U/V_ Size ocument Number Rev H/ O/HOLE Quanta omputer Inc. PROJET : FH ate: Tuesday, ecember, 00 Sheet 0 of